aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorAlex Deucher <alexander.deucher@amd.com>2015-11-23 13:13:45 -0500
committerAlex Deucher <alexander.deucher@amd.com>2015-12-02 12:45:54 -0500
commit8333f607a6317565a71f286728cf6a1f08e56004 (patch)
tree2baad6d3029281a5cdcad37dd5d0493cda9bfbf6
parent80d69009ef67d0753c1c30c62056a04275898531 (diff)
drm/radeon: remove UMS support
It's been deprecated behind a kconfig option for almost two years and hasn't really been supported for years before that. DDX support was dropped more than three years ago. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat
-rw-r--r--drivers/gpu/drm/radeon/Kconfig9
-rw-r--r--drivers/gpu/drm/radeon/Makefile4
-rw-r--r--drivers/gpu/drm/radeon/drm_buffer.c177
-rw-r--r--drivers/gpu/drm/radeon/drm_buffer.h148
-rw-r--r--drivers/gpu/drm/radeon/r300_cmdbuf.c1186
-rw-r--r--drivers/gpu/drm/radeon/r600_blit.c874
-rw-r--r--drivers/gpu/drm/radeon/r600_cp.c2660
-rw-r--r--drivers/gpu/drm/radeon/r600_cs.c95
-rw-r--r--drivers/gpu/drm/radeon/radeon_cp.c2243
-rw-r--r--drivers/gpu/drm/radeon/radeon_drv.c97
-rw-r--r--drivers/gpu/drm/radeon/radeon_drv.h2048
-rw-r--r--drivers/gpu/drm/radeon/radeon_irq.c402
-rw-r--r--drivers/gpu/drm/radeon/radeon_mem.c302
-rw-r--r--drivers/gpu/drm/radeon/radeon_state.c3261
14 files changed, 0 insertions, 13506 deletions
diff --git a/drivers/gpu/drm/radeon/Kconfig b/drivers/gpu/drm/radeon/Kconfig
index 421ae130809b..9909f5c68d76 100644
--- a/drivers/gpu/drm/radeon/Kconfig
+++ b/drivers/gpu/drm/radeon/Kconfig
@@ -5,12 +5,3 @@ config DRM_RADEON_USERPTR
5 help 5 help
6 This option selects CONFIG_MMU_NOTIFIER if it isn't already 6 This option selects CONFIG_MMU_NOTIFIER if it isn't already
7 selected to enabled full userptr support. 7 selected to enabled full userptr support.
8
9config DRM_RADEON_UMS
10 bool "Enable userspace modesetting on radeon (DEPRECATED)"
11 depends on DRM_RADEON
12 help
13 Choose this option if you still need userspace modesetting.
14
15 Userspace modesetting is deprecated for quite some time now, so
16 enable this only if you have ancient versions of the DDX drivers.
diff --git a/drivers/gpu/drm/radeon/Makefile b/drivers/gpu/drm/radeon/Makefile
index dea53e36a2ef..08bd17d3925c 100644
--- a/drivers/gpu/drm/radeon/Makefile
+++ b/drivers/gpu/drm/radeon/Makefile
@@ -58,10 +58,6 @@ $(obj)/evergreen_cs.o: $(obj)/evergreen_reg_safe.h $(obj)/cayman_reg_safe.h
58 58
59radeon-y := radeon_drv.o 59radeon-y := radeon_drv.o
60 60
61# add UMS driver
62radeon-$(CONFIG_DRM_RADEON_UMS)+= radeon_cp.o radeon_state.o radeon_mem.o \
63 radeon_irq.o r300_cmdbuf.o r600_cp.o r600_blit.o drm_buffer.o
64
65# add KMS driver 61# add KMS driver
66radeon-y += radeon_device.o radeon_asic.o radeon_kms.o \ 62radeon-y += radeon_device.o radeon_asic.o radeon_kms.o \
67 radeon_atombios.o radeon_agp.o atombios_crtc.o radeon_combios.o \ 63 radeon_atombios.o radeon_agp.o atombios_crtc.o radeon_combios.o \
diff --git a/drivers/gpu/drm/radeon/drm_buffer.c b/drivers/gpu/drm/radeon/drm_buffer.c
deleted file mode 100644
index f4e0f3a3d7b1..000000000000
--- a/drivers/gpu/drm/radeon/drm_buffer.c
+++ /dev/null
@@ -1,177 +0,0 @@
1/**************************************************************************
2 *
3 * Copyright 2010 Pauli Nieminen.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
24 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 *
27 **************************************************************************/
28/*
29 * Multipart buffer for coping data which is larger than the page size.
30 *
31 * Authors:
32 * Pauli Nieminen <suokkos-at-gmail-dot-com>
33 */
34
35#include <linux/export.h>
36#include "drm_buffer.h"
37
38/**
39 * Allocate the drm buffer object.
40 *
41 * buf: Pointer to a pointer where the object is stored.
42 * size: The number of bytes to allocate.
43 */
44int drm_buffer_alloc(struct drm_buffer **buf, int size)
45{
46 int nr_pages = size / PAGE_SIZE + 1;
47 int idx;
48
49 /* Allocating pointer table to end of structure makes drm_buffer
50 * variable sized */
51 *buf = kzalloc(sizeof(struct drm_buffer) + nr_pages*sizeof(char *),
52 GFP_KERNEL);
53
54 if (*buf == NULL) {
55 DRM_ERROR("Failed to allocate drm buffer object to hold"
56 " %d bytes in %d pages.\n",
57 size, nr_pages);
58 return -ENOMEM;
59 }
60
61 (*buf)->size = size;
62
63 for (idx = 0; idx < nr_pages; ++idx) {
64
65 (*buf)->data[idx] =
66 kmalloc(min(PAGE_SIZE, size - idx * PAGE_SIZE),
67 GFP_KERNEL);
68
69
70 if ((*buf)->data[idx] == NULL) {
71 DRM_ERROR("Failed to allocate %dth page for drm"
72 " buffer with %d bytes and %d pages.\n",
73 idx + 1, size, nr_pages);
74 goto error_out;
75 }
76
77 }
78
79 return 0;
80
81error_out:
82
83 for (; idx >= 0; --idx)
84 kfree((*buf)->data[idx]);
85
86 kfree(*buf);
87 return -ENOMEM;
88}
89
90/**
91 * Copy the user data to the begin of the buffer and reset the processing
92 * iterator.
93 *
94 * user_data: A pointer the data that is copied to the buffer.
95 * size: The Number of bytes to copy.
96 */
97int drm_buffer_copy_from_user(struct drm_buffer *buf,
98 void __user *user_data, int size)
99{
100 int nr_pages = size / PAGE_SIZE + 1;
101 int idx;
102
103 if (size > buf->size) {
104 DRM_ERROR("Requesting to copy %d bytes to a drm buffer with"
105 " %d bytes space\n",
106 size, buf->size);
107 return -EFAULT;
108 }
109
110 for (idx = 0; idx < nr_pages; ++idx) {
111
112 if (copy_from_user(buf->data[idx],
113 user_data + idx * PAGE_SIZE,
114 min(PAGE_SIZE, size - idx * PAGE_SIZE))) {
115 DRM_ERROR("Failed to copy user data (%p) to drm buffer"
116 " (%p) %dth page.\n",
117 user_data, buf, idx);
118 return -EFAULT;
119
120 }
121 }
122 buf->iterator = 0;
123 return 0;
124}
125
126/**
127 * Free the drm buffer object
128 */
129void drm_buffer_free(struct drm_buffer *buf)
130{
131
132 if (buf != NULL) {
133
134 int nr_pages = buf->size / PAGE_SIZE + 1;
135 int idx;
136 for (idx = 0; idx < nr_pages; ++idx)
137 kfree(buf->data[idx]);
138
139 kfree(buf);
140 }
141}
142
143/**
144 * Read an object from buffer that may be split to multiple parts. If object
145 * is not split function just returns the pointer to object in buffer. But in
146 * case of split object data is copied to given stack object that is suplied
147 * by caller.
148 *
149 * The processing location of the buffer is also advanced to the next byte
150 * after the object.
151 *
152 * objsize: The size of the objet in bytes.
153 * stack_obj: A pointer to a memory location where object can be copied.
154 */
155void *drm_buffer_read_object(struct drm_buffer *buf,
156 int objsize, void *stack_obj)
157{
158 int idx = drm_buffer_index(buf);
159 int page = drm_buffer_page(buf);
160 void *obj = NULL;
161
162 if (idx + objsize <= PAGE_SIZE) {
163 obj = &buf->data[page][idx];
164 } else {
165 /* The object is split which forces copy to temporary object.*/
166 int beginsz = PAGE_SIZE - idx;
167 memcpy(stack_obj, &buf->data[page][idx], beginsz);
168
169 memcpy(stack_obj + beginsz, &buf->data[page + 1][0],
170 objsize - beginsz);
171
172 obj = stack_obj;
173 }
174
175 drm_buffer_advance(buf, objsize);
176 return obj;
177}
diff --git a/drivers/gpu/drm/radeon/drm_buffer.h b/drivers/gpu/drm/radeon/drm_buffer.h
deleted file mode 100644
index c80d3a340b94..000000000000
--- a/drivers/gpu/drm/radeon/drm_buffer.h
+++ /dev/null
@@ -1,148 +0,0 @@
1/**************************************************************************
2 *
3 * Copyright 2010 Pauli Nieminen.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
24 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 *
27 **************************************************************************/
28/*
29 * Multipart buffer for coping data which is larger than the page size.
30 *
31 * Authors:
32 * Pauli Nieminen <suokkos-at-gmail-dot-com>
33 */
34
35#ifndef _DRM_BUFFER_H_
36#define _DRM_BUFFER_H_
37
38#include <drm/drmP.h>
39
40struct drm_buffer {
41 int iterator;
42 int size;
43 char *data[];
44};
45
46
47/**
48 * Return the index of page that buffer is currently pointing at.
49 */
50static inline int drm_buffer_page(struct drm_buffer *buf)
51{
52 return buf->iterator / PAGE_SIZE;
53}
54/**
55 * Return the index of the current byte in the page
56 */
57static inline int drm_buffer_index(struct drm_buffer *buf)
58{
59 return buf->iterator & (PAGE_SIZE - 1);
60}
61/**
62 * Return number of bytes that is left to process
63 */
64static inline int drm_buffer_unprocessed(struct drm_buffer *buf)
65{
66 return buf->size - buf->iterator;
67}
68
69/**
70 * Advance the buffer iterator number of bytes that is given.
71 */
72static inline void drm_buffer_advance(struct drm_buffer *buf, int bytes)
73{
74 buf->iterator += bytes;
75}
76
77/**
78 * Allocate the drm buffer object.
79 *
80 * buf: A pointer to a pointer where the object is stored.
81 * size: The number of bytes to allocate.
82 */
83extern int drm_buffer_alloc(struct drm_buffer **buf, int size);
84
85/**
86 * Copy the user data to the begin of the buffer and reset the processing
87 * iterator.
88 *
89 * user_data: A pointer the data that is copied to the buffer.
90 * size: The Number of bytes to copy.
91 */
92extern int drm_buffer_copy_from_user(struct drm_buffer *buf,
93 void __user *user_data, int size);
94
95/**
96 * Free the drm buffer object
97 */
98extern void drm_buffer_free(struct drm_buffer *buf);
99
100/**
101 * Read an object from buffer that may be split to multiple parts. If object
102 * is not split function just returns the pointer to object in buffer. But in
103 * case of split object data is copied to given stack object that is suplied
104 * by caller.
105 *
106 * The processing location of the buffer is also advanced to the next byte
107 * after the object.
108 *
109 * objsize: The size of the objet in bytes.
110 * stack_obj: A pointer to a memory location where object can be copied.
111 */
112extern void *drm_buffer_read_object(struct drm_buffer *buf,
113 int objsize, void *stack_obj);
114
115/**
116 * Returns the pointer to the dword which is offset number of elements from the
117 * current processing location.
118 *
119 * Caller must make sure that dword is not split in the buffer. This
120 * requirement is easily met if all the sizes of objects in buffer are
121 * multiples of dword and PAGE_SIZE is multiple dword.
122 *
123 * Call to this function doesn't change the processing location.
124 *
125 * offset: The index of the dword relative to the internat iterator.
126 */
127static inline void *drm_buffer_pointer_to_dword(struct drm_buffer *buffer,
128 int offset)
129{
130 int iter = buffer->iterator + offset * 4;
131 return &buffer->data[iter / PAGE_SIZE][iter & (PAGE_SIZE - 1)];
132}
133/**
134 * Returns the pointer to the dword which is offset number of elements from
135 * the current processing location.
136 *
137 * Call to this function doesn't change the processing location.
138 *
139 * offset: The index of the byte relative to the internat iterator.
140 */
141static inline void *drm_buffer_pointer_to_byte(struct drm_buffer *buffer,
142 int offset)
143{
144 int iter = buffer->iterator + offset;
145 return &buffer->data[iter / PAGE_SIZE][iter & (PAGE_SIZE - 1)];
146}
147
148#endif
diff --git a/drivers/gpu/drm/radeon/r300_cmdbuf.c b/drivers/gpu/drm/radeon/r300_cmdbuf.c
deleted file mode 100644
index 9418e388b045..000000000000
--- a/drivers/gpu/drm/radeon/r300_cmdbuf.c
+++ /dev/null
@@ -1,1186 +0,0 @@
1/* r300_cmdbuf.c -- Command buffer emission for R300 -*- linux-c -*-
2 *
3 * Copyright (C) The Weather Channel, Inc. 2002.
4 * Copyright (C) 2004 Nicolai Haehnle.
5 * All Rights Reserved.
6 *
7 * The Weather Channel (TM) funded Tungsten Graphics to develop the
8 * initial release of the Radeon 8500 driver under the XFree86 license.
9 * This notice must be preserved.
10 *
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
17 *
18 * The above copyright notice and this permission notice (including the next
19 * paragraph) shall be included in all copies or substantial portions of the
20 * Software.
21 *
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
25 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
26 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
27 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28 * DEALINGS IN THE SOFTWARE.
29 *
30 * Authors:
31 * Nicolai Haehnle <prefect_@gmx.net>
32 *
33 * ------------------------ This file is DEPRECATED! -------------------------
34 */
35
36#include <drm/drmP.h>
37#include <drm/radeon_drm.h>
38#include "radeon_drv.h"
39#include "r300_reg.h"
40#include "drm_buffer.h"
41
42#include <asm/unaligned.h>
43
44#define R300_SIMULTANEOUS_CLIPRECTS 4
45
46/* Values for R300_RE_CLIPRECT_CNTL depending on the number of cliprects
47 */
48static const int r300_cliprect_cntl[4] = {
49 0xAAAA,
50 0xEEEE,
51 0xFEFE,
52 0xFFFE
53};
54
55/**
56 * Emit up to R300_SIMULTANEOUS_CLIPRECTS cliprects from the given command
57 * buffer, starting with index n.
58 */
59static int r300_emit_cliprects(drm_radeon_private_t *dev_priv,
60 drm_radeon_kcmd_buffer_t *cmdbuf, int n)
61{
62 struct drm_clip_rect box;
63 int nr;
64 int i;
65 RING_LOCALS;
66
67 nr = cmdbuf->nbox - n;
68 if (nr > R300_SIMULTANEOUS_CLIPRECTS)
69 nr = R300_SIMULTANEOUS_CLIPRECTS;
70
71 DRM_DEBUG("%i cliprects\n", nr);
72
73 if (nr) {
74 BEGIN_RING(6 + nr * 2);
75 OUT_RING(CP_PACKET0(R300_RE_CLIPRECT_TL_0, nr * 2 - 1));
76
77 for (i = 0; i < nr; ++i) {
78 if (copy_from_user
79 (&box, &cmdbuf->boxes[n + i], sizeof(box))) {
80 DRM_ERROR("copy cliprect faulted\n");
81 return -EFAULT;
82 }
83
84 box.x2--; /* Hardware expects inclusive bottom-right corner */
85 box.y2--;
86
87 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) {
88 box.x1 = (box.x1) &
89 R300_CLIPRECT_MASK;
90 box.y1 = (box.y1) &
91 R300_CLIPRECT_MASK;
92 box.x2 = (box.x2) &
93 R300_CLIPRECT_MASK;
94 box.y2 = (box.y2) &
95 R300_CLIPRECT_MASK;
96 } else {
97 box.x1 = (box.x1 + R300_CLIPRECT_OFFSET) &
98 R300_CLIPRECT_MASK;
99 box.y1 = (box.y1 + R300_CLIPRECT_OFFSET) &
100 R300_CLIPRECT_MASK;
101 box.x2 = (box.x2 + R300_CLIPRECT_OFFSET) &
102 R300_CLIPRECT_MASK;
103 box.y2 = (box.y2 + R300_CLIPRECT_OFFSET) &
104 R300_CLIPRECT_MASK;
105 }
106
107 OUT_RING((box.x1 << R300_CLIPRECT_X_SHIFT) |
108 (box.y1 << R300_CLIPRECT_Y_SHIFT));
109 OUT_RING((box.x2 << R300_CLIPRECT_X_SHIFT) |
110 (box.y2 << R300_CLIPRECT_Y_SHIFT));
111
112 }
113
114 OUT_RING_REG(R300_RE_CLIPRECT_CNTL, r300_cliprect_cntl[nr - 1]);
115
116 /* TODO/SECURITY: Force scissors to a safe value, otherwise the
117 * client might be able to trample over memory.
118 * The impact should be very limited, but I'd rather be safe than
119 * sorry.
120 */
121 OUT_RING(CP_PACKET0(R300_RE_SCISSORS_TL, 1));
122 OUT_RING(0);
123 OUT_RING(R300_SCISSORS_X_MASK | R300_SCISSORS_Y_MASK);
124 ADVANCE_RING();
125 } else {
126 /* Why we allow zero cliprect rendering:
127 * There are some commands in a command buffer that must be submitted
128 * even when there are no cliprects, e.g. DMA buffer discard
129 * or state setting (though state setting could be avoided by
130 * simulating a loss of context).
131 *
132 * Now since the cmdbuf interface is so chaotic right now (and is
133 * bound to remain that way for a bit until things settle down),
134 * it is basically impossible to filter out the commands that are
135 * necessary and those that aren't.
136 *
137 * So I choose the safe way and don't do any filtering at all;
138 * instead, I simply set up the engine so that all rendering
139 * can't produce any fragments.
140 */
141 BEGIN_RING(2);
142 OUT_RING_REG(R300_RE_CLIPRECT_CNTL, 0);
143 ADVANCE_RING();
144 }
145
146 /* flus cache and wait idle clean after cliprect change */
147 BEGIN_RING(2);
148 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
149 OUT_RING(R300_RB3D_DC_FLUSH);
150 ADVANCE_RING();
151 BEGIN_RING(2);
152 OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0));
153 OUT_RING(RADEON_WAIT_3D_IDLECLEAN);
154 ADVANCE_RING();
155 /* set flush flag */
156 dev_priv->track_flush |= RADEON_FLUSH_EMITED;
157
158 return 0;
159}
160
161static u8 r300_reg_flags[0x10000 >> 2];
162
163void r300_init_reg_flags(struct drm_device *dev)
164{
165 int i;
166 drm_radeon_private_t *dev_priv = dev->dev_private;
167
168 memset(r300_reg_flags, 0, 0x10000 >> 2);
169#define ADD_RANGE_MARK(reg, count,mark) \
170 for(i=((reg)>>2);i<((reg)>>2)+(count);i++)\
171 r300_reg_flags[i]|=(mark);
172
173#define MARK_SAFE 1
174#define MARK_CHECK_OFFSET 2
175
176#define ADD_RANGE(reg, count) ADD_RANGE_MARK(reg, count, MARK_SAFE)
177
178 /* these match cmducs() command in r300_driver/r300/r300_cmdbuf.c */
179 ADD_RANGE(R300_SE_VPORT_XSCALE, 6);
180 ADD_RANGE(R300_VAP_CNTL, 1);
181 ADD_RANGE(R300_SE_VTE_CNTL, 2);
182 ADD_RANGE(0x2134, 2);
183 ADD_RANGE(R300_VAP_CNTL_STATUS, 1);
184 ADD_RANGE(R300_VAP_INPUT_CNTL_0, 2);
185 ADD_RANGE(0x21DC, 1);
186 ADD_RANGE(R300_VAP_UNKNOWN_221C, 1);
187 ADD_RANGE(R300_VAP_CLIP_X_0, 4);
188 ADD_RANGE(R300_VAP_PVS_STATE_FLUSH_REG, 1);
189 ADD_RANGE(R300_VAP_UNKNOWN_2288, 1);
190 ADD_RANGE(R300_VAP_OUTPUT_VTX_FMT_0, 2);
191 ADD_RANGE(R300_VAP_PVS_CNTL_1, 3);
192 ADD_RANGE(R300_GB_ENABLE, 1);
193 ADD_RANGE(R300_GB_MSPOS0, 5);
194 ADD_RANGE(R300_TX_INVALTAGS, 1);
195 ADD_RANGE(R300_TX_ENABLE, 1);
196 ADD_RANGE(0x4200, 4);
197 ADD_RANGE(0x4214, 1);
198 ADD_RANGE(R300_RE_POINTSIZE, 1);
199 ADD_RANGE(0x4230, 3);
200 ADD_RANGE(R300_RE_LINE_CNT, 1);
201 ADD_RANGE(R300_RE_UNK4238, 1);
202 ADD_RANGE(0x4260, 3);
203 ADD_RANGE(R300_RE_SHADE, 4);
204 ADD_RANGE(R300_RE_POLYGON_MODE, 5);
205 ADD_RANGE(R300_RE_ZBIAS_CNTL, 1);
206 ADD_RANGE(R300_RE_ZBIAS_T_FACTOR, 4);
207 ADD_RANGE(R300_RE_OCCLUSION_CNTL, 1);
208 ADD_RANGE(R300_RE_CULL_CNTL, 1);
209 ADD_RANGE(0x42C0, 2);
210 ADD_RANGE(R300_RS_CNTL_0, 2);
211
212 ADD_RANGE(R300_SU_REG_DEST, 1);
213 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530)
214 ADD_RANGE(RV530_FG_ZBREG_DEST, 1);
215
216 ADD_RANGE(R300_SC_HYPERZ, 2);
217 ADD_RANGE(0x43E8, 1);
218
219 ADD_RANGE(0x46A4, 5);
220
221 ADD_RANGE(R300_RE_FOG_STATE, 1);
222 ADD_RANGE(R300_FOG_COLOR_R, 3);
223 ADD_RANGE(R300_PP_ALPHA_TEST, 2);
224 ADD_RANGE(0x4BD8, 1);
225 ADD_RANGE(R300_PFS_PARAM_0_X, 64);
226 ADD_RANGE(0x4E00, 1);
227 ADD_RANGE(R300_RB3D_CBLEND, 2);
228 ADD_RANGE(R300_RB3D_COLORMASK, 1);
229 ADD_RANGE(R300_RB3D_BLEND_COLOR, 3);
230 ADD_RANGE_MARK(R300_RB3D_COLOROFFSET0, 1, MARK_CHECK_OFFSET); /* check offset */
231 ADD_RANGE(R300_RB3D_COLORPITCH0, 1);
232 ADD_RANGE(0x4E50, 9);
233 ADD_RANGE(0x4E88, 1);
234 ADD_RANGE(0x4EA0, 2);
235 ADD_RANGE(R300_ZB_CNTL, 3);
236 ADD_RANGE(R300_ZB_FORMAT, 4);
237 ADD_RANGE_MARK(R300_ZB_DEPTHOFFSET, 1, MARK_CHECK_OFFSET); /* check offset */
238 ADD_RANGE(R300_ZB_DEPTHPITCH, 1);
239 ADD_RANGE(R300_ZB_DEPTHCLEARVALUE, 1);
240 ADD_RANGE(R300_ZB_ZMASK_OFFSET, 13);
241 ADD_RANGE(R300_ZB_ZPASS_DATA, 2); /* ZB_ZPASS_DATA, ZB_ZPASS_ADDR */
242
243 ADD_RANGE(R300_TX_FILTER_0, 16);
244 ADD_RANGE(R300_TX_FILTER1_0, 16);
245 ADD_RANGE(R300_TX_SIZE_0, 16);
246 ADD_RANGE(R300_TX_FORMAT_0, 16);
247 ADD_RANGE(R300_TX_PITCH_0, 16);
248 /* Texture offset is dangerous and needs more checking */
249 ADD_RANGE_MARK(R300_TX_OFFSET_0, 16, MARK_CHECK_OFFSET);
250 ADD_RANGE(R300_TX_CHROMA_KEY_0, 16);
251 ADD_RANGE(R300_TX_BORDER_COLOR_0, 16);
252
253 /* Sporadic registers used as primitives are emitted */
254 ADD_RANGE(R300_ZB_ZCACHE_CTLSTAT, 1);
255 ADD_RANGE(R300_RB3D_DSTCACHE_CTLSTAT, 1);
256 ADD_RANGE(R300_VAP_INPUT_ROUTE_0_0, 8);
257 ADD_RANGE(R300_VAP_INPUT_ROUTE_1_0, 8);
258
259 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) {
260 ADD_RANGE(R500_VAP_INDEX_OFFSET, 1);
261 ADD_RANGE(R500_US_CONFIG, 2);
262 ADD_RANGE(R500_US_CODE_ADDR, 3);
263 ADD_RANGE(R500_US_FC_CTRL, 1);
264 ADD_RANGE(R500_RS_IP_0, 16);
265 ADD_RANGE(R500_RS_INST_0, 16);
266 ADD_RANGE(R500_RB3D_COLOR_CLEAR_VALUE_AR, 2);
267 ADD_RANGE(R500_RB3D_CONSTANT_COLOR_AR, 2);
268 ADD_RANGE(R500_ZB_FIFO_SIZE, 2);
269 } else {
270 ADD_RANGE(R300_PFS_CNTL_0, 3);
271 ADD_RANGE(R300_PFS_NODE_0, 4);
272 ADD_RANGE(R300_PFS_TEXI_0, 64);
273 ADD_RANGE(R300_PFS_INSTR0_0, 64);
274 ADD_RANGE(R300_PFS_INSTR1_0, 64);
275 ADD_RANGE(R300_PFS_INSTR2_0, 64);
276 ADD_RANGE(R300_PFS_INSTR3_0, 64);
277 ADD_RANGE(R300_RS_INTERP_0, 8);
278 ADD_RANGE(R300_RS_ROUTE_0, 8);
279
280 }
281}
282
283static __inline__ int r300_check_range(unsigned reg, int count)
284{
285 int i;
286 if (reg & ~0xffff)
287 return -1;
288 for (i = (reg >> 2); i < (reg >> 2) + count; i++)
289 if (r300_reg_flags[i] != MARK_SAFE)
290 return 1;
291 return 0;
292}
293
294static __inline__ int r300_emit_carefully_checked_packet0(drm_radeon_private_t *
295 dev_priv,
296 drm_radeon_kcmd_buffer_t
297 * cmdbuf,
298 drm_r300_cmd_header_t
299 header)
300{
301 int reg;
302 int sz;
303 int i;
304 u32 *value;
305 RING_LOCALS;
306
307 sz = header.packet0.count;
308 reg = (header.packet0.reghi << 8) | header.packet0.reglo;
309
310 if ((sz > 64) || (sz < 0)) {
311 DRM_ERROR("Cannot emit more than 64 values at a time (reg=%04x sz=%d)\n",
312 reg, sz);
313 return -EINVAL;
314 }
315
316 for (i = 0; i < sz; i++) {
317 switch (r300_reg_flags[(reg >> 2) + i]) {
318 case MARK_SAFE:
319 break;
320 case MARK_CHECK_OFFSET:
321 value = drm_buffer_pointer_to_dword(cmdbuf->buffer, i);
322 if (!radeon_check_offset(dev_priv, *value)) {
323 DRM_ERROR("Offset failed range check (reg=%04x sz=%d)\n",
324 reg, sz);
325 return -EINVAL;
326 }
327 break;
328 default:
329 DRM_ERROR("Register %04x failed check as flag=%02x\n",
330 reg + i * 4, r300_reg_flags[(reg >> 2) + i]);
331 return -EINVAL;
332 }
333 }
334
335 BEGIN_RING(1 + sz);
336 OUT_RING(CP_PACKET0(reg, sz - 1));
337 OUT_RING_DRM_BUFFER(cmdbuf->buffer, sz);
338 ADVANCE_RING();
339
340 return 0;
341}
342
343/**
344 * Emits a packet0 setting arbitrary registers.
345 * Called by r300_do_cp_cmdbuf.
346 *
347 * Note that checks are performed on contents and addresses of the registers
348 */
349static __inline__ int r300_emit_packet0(drm_radeon_private_t *dev_priv,
350 drm_radeon_kcmd_buffer_t *cmdbuf,
351 drm_r300_cmd_header_t header)
352{
353 int reg;
354 int sz;
355 RING_LOCALS;
356
357 sz = header.packet0.count;
358 reg = (header.packet0.reghi << 8) | header.packet0.reglo;
359
360 if (!sz)
361 return 0;
362
363 if (sz * 4 > drm_buffer_unprocessed(cmdbuf->buffer))
364 return -EINVAL;
365
366 if (reg + sz * 4 >= 0x10000) {
367 DRM_ERROR("No such registers in hardware reg=%04x sz=%d\n", reg,
368 sz);
369 return -EINVAL;
370 }
371
372 if (r300_check_range(reg, sz)) {
373 /* go and check everything */
374 return r300_emit_carefully_checked_packet0(dev_priv, cmdbuf,
375 header);
376 }
377 /* the rest of the data is safe to emit, whatever the values the user passed */
378
379 BEGIN_RING(1 + sz);
380 OUT_RING(CP_PACKET0(reg, sz - 1));
381 OUT_RING_DRM_BUFFER(cmdbuf->buffer, sz);
382 ADVANCE_RING();
383
384 return 0;
385}
386
387/**
388 * Uploads user-supplied vertex program instructions or parameters onto
389 * the graphics card.
390 * Called by r300_do_cp_cmdbuf.
391 */
392static __inline__ int r300_emit_vpu(drm_radeon_private_t *dev_priv,
393 drm_radeon_kcmd_buffer_t *cmdbuf,
394 drm_r300_cmd_header_t header)
395{
396 int sz;
397 int addr;
398 RING_LOCALS;
399
400 sz = header.vpu.count;
401 addr = (header.vpu.adrhi << 8) | header.vpu.adrlo;
402
403 if (!sz)
404 return 0;
405 if (sz * 16 > drm_buffer_unprocessed(cmdbuf->buffer))
406 return -EINVAL;
407
408 /* VAP is very sensitive so we purge cache before we program it
409 * and we also flush its state before & after */
410 BEGIN_RING(6);
411 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
412 OUT_RING(R300_RB3D_DC_FLUSH);
413 OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0));
414 OUT_RING(RADEON_WAIT_3D_IDLECLEAN);
415 OUT_RING(CP_PACKET0(R300_VAP_PVS_STATE_FLUSH_REG, 0));
416 OUT_RING(0);
417 ADVANCE_RING();
418 /* set flush flag */
419 dev_priv->track_flush |= RADEON_FLUSH_EMITED;
420
421 BEGIN_RING(3 + sz * 4);
422 OUT_RING_REG(R300_VAP_PVS_UPLOAD_ADDRESS, addr);
423 OUT_RING(CP_PACKET0_TABLE(R300_VAP_PVS_UPLOAD_DATA, sz * 4 - 1));
424 OUT_RING_DRM_BUFFER(cmdbuf->buffer, sz * 4);
425 ADVANCE_RING();
426
427 BEGIN_RING(2);
428 OUT_RING(CP_PACKET0(R300_VAP_PVS_STATE_FLUSH_REG, 0));
429 OUT_RING(0);
430 ADVANCE_RING();
431
432 return 0;
433}
434
435/**
436 * Emit a clear packet from userspace.
437 * Called by r300_emit_packet3.
438 */
439static __inline__ int r300_emit_clear(drm_radeon_private_t *dev_priv,
440 drm_radeon_kcmd_buffer_t *cmdbuf)
441{
442 RING_LOCALS;
443
444 if (8 * 4 > drm_buffer_unprocessed(cmdbuf->buffer))
445 return -EINVAL;
446
447 BEGIN_RING(10);
448 OUT_RING(CP_PACKET3(R200_3D_DRAW_IMMD_2, 8));
449 OUT_RING(R300_PRIM_TYPE_POINT | R300_PRIM_WALK_RING |
450 (1 << R300_PRIM_NUM_VERTICES_SHIFT));
451 OUT_RING_DRM_BUFFER(cmdbuf->buffer, 8);
452 ADVANCE_RING();
453
454 BEGIN_RING(4);
455 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
456 OUT_RING(R300_RB3D_DC_FLUSH);
457 OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0));
458 OUT_RING(RADEON_WAIT_3D_IDLECLEAN);
459 ADVANCE_RING();
460 /* set flush flag */
461 dev_priv->track_flush |= RADEON_FLUSH_EMITED;
462
463 return 0;
464}
465
466static __inline__ int r300_emit_3d_load_vbpntr(drm_radeon_private_t *dev_priv,
467 drm_radeon_kcmd_buffer_t *cmdbuf,
468 u32 header)
469{
470 int count, i, k;
471#define MAX_ARRAY_PACKET 64
472 u32 *data;
473 u32 narrays;
474 RING_LOCALS;
475
476 count = (header & RADEON_CP_PACKET_COUNT_MASK) >> 16;
477
478 if ((count + 1) > MAX_ARRAY_PACKET) {
479 DRM_ERROR("Too large payload in 3D_LOAD_VBPNTR (count=%d)\n",
480 count);
481 return -EINVAL;
482 }
483 /* carefully check packet contents */
484
485 /* We have already read the header so advance the buffer. */
486 drm_buffer_advance(cmdbuf->buffer, 4);
487
488 narrays = *(u32 *)drm_buffer_pointer_to_dword(cmdbuf->buffer, 0);
489 k = 0;
490 i = 1;
491 while ((k < narrays) && (i < (count + 1))) {
492 i++; /* skip attribute field */
493 data = drm_buffer_pointer_to_dword(cmdbuf->buffer, i);
494 if (!radeon_check_offset(dev_priv, *data)) {
495 DRM_ERROR
496 ("Offset failed range check (k=%d i=%d) while processing 3D_LOAD_VBPNTR packet.\n",
497 k, i);
498 return -EINVAL;
499 }
500 k++;
501 i++;
502 if (k == narrays)
503 break;
504 /* have one more to process, they come in pairs */
505 data = drm_buffer_pointer_to_dword(cmdbuf->buffer, i);
506 if (!radeon_check_offset(dev_priv, *data)) {
507 DRM_ERROR
508 ("Offset failed range check (k=%d i=%d) while processing 3D_LOAD_VBPNTR packet.\n",
509 k, i);
510 return -EINVAL;
511 }
512 k++;
513 i++;
514 }
515 /* do the counts match what we expect ? */
516 if ((k != narrays) || (i != (count + 1))) {
517 DRM_ERROR
518 ("Malformed 3D_LOAD_VBPNTR packet (k=%d i=%d narrays=%d count+1=%d).\n",
519 k, i, narrays, count + 1);
520 return -EINVAL;
521 }
522
523 /* all clear, output packet */
524
525 BEGIN_RING(count + 2);
526 OUT_RING(header);
527 OUT_RING_DRM_BUFFER(cmdbuf->buffer, count + 1);
528 ADVANCE_RING();
529
530 return 0;
531}
532
533static __inline__ int r300_emit_bitblt_multi(drm_radeon_private_t *dev_priv,
534 drm_radeon_kcmd_buffer_t *cmdbuf)
535{
536 u32 *cmd = drm_buffer_pointer_to_dword(cmdbuf->buffer, 0);
537 int count, ret;
538 RING_LOCALS;
539
540
541 count = (*cmd & RADEON_CP_PACKET_COUNT_MASK) >> 16;
542
543 if (*cmd & 0x8000) {
544 u32 offset;
545 u32 *cmd1 = drm_buffer_pointer_to_dword(cmdbuf->buffer, 1);
546 if (*cmd1 & (RADEON_GMC_SRC_PITCH_OFFSET_CNTL
547 | RADEON_GMC_DST_PITCH_OFFSET_CNTL)) {
548
549 u32 *cmd2 = drm_buffer_pointer_to_dword(cmdbuf->buffer, 2);
550 offset = *cmd2 << 10;
551 ret = !radeon_check_offset(dev_priv, offset);
552 if (ret) {
553 DRM_ERROR("Invalid bitblt first offset is %08X\n", offset);
554 return -EINVAL;
555 }
556 }
557
558 if ((*cmd1 & RADEON_GMC_SRC_PITCH_OFFSET_CNTL) &&
559 (*cmd1 & RADEON_GMC_DST_PITCH_OFFSET_CNTL)) {
560 u32 *cmd3 = drm_buffer_pointer_to_dword(cmdbuf->buffer, 3);
561 offset = *cmd3 << 10;
562 ret = !radeon_check_offset(dev_priv, offset);
563 if (ret) {
564 DRM_ERROR("Invalid bitblt second offset is %08X\n", offset);
565 return -EINVAL;
566 }
567
568 }
569 }
570
571 BEGIN_RING(count+2);
572 OUT_RING_DRM_BUFFER(cmdbuf->buffer, count + 2);
573 ADVANCE_RING();
574
575 return 0;
576}
577
578static __inline__ int r300_emit_draw_indx_2(drm_radeon_private_t *dev_priv,
579 drm_radeon_kcmd_buffer_t *cmdbuf)
580{
581 u32 *cmd = drm_buffer_pointer_to_dword(cmdbuf->buffer, 0);
582 u32 *cmd1 = drm_buffer_pointer_to_dword(cmdbuf->buffer, 1);
583 int count;
584 int expected_count;
585 RING_LOCALS;
586
587 count = (*cmd & RADEON_CP_PACKET_COUNT_MASK) >> 16;
588
589 expected_count = *cmd1 >> 16;
590 if (!(*cmd1 & R300_VAP_VF_CNTL__INDEX_SIZE_32bit))
591 expected_count = (expected_count+1)/2;
592
593 if (count && count != expected_count) {
594 DRM_ERROR("3D_DRAW_INDX_2: packet size %i, expected %i\n",
595 count, expected_count);
596 return -EINVAL;
597 }
598
599 BEGIN_RING(count+2);
600 OUT_RING_DRM_BUFFER(cmdbuf->buffer, count + 2);
601 ADVANCE_RING();
602
603 if (!count) {
604 drm_r300_cmd_header_t stack_header, *header;
605 u32 *cmd1, *cmd2, *cmd3;
606
607 if (drm_buffer_unprocessed(cmdbuf->buffer)
608 < 4*4 + sizeof(stack_header)) {
609 DRM_ERROR("3D_DRAW_INDX_2: expect subsequent INDX_BUFFER, but stream is too short.\n");
610 return -EINVAL;
611 }
612
613 header = drm_buffer_read_object(cmdbuf->buffer,
614 sizeof(stack_header), &stack_header);
615
616 cmd = drm_buffer_pointer_to_dword(cmdbuf->buffer, 0);
617 cmd1 = drm_buffer_pointer_to_dword(cmdbuf->buffer, 1);
618 cmd2 = drm_buffer_pointer_to_dword(cmdbuf->buffer, 2);
619 cmd3 = drm_buffer_pointer_to_dword(cmdbuf->buffer, 3);
620
621 if (header->header.cmd_type != R300_CMD_PACKET3 ||
622 header->packet3.packet != R300_CMD_PACKET3_RAW ||
623 *cmd != CP_PACKET3(RADEON_CP_INDX_BUFFER, 2)) {
624 DRM_ERROR("3D_DRAW_INDX_2: expect subsequent INDX_BUFFER.\n");
625 return -EINVAL;
626 }
627
628 if ((*cmd1 & 0x8000ffff) != 0x80000810) {
629 DRM_ERROR("Invalid indx_buffer reg address %08X\n",
630 *cmd1);
631 return -EINVAL;
632 }
633 if (!radeon_check_offset(dev_priv, *cmd2)) {
634 DRM_ERROR("Invalid indx_buffer offset is %08X\n",
635 *cmd2);
636 return -EINVAL;
637 }
638 if (*cmd3 != expected_count) {
639 DRM_ERROR("INDX_BUFFER: buffer size %i, expected %i\n",
640 *cmd3, expected_count);
641 return -EINVAL;
642 }
643
644 BEGIN_RING(4);
645 OUT_RING_DRM_BUFFER(cmdbuf->buffer, 4);
646 ADVANCE_RING();
647 }
648
649 return 0;
650}
651
652static __inline__ int r300_emit_raw_packet3(drm_radeon_private_t *dev_priv,
653 drm_radeon_kcmd_buffer_t *cmdbuf)
654{
655 u32 *header;
656 int count;
657 RING_LOCALS;
658
659 if (4 > drm_buffer_unprocessed(cmdbuf->buffer))
660 return -EINVAL;
661
662 /* Fixme !! This simply emits a packet without much checking.
663 We need to be smarter. */
664
665 /* obtain first word - actual packet3 header */
666 header = drm_buffer_pointer_to_dword(cmdbuf->buffer, 0);
667
668 /* Is it packet 3 ? */
669 if ((*header >> 30) != 0x3) {
670 DRM_ERROR("Not a packet3 header (0x%08x)\n", *header);
671 return -EINVAL;
672 }
673
674 count = (*header >> 16) & 0x3fff;
675
676 /* Check again now that we know how much data to expect */
677 if ((count + 2) * 4 > drm_buffer_unprocessed(cmdbuf->buffer)) {
678 DRM_ERROR
679 ("Expected packet3 of length %d but have only %d bytes left\n",
680 (count + 2) * 4, drm_buffer_unprocessed(cmdbuf->buffer));
681 return -EINVAL;
682 }
683
684 /* Is it a packet type we know about ? */
685 switch (*header & 0xff00) {
686 case RADEON_3D_LOAD_VBPNTR: /* load vertex array pointers */
687 return r300_emit_3d_load_vbpntr(dev_priv, cmdbuf, *header);
688
689 case RADEON_CNTL_BITBLT_MULTI:
690 return r300_emit_bitblt_multi(dev_priv, cmdbuf);
691
692 case RADEON_CP_INDX_BUFFER:
693 DRM_ERROR("packet3 INDX_BUFFER without preceding 3D_DRAW_INDX_2 is illegal.\n");
694 return -EINVAL;
695 case RADEON_CP_3D_DRAW_IMMD_2:
696 /* triggers drawing using in-packet vertex data */
697 case RADEON_CP_3D_DRAW_VBUF_2:
698 /* triggers drawing of vertex buffers setup elsewhere */
699 dev_priv->track_flush &= ~(RADEON_FLUSH_EMITED |
700 RADEON_PURGE_EMITED);
701 break;
702 case RADEON_CP_3D_DRAW_INDX_2:
703 /* triggers drawing using indices to vertex buffer */
704 /* whenever we send vertex we clear flush & purge */
705 dev_priv->track_flush &= ~(RADEON_FLUSH_EMITED |
706 RADEON_PURGE_EMITED);
707 return r300_emit_draw_indx_2(dev_priv, cmdbuf);
708 case RADEON_WAIT_FOR_IDLE:
709 case RADEON_CP_NOP:
710 /* these packets are safe */
711 break;
712 default:
713 DRM_ERROR("Unknown packet3 header (0x%08x)\n", *header);
714 return -EINVAL;
715 }
716
717 BEGIN_RING(count + 2);
718 OUT_RING_DRM_BUFFER(cmdbuf->buffer, count + 2);
719 ADVANCE_RING();
720
721 return 0;
722}
723
724/**
725 * Emit a rendering packet3 from userspace.
726 * Called by r300_do_cp_cmdbuf.
727 */
728static __inline__ int r300_emit_packet3(drm_radeon_private_t *dev_priv,
729 drm_radeon_kcmd_buffer_t *cmdbuf,
730 drm_r300_cmd_header_t header)
731{
732 int n;
733 int ret;
734 int orig_iter = cmdbuf->buffer->iterator;
735
736 /* This is a do-while-loop so that we run the interior at least once,
737 * even if cmdbuf->nbox is 0. Compare r300_emit_cliprects for rationale.
738 */
739 n = 0;
740 do {
741 if (cmdbuf->nbox > R300_SIMULTANEOUS_CLIPRECTS) {
742 ret = r300_emit_cliprects(dev_priv, cmdbuf, n);
743 if (ret)
744 return ret;
745
746 cmdbuf->buffer->iterator = orig_iter;
747 }
748
749 switch (header.packet3.packet) {
750 case R300_CMD_PACKET3_CLEAR:
751 DRM_DEBUG("R300_CMD_PACKET3_CLEAR\n");
752 ret = r300_emit_clear(dev_priv, cmdbuf);
753 if (ret) {
754 DRM_ERROR("r300_emit_clear failed\n");
755 return ret;
756 }
757 break;
758
759 case R300_CMD_PACKET3_RAW:
760 DRM_DEBUG("R300_CMD_PACKET3_RAW\n");
761 ret = r300_emit_raw_packet3(dev_priv, cmdbuf);
762 if (ret) {
763 DRM_ERROR("r300_emit_raw_packet3 failed\n");
764 return ret;
765 }
766 break;
767
768 default:
769 DRM_ERROR("bad packet3 type %i at byte %d\n",
770 header.packet3.packet,
771 cmdbuf->buffer->iterator - (int)sizeof(header));
772 return -EINVAL;
773 }
774
775 n += R300_SIMULTANEOUS_CLIPRECTS;
776 } while (n < cmdbuf->nbox);
777
778 return 0;
779}
780
781/* Some of the R300 chips seem to be extremely touchy about the two registers
782 * that are configured in r300_pacify.
783 * Among the worst offenders seems to be the R300 ND (0x4E44): When userspace
784 * sends a command buffer that contains only state setting commands and a
785 * vertex program/parameter upload sequence, this will eventually lead to a
786 * lockup, unless the sequence is bracketed by calls to r300_pacify.
787 * So we should take great care to *always* call r300_pacify before
788 * *anything* 3D related, and again afterwards. This is what the
789 * call bracket in r300_do_cp_cmdbuf is for.
790 */
791
792/**
793 * Emit the sequence to pacify R300.
794 */
795static void r300_pacify(drm_radeon_private_t *dev_priv)
796{
797 uint32_t cache_z, cache_3d, cache_2d;
798 RING_LOCALS;
799
800 cache_z = R300_ZC_FLUSH;
801 cache_2d = R300_RB2D_DC_FLUSH;
802 cache_3d = R300_RB3D_DC_FLUSH;
803 if (!(dev_priv->track_flush & RADEON_PURGE_EMITED)) {
804 /* we can purge, primitive where draw since last purge */
805 cache_z |= R300_ZC_FREE;
806 cache_2d |= R300_RB2D_DC_FREE;
807 cache_3d |= R300_RB3D_DC_FREE;
808 }
809
810 /* flush & purge zbuffer */
811 BEGIN_RING(2);
812 OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0));
813 OUT_RING(cache_z);
814 ADVANCE_RING();
815 /* flush & purge 3d */
816 BEGIN_RING(2);
817 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
818 OUT_RING(cache_3d);
819 ADVANCE_RING();
820 /* flush & purge texture */
821 BEGIN_RING(2);
822 OUT_RING(CP_PACKET0(R300_TX_INVALTAGS, 0));
823 OUT_RING(0);
824 ADVANCE_RING();
825 /* FIXME: is this one really needed ? */
826 BEGIN_RING(2);
827 OUT_RING(CP_PACKET0(R300_RB3D_AARESOLVE_CTL, 0));
828 OUT_RING(0);
829 ADVANCE_RING();
830 BEGIN_RING(2);
831 OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0));
832 OUT_RING(RADEON_WAIT_3D_IDLECLEAN);
833 ADVANCE_RING();
834 /* flush & purge 2d through E2 as RB2D will trigger lockup */
835 BEGIN_RING(4);
836 OUT_RING(CP_PACKET0(R300_DSTCACHE_CTLSTAT, 0));
837 OUT_RING(cache_2d);
838 OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0));
839 OUT_RING(RADEON_WAIT_2D_IDLECLEAN |
840 RADEON_WAIT_HOST_IDLECLEAN);
841 ADVANCE_RING();
842 /* set flush & purge flags */
843 dev_priv->track_flush |= RADEON_FLUSH_EMITED | RADEON_PURGE_EMITED;
844}
845
846/**
847 * Called by r300_do_cp_cmdbuf to update the internal buffer age and state.
848 * The actual age emit is done by r300_do_cp_cmdbuf, which is why you must
849 * be careful about how this function is called.
850 */
851static void r300_discard_buffer(struct drm_device *dev, struct drm_master *master, struct drm_buf *buf)
852{
853 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
854 struct drm_radeon_master_private *master_priv = master->driver_priv;
855
856 buf_priv->age = ++master_priv->sarea_priv->last_dispatch;
857 buf->pending = 1;
858 buf->used = 0;
859}
860
861static void r300_cmd_wait(drm_radeon_private_t * dev_priv,
862 drm_r300_cmd_header_t header)
863{
864 u32 wait_until;
865 RING_LOCALS;
866
867 if (!header.wait.flags)
868 return;
869
870 wait_until = 0;
871
872 switch(header.wait.flags) {
873 case R300_WAIT_2D:
874 wait_until = RADEON_WAIT_2D_IDLE;
875 break;
876 case R300_WAIT_3D:
877 wait_until = RADEON_WAIT_3D_IDLE;
878 break;
879 case R300_NEW_WAIT_2D_3D:
880 wait_until = RADEON_WAIT_2D_IDLE|RADEON_WAIT_3D_IDLE;
881 break;
882 case R300_NEW_WAIT_2D_2D_CLEAN:
883 wait_until = RADEON_WAIT_2D_IDLE|RADEON_WAIT_2D_IDLECLEAN;
884 break;
885 case R300_NEW_WAIT_3D_3D_CLEAN:
886 wait_until = RADEON_WAIT_3D_IDLE|RADEON_WAIT_3D_IDLECLEAN;
887 break;
888 case R300_NEW_WAIT_2D_2D_CLEAN_3D_3D_CLEAN:
889 wait_until = RADEON_WAIT_2D_IDLE|RADEON_WAIT_2D_IDLECLEAN;
890 wait_until |= RADEON_WAIT_3D_IDLE|RADEON_WAIT_3D_IDLECLEAN;
891 break;
892 default:
893 return;
894 }
895
896 BEGIN_RING(2);
897 OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0));
898 OUT_RING(wait_until);
899 ADVANCE_RING();
900}
901
902static int r300_scratch(drm_radeon_private_t *dev_priv,
903 drm_radeon_kcmd_buffer_t *cmdbuf,
904 drm_r300_cmd_header_t header)
905{
906 u32 *ref_age_base;
907 u32 i, *buf_idx, h_pending;
908 u64 *ptr_addr;
909 u64 stack_ptr_addr;
910 RING_LOCALS;
911
912 if (drm_buffer_unprocessed(cmdbuf->buffer) <
913 (sizeof(u64) + header.scratch.n_bufs * sizeof(*buf_idx))) {
914 return -EINVAL;
915 }
916
917 if (header.scratch.reg >= 5) {
918 return -EINVAL;
919 }
920
921 dev_priv->scratch_ages[header.scratch.reg]++;
922
923 ptr_addr = drm_buffer_read_object(cmdbuf->buffer,
924 sizeof(stack_ptr_addr), &stack_ptr_addr);
925 ref_age_base = (u32 *)(unsigned long)get_unaligned(ptr_addr);
926
927 for (i=0; i < header.scratch.n_bufs; i++) {
928 buf_idx = drm_buffer_pointer_to_dword(cmdbuf->buffer, 0);
929 *buf_idx *= 2; /* 8 bytes per buf */
930
931 if (copy_to_user(ref_age_base + *buf_idx,
932 &dev_priv->scratch_ages[header.scratch.reg],
933 sizeof(u32)))
934 return -EINVAL;
935
936 if (copy_from_user(&h_pending,
937 ref_age_base + *buf_idx + 1,
938 sizeof(u32)))
939 return -EINVAL;
940
941 if (h_pending == 0)
942 return -EINVAL;
943
944 h_pending--;
945
946 if (copy_to_user(ref_age_base + *buf_idx + 1,
947 &h_pending,
948 sizeof(u32)))
949 return -EINVAL;
950
951 drm_buffer_advance(cmdbuf->buffer, sizeof(*buf_idx));
952 }
953
954 BEGIN_RING(2);
955 OUT_RING( CP_PACKET0( RADEON_SCRATCH_REG0 + header.scratch.reg * 4, 0 ) );
956 OUT_RING( dev_priv->scratch_ages[header.scratch.reg] );
957 ADVANCE_RING();
958
959 return 0;
960}
961
962/**
963 * Uploads user-supplied vertex program instructions or parameters onto
964 * the graphics card.
965 * Called by r300_do_cp_cmdbuf.
966 */
967static inline int r300_emit_r500fp(drm_radeon_private_t *dev_priv,
968 drm_radeon_kcmd_buffer_t *cmdbuf,
969 drm_r300_cmd_header_t header)
970{
971 int sz;
972 int addr;
973 int type;
974 int isclamp;
975 int stride;
976 RING_LOCALS;
977
978 sz = header.r500fp.count;
979 /* address is 9 bits 0 - 8, bit 1 of flags is part of address */
980 addr = ((header.r500fp.adrhi_flags & 1) << 8) | header.r500fp.adrlo;
981
982 type = !!(header.r500fp.adrhi_flags & R500FP_CONSTANT_TYPE);
983 isclamp = !!(header.r500fp.adrhi_flags & R500FP_CONSTANT_CLAMP);
984
985 addr |= (type << 16);
986 addr |= (isclamp << 17);
987
988 stride = type ? 4 : 6;
989
990 DRM_DEBUG("r500fp %d %d type: %d\n", sz, addr, type);
991 if (!sz)
992 return 0;
993 if (sz * stride * 4 > drm_buffer_unprocessed(cmdbuf->buffer))
994 return -EINVAL;
995
996 BEGIN_RING(3 + sz * stride);
997 OUT_RING_REG(R500_GA_US_VECTOR_INDEX, addr);
998 OUT_RING(CP_PACKET0_TABLE(R500_GA_US_VECTOR_DATA, sz * stride - 1));
999 OUT_RING_DRM_BUFFER(cmdbuf->buffer, sz * stride);
1000
1001 ADVANCE_RING();
1002
1003 return 0;
1004}
1005
1006
1007/**
1008 * Parses and validates a user-supplied command buffer and emits appropriate
1009 * commands on the DMA ring buffer.
1010 * Called by the ioctl handler function radeon_cp_cmdbuf.
1011 */
1012int r300_do_cp_cmdbuf(struct drm_device *dev,
1013 struct drm_file *file_priv,
1014 drm_radeon_kcmd_buffer_t *cmdbuf)
1015{
1016 drm_radeon_private_t *dev_priv = dev->dev_private;
1017 struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv;
1018 struct drm_device_dma *dma = dev->dma;
1019 struct drm_buf *buf = NULL;
1020 int emit_dispatch_age = 0;
1021 int ret = 0;
1022
1023 DRM_DEBUG("\n");
1024
1025 /* pacify */
1026 r300_pacify(dev_priv);
1027
1028 if (cmdbuf->nbox <= R300_SIMULTANEOUS_CLIPRECTS) {
1029 ret = r300_emit_cliprects(dev_priv, cmdbuf, 0);
1030 if (ret)
1031 goto cleanup;
1032 }
1033
1034 while (drm_buffer_unprocessed(cmdbuf->buffer)
1035 >= sizeof(drm_r300_cmd_header_t)) {
1036 int idx;
1037 drm_r300_cmd_header_t *header, stack_header;
1038
1039 header = drm_buffer_read_object(cmdbuf->buffer,
1040 sizeof(stack_header), &stack_header);
1041
1042 switch (header->header.cmd_type) {
1043 case R300_CMD_PACKET0:
1044 DRM_DEBUG("R300_CMD_PACKET0\n");
1045 ret = r300_emit_packet0(dev_priv, cmdbuf, *header);
1046 if (ret) {
1047 DRM_ERROR("r300_emit_packet0 failed\n");
1048 goto cleanup;
1049 }
1050 break;
1051
1052 case R300_CMD_VPU:
1053 DRM_DEBUG("R300_CMD_VPU\n");
1054 ret = r300_emit_vpu(dev_priv, cmdbuf, *header);
1055 if (ret) {
1056 DRM_ERROR("r300_emit_vpu failed\n");
1057 goto cleanup;
1058 }
1059 break;
1060
1061 case R300_CMD_PACKET3:
1062 DRM_DEBUG("R300_CMD_PACKET3\n");
1063 ret = r300_emit_packet3(dev_priv, cmdbuf, *header);
1064 if (ret) {
1065 DRM_ERROR("r300_emit_packet3 failed\n");
1066 goto cleanup;
1067 }
1068 break;
1069
1070 case R300_CMD_END3D:
1071 DRM_DEBUG("R300_CMD_END3D\n");
1072 /* TODO:
1073 Ideally userspace driver should not need to issue this call,
1074 i.e. the drm driver should issue it automatically and prevent
1075 lockups.
1076
1077 In practice, we do not understand why this call is needed and what
1078 it does (except for some vague guesses that it has to do with cache
1079 coherence) and so the user space driver does it.
1080
1081 Once we are sure which uses prevent lockups the code could be moved
1082 into the kernel and the userspace driver will not
1083 need to use this command.
1084
1085 Note that issuing this command does not hurt anything
1086 except, possibly, performance */
1087 r300_pacify(dev_priv);
1088 break;
1089
1090 case R300_CMD_CP_DELAY:
1091 /* simple enough, we can do it here */
1092 DRM_DEBUG("R300_CMD_CP_DELAY\n");
1093 {
1094 int i;
1095 RING_LOCALS;
1096
1097 BEGIN_RING(header->delay.count);
1098 for (i = 0; i < header->delay.count; i++)
1099 OUT_RING(RADEON_CP_PACKET2);
1100 ADVANCE_RING();
1101 }
1102 break;
1103
1104 case R300_CMD_DMA_DISCARD:
1105 DRM_DEBUG("RADEON_CMD_DMA_DISCARD\n");
1106 idx = header->dma.buf_idx;
1107 if (idx < 0 || idx >= dma->buf_count) {
1108 DRM_ERROR("buffer index %d (of %d max)\n",
1109 idx, dma->buf_count - 1);
1110 ret = -EINVAL;
1111 goto cleanup;
1112 }
1113
1114 buf = dma->buflist[idx];
1115 if (buf->file_priv != file_priv || buf->pending) {
1116 DRM_ERROR("bad buffer %p %p %d\n",
1117 buf->file_priv, file_priv,
1118 buf->pending);
1119 ret = -EINVAL;
1120 goto cleanup;
1121 }
1122
1123 emit_dispatch_age = 1;
1124 r300_discard_buffer(dev, file_priv->master, buf);
1125 break;
1126
1127 case R300_CMD_WAIT:
1128 DRM_DEBUG("R300_CMD_WAIT\n");
1129 r300_cmd_wait(dev_priv, *header);
1130 break;
1131
1132 case R300_CMD_SCRATCH:
1133 DRM_DEBUG("R300_CMD_SCRATCH\n");
1134 ret = r300_scratch(dev_priv, cmdbuf, *header);
1135 if (ret) {
1136 DRM_ERROR("r300_scratch failed\n");
1137 goto cleanup;
1138 }
1139 break;
1140
1141 case R300_CMD_R500FP:
1142 if ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV515) {
1143 DRM_ERROR("Calling r500 command on r300 card\n");
1144 ret = -EINVAL;
1145 goto cleanup;
1146 }
1147 DRM_DEBUG("R300_CMD_R500FP\n");
1148 ret = r300_emit_r500fp(dev_priv, cmdbuf, *header);
1149 if (ret) {
1150 DRM_ERROR("r300_emit_r500fp failed\n");
1151 goto cleanup;
1152 }
1153 break;
1154 default:
1155 DRM_ERROR("bad cmd_type %i at byte %d\n",
1156 header->header.cmd_type,
1157 cmdbuf->buffer->iterator - (int)sizeof(*header));
1158 ret = -EINVAL;
1159 goto cleanup;
1160 }
1161 }
1162
1163 DRM_DEBUG("END\n");
1164
1165 cleanup:
1166 r300_pacify(dev_priv);
1167
1168 /* We emit the vertex buffer age here, outside the pacifier "brackets"
1169 * for two reasons:
1170 * (1) This may coalesce multiple age emissions into a single one and
1171 * (2) more importantly, some chips lock up hard when scratch registers
1172 * are written inside the pacifier bracket.
1173 */
1174 if (emit_dispatch_age) {
1175 RING_LOCALS;
1176
1177 /* Emit the vertex buffer age */
1178 BEGIN_RING(2);
1179 RADEON_DISPATCH_AGE(master_priv->sarea_priv->last_dispatch);
1180 ADVANCE_RING();
1181 }
1182
1183 COMMIT_RING();
1184
1185 return ret;
1186}
diff --git a/drivers/gpu/drm/radeon/r600_blit.c b/drivers/gpu/drm/radeon/r600_blit.c
deleted file mode 100644
index daf7572be976..000000000000
--- a/drivers/gpu/drm/radeon/r600_blit.c
+++ /dev/null
@@ -1,874 +0,0 @@
1/*
2 * Copyright 2009 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Alex Deucher <alexander.deucher@amd.com>
25 *
26 * ------------------------ This file is DEPRECATED! -------------------------
27 */
28#include <drm/drmP.h>
29#include <drm/radeon_drm.h>
30#include "radeon_drv.h"
31
32#include "r600_blit_shaders.h"
33
34/* 23 bits of float fractional data */
35#define I2F_FRAC_BITS 23
36#define I2F_MASK ((1 << I2F_FRAC_BITS) - 1)
37
38/*
39 * Converts unsigned integer into 32-bit IEEE floating point representation.
40 * Will be exact from 0 to 2^24. Above that, we round towards zero
41 * as the fractional bits will not fit in a float. (It would be better to
42 * round towards even as the fpu does, but that is slower.)
43 */
44static __pure uint32_t int2float(uint32_t x)
45{
46 uint32_t msb, exponent, fraction;
47
48 /* Zero is special */
49 if (!x) return 0;
50
51 /* Get location of the most significant bit */
52 msb = __fls(x);
53
54 /*
55 * Use a rotate instead of a shift because that works both leftwards
56 * and rightwards due to the mod(32) behaviour. This means we don't
57 * need to check to see if we are above 2^24 or not.
58 */
59 fraction = ror32(x, (msb - I2F_FRAC_BITS) & 0x1f) & I2F_MASK;
60 exponent = (127 + msb) << I2F_FRAC_BITS;
61
62 return fraction + exponent;
63}
64
65#define DI_PT_RECTLIST 0x11
66#define DI_INDEX_SIZE_16_BIT 0x0
67#define DI_SRC_SEL_AUTO_INDEX 0x2
68
69#define FMT_8 0x1
70#define FMT_5_6_5 0x8
71#define FMT_8_8_8_8 0x1a
72#define COLOR_8 0x1
73#define COLOR_5_6_5 0x8
74#define COLOR_8_8_8_8 0x1a
75
76static void
77set_render_target(drm_radeon_private_t *dev_priv, int format, int w, int h, u64 gpu_addr)
78{
79 u32 cb_color_info;
80 int pitch, slice;
81 RING_LOCALS;
82 DRM_DEBUG("\n");
83
84 h = ALIGN(h, 8);
85 if (h < 8)
86 h = 8;
87
88 cb_color_info = ((format << 2) | (1 << 27));
89 pitch = (w / 8) - 1;
90 slice = ((w * h) / 64) - 1;
91
92 if (((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_R600) &&
93 ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV770)) {
94 BEGIN_RING(21 + 2);
95 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
96 OUT_RING((R600_CB_COLOR0_BASE - R600_SET_CONTEXT_REG_OFFSET) >> 2);
97 OUT_RING(gpu_addr >> 8);
98 OUT_RING(CP_PACKET3(R600_IT_SURFACE_BASE_UPDATE, 0));
99 OUT_RING(2 << 0);
100 } else {
101 BEGIN_RING(21);
102 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
103 OUT_RING((R600_CB_COLOR0_BASE - R600_SET_CONTEXT_REG_OFFSET) >> 2);
104 OUT_RING(gpu_addr >> 8);
105 }
106
107 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
108 OUT_RING((R600_CB_COLOR0_SIZE - R600_SET_CONTEXT_REG_OFFSET) >> 2);
109 OUT_RING((pitch << 0) | (slice << 10));
110
111 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
112 OUT_RING((R600_CB_COLOR0_VIEW - R600_SET_CONTEXT_REG_OFFSET) >> 2);
113 OUT_RING(0);
114
115 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
116 OUT_RING((R600_CB_COLOR0_INFO - R600_SET_CONTEXT_REG_OFFSET) >> 2);
117 OUT_RING(cb_color_info);
118
119 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
120 OUT_RING((R600_CB_COLOR0_TILE - R600_SET_CONTEXT_REG_OFFSET) >> 2);
121 OUT_RING(0);
122
123 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
124 OUT_RING((R600_CB_COLOR0_FRAG - R600_SET_CONTEXT_REG_OFFSET) >> 2);
125 OUT_RING(0);
126
127 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
128 OUT_RING((R600_CB_COLOR0_MASK - R600_SET_CONTEXT_REG_OFFSET) >> 2);
129 OUT_RING(0);
130
131 ADVANCE_RING();
132}
133
134static void
135cp_set_surface_sync(drm_radeon_private_t *dev_priv,
136 u32 sync_type, u32 size, u64 mc_addr)
137{
138 u32 cp_coher_size;
139 RING_LOCALS;
140 DRM_DEBUG("\n");
141
142 if (size == 0xffffffff)
143 cp_coher_size = 0xffffffff;
144 else
145 cp_coher_size = ((size + 255) >> 8);
146
147 BEGIN_RING(5);
148 OUT_RING(CP_PACKET3(R600_IT_SURFACE_SYNC, 3));
149 OUT_RING(sync_type);
150 OUT_RING(cp_coher_size);
151 OUT_RING((mc_addr >> 8));
152 OUT_RING(10); /* poll interval */
153 ADVANCE_RING();
154}
155
156static void
157set_shaders(struct drm_device *dev)
158{
159 drm_radeon_private_t *dev_priv = dev->dev_private;
160 u64 gpu_addr;
161 int i;
162 u32 *vs, *ps;
163 uint32_t sq_pgm_resources;
164 RING_LOCALS;
165 DRM_DEBUG("\n");
166
167 /* load shaders */
168 vs = (u32 *) ((char *)dev->agp_buffer_map->handle + dev_priv->blit_vb->offset);
169 ps = (u32 *) ((char *)dev->agp_buffer_map->handle + dev_priv->blit_vb->offset + 256);
170
171 for (i = 0; i < r6xx_vs_size; i++)
172 vs[i] = cpu_to_le32(r6xx_vs[i]);
173 for (i = 0; i < r6xx_ps_size; i++)
174 ps[i] = cpu_to_le32(r6xx_ps[i]);
175
176 dev_priv->blit_vb->used = 512;
177
178 gpu_addr = dev_priv->gart_buffers_offset + dev_priv->blit_vb->offset;
179
180 /* setup shader regs */
181 sq_pgm_resources = (1 << 0);
182
183 BEGIN_RING(9 + 12);
184 /* VS */
185 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
186 OUT_RING((R600_SQ_PGM_START_VS - R600_SET_CONTEXT_REG_OFFSET) >> 2);
187 OUT_RING(gpu_addr >> 8);
188
189 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
190 OUT_RING((R600_SQ_PGM_RESOURCES_VS - R600_SET_CONTEXT_REG_OFFSET) >> 2);
191 OUT_RING(sq_pgm_resources);
192
193 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
194 OUT_RING((R600_SQ_PGM_CF_OFFSET_VS - R600_SET_CONTEXT_REG_OFFSET) >> 2);
195 OUT_RING(0);
196
197 /* PS */
198 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
199 OUT_RING((R600_SQ_PGM_START_PS - R600_SET_CONTEXT_REG_OFFSET) >> 2);
200 OUT_RING((gpu_addr + 256) >> 8);
201
202 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
203 OUT_RING((R600_SQ_PGM_RESOURCES_PS - R600_SET_CONTEXT_REG_OFFSET) >> 2);
204 OUT_RING(sq_pgm_resources | (1 << 28));
205
206 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
207 OUT_RING((R600_SQ_PGM_EXPORTS_PS - R600_SET_CONTEXT_REG_OFFSET) >> 2);
208 OUT_RING(2);
209
210 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 1));
211 OUT_RING((R600_SQ_PGM_CF_OFFSET_PS - R600_SET_CONTEXT_REG_OFFSET) >> 2);
212 OUT_RING(0);
213 ADVANCE_RING();
214
215 cp_set_surface_sync(dev_priv,
216 R600_SH_ACTION_ENA, 512, gpu_addr);
217}
218
219static void
220set_vtx_resource(drm_radeon_private_t *dev_priv, u64 gpu_addr)
221{
222 uint32_t sq_vtx_constant_word2;
223 RING_LOCALS;
224 DRM_DEBUG("\n");
225
226 sq_vtx_constant_word2 = (((gpu_addr >> 32) & 0xff) | (16 << 8));
227#ifdef __BIG_ENDIAN
228 sq_vtx_constant_word2 |= (2 << 30);
229#endif
230
231 BEGIN_RING(9);
232 OUT_RING(CP_PACKET3(R600_IT_SET_RESOURCE, 7));
233 OUT_RING(0x460);
234 OUT_RING(gpu_addr & 0xffffffff);
235 OUT_RING(48 - 1);
236 OUT_RING(sq_vtx_constant_word2);
237 OUT_RING(1 << 0);
238 OUT_RING(0);
239 OUT_RING(0);
240 OUT_RING(R600_SQ_TEX_VTX_VALID_BUFFER << 30);
241 ADVANCE_RING();
242
243 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
244 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
245 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
246 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880) ||
247 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710))
248 cp_set_surface_sync(dev_priv,
249 R600_TC_ACTION_ENA, 48, gpu_addr);
250 else
251 cp_set_surface_sync(dev_priv,
252 R600_VC_ACTION_ENA, 48, gpu_addr);
253}
254
255static void
256set_tex_resource(drm_radeon_private_t *dev_priv,
257 int format, int w, int h, int pitch, u64 gpu_addr)
258{
259 uint32_t sq_tex_resource_word0, sq_tex_resource_word1, sq_tex_resource_word4;
260 RING_LOCALS;
261 DRM_DEBUG("\n");
262
263 if (h < 1)
264 h = 1;
265
266 sq_tex_resource_word0 = (1 << 0);
267 sq_tex_resource_word0 |= ((((pitch >> 3) - 1) << 8) |
268 ((w - 1) << 19));
269
270 sq_tex_resource_word1 = (format << 26);
271 sq_tex_resource_word1 |= ((h - 1) << 0);
272
273 sq_tex_resource_word4 = ((1 << 14) |
274 (0 << 16) |
275 (1 << 19) |
276 (2 << 22) |
277 (3 << 25));
278
279 BEGIN_RING(9);
280 OUT_RING(CP_PACKET3(R600_IT_SET_RESOURCE, 7));
281 OUT_RING(0);
282 OUT_RING(sq_tex_resource_word0);
283 OUT_RING(sq_tex_resource_word1);
284 OUT_RING(gpu_addr >> 8);
285 OUT_RING(gpu_addr >> 8);
286 OUT_RING(sq_tex_resource_word4);
287 OUT_RING(0);
288 OUT_RING(R600_SQ_TEX_VTX_VALID_TEXTURE << 30);
289 ADVANCE_RING();
290
291}
292
293static void
294set_scissors(drm_radeon_private_t *dev_priv, int x1, int y1, int x2, int y2)
295{
296 RING_LOCALS;
297 DRM_DEBUG("\n");
298
299 BEGIN_RING(12);
300 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 2));
301 OUT_RING((R600_PA_SC_SCREEN_SCISSOR_TL - R600_SET_CONTEXT_REG_OFFSET) >> 2);
302 OUT_RING((x1 << 0) | (y1 << 16));
303 OUT_RING((x2 << 0) | (y2 << 16));
304
305 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 2));
306 OUT_RING((R600_PA_SC_GENERIC_SCISSOR_TL - R600_SET_CONTEXT_REG_OFFSET) >> 2);
307 OUT_RING((x1 << 0) | (y1 << 16) | (1 << 31));
308 OUT_RING((x2 << 0) | (y2 << 16));
309
310 OUT_RING(CP_PACKET3(R600_IT_SET_CONTEXT_REG, 2));
311 OUT_RING((R600_PA_SC_WINDOW_SCISSOR_TL - R600_SET_CONTEXT_REG_OFFSET) >> 2);
312 OUT_RING((x1 << 0) | (y1 << 16) | (1 << 31));
313 OUT_RING((x2 << 0) | (y2 << 16));
314 ADVANCE_RING();
315}
316
317static void
318draw_auto(drm_radeon_private_t *dev_priv)
319{
320 RING_LOCALS;
321 DRM_DEBUG("\n");
322
323 BEGIN_RING(10);
324 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1));
325 OUT_RING((R600_VGT_PRIMITIVE_TYPE - R600_SET_CONFIG_REG_OFFSET) >> 2);
326 OUT_RING(DI_PT_RECTLIST);
327
328 OUT_RING(CP_PACKET3(R600_IT_INDEX_TYPE, 0));
329#ifdef __BIG_ENDIAN
330 OUT_RING((2 << 2) | DI_INDEX_SIZE_16_BIT);
331#else
332 OUT_RING(DI_INDEX_SIZE_16_BIT);
333#endif
334
335 OUT_RING(CP_PACKET3(R600_IT_NUM_INSTANCES, 0));
336 OUT_RING(1);
337
338 OUT_RING(CP_PACKET3(R600_IT_DRAW_INDEX_AUTO, 1));
339 OUT_RING(3);
340 OUT_RING(DI_SRC_SEL_AUTO_INDEX);
341
342 ADVANCE_RING();
343 COMMIT_RING();
344}
345
346static void
347set_default_state(drm_radeon_private_t *dev_priv)
348{
349 int i;
350 u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2;
351 u32 sq_thread_resource_mgmt, sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2;
352 int num_ps_gprs, num_vs_gprs, num_temp_gprs, num_gs_gprs, num_es_gprs;
353 int num_ps_threads, num_vs_threads, num_gs_threads, num_es_threads;
354 int num_ps_stack_entries, num_vs_stack_entries, num_gs_stack_entries, num_es_stack_entries;
355 RING_LOCALS;
356
357 switch ((dev_priv->flags & RADEON_FAMILY_MASK)) {
358 case CHIP_R600:
359 num_ps_gprs = 192;
360 num_vs_gprs = 56;
361 num_temp_gprs = 4;
362 num_gs_gprs = 0;
363 num_es_gprs = 0;
364 num_ps_threads = 136;
365 num_vs_threads = 48;
366 num_gs_threads = 4;
367 num_es_threads = 4;
368 num_ps_stack_entries = 128;
369 num_vs_stack_entries = 128;
370 num_gs_stack_entries = 0;
371 num_es_stack_entries = 0;
372 break;
373 case CHIP_RV630:
374 case CHIP_RV635:
375 num_ps_gprs = 84;
376 num_vs_gprs = 36;
377 num_temp_gprs = 4;
378 num_gs_gprs = 0;
379 num_es_gprs = 0;
380 num_ps_threads = 144;
381 num_vs_threads = 40;
382 num_gs_threads = 4;
383 num_es_threads = 4;
384 num_ps_stack_entries = 40;
385 num_vs_stack_entries = 40;
386 num_gs_stack_entries = 32;
387 num_es_stack_entries = 16;
388 break;
389 case CHIP_RV610:
390 case CHIP_RV620:
391 case CHIP_RS780:
392 case CHIP_RS880:
393 default:
394 num_ps_gprs = 84;
395 num_vs_gprs = 36;
396 num_temp_gprs = 4;
397 num_gs_gprs = 0;
398 num_es_gprs = 0;
399 num_ps_threads = 136;
400 num_vs_threads = 48;
401 num_gs_threads = 4;
402 num_es_threads = 4;
403 num_ps_stack_entries = 40;
404 num_vs_stack_entries = 40;
405 num_gs_stack_entries = 32;
406 num_es_stack_entries = 16;
407 break;
408 case CHIP_RV670:
409 num_ps_gprs = 144;
410 num_vs_gprs = 40;
411 num_temp_gprs = 4;
412 num_gs_gprs = 0;
413 num_es_gprs = 0;
414 num_ps_threads = 136;
415 num_vs_threads = 48;
416 num_gs_threads = 4;
417 num_es_threads = 4;
418 num_ps_stack_entries = 40;
419 num_vs_stack_entries = 40;
420 num_gs_stack_entries = 32;
421 num_es_stack_entries = 16;
422 break;
423 case CHIP_RV770:
424 num_ps_gprs = 192;
425 num_vs_gprs = 56;
426 num_temp_gprs = 4;
427 num_gs_gprs = 0;
428 num_es_gprs = 0;
429 num_ps_threads = 188;
430 num_vs_threads = 60;
431 num_gs_threads = 0;
432 num_es_threads = 0;
433 num_ps_stack_entries = 256;
434 num_vs_stack_entries = 256;
435 num_gs_stack_entries = 0;
436 num_es_stack_entries = 0;
437 break;
438 case CHIP_RV730:
439 case CHIP_RV740:
440 num_ps_gprs = 84;
441 num_vs_gprs = 36;
442 num_temp_gprs = 4;
443 num_gs_gprs = 0;
444 num_es_gprs = 0;
445 num_ps_threads = 188;
446 num_vs_threads = 60;
447 num_gs_threads = 0;
448 num_es_threads = 0;
449 num_ps_stack_entries = 128;
450 num_vs_stack_entries = 128;
451 num_gs_stack_entries = 0;
452 num_es_stack_entries = 0;
453 break;
454 case CHIP_RV710:
455 num_ps_gprs = 192;
456 num_vs_gprs = 56;
457 num_temp_gprs = 4;
458 num_gs_gprs = 0;
459 num_es_gprs = 0;
460 num_ps_threads = 144;
461 num_vs_threads = 48;
462 num_gs_threads = 0;
463 num_es_threads = 0;
464 num_ps_stack_entries = 128;
465 num_vs_stack_entries = 128;
466 num_gs_stack_entries = 0;
467 num_es_stack_entries = 0;
468 break;
469 }
470
471 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
472 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
473 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
474 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880) ||
475 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710))
476 sq_config = 0;
477 else
478 sq_config = R600_VC_ENABLE;
479
480 sq_config |= (R600_DX9_CONSTS |
481 R600_ALU_INST_PREFER_VECTOR |
482 R600_PS_PRIO(0) |
483 R600_VS_PRIO(1) |
484 R600_GS_PRIO(2) |
485 R600_ES_PRIO(3));
486
487 sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(num_ps_gprs) |
488 R600_NUM_VS_GPRS(num_vs_gprs) |
489 R600_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs));
490 sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(num_gs_gprs) |
491 R600_NUM_ES_GPRS(num_es_gprs));
492 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(num_ps_threads) |
493 R600_NUM_VS_THREADS(num_vs_threads) |
494 R600_NUM_GS_THREADS(num_gs_threads) |
495 R600_NUM_ES_THREADS(num_es_threads));
496 sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(num_ps_stack_entries) |
497 R600_NUM_VS_STACK_ENTRIES(num_vs_stack_entries));
498 sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(num_gs_stack_entries) |
499 R600_NUM_ES_STACK_ENTRIES(num_es_stack_entries));
500
501 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) {
502 BEGIN_RING(r7xx_default_size + 10);
503 for (i = 0; i < r7xx_default_size; i++)
504 OUT_RING(r7xx_default_state[i]);
505 } else {
506 BEGIN_RING(r6xx_default_size + 10);
507 for (i = 0; i < r6xx_default_size; i++)
508 OUT_RING(r6xx_default_state[i]);
509 }
510 OUT_RING(CP_PACKET3(R600_IT_EVENT_WRITE, 0));
511 OUT_RING(R600_CACHE_FLUSH_AND_INV_EVENT);
512 /* SQ config */
513 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 6));
514 OUT_RING((R600_SQ_CONFIG - R600_SET_CONFIG_REG_OFFSET) >> 2);
515 OUT_RING(sq_config);
516 OUT_RING(sq_gpr_resource_mgmt_1);
517 OUT_RING(sq_gpr_resource_mgmt_2);
518 OUT_RING(sq_thread_resource_mgmt);
519 OUT_RING(sq_stack_resource_mgmt_1);
520 OUT_RING(sq_stack_resource_mgmt_2);
521 ADVANCE_RING();
522}
523
524static int r600_nomm_get_vb(struct drm_device *dev)
525{
526 drm_radeon_private_t *dev_priv = dev->dev_private;
527 dev_priv->blit_vb = radeon_freelist_get(dev);
528 if (!dev_priv->blit_vb) {
529 DRM_ERROR("Unable to allocate vertex buffer for blit\n");
530 return -EAGAIN;
531 }
532 return 0;
533}
534
535static void r600_nomm_put_vb(struct drm_device *dev)
536{
537 drm_radeon_private_t *dev_priv = dev->dev_private;
538
539 dev_priv->blit_vb->used = 0;
540 radeon_cp_discard_buffer(dev, dev_priv->blit_vb->file_priv->master, dev_priv->blit_vb);
541}
542
543static void *r600_nomm_get_vb_ptr(struct drm_device *dev)
544{
545 drm_radeon_private_t *dev_priv = dev->dev_private;
546 return (((char *)dev->agp_buffer_map->handle +
547 dev_priv->blit_vb->offset + dev_priv->blit_vb->used));
548}
549
550int
551r600_prepare_blit_copy(struct drm_device *dev, struct drm_file *file_priv)
552{
553 drm_radeon_private_t *dev_priv = dev->dev_private;
554 int ret;
555 DRM_DEBUG("\n");
556
557 ret = r600_nomm_get_vb(dev);
558 if (ret)
559 return ret;
560
561 dev_priv->blit_vb->file_priv = file_priv;
562
563 set_default_state(dev_priv);
564 set_shaders(dev);
565
566 return 0;
567}
568
569
570void
571r600_done_blit_copy(struct drm_device *dev)
572{
573 drm_radeon_private_t *dev_priv = dev->dev_private;
574 RING_LOCALS;
575 DRM_DEBUG("\n");
576
577 BEGIN_RING(5);
578 OUT_RING(CP_PACKET3(R600_IT_EVENT_WRITE, 0));
579 OUT_RING(R600_CACHE_FLUSH_AND_INV_EVENT);
580 /* wait for 3D idle clean */
581 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1));
582 OUT_RING((R600_WAIT_UNTIL - R600_SET_CONFIG_REG_OFFSET) >> 2);
583 OUT_RING(RADEON_WAIT_3D_IDLE | RADEON_WAIT_3D_IDLECLEAN);
584
585 ADVANCE_RING();
586 COMMIT_RING();
587
588 r600_nomm_put_vb(dev);
589}
590
591void
592r600_blit_copy(struct drm_device *dev,
593 uint64_t src_gpu_addr, uint64_t dst_gpu_addr,
594 int size_bytes)
595{
596 drm_radeon_private_t *dev_priv = dev->dev_private;
597 int max_bytes;
598 u64 vb_addr;
599 u32 *vb;
600
601 vb = r600_nomm_get_vb_ptr(dev);
602
603 if ((size_bytes & 3) || (src_gpu_addr & 3) || (dst_gpu_addr & 3)) {
604 max_bytes = 8192;
605
606 while (size_bytes) {
607 int cur_size = size_bytes;
608 int src_x = src_gpu_addr & 255;
609 int dst_x = dst_gpu_addr & 255;
610 int h = 1;
611 src_gpu_addr = src_gpu_addr & ~255;
612 dst_gpu_addr = dst_gpu_addr & ~255;
613
614 if (!src_x && !dst_x) {
615 h = (cur_size / max_bytes);
616 if (h > 8192)
617 h = 8192;
618 if (h == 0)
619 h = 1;
620 else
621 cur_size = max_bytes;
622 } else {
623 if (cur_size > max_bytes)
624 cur_size = max_bytes;
625 if (cur_size > (max_bytes - dst_x))
626 cur_size = (max_bytes - dst_x);
627 if (cur_size > (max_bytes - src_x))
628 cur_size = (max_bytes - src_x);
629 }
630
631 if ((dev_priv->blit_vb->used + 48) > dev_priv->blit_vb->total) {
632
633 r600_nomm_put_vb(dev);
634 r600_nomm_get_vb(dev);
635 if (!dev_priv->blit_vb)
636 return;
637 set_shaders(dev);
638 vb = r600_nomm_get_vb_ptr(dev);
639 }
640
641 vb[0] = int2float(dst_x);
642 vb[1] = 0;
643 vb[2] = int2float(src_x);
644 vb[3] = 0;
645
646 vb[4] = int2float(dst_x);
647 vb[5] = int2float(h);
648 vb[6] = int2float(src_x);
649 vb[7] = int2float(h);
650
651 vb[8] = int2float(dst_x + cur_size);
652 vb[9] = int2float(h);
653 vb[10] = int2float(src_x + cur_size);
654 vb[11] = int2float(h);
655
656 /* src */
657 set_tex_resource(dev_priv, FMT_8,
658 src_x + cur_size, h, src_x + cur_size,
659 src_gpu_addr);
660
661 cp_set_surface_sync(dev_priv,
662 R600_TC_ACTION_ENA, (src_x + cur_size * h), src_gpu_addr);
663
664 /* dst */
665 set_render_target(dev_priv, COLOR_8,
666 dst_x + cur_size, h,
667 dst_gpu_addr);
668
669 /* scissors */
670 set_scissors(dev_priv, dst_x, 0, dst_x + cur_size, h);
671
672 /* Vertex buffer setup */
673 vb_addr = dev_priv->gart_buffers_offset +
674 dev_priv->blit_vb->offset +
675 dev_priv->blit_vb->used;
676 set_vtx_resource(dev_priv, vb_addr);
677
678 /* draw */
679 draw_auto(dev_priv);
680
681 cp_set_surface_sync(dev_priv,
682 R600_CB_ACTION_ENA | R600_CB0_DEST_BASE_ENA,
683 cur_size * h, dst_gpu_addr);
684
685 vb += 12;
686 dev_priv->blit_vb->used += 12 * 4;
687
688 src_gpu_addr += cur_size * h;
689 dst_gpu_addr += cur_size * h;
690 size_bytes -= cur_size * h;
691 }
692 } else {
693 max_bytes = 8192 * 4;
694
695 while (size_bytes) {
696 int cur_size = size_bytes;
697 int src_x = (src_gpu_addr & 255);
698 int dst_x = (dst_gpu_addr & 255);
699 int h = 1;
700 src_gpu_addr = src_gpu_addr & ~255;
701 dst_gpu_addr = dst_gpu_addr & ~255;
702
703 if (!src_x && !dst_x) {
704 h = (cur_size / max_bytes);
705 if (h > 8192)
706 h = 8192;
707 if (h == 0)
708 h = 1;
709 else
710 cur_size = max_bytes;
711 } else {
712 if (cur_size > max_bytes)
713 cur_size = max_bytes;
714 if (cur_size > (max_bytes - dst_x))
715 cur_size = (max_bytes - dst_x);
716 if (cur_size > (max_bytes - src_x))
717 cur_size = (max_bytes - src_x);
718 }
719
720 if ((dev_priv->blit_vb->used + 48) > dev_priv->blit_vb->total) {
721 r600_nomm_put_vb(dev);
722 r600_nomm_get_vb(dev);
723 if (!dev_priv->blit_vb)
724 return;
725
726 set_shaders(dev);
727 vb = r600_nomm_get_vb_ptr(dev);
728 }
729
730 vb[0] = int2float(dst_x / 4);
731 vb[1] = 0;
732 vb[2] = int2float(src_x / 4);
733 vb[3] = 0;
734
735 vb[4] = int2float(dst_x / 4);
736 vb[5] = int2float(h);
737 vb[6] = int2float(src_x / 4);
738 vb[7] = int2float(h);
739
740 vb[8] = int2float((dst_x + cur_size) / 4);
741 vb[9] = int2float(h);
742 vb[10] = int2float((src_x + cur_size) / 4);
743 vb[11] = int2float(h);
744
745 /* src */
746 set_tex_resource(dev_priv, FMT_8_8_8_8,
747 (src_x + cur_size) / 4,
748 h, (src_x + cur_size) / 4,
749 src_gpu_addr);
750
751 cp_set_surface_sync(dev_priv,
752 R600_TC_ACTION_ENA, (src_x + cur_size * h), src_gpu_addr);
753
754 /* dst */
755 set_render_target(dev_priv, COLOR_8_8_8_8,
756 (dst_x + cur_size) / 4, h,
757 dst_gpu_addr);
758
759 /* scissors */
760 set_scissors(dev_priv, (dst_x / 4), 0, (dst_x + cur_size / 4), h);
761
762 /* Vertex buffer setup */
763 vb_addr = dev_priv->gart_buffers_offset +
764 dev_priv->blit_vb->offset +
765 dev_priv->blit_vb->used;
766 set_vtx_resource(dev_priv, vb_addr);
767
768 /* draw */
769 draw_auto(dev_priv);
770
771 cp_set_surface_sync(dev_priv,
772 R600_CB_ACTION_ENA | R600_CB0_DEST_BASE_ENA,
773 cur_size * h, dst_gpu_addr);
774
775 vb += 12;
776 dev_priv->blit_vb->used += 12 * 4;
777
778 src_gpu_addr += cur_size * h;
779 dst_gpu_addr += cur_size * h;
780 size_bytes -= cur_size * h;
781 }
782 }
783}
784
785void
786r600_blit_swap(struct drm_device *dev,
787 uint64_t src_gpu_addr, uint64_t dst_gpu_addr,
788 int sx, int sy, int dx, int dy,
789 int w, int h, int src_pitch, int dst_pitch, int cpp)
790{
791 drm_radeon_private_t *dev_priv = dev->dev_private;
792 int cb_format, tex_format;
793 int sx2, sy2, dx2, dy2;
794 u64 vb_addr;
795 u32 *vb;
796
797 if ((dev_priv->blit_vb->used + 48) > dev_priv->blit_vb->total) {
798
799 r600_nomm_put_vb(dev);
800 r600_nomm_get_vb(dev);
801 if (!dev_priv->blit_vb)
802 return;
803
804 set_shaders(dev);
805 }
806 vb = r600_nomm_get_vb_ptr(dev);
807
808 sx2 = sx + w;
809 sy2 = sy + h;
810 dx2 = dx + w;
811 dy2 = dy + h;
812
813 vb[0] = int2float(dx);
814 vb[1] = int2float(dy);
815 vb[2] = int2float(sx);
816 vb[3] = int2float(sy);
817
818 vb[4] = int2float(dx);
819 vb[5] = int2float(dy2);
820 vb[6] = int2float(sx);
821 vb[7] = int2float(sy2);
822
823 vb[8] = int2float(dx2);
824 vb[9] = int2float(dy2);
825 vb[10] = int2float(sx2);
826 vb[11] = int2float(sy2);
827
828 switch(cpp) {
829 case 4:
830 cb_format = COLOR_8_8_8_8;
831 tex_format = FMT_8_8_8_8;
832 break;
833 case 2:
834 cb_format = COLOR_5_6_5;
835 tex_format = FMT_5_6_5;
836 break;
837 default:
838 cb_format = COLOR_8;
839 tex_format = FMT_8;
840 break;
841 }
842
843 /* src */
844 set_tex_resource(dev_priv, tex_format,
845 src_pitch / cpp,
846 sy2, src_pitch / cpp,
847 src_gpu_addr);
848
849 cp_set_surface_sync(dev_priv,
850 R600_TC_ACTION_ENA, src_pitch * sy2, src_gpu_addr);
851
852 /* dst */
853 set_render_target(dev_priv, cb_format,
854 dst_pitch / cpp, dy2,
855 dst_gpu_addr);
856
857 /* scissors */
858 set_scissors(dev_priv, dx, dy, dx2, dy2);
859
860 /* Vertex buffer setup */
861 vb_addr = dev_priv->gart_buffers_offset +
862 dev_priv->blit_vb->offset +
863 dev_priv->blit_vb->used;
864 set_vtx_resource(dev_priv, vb_addr);
865
866 /* draw */
867 draw_auto(dev_priv);
868
869 cp_set_surface_sync(dev_priv,
870 R600_CB_ACTION_ENA | R600_CB0_DEST_BASE_ENA,
871 dst_pitch * dy2, dst_gpu_addr);
872
873 dev_priv->blit_vb->used += 12 * 4;
874}
diff --git a/drivers/gpu/drm/radeon/r600_cp.c b/drivers/gpu/drm/radeon/r600_cp.c
deleted file mode 100644
index e231eeafef23..000000000000
--- a/drivers/gpu/drm/radeon/r600_cp.c
+++ /dev/null
@@ -1,2660 +0,0 @@
1/*
2 * Copyright 2008-2009 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Dave Airlie <airlied@redhat.com>
26 * Alex Deucher <alexander.deucher@amd.com>
27 *
28 * ------------------------ This file is DEPRECATED! -------------------------
29 */
30
31#include <linux/module.h>
32
33#include <drm/drmP.h>
34#include <drm/radeon_drm.h>
35#include "radeon_drv.h"
36
37#define PFP_UCODE_SIZE 576
38#define PM4_UCODE_SIZE 1792
39#define R700_PFP_UCODE_SIZE 848
40#define R700_PM4_UCODE_SIZE 1360
41
42/* Firmware Names */
43MODULE_FIRMWARE("radeon/R600_pfp.bin");
44MODULE_FIRMWARE("radeon/R600_me.bin");
45MODULE_FIRMWARE("radeon/RV610_pfp.bin");
46MODULE_FIRMWARE("radeon/RV610_me.bin");
47MODULE_FIRMWARE("radeon/RV630_pfp.bin");
48MODULE_FIRMWARE("radeon/RV630_me.bin");
49MODULE_FIRMWARE("radeon/RV620_pfp.bin");
50MODULE_FIRMWARE("radeon/RV620_me.bin");
51MODULE_FIRMWARE("radeon/RV635_pfp.bin");
52MODULE_FIRMWARE("radeon/RV635_me.bin");
53MODULE_FIRMWARE("radeon/RV670_pfp.bin");
54MODULE_FIRMWARE("radeon/RV670_me.bin");
55MODULE_FIRMWARE("radeon/RS780_pfp.bin");
56MODULE_FIRMWARE("radeon/RS780_me.bin");
57MODULE_FIRMWARE("radeon/RV770_pfp.bin");
58MODULE_FIRMWARE("radeon/RV770_me.bin");
59MODULE_FIRMWARE("radeon/RV730_pfp.bin");
60MODULE_FIRMWARE("radeon/RV730_me.bin");
61MODULE_FIRMWARE("radeon/RV710_pfp.bin");
62MODULE_FIRMWARE("radeon/RV710_me.bin");
63
64
65int r600_cs_legacy(struct drm_device *dev, void *data, struct drm_file *filp,
66 unsigned family, u32 *ib, int *l);
67void r600_cs_legacy_init(void);
68
69
70# define ATI_PCIGART_PAGE_SIZE 4096 /**< PCI GART page size */
71# define ATI_PCIGART_PAGE_MASK (~(ATI_PCIGART_PAGE_SIZE-1))
72
73#define R600_PTE_VALID (1 << 0)
74#define R600_PTE_SYSTEM (1 << 1)
75#define R600_PTE_SNOOPED (1 << 2)
76#define R600_PTE_READABLE (1 << 5)
77#define R600_PTE_WRITEABLE (1 << 6)
78
79/* MAX values used for gfx init */
80#define R6XX_MAX_SH_GPRS 256
81#define R6XX_MAX_TEMP_GPRS 16
82#define R6XX_MAX_SH_THREADS 256
83#define R6XX_MAX_SH_STACK_ENTRIES 4096
84#define R6XX_MAX_BACKENDS 8
85#define R6XX_MAX_BACKENDS_MASK 0xff
86#define R6XX_MAX_SIMDS 8
87#define R6XX_MAX_SIMDS_MASK 0xff
88#define R6XX_MAX_PIPES 8
89#define R6XX_MAX_PIPES_MASK 0xff
90
91#define R7XX_MAX_SH_GPRS 256
92#define R7XX_MAX_TEMP_GPRS 16
93#define R7XX_MAX_SH_THREADS 256
94#define R7XX_MAX_SH_STACK_ENTRIES 4096
95#define R7XX_MAX_BACKENDS 8
96#define R7XX_MAX_BACKENDS_MASK 0xff
97#define R7XX_MAX_SIMDS 16
98#define R7XX_MAX_SIMDS_MASK 0xffff
99#define R7XX_MAX_PIPES 8
100#define R7XX_MAX_PIPES_MASK 0xff
101
102static int r600_do_wait_for_fifo(drm_radeon_private_t *dev_priv, int entries)
103{
104 int i;
105
106 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
107
108 for (i = 0; i < dev_priv->usec_timeout; i++) {
109 int slots;
110 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
111 slots = (RADEON_READ(R600_GRBM_STATUS)
112 & R700_CMDFIFO_AVAIL_MASK);
113 else
114 slots = (RADEON_READ(R600_GRBM_STATUS)
115 & R600_CMDFIFO_AVAIL_MASK);
116 if (slots >= entries)
117 return 0;
118 DRM_UDELAY(1);
119 }
120 DRM_INFO("wait for fifo failed status : 0x%08X 0x%08X\n",
121 RADEON_READ(R600_GRBM_STATUS),
122 RADEON_READ(R600_GRBM_STATUS2));
123
124 return -EBUSY;
125}
126
127static int r600_do_wait_for_idle(drm_radeon_private_t *dev_priv)
128{
129 int i, ret;
130
131 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
132
133 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
134 ret = r600_do_wait_for_fifo(dev_priv, 8);
135 else
136 ret = r600_do_wait_for_fifo(dev_priv, 16);
137 if (ret)
138 return ret;
139 for (i = 0; i < dev_priv->usec_timeout; i++) {
140 if (!(RADEON_READ(R600_GRBM_STATUS) & R600_GUI_ACTIVE))
141 return 0;
142 DRM_UDELAY(1);
143 }
144 DRM_INFO("wait idle failed status : 0x%08X 0x%08X\n",
145 RADEON_READ(R600_GRBM_STATUS),
146 RADEON_READ(R600_GRBM_STATUS2));
147
148 return -EBUSY;
149}
150
151void r600_page_table_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info)
152{
153 struct drm_sg_mem *entry = dev->sg;
154 int max_pages;
155 int pages;
156 int i;
157
158 if (!entry)
159 return;
160
161 if (gart_info->bus_addr) {
162 max_pages = (gart_info->table_size / sizeof(u64));
163 pages = (entry->pages <= max_pages)
164 ? entry->pages : max_pages;
165
166 for (i = 0; i < pages; i++) {
167 if (!entry->busaddr[i])
168 break;
169 pci_unmap_page(dev->pdev, entry->busaddr[i],
170 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
171 }
172 if (gart_info->gart_table_location == DRM_ATI_GART_MAIN)
173 gart_info->bus_addr = 0;
174 }
175}
176
177/* R600 has page table setup */
178int r600_page_table_init(struct drm_device *dev)
179{
180 drm_radeon_private_t *dev_priv = dev->dev_private;
181 struct drm_ati_pcigart_info *gart_info = &dev_priv->gart_info;
182 struct drm_local_map *map = &gart_info->mapping;
183 struct drm_sg_mem *entry = dev->sg;
184 int ret = 0;
185 int i, j;
186 int pages;
187 u64 page_base;
188 dma_addr_t entry_addr;
189 int max_ati_pages, max_real_pages, gart_idx;
190
191 /* okay page table is available - lets rock */
192 max_ati_pages = (gart_info->table_size / sizeof(u64));
193 max_real_pages = max_ati_pages / (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE);
194
195 pages = (entry->pages <= max_real_pages) ?
196 entry->pages : max_real_pages;
197
198 memset_io((void __iomem *)map->handle, 0, max_ati_pages * sizeof(u64));
199
200 gart_idx = 0;
201 for (i = 0; i < pages; i++) {
202 entry->busaddr[i] = pci_map_page(dev->pdev,
203 entry->pagelist[i], 0,
204 PAGE_SIZE,
205 PCI_DMA_BIDIRECTIONAL);
206 if (pci_dma_mapping_error(dev->pdev, entry->busaddr[i])) {
207 DRM_ERROR("unable to map PCIGART pages!\n");
208 r600_page_table_cleanup(dev, gart_info);
209 goto done;
210 }
211 entry_addr = entry->busaddr[i];
212 for (j = 0; j < (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE); j++) {
213 page_base = (u64) entry_addr & ATI_PCIGART_PAGE_MASK;
214 page_base |= R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED;
215 page_base |= R600_PTE_READABLE | R600_PTE_WRITEABLE;
216
217 DRM_WRITE64(map, gart_idx * sizeof(u64), page_base);
218
219 gart_idx++;
220
221 if ((i % 128) == 0)
222 DRM_DEBUG("page entry %d: 0x%016llx\n",
223 i, (unsigned long long)page_base);
224 entry_addr += ATI_PCIGART_PAGE_SIZE;
225 }
226 }
227 ret = 1;
228done:
229 return ret;
230}
231
232static void r600_vm_flush_gart_range(struct drm_device *dev)
233{
234 drm_radeon_private_t *dev_priv = dev->dev_private;
235 u32 resp, countdown = 1000;
236 RADEON_WRITE(R600_VM_CONTEXT0_INVALIDATION_LOW_ADDR, dev_priv->gart_vm_start >> 12);
237 RADEON_WRITE(R600_VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
238 RADEON_WRITE(R600_VM_CONTEXT0_REQUEST_RESPONSE, 2);
239
240 do {
241 resp = RADEON_READ(R600_VM_CONTEXT0_REQUEST_RESPONSE);
242 countdown--;
243 DRM_UDELAY(1);
244 } while (((resp & 0xf0) == 0) && countdown);
245}
246
247static void r600_vm_init(struct drm_device *dev)
248{
249 drm_radeon_private_t *dev_priv = dev->dev_private;
250 /* initialise the VM to use the page table we constructed up there */
251 u32 vm_c0, i;
252 u32 mc_rd_a;
253 u32 vm_l2_cntl, vm_l2_cntl3;
254 /* okay set up the PCIE aperture type thingo */
255 RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR, dev_priv->gart_vm_start >> 12);
256 RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
257 RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
258
259 /* setup MC RD a */
260 mc_rd_a = R600_MCD_L1_TLB | R600_MCD_L1_FRAG_PROC | R600_MCD_SYSTEM_ACCESS_MODE_IN_SYS |
261 R600_MCD_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | R600_MCD_EFFECTIVE_L1_TLB_SIZE(5) |
262 R600_MCD_EFFECTIVE_L1_QUEUE_SIZE(5) | R600_MCD_WAIT_L2_QUERY;
263
264 RADEON_WRITE(R600_MCD_RD_A_CNTL, mc_rd_a);
265 RADEON_WRITE(R600_MCD_RD_B_CNTL, mc_rd_a);
266
267 RADEON_WRITE(R600_MCD_WR_A_CNTL, mc_rd_a);
268 RADEON_WRITE(R600_MCD_WR_B_CNTL, mc_rd_a);
269
270 RADEON_WRITE(R600_MCD_RD_GFX_CNTL, mc_rd_a);
271 RADEON_WRITE(R600_MCD_WR_GFX_CNTL, mc_rd_a);
272
273 RADEON_WRITE(R600_MCD_RD_SYS_CNTL, mc_rd_a);
274 RADEON_WRITE(R600_MCD_WR_SYS_CNTL, mc_rd_a);
275
276 RADEON_WRITE(R600_MCD_RD_HDP_CNTL, mc_rd_a | R600_MCD_L1_STRICT_ORDERING);
277 RADEON_WRITE(R600_MCD_WR_HDP_CNTL, mc_rd_a /*| R600_MCD_L1_STRICT_ORDERING*/);
278
279 RADEON_WRITE(R600_MCD_RD_PDMA_CNTL, mc_rd_a);
280 RADEON_WRITE(R600_MCD_WR_PDMA_CNTL, mc_rd_a);
281
282 RADEON_WRITE(R600_MCD_RD_SEM_CNTL, mc_rd_a | R600_MCD_SEMAPHORE_MODE);
283 RADEON_WRITE(R600_MCD_WR_SEM_CNTL, mc_rd_a);
284
285 vm_l2_cntl = R600_VM_L2_CACHE_EN | R600_VM_L2_FRAG_PROC | R600_VM_ENABLE_PTE_CACHE_LRU_W;
286 vm_l2_cntl |= R600_VM_L2_CNTL_QUEUE_SIZE(7);
287 RADEON_WRITE(R600_VM_L2_CNTL, vm_l2_cntl);
288
289 RADEON_WRITE(R600_VM_L2_CNTL2, 0);
290 vm_l2_cntl3 = (R600_VM_L2_CNTL3_BANK_SELECT_0(0) |
291 R600_VM_L2_CNTL3_BANK_SELECT_1(1) |
292 R600_VM_L2_CNTL3_CACHE_UPDATE_MODE(2));
293 RADEON_WRITE(R600_VM_L2_CNTL3, vm_l2_cntl3);
294
295 vm_c0 = R600_VM_ENABLE_CONTEXT | R600_VM_PAGE_TABLE_DEPTH_FLAT;
296
297 RADEON_WRITE(R600_VM_CONTEXT0_CNTL, vm_c0);
298
299 vm_c0 &= ~R600_VM_ENABLE_CONTEXT;
300
301 /* disable all other contexts */
302 for (i = 1; i < 8; i++)
303 RADEON_WRITE(R600_VM_CONTEXT0_CNTL + (i * 4), vm_c0);
304
305 RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, dev_priv->gart_info.bus_addr >> 12);
306 RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_START_ADDR, dev_priv->gart_vm_start >> 12);
307 RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_END_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
308
309 r600_vm_flush_gart_range(dev);
310}
311
312static int r600_cp_init_microcode(drm_radeon_private_t *dev_priv)
313{
314 struct platform_device *pdev;
315 const char *chip_name;
316 size_t pfp_req_size, me_req_size;
317 char fw_name[30];
318 int err;
319
320 pdev = platform_device_register_simple("r600_cp", 0, NULL, 0);
321 err = IS_ERR(pdev);
322 if (err) {
323 printk(KERN_ERR "r600_cp: Failed to register firmware\n");
324 return -EINVAL;
325 }
326
327 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
328 case CHIP_R600: chip_name = "R600"; break;
329 case CHIP_RV610: chip_name = "RV610"; break;
330 case CHIP_RV630: chip_name = "RV630"; break;
331 case CHIP_RV620: chip_name = "RV620"; break;
332 case CHIP_RV635: chip_name = "RV635"; break;
333 case CHIP_RV670: chip_name = "RV670"; break;
334 case CHIP_RS780:
335 case CHIP_RS880: chip_name = "RS780"; break;
336 case CHIP_RV770: chip_name = "RV770"; break;
337 case CHIP_RV730:
338 case CHIP_RV740: chip_name = "RV730"; break;
339 case CHIP_RV710: chip_name = "RV710"; break;
340 default: BUG();
341 }
342
343 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) {
344 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
345 me_req_size = R700_PM4_UCODE_SIZE * 4;
346 } else {
347 pfp_req_size = PFP_UCODE_SIZE * 4;
348 me_req_size = PM4_UCODE_SIZE * 12;
349 }
350
351 DRM_INFO("Loading %s CP Microcode\n", chip_name);
352
353 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
354 err = request_firmware(&dev_priv->pfp_fw, fw_name, &pdev->dev);
355 if (err)
356 goto out;
357 if (dev_priv->pfp_fw->size != pfp_req_size) {
358 printk(KERN_ERR
359 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
360 dev_priv->pfp_fw->size, fw_name);
361 err = -EINVAL;
362 goto out;
363 }
364
365 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
366 err = request_firmware(&dev_priv->me_fw, fw_name, &pdev->dev);
367 if (err)
368 goto out;
369 if (dev_priv->me_fw->size != me_req_size) {
370 printk(KERN_ERR
371 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
372 dev_priv->me_fw->size, fw_name);
373 err = -EINVAL;
374 }
375out:
376 platform_device_unregister(pdev);
377
378 if (err) {
379 if (err != -EINVAL)
380 printk(KERN_ERR
381 "r600_cp: Failed to load firmware \"%s\"\n",
382 fw_name);
383 release_firmware(dev_priv->pfp_fw);
384 dev_priv->pfp_fw = NULL;
385 release_firmware(dev_priv->me_fw);
386 dev_priv->me_fw = NULL;
387 }
388 return err;
389}
390
391static void r600_cp_load_microcode(drm_radeon_private_t *dev_priv)
392{
393 const __be32 *fw_data;
394 int i;
395
396 if (!dev_priv->me_fw || !dev_priv->pfp_fw)
397 return;
398
399 r600_do_cp_stop(dev_priv);
400
401 RADEON_WRITE(R600_CP_RB_CNTL,
402#ifdef __BIG_ENDIAN
403 R600_BUF_SWAP_32BIT |
404#endif
405 R600_RB_NO_UPDATE |
406 R600_RB_BLKSZ(15) |
407 R600_RB_BUFSZ(3));
408
409 RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP);
410 RADEON_READ(R600_GRBM_SOFT_RESET);
411 mdelay(15);
412 RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
413
414 fw_data = (const __be32 *)dev_priv->me_fw->data;
415 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
416 for (i = 0; i < PM4_UCODE_SIZE * 3; i++)
417 RADEON_WRITE(R600_CP_ME_RAM_DATA,
418 be32_to_cpup(fw_data++));
419
420 fw_data = (const __be32 *)dev_priv->pfp_fw->data;
421 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
422 for (i = 0; i < PFP_UCODE_SIZE; i++)
423 RADEON_WRITE(R600_CP_PFP_UCODE_DATA,
424 be32_to_cpup(fw_data++));
425
426 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
427 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
428 RADEON_WRITE(R600_CP_ME_RAM_RADDR, 0);
429
430}
431
432static void r700_vm_init(struct drm_device *dev)
433{
434 drm_radeon_private_t *dev_priv = dev->dev_private;
435 /* initialise the VM to use the page table we constructed up there */
436 u32 vm_c0, i;
437 u32 mc_vm_md_l1;
438 u32 vm_l2_cntl, vm_l2_cntl3;
439 /* okay set up the PCIE aperture type thingo */
440 RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR, dev_priv->gart_vm_start >> 12);
441 RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
442 RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
443
444 mc_vm_md_l1 = R700_ENABLE_L1_TLB |
445 R700_ENABLE_L1_FRAGMENT_PROCESSING |
446 R700_SYSTEM_ACCESS_MODE_IN_SYS |
447 R700_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
448 R700_EFFECTIVE_L1_TLB_SIZE(5) |
449 R700_EFFECTIVE_L1_QUEUE_SIZE(5);
450
451 RADEON_WRITE(R700_MC_VM_MD_L1_TLB0_CNTL, mc_vm_md_l1);
452 RADEON_WRITE(R700_MC_VM_MD_L1_TLB1_CNTL, mc_vm_md_l1);
453 RADEON_WRITE(R700_MC_VM_MD_L1_TLB2_CNTL, mc_vm_md_l1);
454 RADEON_WRITE(R700_MC_VM_MB_L1_TLB0_CNTL, mc_vm_md_l1);
455 RADEON_WRITE(R700_MC_VM_MB_L1_TLB1_CNTL, mc_vm_md_l1);
456 RADEON_WRITE(R700_MC_VM_MB_L1_TLB2_CNTL, mc_vm_md_l1);
457 RADEON_WRITE(R700_MC_VM_MB_L1_TLB3_CNTL, mc_vm_md_l1);
458
459 vm_l2_cntl = R600_VM_L2_CACHE_EN | R600_VM_L2_FRAG_PROC | R600_VM_ENABLE_PTE_CACHE_LRU_W;
460 vm_l2_cntl |= R700_VM_L2_CNTL_QUEUE_SIZE(7);
461 RADEON_WRITE(R600_VM_L2_CNTL, vm_l2_cntl);
462
463 RADEON_WRITE(R600_VM_L2_CNTL2, 0);
464 vm_l2_cntl3 = R700_VM_L2_CNTL3_BANK_SELECT(0) | R700_VM_L2_CNTL3_CACHE_UPDATE_MODE(2);
465 RADEON_WRITE(R600_VM_L2_CNTL3, vm_l2_cntl3);
466
467 vm_c0 = R600_VM_ENABLE_CONTEXT | R600_VM_PAGE_TABLE_DEPTH_FLAT;
468
469 RADEON_WRITE(R600_VM_CONTEXT0_CNTL, vm_c0);
470
471 vm_c0 &= ~R600_VM_ENABLE_CONTEXT;
472
473 /* disable all other contexts */
474 for (i = 1; i < 8; i++)
475 RADEON_WRITE(R600_VM_CONTEXT0_CNTL + (i * 4), vm_c0);
476
477 RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, dev_priv->gart_info.bus_addr >> 12);
478 RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_START_ADDR, dev_priv->gart_vm_start >> 12);
479 RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_END_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
480
481 r600_vm_flush_gart_range(dev);
482}
483
484static void r700_cp_load_microcode(drm_radeon_private_t *dev_priv)
485{
486 const __be32 *fw_data;
487 int i;
488
489 if (!dev_priv->me_fw || !dev_priv->pfp_fw)
490 return;
491
492 r600_do_cp_stop(dev_priv);
493
494 RADEON_WRITE(R600_CP_RB_CNTL,
495#ifdef __BIG_ENDIAN
496 R600_BUF_SWAP_32BIT |
497#endif
498 R600_RB_NO_UPDATE |
499 R600_RB_BLKSZ(15) |
500 R600_RB_BUFSZ(3));
501
502 RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP);
503 RADEON_READ(R600_GRBM_SOFT_RESET);
504 mdelay(15);
505 RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
506
507 fw_data = (const __be32 *)dev_priv->pfp_fw->data;
508 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
509 for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
510 RADEON_WRITE(R600_CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
511 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
512
513 fw_data = (const __be32 *)dev_priv->me_fw->data;
514 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
515 for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
516 RADEON_WRITE(R600_CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
517 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
518
519 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
520 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
521 RADEON_WRITE(R600_CP_ME_RAM_RADDR, 0);
522
523}
524
525static void r600_test_writeback(drm_radeon_private_t *dev_priv)
526{
527 u32 tmp;
528
529 /* Start with assuming that writeback doesn't work */
530 dev_priv->writeback_works = 0;
531
532 /* Writeback doesn't seem to work everywhere, test it here and possibly
533 * enable it if it appears to work
534 */
535 radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(1), 0);
536
537 RADEON_WRITE(R600_SCRATCH_REG1, 0xdeadbeef);
538
539 for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
540 u32 val;
541
542 val = radeon_read_ring_rptr(dev_priv, R600_SCRATCHOFF(1));
543 if (val == 0xdeadbeef)
544 break;
545 DRM_UDELAY(1);
546 }
547
548 if (tmp < dev_priv->usec_timeout) {
549 dev_priv->writeback_works = 1;
550 DRM_INFO("writeback test succeeded in %d usecs\n", tmp);
551 } else {
552 dev_priv->writeback_works = 0;
553 DRM_INFO("writeback test failed\n");
554 }
555 if (radeon_no_wb == 1) {
556 dev_priv->writeback_works = 0;
557 DRM_INFO("writeback forced off\n");
558 }
559
560 if (!dev_priv->writeback_works) {
561 /* Disable writeback to avoid unnecessary bus master transfer */
562 RADEON_WRITE(R600_CP_RB_CNTL,
563#ifdef __BIG_ENDIAN
564 R600_BUF_SWAP_32BIT |
565#endif
566 RADEON_READ(R600_CP_RB_CNTL) |
567 R600_RB_NO_UPDATE);
568 RADEON_WRITE(R600_SCRATCH_UMSK, 0);
569 }
570}
571
572int r600_do_engine_reset(struct drm_device *dev)
573{
574 drm_radeon_private_t *dev_priv = dev->dev_private;
575 u32 cp_ptr, cp_me_cntl, cp_rb_cntl;
576
577 DRM_INFO("Resetting GPU\n");
578
579 cp_ptr = RADEON_READ(R600_CP_RB_WPTR);
580 cp_me_cntl = RADEON_READ(R600_CP_ME_CNTL);
581 RADEON_WRITE(R600_CP_ME_CNTL, R600_CP_ME_HALT);
582
583 RADEON_WRITE(R600_GRBM_SOFT_RESET, 0x7fff);
584 RADEON_READ(R600_GRBM_SOFT_RESET);
585 DRM_UDELAY(50);
586 RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
587 RADEON_READ(R600_GRBM_SOFT_RESET);
588
589 RADEON_WRITE(R600_CP_RB_WPTR_DELAY, 0);
590 cp_rb_cntl = RADEON_READ(R600_CP_RB_CNTL);
591 RADEON_WRITE(R600_CP_RB_CNTL,
592#ifdef __BIG_ENDIAN
593 R600_BUF_SWAP_32BIT |
594#endif
595 R600_RB_RPTR_WR_ENA);
596
597 RADEON_WRITE(R600_CP_RB_RPTR_WR, cp_ptr);
598 RADEON_WRITE(R600_CP_RB_WPTR, cp_ptr);
599 RADEON_WRITE(R600_CP_RB_CNTL, cp_rb_cntl);
600 RADEON_WRITE(R600_CP_ME_CNTL, cp_me_cntl);
601
602 /* Reset the CP ring */
603 r600_do_cp_reset(dev_priv);
604
605 /* The CP is no longer running after an engine reset */
606 dev_priv->cp_running = 0;
607
608 /* Reset any pending vertex, indirect buffers */
609 radeon_freelist_reset(dev);
610
611 return 0;
612
613}
614
615static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
616 u32 num_backends,
617 u32 backend_disable_mask)
618{
619 u32 backend_map = 0;
620 u32 enabled_backends_mask;
621 u32 enabled_backends_count;
622 u32 cur_pipe;
623 u32 swizzle_pipe[R6XX_MAX_PIPES];
624 u32 cur_backend;
625 u32 i;
626
627 if (num_tile_pipes > R6XX_MAX_PIPES)
628 num_tile_pipes = R6XX_MAX_PIPES;
629 if (num_tile_pipes < 1)
630 num_tile_pipes = 1;
631 if (num_backends > R6XX_MAX_BACKENDS)
632 num_backends = R6XX_MAX_BACKENDS;
633 if (num_backends < 1)
634 num_backends = 1;
635
636 enabled_backends_mask = 0;
637 enabled_backends_count = 0;
638 for (i = 0; i < R6XX_MAX_BACKENDS; ++i) {
639 if (((backend_disable_mask >> i) & 1) == 0) {
640 enabled_backends_mask |= (1 << i);
641 ++enabled_backends_count;
642 }
643 if (enabled_backends_count == num_backends)
644 break;
645 }
646
647 if (enabled_backends_count == 0) {
648 enabled_backends_mask = 1;
649 enabled_backends_count = 1;
650 }
651
652 if (enabled_backends_count != num_backends)
653 num_backends = enabled_backends_count;
654
655 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES);
656 switch (num_tile_pipes) {
657 case 1:
658 swizzle_pipe[0] = 0;
659 break;
660 case 2:
661 swizzle_pipe[0] = 0;
662 swizzle_pipe[1] = 1;
663 break;
664 case 3:
665 swizzle_pipe[0] = 0;
666 swizzle_pipe[1] = 1;
667 swizzle_pipe[2] = 2;
668 break;
669 case 4:
670 swizzle_pipe[0] = 0;
671 swizzle_pipe[1] = 1;
672 swizzle_pipe[2] = 2;
673 swizzle_pipe[3] = 3;
674 break;
675 case 5:
676 swizzle_pipe[0] = 0;
677 swizzle_pipe[1] = 1;
678 swizzle_pipe[2] = 2;
679 swizzle_pipe[3] = 3;
680 swizzle_pipe[4] = 4;
681 break;
682 case 6:
683 swizzle_pipe[0] = 0;
684 swizzle_pipe[1] = 2;
685 swizzle_pipe[2] = 4;
686 swizzle_pipe[3] = 5;
687 swizzle_pipe[4] = 1;
688 swizzle_pipe[5] = 3;
689 break;
690 case 7:
691 swizzle_pipe[0] = 0;
692 swizzle_pipe[1] = 2;
693 swizzle_pipe[2] = 4;
694 swizzle_pipe[3] = 6;
695 swizzle_pipe[4] = 1;
696 swizzle_pipe[5] = 3;
697 swizzle_pipe[6] = 5;
698 break;
699 case 8:
700 swizzle_pipe[0] = 0;
701 swizzle_pipe[1] = 2;
702 swizzle_pipe[2] = 4;
703 swizzle_pipe[3] = 6;
704 swizzle_pipe[4] = 1;
705 swizzle_pipe[5] = 3;
706 swizzle_pipe[6] = 5;
707 swizzle_pipe[7] = 7;
708 break;
709 }
710
711 cur_backend = 0;
712 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
713 while (((1 << cur_backend) & enabled_backends_mask) == 0)
714 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
715
716 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
717
718 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
719 }
720
721 return backend_map;
722}
723
724static int r600_count_pipe_bits(uint32_t val)
725{
726 return hweight32(val);
727}
728
729static void r600_gfx_init(struct drm_device *dev,
730 drm_radeon_private_t *dev_priv)
731{
732 int i, j, num_qd_pipes;
733 u32 sx_debug_1;
734 u32 tc_cntl;
735 u32 arb_pop;
736 u32 num_gs_verts_per_thread;
737 u32 vgt_gs_per_es;
738 u32 gs_prim_buffer_depth = 0;
739 u32 sq_ms_fifo_sizes;
740 u32 sq_config;
741 u32 sq_gpr_resource_mgmt_1 = 0;
742 u32 sq_gpr_resource_mgmt_2 = 0;
743 u32 sq_thread_resource_mgmt = 0;
744 u32 sq_stack_resource_mgmt_1 = 0;
745 u32 sq_stack_resource_mgmt_2 = 0;
746 u32 hdp_host_path_cntl;
747 u32 backend_map;
748 u32 gb_tiling_config = 0;
749 u32 cc_rb_backend_disable;
750 u32 cc_gc_shader_pipe_config;
751 u32 ramcfg;
752
753 /* setup chip specs */
754 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
755 case CHIP_R600:
756 dev_priv->r600_max_pipes = 4;
757 dev_priv->r600_max_tile_pipes = 8;
758 dev_priv->r600_max_simds = 4;
759 dev_priv->r600_max_backends = 4;
760 dev_priv->r600_max_gprs = 256;
761 dev_priv->r600_max_threads = 192;
762 dev_priv->r600_max_stack_entries = 256;
763 dev_priv->r600_max_hw_contexts = 8;
764 dev_priv->r600_max_gs_threads = 16;
765 dev_priv->r600_sx_max_export_size = 128;
766 dev_priv->r600_sx_max_export_pos_size = 16;
767 dev_priv->r600_sx_max_export_smx_size = 128;
768 dev_priv->r600_sq_num_cf_insts = 2;
769 break;
770 case CHIP_RV630:
771 case CHIP_RV635:
772 dev_priv->r600_max_pipes = 2;
773 dev_priv->r600_max_tile_pipes = 2;
774 dev_priv->r600_max_simds = 3;
775 dev_priv->r600_max_backends = 1;
776 dev_priv->r600_max_gprs = 128;
777 dev_priv->r600_max_threads = 192;
778 dev_priv->r600_max_stack_entries = 128;
779 dev_priv->r600_max_hw_contexts = 8;
780 dev_priv->r600_max_gs_threads = 4;
781 dev_priv->r600_sx_max_export_size = 128;
782 dev_priv->r600_sx_max_export_pos_size = 16;
783 dev_priv->r600_sx_max_export_smx_size = 128;
784 dev_priv->r600_sq_num_cf_insts = 2;
785 break;
786 case CHIP_RV610:
787 case CHIP_RS780:
788 case CHIP_RS880:
789 case CHIP_RV620:
790 dev_priv->r600_max_pipes = 1;
791 dev_priv->r600_max_tile_pipes = 1;
792 dev_priv->r600_max_simds = 2;
793 dev_priv->r600_max_backends = 1;
794 dev_priv->r600_max_gprs = 128;
795 dev_priv->r600_max_threads = 192;
796 dev_priv->r600_max_stack_entries = 128;
797 dev_priv->r600_max_hw_contexts = 4;
798 dev_priv->r600_max_gs_threads = 4;
799 dev_priv->r600_sx_max_export_size = 128;
800 dev_priv->r600_sx_max_export_pos_size = 16;
801 dev_priv->r600_sx_max_export_smx_size = 128;
802 dev_priv->r600_sq_num_cf_insts = 1;
803 break;
804 case CHIP_RV670:
805 dev_priv->r600_max_pipes = 4;
806 dev_priv->r600_max_tile_pipes = 4;
807 dev_priv->r600_max_simds = 4;
808 dev_priv->r600_max_backends = 4;
809 dev_priv->r600_max_gprs = 192;
810 dev_priv->r600_max_threads = 192;
811 dev_priv->r600_max_stack_entries = 256;
812 dev_priv->r600_max_hw_contexts = 8;
813 dev_priv->r600_max_gs_threads = 16;
814 dev_priv->r600_sx_max_export_size = 128;
815 dev_priv->r600_sx_max_export_pos_size = 16;
816 dev_priv->r600_sx_max_export_smx_size = 128;
817 dev_priv->r600_sq_num_cf_insts = 2;
818 break;
819 default:
820 break;
821 }
822
823 /* Initialize HDP */
824 j = 0;
825 for (i = 0; i < 32; i++) {
826 RADEON_WRITE((0x2c14 + j), 0x00000000);
827 RADEON_WRITE((0x2c18 + j), 0x00000000);
828 RADEON_WRITE((0x2c1c + j), 0x00000000);
829 RADEON_WRITE((0x2c20 + j), 0x00000000);
830 RADEON_WRITE((0x2c24 + j), 0x00000000);
831 j += 0x18;
832 }
833
834 RADEON_WRITE(R600_GRBM_CNTL, R600_GRBM_READ_TIMEOUT(0xff));
835
836 /* setup tiling, simd, pipe config */
837 ramcfg = RADEON_READ(R600_RAMCFG);
838
839 switch (dev_priv->r600_max_tile_pipes) {
840 case 1:
841 gb_tiling_config |= R600_PIPE_TILING(0);
842 break;
843 case 2:
844 gb_tiling_config |= R600_PIPE_TILING(1);
845 break;
846 case 4:
847 gb_tiling_config |= R600_PIPE_TILING(2);
848 break;
849 case 8:
850 gb_tiling_config |= R600_PIPE_TILING(3);
851 break;
852 default:
853 break;
854 }
855
856 gb_tiling_config |= R600_BANK_TILING((ramcfg >> R600_NOOFBANK_SHIFT) & R600_NOOFBANK_MASK);
857
858 gb_tiling_config |= R600_GROUP_SIZE(0);
859
860 if (((ramcfg >> R600_NOOFROWS_SHIFT) & R600_NOOFROWS_MASK) > 3) {
861 gb_tiling_config |= R600_ROW_TILING(3);
862 gb_tiling_config |= R600_SAMPLE_SPLIT(3);
863 } else {
864 gb_tiling_config |=
865 R600_ROW_TILING(((ramcfg >> R600_NOOFROWS_SHIFT) & R600_NOOFROWS_MASK));
866 gb_tiling_config |=
867 R600_SAMPLE_SPLIT(((ramcfg >> R600_NOOFROWS_SHIFT) & R600_NOOFROWS_MASK));
868 }
869
870 gb_tiling_config |= R600_BANK_SWAPS(1);
871
872 cc_rb_backend_disable = RADEON_READ(R600_CC_RB_BACKEND_DISABLE) & 0x00ff0000;
873 cc_rb_backend_disable |=
874 R600_BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << dev_priv->r600_max_backends) & R6XX_MAX_BACKENDS_MASK);
875
876 cc_gc_shader_pipe_config = RADEON_READ(R600_CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
877 cc_gc_shader_pipe_config |=
878 R600_INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << dev_priv->r600_max_pipes) & R6XX_MAX_PIPES_MASK);
879 cc_gc_shader_pipe_config |=
880 R600_INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << dev_priv->r600_max_simds) & R6XX_MAX_SIMDS_MASK);
881
882 backend_map = r600_get_tile_pipe_to_backend_map(dev_priv->r600_max_tile_pipes,
883 (R6XX_MAX_BACKENDS -
884 r600_count_pipe_bits((cc_rb_backend_disable &
885 R6XX_MAX_BACKENDS_MASK) >> 16)),
886 (cc_rb_backend_disable >> 16));
887 gb_tiling_config |= R600_BACKEND_MAP(backend_map);
888
889 RADEON_WRITE(R600_GB_TILING_CONFIG, gb_tiling_config);
890 RADEON_WRITE(R600_DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
891 RADEON_WRITE(R600_HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
892 if (gb_tiling_config & 0xc0) {
893 dev_priv->r600_group_size = 512;
894 } else {
895 dev_priv->r600_group_size = 256;
896 }
897 dev_priv->r600_npipes = 1 << ((gb_tiling_config >> 1) & 0x7);
898 if (gb_tiling_config & 0x30) {
899 dev_priv->r600_nbanks = 8;
900 } else {
901 dev_priv->r600_nbanks = 4;
902 }
903
904 RADEON_WRITE(R600_CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
905 RADEON_WRITE(R600_CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
906 RADEON_WRITE(R600_GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
907
908 num_qd_pipes =
909 R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & R600_INACTIVE_QD_PIPES_MASK) >> 8);
910 RADEON_WRITE(R600_VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & R600_DEALLOC_DIST_MASK);
911 RADEON_WRITE(R600_VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & R600_VTX_REUSE_DEPTH_MASK);
912
913 /* set HW defaults for 3D engine */
914 RADEON_WRITE(R600_CP_QUEUE_THRESHOLDS, (R600_ROQ_IB1_START(0x16) |
915 R600_ROQ_IB2_START(0x2b)));
916
917 RADEON_WRITE(R600_CP_MEQ_THRESHOLDS, (R600_MEQ_END(0x40) |
918 R600_ROQ_END(0x40)));
919
920 RADEON_WRITE(R600_TA_CNTL_AUX, (R600_DISABLE_CUBE_ANISO |
921 R600_SYNC_GRADIENT |
922 R600_SYNC_WALKER |
923 R600_SYNC_ALIGNER));
924
925 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV670)
926 RADEON_WRITE(R600_ARB_GDEC_RD_CNTL, 0x00000021);
927
928 sx_debug_1 = RADEON_READ(R600_SX_DEBUG_1);
929 sx_debug_1 |= R600_SMX_EVENT_RELEASE;
930 if (((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_R600))
931 sx_debug_1 |= R600_ENABLE_NEW_SMX_ADDRESS;
932 RADEON_WRITE(R600_SX_DEBUG_1, sx_debug_1);
933
934 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) ||
935 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630) ||
936 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
937 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
938 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
939 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880))
940 RADEON_WRITE(R600_DB_DEBUG, R600_PREZ_MUST_WAIT_FOR_POSTZ_DONE);
941 else
942 RADEON_WRITE(R600_DB_DEBUG, 0);
943
944 RADEON_WRITE(R600_DB_WATERMARKS, (R600_DEPTH_FREE(4) |
945 R600_DEPTH_FLUSH(16) |
946 R600_DEPTH_PENDING_FREE(4) |
947 R600_DEPTH_CACHELINE_FREE(16)));
948 RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0);
949 RADEON_WRITE(R600_VGT_NUM_INSTANCES, 0);
950
951 RADEON_WRITE(R600_SPI_CONFIG_CNTL, R600_GPR_WRITE_PRIORITY(0));
952 RADEON_WRITE(R600_SPI_CONFIG_CNTL_1, R600_VTX_DONE_DELAY(0));
953
954 sq_ms_fifo_sizes = RADEON_READ(R600_SQ_MS_FIFO_SIZES);
955 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
956 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
957 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
958 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880)) {
959 sq_ms_fifo_sizes = (R600_CACHE_FIFO_SIZE(0xa) |
960 R600_FETCH_FIFO_HIWATER(0xa) |
961 R600_DONE_FIFO_HIWATER(0xe0) |
962 R600_ALU_UPDATE_FIFO_HIWATER(0x8));
963 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) ||
964 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630)) {
965 sq_ms_fifo_sizes &= ~R600_DONE_FIFO_HIWATER(0xff);
966 sq_ms_fifo_sizes |= R600_DONE_FIFO_HIWATER(0x4);
967 }
968 RADEON_WRITE(R600_SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes);
969
970 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
971 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
972 */
973 sq_config = RADEON_READ(R600_SQ_CONFIG);
974 sq_config &= ~(R600_PS_PRIO(3) |
975 R600_VS_PRIO(3) |
976 R600_GS_PRIO(3) |
977 R600_ES_PRIO(3));
978 sq_config |= (R600_DX9_CONSTS |
979 R600_VC_ENABLE |
980 R600_PS_PRIO(0) |
981 R600_VS_PRIO(1) |
982 R600_GS_PRIO(2) |
983 R600_ES_PRIO(3));
984
985 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) {
986 sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(124) |
987 R600_NUM_VS_GPRS(124) |
988 R600_NUM_CLAUSE_TEMP_GPRS(4));
989 sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(0) |
990 R600_NUM_ES_GPRS(0));
991 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(136) |
992 R600_NUM_VS_THREADS(48) |
993 R600_NUM_GS_THREADS(4) |
994 R600_NUM_ES_THREADS(4));
995 sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(128) |
996 R600_NUM_VS_STACK_ENTRIES(128));
997 sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(0) |
998 R600_NUM_ES_STACK_ENTRIES(0));
999 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
1000 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
1001 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
1002 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880)) {
1003 /* no vertex cache */
1004 sq_config &= ~R600_VC_ENABLE;
1005
1006 sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) |
1007 R600_NUM_VS_GPRS(44) |
1008 R600_NUM_CLAUSE_TEMP_GPRS(2));
1009 sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(17) |
1010 R600_NUM_ES_GPRS(17));
1011 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(79) |
1012 R600_NUM_VS_THREADS(78) |
1013 R600_NUM_GS_THREADS(4) |
1014 R600_NUM_ES_THREADS(31));
1015 sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(40) |
1016 R600_NUM_VS_STACK_ENTRIES(40));
1017 sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(32) |
1018 R600_NUM_ES_STACK_ENTRIES(16));
1019 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630) ||
1020 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV635)) {
1021 sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) |
1022 R600_NUM_VS_GPRS(44) |
1023 R600_NUM_CLAUSE_TEMP_GPRS(2));
1024 sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(18) |
1025 R600_NUM_ES_GPRS(18));
1026 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(79) |
1027 R600_NUM_VS_THREADS(78) |
1028 R600_NUM_GS_THREADS(4) |
1029 R600_NUM_ES_THREADS(31));
1030 sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(40) |
1031 R600_NUM_VS_STACK_ENTRIES(40));
1032 sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(32) |
1033 R600_NUM_ES_STACK_ENTRIES(16));
1034 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV670) {
1035 sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) |
1036 R600_NUM_VS_GPRS(44) |
1037 R600_NUM_CLAUSE_TEMP_GPRS(2));
1038 sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(17) |
1039 R600_NUM_ES_GPRS(17));
1040 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(79) |
1041 R600_NUM_VS_THREADS(78) |
1042 R600_NUM_GS_THREADS(4) |
1043 R600_NUM_ES_THREADS(31));
1044 sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(64) |
1045 R600_NUM_VS_STACK_ENTRIES(64));
1046 sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(64) |
1047 R600_NUM_ES_STACK_ENTRIES(64));
1048 }
1049
1050 RADEON_WRITE(R600_SQ_CONFIG, sq_config);
1051 RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
1052 RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
1053 RADEON_WRITE(R600_SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1054 RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
1055 RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
1056
1057 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
1058 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
1059 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
1060 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880))
1061 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, R600_CACHE_INVALIDATION(R600_TC_ONLY));
1062 else
1063 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, R600_CACHE_INVALIDATION(R600_VC_AND_TC));
1064
1065 RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_2S, (R600_S0_X(0xc) |
1066 R600_S0_Y(0x4) |
1067 R600_S1_X(0x4) |
1068 R600_S1_Y(0xc)));
1069 RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_4S, (R600_S0_X(0xe) |
1070 R600_S0_Y(0xe) |
1071 R600_S1_X(0x2) |
1072 R600_S1_Y(0x2) |
1073 R600_S2_X(0xa) |
1074 R600_S2_Y(0x6) |
1075 R600_S3_X(0x6) |
1076 R600_S3_Y(0xa)));
1077 RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_8S_WD0, (R600_S0_X(0xe) |
1078 R600_S0_Y(0xb) |
1079 R600_S1_X(0x4) |
1080 R600_S1_Y(0xc) |
1081 R600_S2_X(0x1) |
1082 R600_S2_Y(0x6) |
1083 R600_S3_X(0xa) |
1084 R600_S3_Y(0xe)));
1085 RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_8S_WD1, (R600_S4_X(0x6) |
1086 R600_S4_Y(0x1) |
1087 R600_S5_X(0x0) |
1088 R600_S5_Y(0x0) |
1089 R600_S6_X(0xb) |
1090 R600_S6_Y(0x4) |
1091 R600_S7_X(0x7) |
1092 R600_S7_Y(0x8)));
1093
1094
1095 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1096 case CHIP_R600:
1097 case CHIP_RV630:
1098 case CHIP_RV635:
1099 gs_prim_buffer_depth = 0;
1100 break;
1101 case CHIP_RV610:
1102 case CHIP_RS780:
1103 case CHIP_RS880:
1104 case CHIP_RV620:
1105 gs_prim_buffer_depth = 32;
1106 break;
1107 case CHIP_RV670:
1108 gs_prim_buffer_depth = 128;
1109 break;
1110 default:
1111 break;
1112 }
1113
1114 num_gs_verts_per_thread = dev_priv->r600_max_pipes * 16;
1115 vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread;
1116 /* Max value for this is 256 */
1117 if (vgt_gs_per_es > 256)
1118 vgt_gs_per_es = 256;
1119
1120 RADEON_WRITE(R600_VGT_ES_PER_GS, 128);
1121 RADEON_WRITE(R600_VGT_GS_PER_ES, vgt_gs_per_es);
1122 RADEON_WRITE(R600_VGT_GS_PER_VS, 2);
1123 RADEON_WRITE(R600_VGT_GS_VERTEX_REUSE, 16);
1124
1125 /* more default values. 2D/3D driver should adjust as needed */
1126 RADEON_WRITE(R600_PA_SC_LINE_STIPPLE_STATE, 0);
1127 RADEON_WRITE(R600_VGT_STRMOUT_EN, 0);
1128 RADEON_WRITE(R600_SX_MISC, 0);
1129 RADEON_WRITE(R600_PA_SC_MODE_CNTL, 0);
1130 RADEON_WRITE(R600_PA_SC_AA_CONFIG, 0);
1131 RADEON_WRITE(R600_PA_SC_LINE_STIPPLE, 0);
1132 RADEON_WRITE(R600_SPI_INPUT_Z, 0);
1133 RADEON_WRITE(R600_SPI_PS_IN_CONTROL_0, R600_NUM_INTERP(2));
1134 RADEON_WRITE(R600_CB_COLOR7_FRAG, 0);
1135
1136 /* clear render buffer base addresses */
1137 RADEON_WRITE(R600_CB_COLOR0_BASE, 0);
1138 RADEON_WRITE(R600_CB_COLOR1_BASE, 0);
1139 RADEON_WRITE(R600_CB_COLOR2_BASE, 0);
1140 RADEON_WRITE(R600_CB_COLOR3_BASE, 0);
1141 RADEON_WRITE(R600_CB_COLOR4_BASE, 0);
1142 RADEON_WRITE(R600_CB_COLOR5_BASE, 0);
1143 RADEON_WRITE(R600_CB_COLOR6_BASE, 0);
1144 RADEON_WRITE(R600_CB_COLOR7_BASE, 0);
1145
1146 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1147 case CHIP_RV610:
1148 case CHIP_RS780:
1149 case CHIP_RS880:
1150 case CHIP_RV620:
1151 tc_cntl = R600_TC_L2_SIZE(8);
1152 break;
1153 case CHIP_RV630:
1154 case CHIP_RV635:
1155 tc_cntl = R600_TC_L2_SIZE(4);
1156 break;
1157 case CHIP_R600:
1158 tc_cntl = R600_TC_L2_SIZE(0) | R600_L2_DISABLE_LATE_HIT;
1159 break;
1160 default:
1161 tc_cntl = R600_TC_L2_SIZE(0);
1162 break;
1163 }
1164
1165 RADEON_WRITE(R600_TC_CNTL, tc_cntl);
1166
1167 hdp_host_path_cntl = RADEON_READ(R600_HDP_HOST_PATH_CNTL);
1168 RADEON_WRITE(R600_HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1169
1170 arb_pop = RADEON_READ(R600_ARB_POP);
1171 arb_pop |= R600_ENABLE_TC128;
1172 RADEON_WRITE(R600_ARB_POP, arb_pop);
1173
1174 RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0);
1175 RADEON_WRITE(R600_PA_CL_ENHANCE, (R600_CLIP_VTX_REORDER_ENA |
1176 R600_NUM_CLIP_SEQ(3)));
1177 RADEON_WRITE(R600_PA_SC_ENHANCE, R600_FORCE_EOV_MAX_CLK_CNT(4095));
1178
1179}
1180
1181static u32 r700_get_tile_pipe_to_backend_map(drm_radeon_private_t *dev_priv,
1182 u32 num_tile_pipes,
1183 u32 num_backends,
1184 u32 backend_disable_mask)
1185{
1186 u32 backend_map = 0;
1187 u32 enabled_backends_mask;
1188 u32 enabled_backends_count;
1189 u32 cur_pipe;
1190 u32 swizzle_pipe[R7XX_MAX_PIPES];
1191 u32 cur_backend;
1192 u32 i;
1193 bool force_no_swizzle;
1194
1195 if (num_tile_pipes > R7XX_MAX_PIPES)
1196 num_tile_pipes = R7XX_MAX_PIPES;
1197 if (num_tile_pipes < 1)
1198 num_tile_pipes = 1;
1199 if (num_backends > R7XX_MAX_BACKENDS)
1200 num_backends = R7XX_MAX_BACKENDS;
1201 if (num_backends < 1)
1202 num_backends = 1;
1203
1204 enabled_backends_mask = 0;
1205 enabled_backends_count = 0;
1206 for (i = 0; i < R7XX_MAX_BACKENDS; ++i) {
1207 if (((backend_disable_mask >> i) & 1) == 0) {
1208 enabled_backends_mask |= (1 << i);
1209 ++enabled_backends_count;
1210 }
1211 if (enabled_backends_count == num_backends)
1212 break;
1213 }
1214
1215 if (enabled_backends_count == 0) {
1216 enabled_backends_mask = 1;
1217 enabled_backends_count = 1;
1218 }
1219
1220 if (enabled_backends_count != num_backends)
1221 num_backends = enabled_backends_count;
1222
1223 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1224 case CHIP_RV770:
1225 case CHIP_RV730:
1226 force_no_swizzle = false;
1227 break;
1228 case CHIP_RV710:
1229 case CHIP_RV740:
1230 default:
1231 force_no_swizzle = true;
1232 break;
1233 }
1234
1235 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R7XX_MAX_PIPES);
1236 switch (num_tile_pipes) {
1237 case 1:
1238 swizzle_pipe[0] = 0;
1239 break;
1240 case 2:
1241 swizzle_pipe[0] = 0;
1242 swizzle_pipe[1] = 1;
1243 break;
1244 case 3:
1245 if (force_no_swizzle) {
1246 swizzle_pipe[0] = 0;
1247 swizzle_pipe[1] = 1;
1248 swizzle_pipe[2] = 2;
1249 } else {
1250 swizzle_pipe[0] = 0;
1251 swizzle_pipe[1] = 2;
1252 swizzle_pipe[2] = 1;
1253 }
1254 break;
1255 case 4:
1256 if (force_no_swizzle) {
1257 swizzle_pipe[0] = 0;
1258 swizzle_pipe[1] = 1;
1259 swizzle_pipe[2] = 2;
1260 swizzle_pipe[3] = 3;
1261 } else {
1262 swizzle_pipe[0] = 0;
1263 swizzle_pipe[1] = 2;
1264 swizzle_pipe[2] = 3;
1265 swizzle_pipe[3] = 1;
1266 }
1267 break;
1268 case 5:
1269 if (force_no_swizzle) {
1270 swizzle_pipe[0] = 0;
1271 swizzle_pipe[1] = 1;
1272 swizzle_pipe[2] = 2;
1273 swizzle_pipe[3] = 3;
1274 swizzle_pipe[4] = 4;
1275 } else {
1276 swizzle_pipe[0] = 0;
1277 swizzle_pipe[1] = 2;
1278 swizzle_pipe[2] = 4;
1279 swizzle_pipe[3] = 1;
1280 swizzle_pipe[4] = 3;
1281 }
1282 break;
1283 case 6:
1284 if (force_no_swizzle) {
1285 swizzle_pipe[0] = 0;
1286 swizzle_pipe[1] = 1;
1287 swizzle_pipe[2] = 2;
1288 swizzle_pipe[3] = 3;
1289 swizzle_pipe[4] = 4;
1290 swizzle_pipe[5] = 5;
1291 } else {
1292 swizzle_pipe[0] = 0;
1293 swizzle_pipe[1] = 2;
1294 swizzle_pipe[2] = 4;
1295 swizzle_pipe[3] = 5;
1296 swizzle_pipe[4] = 3;
1297 swizzle_pipe[5] = 1;
1298 }
1299 break;
1300 case 7:
1301 if (force_no_swizzle) {
1302 swizzle_pipe[0] = 0;
1303 swizzle_pipe[1] = 1;
1304 swizzle_pipe[2] = 2;
1305 swizzle_pipe[3] = 3;
1306 swizzle_pipe[4] = 4;
1307 swizzle_pipe[5] = 5;
1308 swizzle_pipe[6] = 6;
1309 } else {
1310 swizzle_pipe[0] = 0;
1311 swizzle_pipe[1] = 2;
1312 swizzle_pipe[2] = 4;
1313 swizzle_pipe[3] = 6;
1314 swizzle_pipe[4] = 3;
1315 swizzle_pipe[5] = 1;
1316 swizzle_pipe[6] = 5;
1317 }
1318 break;
1319 case 8:
1320 if (force_no_swizzle) {
1321 swizzle_pipe[0] = 0;
1322 swizzle_pipe[1] = 1;
1323 swizzle_pipe[2] = 2;
1324 swizzle_pipe[3] = 3;
1325 swizzle_pipe[4] = 4;
1326 swizzle_pipe[5] = 5;
1327 swizzle_pipe[6] = 6;
1328 swizzle_pipe[7] = 7;
1329 } else {
1330 swizzle_pipe[0] = 0;
1331 swizzle_pipe[1] = 2;
1332 swizzle_pipe[2] = 4;
1333 swizzle_pipe[3] = 6;
1334 swizzle_pipe[4] = 3;
1335 swizzle_pipe[5] = 1;
1336 swizzle_pipe[6] = 7;
1337 swizzle_pipe[7] = 5;
1338 }
1339 break;
1340 }
1341
1342 cur_backend = 0;
1343 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
1344 while (((1 << cur_backend) & enabled_backends_mask) == 0)
1345 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
1346
1347 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
1348
1349 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
1350 }
1351
1352 return backend_map;
1353}
1354
1355static void r700_gfx_init(struct drm_device *dev,
1356 drm_radeon_private_t *dev_priv)
1357{
1358 int i, j, num_qd_pipes;
1359 u32 ta_aux_cntl;
1360 u32 sx_debug_1;
1361 u32 smx_dc_ctl0;
1362 u32 db_debug3;
1363 u32 num_gs_verts_per_thread;
1364 u32 vgt_gs_per_es;
1365 u32 gs_prim_buffer_depth = 0;
1366 u32 sq_ms_fifo_sizes;
1367 u32 sq_config;
1368 u32 sq_thread_resource_mgmt;
1369 u32 hdp_host_path_cntl;
1370 u32 sq_dyn_gpr_size_simd_ab_0;
1371 u32 backend_map;
1372 u32 gb_tiling_config = 0;
1373 u32 cc_rb_backend_disable;
1374 u32 cc_gc_shader_pipe_config;
1375 u32 mc_arb_ramcfg;
1376 u32 db_debug4;
1377
1378 /* setup chip specs */
1379 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1380 case CHIP_RV770:
1381 dev_priv->r600_max_pipes = 4;
1382 dev_priv->r600_max_tile_pipes = 8;
1383 dev_priv->r600_max_simds = 10;
1384 dev_priv->r600_max_backends = 4;
1385 dev_priv->r600_max_gprs = 256;
1386 dev_priv->r600_max_threads = 248;
1387 dev_priv->r600_max_stack_entries = 512;
1388 dev_priv->r600_max_hw_contexts = 8;
1389 dev_priv->r600_max_gs_threads = 16 * 2;
1390 dev_priv->r600_sx_max_export_size = 128;
1391 dev_priv->r600_sx_max_export_pos_size = 16;
1392 dev_priv->r600_sx_max_export_smx_size = 112;
1393 dev_priv->r600_sq_num_cf_insts = 2;
1394
1395 dev_priv->r700_sx_num_of_sets = 7;
1396 dev_priv->r700_sc_prim_fifo_size = 0xF9;
1397 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30;
1398 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130;
1399 break;
1400 case CHIP_RV730:
1401 dev_priv->r600_max_pipes = 2;
1402 dev_priv->r600_max_tile_pipes = 4;
1403 dev_priv->r600_max_simds = 8;
1404 dev_priv->r600_max_backends = 2;
1405 dev_priv->r600_max_gprs = 128;
1406 dev_priv->r600_max_threads = 248;
1407 dev_priv->r600_max_stack_entries = 256;
1408 dev_priv->r600_max_hw_contexts = 8;
1409 dev_priv->r600_max_gs_threads = 16 * 2;
1410 dev_priv->r600_sx_max_export_size = 256;
1411 dev_priv->r600_sx_max_export_pos_size = 32;
1412 dev_priv->r600_sx_max_export_smx_size = 224;
1413 dev_priv->r600_sq_num_cf_insts = 2;
1414
1415 dev_priv->r700_sx_num_of_sets = 7;
1416 dev_priv->r700_sc_prim_fifo_size = 0xf9;
1417 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30;
1418 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130;
1419 if (dev_priv->r600_sx_max_export_pos_size > 16) {
1420 dev_priv->r600_sx_max_export_pos_size -= 16;
1421 dev_priv->r600_sx_max_export_smx_size += 16;
1422 }
1423 break;
1424 case CHIP_RV710:
1425 dev_priv->r600_max_pipes = 2;
1426 dev_priv->r600_max_tile_pipes = 2;
1427 dev_priv->r600_max_simds = 2;
1428 dev_priv->r600_max_backends = 1;
1429 dev_priv->r600_max_gprs = 256;
1430 dev_priv->r600_max_threads = 192;
1431 dev_priv->r600_max_stack_entries = 256;
1432 dev_priv->r600_max_hw_contexts = 4;
1433 dev_priv->r600_max_gs_threads = 8 * 2;
1434 dev_priv->r600_sx_max_export_size = 128;
1435 dev_priv->r600_sx_max_export_pos_size = 16;
1436 dev_priv->r600_sx_max_export_smx_size = 112;
1437 dev_priv->r600_sq_num_cf_insts = 1;
1438
1439 dev_priv->r700_sx_num_of_sets = 7;
1440 dev_priv->r700_sc_prim_fifo_size = 0x40;
1441 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30;
1442 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130;
1443 break;
1444 case CHIP_RV740:
1445 dev_priv->r600_max_pipes = 4;
1446 dev_priv->r600_max_tile_pipes = 4;
1447 dev_priv->r600_max_simds = 8;
1448 dev_priv->r600_max_backends = 4;
1449 dev_priv->r600_max_gprs = 256;
1450 dev_priv->r600_max_threads = 248;
1451 dev_priv->r600_max_stack_entries = 512;
1452 dev_priv->r600_max_hw_contexts = 8;
1453 dev_priv->r600_max_gs_threads = 16 * 2;
1454 dev_priv->r600_sx_max_export_size = 256;
1455 dev_priv->r600_sx_max_export_pos_size = 32;
1456 dev_priv->r600_sx_max_export_smx_size = 224;
1457 dev_priv->r600_sq_num_cf_insts = 2;
1458
1459 dev_priv->r700_sx_num_of_sets = 7;
1460 dev_priv->r700_sc_prim_fifo_size = 0x100;
1461 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30;
1462 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130;
1463
1464 if (dev_priv->r600_sx_max_export_pos_size > 16) {
1465 dev_priv->r600_sx_max_export_pos_size -= 16;
1466 dev_priv->r600_sx_max_export_smx_size += 16;
1467 }
1468 break;
1469 default:
1470 break;
1471 }
1472
1473 /* Initialize HDP */
1474 j = 0;
1475 for (i = 0; i < 32; i++) {
1476 RADEON_WRITE((0x2c14 + j), 0x00000000);
1477 RADEON_WRITE((0x2c18 + j), 0x00000000);
1478 RADEON_WRITE((0x2c1c + j), 0x00000000);
1479 RADEON_WRITE((0x2c20 + j), 0x00000000);
1480 RADEON_WRITE((0x2c24 + j), 0x00000000);
1481 j += 0x18;
1482 }
1483
1484 RADEON_WRITE(R600_GRBM_CNTL, R600_GRBM_READ_TIMEOUT(0xff));
1485
1486 /* setup tiling, simd, pipe config */
1487 mc_arb_ramcfg = RADEON_READ(R700_MC_ARB_RAMCFG);
1488
1489 switch (dev_priv->r600_max_tile_pipes) {
1490 case 1:
1491 gb_tiling_config |= R600_PIPE_TILING(0);
1492 break;
1493 case 2:
1494 gb_tiling_config |= R600_PIPE_TILING(1);
1495 break;
1496 case 4:
1497 gb_tiling_config |= R600_PIPE_TILING(2);
1498 break;
1499 case 8:
1500 gb_tiling_config |= R600_PIPE_TILING(3);
1501 break;
1502 default:
1503 break;
1504 }
1505
1506 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV770)
1507 gb_tiling_config |= R600_BANK_TILING(1);
1508 else
1509 gb_tiling_config |= R600_BANK_TILING((mc_arb_ramcfg >> R700_NOOFBANK_SHIFT) & R700_NOOFBANK_MASK);
1510
1511 gb_tiling_config |= R600_GROUP_SIZE(0);
1512
1513 if (((mc_arb_ramcfg >> R700_NOOFROWS_SHIFT) & R700_NOOFROWS_MASK) > 3) {
1514 gb_tiling_config |= R600_ROW_TILING(3);
1515 gb_tiling_config |= R600_SAMPLE_SPLIT(3);
1516 } else {
1517 gb_tiling_config |=
1518 R600_ROW_TILING(((mc_arb_ramcfg >> R700_NOOFROWS_SHIFT) & R700_NOOFROWS_MASK));
1519 gb_tiling_config |=
1520 R600_SAMPLE_SPLIT(((mc_arb_ramcfg >> R700_NOOFROWS_SHIFT) & R700_NOOFROWS_MASK));
1521 }
1522
1523 gb_tiling_config |= R600_BANK_SWAPS(1);
1524
1525 cc_rb_backend_disable = RADEON_READ(R600_CC_RB_BACKEND_DISABLE) & 0x00ff0000;
1526 cc_rb_backend_disable |=
1527 R600_BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << dev_priv->r600_max_backends) & R7XX_MAX_BACKENDS_MASK);
1528
1529 cc_gc_shader_pipe_config = RADEON_READ(R600_CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
1530 cc_gc_shader_pipe_config |=
1531 R600_INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << dev_priv->r600_max_pipes) & R7XX_MAX_PIPES_MASK);
1532 cc_gc_shader_pipe_config |=
1533 R600_INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << dev_priv->r600_max_simds) & R7XX_MAX_SIMDS_MASK);
1534
1535 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV740)
1536 backend_map = 0x28;
1537 else
1538 backend_map = r700_get_tile_pipe_to_backend_map(dev_priv,
1539 dev_priv->r600_max_tile_pipes,
1540 (R7XX_MAX_BACKENDS -
1541 r600_count_pipe_bits((cc_rb_backend_disable &
1542 R7XX_MAX_BACKENDS_MASK) >> 16)),
1543 (cc_rb_backend_disable >> 16));
1544 gb_tiling_config |= R600_BACKEND_MAP(backend_map);
1545
1546 RADEON_WRITE(R600_GB_TILING_CONFIG, gb_tiling_config);
1547 RADEON_WRITE(R600_DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
1548 RADEON_WRITE(R600_HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
1549 if (gb_tiling_config & 0xc0) {
1550 dev_priv->r600_group_size = 512;
1551 } else {
1552 dev_priv->r600_group_size = 256;
1553 }
1554 dev_priv->r600_npipes = 1 << ((gb_tiling_config >> 1) & 0x7);
1555 if (gb_tiling_config & 0x30) {
1556 dev_priv->r600_nbanks = 8;
1557 } else {
1558 dev_priv->r600_nbanks = 4;
1559 }
1560
1561 RADEON_WRITE(R600_CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
1562 RADEON_WRITE(R600_CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
1563 RADEON_WRITE(R600_GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
1564
1565 RADEON_WRITE(R700_CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
1566 RADEON_WRITE(R700_CGTS_SYS_TCC_DISABLE, 0);
1567 RADEON_WRITE(R700_CGTS_TCC_DISABLE, 0);
1568 RADEON_WRITE(R700_CGTS_USER_SYS_TCC_DISABLE, 0);
1569 RADEON_WRITE(R700_CGTS_USER_TCC_DISABLE, 0);
1570
1571 num_qd_pipes =
1572 R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & R600_INACTIVE_QD_PIPES_MASK) >> 8);
1573 RADEON_WRITE(R600_VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & R600_DEALLOC_DIST_MASK);
1574 RADEON_WRITE(R600_VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & R600_VTX_REUSE_DEPTH_MASK);
1575
1576 /* set HW defaults for 3D engine */
1577 RADEON_WRITE(R600_CP_QUEUE_THRESHOLDS, (R600_ROQ_IB1_START(0x16) |
1578 R600_ROQ_IB2_START(0x2b)));
1579
1580 RADEON_WRITE(R600_CP_MEQ_THRESHOLDS, R700_STQ_SPLIT(0x30));
1581
1582 ta_aux_cntl = RADEON_READ(R600_TA_CNTL_AUX);
1583 RADEON_WRITE(R600_TA_CNTL_AUX, ta_aux_cntl | R600_DISABLE_CUBE_ANISO);
1584
1585 sx_debug_1 = RADEON_READ(R700_SX_DEBUG_1);
1586 sx_debug_1 |= R700_ENABLE_NEW_SMX_ADDRESS;
1587 RADEON_WRITE(R700_SX_DEBUG_1, sx_debug_1);
1588
1589 smx_dc_ctl0 = RADEON_READ(R600_SMX_DC_CTL0);
1590 smx_dc_ctl0 &= ~R700_CACHE_DEPTH(0x1ff);
1591 smx_dc_ctl0 |= R700_CACHE_DEPTH((dev_priv->r700_sx_num_of_sets * 64) - 1);
1592 RADEON_WRITE(R600_SMX_DC_CTL0, smx_dc_ctl0);
1593
1594 if ((dev_priv->flags & RADEON_FAMILY_MASK) != CHIP_RV740)
1595 RADEON_WRITE(R700_SMX_EVENT_CTL, (R700_ES_FLUSH_CTL(4) |
1596 R700_GS_FLUSH_CTL(4) |
1597 R700_ACK_FLUSH_CTL(3) |
1598 R700_SYNC_FLUSH_CTL));
1599
1600 db_debug3 = RADEON_READ(R700_DB_DEBUG3);
1601 db_debug3 &= ~R700_DB_CLK_OFF_DELAY(0x1f);
1602 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1603 case CHIP_RV770:
1604 case CHIP_RV740:
1605 db_debug3 |= R700_DB_CLK_OFF_DELAY(0x1f);
1606 break;
1607 case CHIP_RV710:
1608 case CHIP_RV730:
1609 default:
1610 db_debug3 |= R700_DB_CLK_OFF_DELAY(2);
1611 break;
1612 }
1613 RADEON_WRITE(R700_DB_DEBUG3, db_debug3);
1614
1615 if ((dev_priv->flags & RADEON_FAMILY_MASK) != CHIP_RV770) {
1616 db_debug4 = RADEON_READ(RV700_DB_DEBUG4);
1617 db_debug4 |= RV700_DISABLE_TILE_COVERED_FOR_PS_ITER;
1618 RADEON_WRITE(RV700_DB_DEBUG4, db_debug4);
1619 }
1620
1621 RADEON_WRITE(R600_SX_EXPORT_BUFFER_SIZES, (R600_COLOR_BUFFER_SIZE((dev_priv->r600_sx_max_export_size / 4) - 1) |
1622 R600_POSITION_BUFFER_SIZE((dev_priv->r600_sx_max_export_pos_size / 4) - 1) |
1623 R600_SMX_BUFFER_SIZE((dev_priv->r600_sx_max_export_smx_size / 4) - 1)));
1624
1625 RADEON_WRITE(R700_PA_SC_FIFO_SIZE_R7XX, (R700_SC_PRIM_FIFO_SIZE(dev_priv->r700_sc_prim_fifo_size) |
1626 R700_SC_HIZ_TILE_FIFO_SIZE(dev_priv->r700_sc_hiz_tile_fifo_size) |
1627 R700_SC_EARLYZ_TILE_FIFO_SIZE(dev_priv->r700_sc_earlyz_tile_fifo_fize)));
1628
1629 RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0);
1630
1631 RADEON_WRITE(R600_VGT_NUM_INSTANCES, 1);
1632
1633 RADEON_WRITE(R600_SPI_CONFIG_CNTL, R600_GPR_WRITE_PRIORITY(0));
1634
1635 RADEON_WRITE(R600_SPI_CONFIG_CNTL_1, R600_VTX_DONE_DELAY(4));
1636
1637 RADEON_WRITE(R600_CP_PERFMON_CNTL, 0);
1638
1639 sq_ms_fifo_sizes = (R600_CACHE_FIFO_SIZE(16 * dev_priv->r600_sq_num_cf_insts) |
1640 R600_DONE_FIFO_HIWATER(0xe0) |
1641 R600_ALU_UPDATE_FIFO_HIWATER(0x8));
1642 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1643 case CHIP_RV770:
1644 case CHIP_RV730:
1645 case CHIP_RV710:
1646 sq_ms_fifo_sizes |= R600_FETCH_FIFO_HIWATER(0x1);
1647 break;
1648 case CHIP_RV740:
1649 default:
1650 sq_ms_fifo_sizes |= R600_FETCH_FIFO_HIWATER(0x4);
1651 break;
1652 }
1653 RADEON_WRITE(R600_SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes);
1654
1655 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1656 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
1657 */
1658 sq_config = RADEON_READ(R600_SQ_CONFIG);
1659 sq_config &= ~(R600_PS_PRIO(3) |
1660 R600_VS_PRIO(3) |
1661 R600_GS_PRIO(3) |
1662 R600_ES_PRIO(3));
1663 sq_config |= (R600_DX9_CONSTS |
1664 R600_VC_ENABLE |
1665 R600_EXPORT_SRC_C |
1666 R600_PS_PRIO(0) |
1667 R600_VS_PRIO(1) |
1668 R600_GS_PRIO(2) |
1669 R600_ES_PRIO(3));
1670 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710)
1671 /* no vertex cache */
1672 sq_config &= ~R600_VC_ENABLE;
1673
1674 RADEON_WRITE(R600_SQ_CONFIG, sq_config);
1675
1676 RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_1, (R600_NUM_PS_GPRS((dev_priv->r600_max_gprs * 24)/64) |
1677 R600_NUM_VS_GPRS((dev_priv->r600_max_gprs * 24)/64) |
1678 R600_NUM_CLAUSE_TEMP_GPRS(((dev_priv->r600_max_gprs * 24)/64)/2)));
1679
1680 RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_2, (R600_NUM_GS_GPRS((dev_priv->r600_max_gprs * 7)/64) |
1681 R600_NUM_ES_GPRS((dev_priv->r600_max_gprs * 7)/64)));
1682
1683 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS((dev_priv->r600_max_threads * 4)/8) |
1684 R600_NUM_VS_THREADS((dev_priv->r600_max_threads * 2)/8) |
1685 R600_NUM_ES_THREADS((dev_priv->r600_max_threads * 1)/8));
1686 if (((dev_priv->r600_max_threads * 1) / 8) > dev_priv->r600_max_gs_threads)
1687 sq_thread_resource_mgmt |= R600_NUM_GS_THREADS(dev_priv->r600_max_gs_threads);
1688 else
1689 sq_thread_resource_mgmt |= R600_NUM_GS_THREADS((dev_priv->r600_max_gs_threads * 1)/8);
1690 RADEON_WRITE(R600_SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1691
1692 RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_1, (R600_NUM_PS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4) |
1693 R600_NUM_VS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4)));
1694
1695 RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_2, (R600_NUM_GS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4) |
1696 R600_NUM_ES_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4)));
1697
1698 sq_dyn_gpr_size_simd_ab_0 = (R700_SIMDA_RING0((dev_priv->r600_max_gprs * 38)/64) |
1699 R700_SIMDA_RING1((dev_priv->r600_max_gprs * 38)/64) |
1700 R700_SIMDB_RING0((dev_priv->r600_max_gprs * 38)/64) |
1701 R700_SIMDB_RING1((dev_priv->r600_max_gprs * 38)/64));
1702
1703 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0);
1704 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0);
1705 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0);
1706 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0);
1707 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0);
1708 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0);
1709 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0);
1710 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0);
1711
1712 RADEON_WRITE(R700_PA_SC_FORCE_EOV_MAX_CNTS, (R700_FORCE_EOV_MAX_CLK_CNT(4095) |
1713 R700_FORCE_EOV_MAX_REZ_CNT(255)));
1714
1715 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710)
1716 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, (R600_CACHE_INVALIDATION(R600_TC_ONLY) |
1717 R700_AUTO_INVLD_EN(R700_ES_AND_GS_AUTO)));
1718 else
1719 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, (R600_CACHE_INVALIDATION(R600_VC_AND_TC) |
1720 R700_AUTO_INVLD_EN(R700_ES_AND_GS_AUTO)));
1721
1722 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1723 case CHIP_RV770:
1724 case CHIP_RV730:
1725 case CHIP_RV740:
1726 gs_prim_buffer_depth = 384;
1727 break;
1728 case CHIP_RV710:
1729 gs_prim_buffer_depth = 128;
1730 break;
1731 default:
1732 break;
1733 }
1734
1735 num_gs_verts_per_thread = dev_priv->r600_max_pipes * 16;
1736 vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread;
1737 /* Max value for this is 256 */
1738 if (vgt_gs_per_es > 256)
1739 vgt_gs_per_es = 256;
1740
1741 RADEON_WRITE(R600_VGT_ES_PER_GS, 128);
1742 RADEON_WRITE(R600_VGT_GS_PER_ES, vgt_gs_per_es);
1743 RADEON_WRITE(R600_VGT_GS_PER_VS, 2);
1744
1745 /* more default values. 2D/3D driver should adjust as needed */
1746 RADEON_WRITE(R600_VGT_GS_VERTEX_REUSE, 16);
1747 RADEON_WRITE(R600_PA_SC_LINE_STIPPLE_STATE, 0);
1748 RADEON_WRITE(R600_VGT_STRMOUT_EN, 0);
1749 RADEON_WRITE(R600_SX_MISC, 0);
1750 RADEON_WRITE(R600_PA_SC_MODE_CNTL, 0);
1751 RADEON_WRITE(R700_PA_SC_EDGERULE, 0xaaaaaaaa);
1752 RADEON_WRITE(R600_PA_SC_AA_CONFIG, 0);
1753 RADEON_WRITE(R600_PA_SC_CLIPRECT_RULE, 0xffff);
1754 RADEON_WRITE(R600_PA_SC_LINE_STIPPLE, 0);
1755 RADEON_WRITE(R600_SPI_INPUT_Z, 0);
1756 RADEON_WRITE(R600_SPI_PS_IN_CONTROL_0, R600_NUM_INTERP(2));
1757 RADEON_WRITE(R600_CB_COLOR7_FRAG, 0);
1758
1759 /* clear render buffer base addresses */
1760 RADEON_WRITE(R600_CB_COLOR0_BASE, 0);
1761 RADEON_WRITE(R600_CB_COLOR1_BASE, 0);
1762 RADEON_WRITE(R600_CB_COLOR2_BASE, 0);
1763 RADEON_WRITE(R600_CB_COLOR3_BASE, 0);
1764 RADEON_WRITE(R600_CB_COLOR4_BASE, 0);
1765 RADEON_WRITE(R600_CB_COLOR5_BASE, 0);
1766 RADEON_WRITE(R600_CB_COLOR6_BASE, 0);
1767 RADEON_WRITE(R600_CB_COLOR7_BASE, 0);
1768
1769 RADEON_WRITE(R700_TCP_CNTL, 0);
1770
1771 hdp_host_path_cntl = RADEON_READ(R600_HDP_HOST_PATH_CNTL);
1772 RADEON_WRITE(R600_HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1773
1774 RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0);
1775
1776 RADEON_WRITE(R600_PA_CL_ENHANCE, (R600_CLIP_VTX_REORDER_ENA |
1777 R600_NUM_CLIP_SEQ(3)));
1778
1779}
1780
1781static void r600_cp_init_ring_buffer(struct drm_device *dev,
1782 drm_radeon_private_t *dev_priv,
1783 struct drm_file *file_priv)
1784{
1785 struct drm_radeon_master_private *master_priv;
1786 u32 ring_start;
1787 u64 rptr_addr;
1788
1789 if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770))
1790 r700_gfx_init(dev, dev_priv);
1791 else
1792 r600_gfx_init(dev, dev_priv);
1793
1794 RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP);
1795 RADEON_READ(R600_GRBM_SOFT_RESET);
1796 mdelay(15);
1797 RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
1798
1799
1800 /* Set ring buffer size */
1801#ifdef __BIG_ENDIAN
1802 RADEON_WRITE(R600_CP_RB_CNTL,
1803 R600_BUF_SWAP_32BIT |
1804 R600_RB_NO_UPDATE |
1805 (dev_priv->ring.rptr_update_l2qw << 8) |
1806 dev_priv->ring.size_l2qw);
1807#else
1808 RADEON_WRITE(R600_CP_RB_CNTL,
1809 RADEON_RB_NO_UPDATE |
1810 (dev_priv->ring.rptr_update_l2qw << 8) |
1811 dev_priv->ring.size_l2qw);
1812#endif
1813
1814 RADEON_WRITE(R600_CP_SEM_WAIT_TIMER, 0x0);
1815
1816 /* Set the write pointer delay */
1817 RADEON_WRITE(R600_CP_RB_WPTR_DELAY, 0);
1818
1819#ifdef __BIG_ENDIAN
1820 RADEON_WRITE(R600_CP_RB_CNTL,
1821 R600_BUF_SWAP_32BIT |
1822 R600_RB_NO_UPDATE |
1823 R600_RB_RPTR_WR_ENA |
1824 (dev_priv->ring.rptr_update_l2qw << 8) |
1825 dev_priv->ring.size_l2qw);
1826#else
1827 RADEON_WRITE(R600_CP_RB_CNTL,
1828 R600_RB_NO_UPDATE |
1829 R600_RB_RPTR_WR_ENA |
1830 (dev_priv->ring.rptr_update_l2qw << 8) |
1831 dev_priv->ring.size_l2qw);
1832#endif
1833
1834 /* Initialize the ring buffer's read and write pointers */
1835 RADEON_WRITE(R600_CP_RB_RPTR_WR, 0);
1836 RADEON_WRITE(R600_CP_RB_WPTR, 0);
1837 SET_RING_HEAD(dev_priv, 0);
1838 dev_priv->ring.tail = 0;
1839
1840#if IS_ENABLED(CONFIG_AGP)
1841 if (dev_priv->flags & RADEON_IS_AGP) {
1842 rptr_addr = dev_priv->ring_rptr->offset
1843 - dev->agp->base +
1844 dev_priv->gart_vm_start;
1845 } else
1846#endif
1847 {
1848 rptr_addr = dev_priv->ring_rptr->offset
1849 - ((unsigned long) dev->sg->virtual)
1850 + dev_priv->gart_vm_start;
1851 }
1852 RADEON_WRITE(R600_CP_RB_RPTR_ADDR, (rptr_addr & 0xfffffffc));
1853 RADEON_WRITE(R600_CP_RB_RPTR_ADDR_HI, upper_32_bits(rptr_addr));
1854
1855#ifdef __BIG_ENDIAN
1856 RADEON_WRITE(R600_CP_RB_CNTL,
1857 RADEON_BUF_SWAP_32BIT |
1858 (dev_priv->ring.rptr_update_l2qw << 8) |
1859 dev_priv->ring.size_l2qw);
1860#else
1861 RADEON_WRITE(R600_CP_RB_CNTL,
1862 (dev_priv->ring.rptr_update_l2qw << 8) |
1863 dev_priv->ring.size_l2qw);
1864#endif
1865
1866#if IS_ENABLED(CONFIG_AGP)
1867 if (dev_priv->flags & RADEON_IS_AGP) {
1868 /* XXX */
1869 radeon_write_agp_base(dev_priv, dev->agp->base);
1870
1871 /* XXX */
1872 radeon_write_agp_location(dev_priv,
1873 (((dev_priv->gart_vm_start - 1 +
1874 dev_priv->gart_size) & 0xffff0000) |
1875 (dev_priv->gart_vm_start >> 16)));
1876
1877 ring_start = (dev_priv->cp_ring->offset
1878 - dev->agp->base
1879 + dev_priv->gart_vm_start);
1880 } else
1881#endif
1882 ring_start = (dev_priv->cp_ring->offset
1883 - (unsigned long)dev->sg->virtual
1884 + dev_priv->gart_vm_start);
1885
1886 RADEON_WRITE(R600_CP_RB_BASE, ring_start >> 8);
1887
1888 RADEON_WRITE(R600_CP_ME_CNTL, 0xff);
1889
1890 RADEON_WRITE(R600_CP_DEBUG, (1 << 27) | (1 << 28));
1891
1892 /* Initialize the scratch register pointer. This will cause
1893 * the scratch register values to be written out to memory
1894 * whenever they are updated.
1895 *
1896 * We simply put this behind the ring read pointer, this works
1897 * with PCI GART as well as (whatever kind of) AGP GART
1898 */
1899 {
1900 u64 scratch_addr;
1901
1902 scratch_addr = RADEON_READ(R600_CP_RB_RPTR_ADDR) & 0xFFFFFFFC;
1903 scratch_addr |= ((u64)RADEON_READ(R600_CP_RB_RPTR_ADDR_HI)) << 32;
1904 scratch_addr += R600_SCRATCH_REG_OFFSET;
1905 scratch_addr >>= 8;
1906 scratch_addr &= 0xffffffff;
1907
1908 RADEON_WRITE(R600_SCRATCH_ADDR, (uint32_t)scratch_addr);
1909 }
1910
1911 RADEON_WRITE(R600_SCRATCH_UMSK, 0x7);
1912
1913 /* Turn on bus mastering */
1914 radeon_enable_bm(dev_priv);
1915
1916 radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(0), 0);
1917 RADEON_WRITE(R600_LAST_FRAME_REG, 0);
1918
1919 radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(1), 0);
1920 RADEON_WRITE(R600_LAST_DISPATCH_REG, 0);
1921
1922 radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(2), 0);
1923 RADEON_WRITE(R600_LAST_CLEAR_REG, 0);
1924
1925 /* reset sarea copies of these */
1926 master_priv = file_priv->master->driver_priv;
1927 if (master_priv->sarea_priv) {
1928 master_priv->sarea_priv->last_frame = 0;
1929 master_priv->sarea_priv->last_dispatch = 0;
1930 master_priv->sarea_priv->last_clear = 0;
1931 }
1932
1933 r600_do_wait_for_idle(dev_priv);
1934
1935}
1936
1937int r600_do_cleanup_cp(struct drm_device *dev)
1938{
1939 drm_radeon_private_t *dev_priv = dev->dev_private;
1940 DRM_DEBUG("\n");
1941
1942 /* Make sure interrupts are disabled here because the uninstall ioctl
1943 * may not have been called from userspace and after dev_private
1944 * is freed, it's too late.
1945 */
1946 if (dev->irq_enabled)
1947 drm_irq_uninstall(dev);
1948
1949#if IS_ENABLED(CONFIG_AGP)
1950 if (dev_priv->flags & RADEON_IS_AGP) {
1951 if (dev_priv->cp_ring != NULL) {
1952 drm_legacy_ioremapfree(dev_priv->cp_ring, dev);
1953 dev_priv->cp_ring = NULL;
1954 }
1955 if (dev_priv->ring_rptr != NULL) {
1956 drm_legacy_ioremapfree(dev_priv->ring_rptr, dev);
1957 dev_priv->ring_rptr = NULL;
1958 }
1959 if (dev->agp_buffer_map != NULL) {
1960 drm_legacy_ioremapfree(dev->agp_buffer_map, dev);
1961 dev->agp_buffer_map = NULL;
1962 }
1963 } else
1964#endif
1965 {
1966
1967 if (dev_priv->gart_info.bus_addr)
1968 r600_page_table_cleanup(dev, &dev_priv->gart_info);
1969
1970 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB) {
1971 drm_legacy_ioremapfree(&dev_priv->gart_info.mapping, dev);
1972 dev_priv->gart_info.addr = NULL;
1973 }
1974 }
1975 /* only clear to the start of flags */
1976 memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1977
1978 return 0;
1979}
1980
1981int r600_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init,
1982 struct drm_file *file_priv)
1983{
1984 drm_radeon_private_t *dev_priv = dev->dev_private;
1985 struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv;
1986
1987 DRM_DEBUG("\n");
1988
1989 mutex_init(&dev_priv->cs_mutex);
1990 r600_cs_legacy_init();
1991 /* if we require new memory map but we don't have it fail */
1992 if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
1993 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
1994 r600_do_cleanup_cp(dev);
1995 return -EINVAL;
1996 }
1997
1998 if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) {
1999 DRM_DEBUG("Forcing AGP card to PCI mode\n");
2000 dev_priv->flags &= ~RADEON_IS_AGP;
2001 /* The writeback test succeeds, but when writeback is enabled,
2002 * the ring buffer read ptr update fails after first 128 bytes.
2003 */
2004 radeon_no_wb = 1;
2005 } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE))
2006 && !init->is_pci) {
2007 DRM_DEBUG("Restoring AGP flag\n");
2008 dev_priv->flags |= RADEON_IS_AGP;
2009 }
2010
2011 dev_priv->usec_timeout = init->usec_timeout;
2012 if (dev_priv->usec_timeout < 1 ||
2013 dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
2014 DRM_DEBUG("TIMEOUT problem!\n");
2015 r600_do_cleanup_cp(dev);
2016 return -EINVAL;
2017 }
2018
2019 /* Enable vblank on CRTC1 for older X servers
2020 */
2021 dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
2022 dev_priv->do_boxes = 0;
2023 dev_priv->cp_mode = init->cp_mode;
2024
2025 /* We don't support anything other than bus-mastering ring mode,
2026 * but the ring can be in either AGP or PCI space for the ring
2027 * read pointer.
2028 */
2029 if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
2030 (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
2031 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
2032 r600_do_cleanup_cp(dev);
2033 return -EINVAL;
2034 }
2035
2036 switch (init->fb_bpp) {
2037 case 16:
2038 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
2039 break;
2040 case 32:
2041 default:
2042 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
2043 break;
2044 }
2045 dev_priv->front_offset = init->front_offset;
2046 dev_priv->front_pitch = init->front_pitch;
2047 dev_priv->back_offset = init->back_offset;
2048 dev_priv->back_pitch = init->back_pitch;
2049
2050 dev_priv->ring_offset = init->ring_offset;
2051 dev_priv->ring_rptr_offset = init->ring_rptr_offset;
2052 dev_priv->buffers_offset = init->buffers_offset;
2053 dev_priv->gart_textures_offset = init->gart_textures_offset;
2054
2055 master_priv->sarea = drm_legacy_getsarea(dev);
2056 if (!master_priv->sarea) {
2057 DRM_ERROR("could not find sarea!\n");
2058 r600_do_cleanup_cp(dev);
2059 return -EINVAL;
2060 }
2061
2062 dev_priv->cp_ring = drm_legacy_findmap(dev, init->ring_offset);
2063 if (!dev_priv->cp_ring) {
2064 DRM_ERROR("could not find cp ring region!\n");
2065 r600_do_cleanup_cp(dev);
2066 return -EINVAL;
2067 }
2068 dev_priv->ring_rptr = drm_legacy_findmap(dev, init->ring_rptr_offset);
2069 if (!dev_priv->ring_rptr) {
2070 DRM_ERROR("could not find ring read pointer!\n");
2071 r600_do_cleanup_cp(dev);
2072 return -EINVAL;
2073 }
2074 dev->agp_buffer_token = init->buffers_offset;
2075 dev->agp_buffer_map = drm_legacy_findmap(dev, init->buffers_offset);
2076 if (!dev->agp_buffer_map) {
2077 DRM_ERROR("could not find dma buffer region!\n");
2078 r600_do_cleanup_cp(dev);
2079 return -EINVAL;
2080 }
2081
2082 if (init->gart_textures_offset) {
2083 dev_priv->gart_textures =
2084 drm_legacy_findmap(dev, init->gart_textures_offset);
2085 if (!dev_priv->gart_textures) {
2086 DRM_ERROR("could not find GART texture region!\n");
2087 r600_do_cleanup_cp(dev);
2088 return -EINVAL;
2089 }
2090 }
2091
2092#if IS_ENABLED(CONFIG_AGP)
2093 /* XXX */
2094 if (dev_priv->flags & RADEON_IS_AGP) {
2095 drm_legacy_ioremap_wc(dev_priv->cp_ring, dev);
2096 drm_legacy_ioremap_wc(dev_priv->ring_rptr, dev);
2097 drm_legacy_ioremap_wc(dev->agp_buffer_map, dev);
2098 if (!dev_priv->cp_ring->handle ||
2099 !dev_priv->ring_rptr->handle ||
2100 !dev->agp_buffer_map->handle) {
2101 DRM_ERROR("could not find ioremap agp regions!\n");
2102 r600_do_cleanup_cp(dev);
2103 return -EINVAL;
2104 }
2105 } else
2106#endif
2107 {
2108 dev_priv->cp_ring->handle = (void *)(unsigned long)dev_priv->cp_ring->offset;
2109 dev_priv->ring_rptr->handle =
2110 (void *)(unsigned long)dev_priv->ring_rptr->offset;
2111 dev->agp_buffer_map->handle =
2112 (void *)(unsigned long)dev->agp_buffer_map->offset;
2113
2114 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
2115 dev_priv->cp_ring->handle);
2116 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
2117 dev_priv->ring_rptr->handle);
2118 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
2119 dev->agp_buffer_map->handle);
2120 }
2121
2122 dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 24;
2123 dev_priv->fb_size =
2124 (((radeon_read_fb_location(dev_priv) & 0xffff0000u) << 8) + 0x1000000)
2125 - dev_priv->fb_location;
2126
2127 dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
2128 ((dev_priv->front_offset
2129 + dev_priv->fb_location) >> 10));
2130
2131 dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
2132 ((dev_priv->back_offset
2133 + dev_priv->fb_location) >> 10));
2134
2135 dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
2136 ((dev_priv->depth_offset
2137 + dev_priv->fb_location) >> 10));
2138
2139 dev_priv->gart_size = init->gart_size;
2140
2141 /* New let's set the memory map ... */
2142 if (dev_priv->new_memmap) {
2143 u32 base = 0;
2144
2145 DRM_INFO("Setting GART location based on new memory map\n");
2146
2147 /* If using AGP, try to locate the AGP aperture at the same
2148 * location in the card and on the bus, though we have to
2149 * align it down.
2150 */
2151#if IS_ENABLED(CONFIG_AGP)
2152 /* XXX */
2153 if (dev_priv->flags & RADEON_IS_AGP) {
2154 base = dev->agp->base;
2155 /* Check if valid */
2156 if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location &&
2157 base < (dev_priv->fb_location + dev_priv->fb_size - 1)) {
2158 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n",
2159 dev->agp->base);
2160 base = 0;
2161 }
2162 }
2163#endif
2164 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */
2165 if (base == 0) {
2166 base = dev_priv->fb_location + dev_priv->fb_size;
2167 if (base < dev_priv->fb_location ||
2168 ((base + dev_priv->gart_size) & 0xfffffffful) < base)
2169 base = dev_priv->fb_location
2170 - dev_priv->gart_size;
2171 }
2172 dev_priv->gart_vm_start = base & 0xffc00000u;
2173 if (dev_priv->gart_vm_start != base)
2174 DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
2175 base, dev_priv->gart_vm_start);
2176 }
2177
2178#if IS_ENABLED(CONFIG_AGP)
2179 /* XXX */
2180 if (dev_priv->flags & RADEON_IS_AGP)
2181 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
2182 - dev->agp->base
2183 + dev_priv->gart_vm_start);
2184 else
2185#endif
2186 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
2187 - (unsigned long)dev->sg->virtual
2188 + dev_priv->gart_vm_start);
2189
2190 DRM_DEBUG("fb 0x%08x size %d\n",
2191 (unsigned int) dev_priv->fb_location,
2192 (unsigned int) dev_priv->fb_size);
2193 DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
2194 DRM_DEBUG("dev_priv->gart_vm_start 0x%08x\n",
2195 (unsigned int) dev_priv->gart_vm_start);
2196 DRM_DEBUG("dev_priv->gart_buffers_offset 0x%08lx\n",
2197 dev_priv->gart_buffers_offset);
2198
2199 dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
2200 dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
2201 + init->ring_size / sizeof(u32));
2202 dev_priv->ring.size = init->ring_size;
2203 dev_priv->ring.size_l2qw = order_base_2(init->ring_size / 8);
2204
2205 dev_priv->ring.rptr_update = /* init->rptr_update */ 4096;
2206 dev_priv->ring.rptr_update_l2qw = order_base_2(/* init->rptr_update */ 4096 / 8);
2207
2208 dev_priv->ring.fetch_size = /* init->fetch_size */ 32;
2209 dev_priv->ring.fetch_size_l2ow = order_base_2(/* init->fetch_size */ 32 / 16);
2210
2211 dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
2212
2213 dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
2214
2215#if IS_ENABLED(CONFIG_AGP)
2216 if (dev_priv->flags & RADEON_IS_AGP) {
2217 /* XXX turn off pcie gart */
2218 } else
2219#endif
2220 {
2221 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
2222 /* if we have an offset set from userspace */
2223 if (!dev_priv->pcigart_offset_set) {
2224 DRM_ERROR("Need gart offset from userspace\n");
2225 r600_do_cleanup_cp(dev);
2226 return -EINVAL;
2227 }
2228
2229 DRM_DEBUG("Using gart offset 0x%08lx\n", dev_priv->pcigart_offset);
2230
2231 dev_priv->gart_info.bus_addr =
2232 dev_priv->pcigart_offset + dev_priv->fb_location;
2233 dev_priv->gart_info.mapping.offset =
2234 dev_priv->pcigart_offset + dev_priv->fb_aper_offset;
2235 dev_priv->gart_info.mapping.size =
2236 dev_priv->gart_info.table_size;
2237
2238 drm_legacy_ioremap_wc(&dev_priv->gart_info.mapping, dev);
2239 if (!dev_priv->gart_info.mapping.handle) {
2240 DRM_ERROR("ioremap failed.\n");
2241 r600_do_cleanup_cp(dev);
2242 return -EINVAL;
2243 }
2244
2245 dev_priv->gart_info.addr =
2246 dev_priv->gart_info.mapping.handle;
2247
2248 DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
2249 dev_priv->gart_info.addr,
2250 dev_priv->pcigart_offset);
2251
2252 if (!r600_page_table_init(dev)) {
2253 DRM_ERROR("Failed to init GART table\n");
2254 r600_do_cleanup_cp(dev);
2255 return -EINVAL;
2256 }
2257
2258 if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770))
2259 r700_vm_init(dev);
2260 else
2261 r600_vm_init(dev);
2262 }
2263
2264 if (!dev_priv->me_fw || !dev_priv->pfp_fw) {
2265 int err = r600_cp_init_microcode(dev_priv);
2266 if (err) {
2267 DRM_ERROR("Failed to load firmware!\n");
2268 r600_do_cleanup_cp(dev);
2269 return err;
2270 }
2271 }
2272 if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770))
2273 r700_cp_load_microcode(dev_priv);
2274 else
2275 r600_cp_load_microcode(dev_priv);
2276
2277 r600_cp_init_ring_buffer(dev, dev_priv, file_priv);
2278
2279 dev_priv->last_buf = 0;
2280
2281 r600_do_engine_reset(dev);
2282 r600_test_writeback(dev_priv);
2283
2284 return 0;
2285}
2286
2287int r600_do_resume_cp(struct drm_device *dev, struct drm_file *file_priv)
2288{
2289 drm_radeon_private_t *dev_priv = dev->dev_private;
2290
2291 DRM_DEBUG("\n");
2292 if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)) {
2293 r700_vm_init(dev);
2294 r700_cp_load_microcode(dev_priv);
2295 } else {
2296 r600_vm_init(dev);
2297 r600_cp_load_microcode(dev_priv);
2298 }
2299 r600_cp_init_ring_buffer(dev, dev_priv, file_priv);
2300 r600_do_engine_reset(dev);
2301
2302 return 0;
2303}
2304
2305/* Wait for the CP to go idle.
2306 */
2307int r600_do_cp_idle(drm_radeon_private_t *dev_priv)
2308{
2309 RING_LOCALS;
2310 DRM_DEBUG("\n");
2311
2312 BEGIN_RING(5);
2313 OUT_RING(CP_PACKET3(R600_IT_EVENT_WRITE, 0));
2314 OUT_RING(R600_CACHE_FLUSH_AND_INV_EVENT);
2315 /* wait for 3D idle clean */
2316 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1));
2317 OUT_RING((R600_WAIT_UNTIL - R600_SET_CONFIG_REG_OFFSET) >> 2);
2318 OUT_RING(RADEON_WAIT_3D_IDLE | RADEON_WAIT_3D_IDLECLEAN);
2319
2320 ADVANCE_RING();
2321 COMMIT_RING();
2322
2323 return r600_do_wait_for_idle(dev_priv);
2324}
2325
2326/* Start the Command Processor.
2327 */
2328void r600_do_cp_start(drm_radeon_private_t *dev_priv)
2329{
2330 u32 cp_me;
2331 RING_LOCALS;
2332 DRM_DEBUG("\n");
2333
2334 BEGIN_RING(7);
2335 OUT_RING(CP_PACKET3(R600_IT_ME_INITIALIZE, 5));
2336 OUT_RING(0x00000001);
2337 if (((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV770))
2338 OUT_RING(0x00000003);
2339 else
2340 OUT_RING(0x00000000);
2341 OUT_RING((dev_priv->r600_max_hw_contexts - 1));
2342 OUT_RING(R600_ME_INITIALIZE_DEVICE_ID(1));
2343 OUT_RING(0x00000000);
2344 OUT_RING(0x00000000);
2345 ADVANCE_RING();
2346 COMMIT_RING();
2347
2348 /* set the mux and reset the halt bit */
2349 cp_me = 0xff;
2350 RADEON_WRITE(R600_CP_ME_CNTL, cp_me);
2351
2352 dev_priv->cp_running = 1;
2353
2354}
2355
2356void r600_do_cp_reset(drm_radeon_private_t *dev_priv)
2357{
2358 u32 cur_read_ptr;
2359 DRM_DEBUG("\n");
2360
2361 cur_read_ptr = RADEON_READ(R600_CP_RB_RPTR);
2362 RADEON_WRITE(R600_CP_RB_WPTR, cur_read_ptr);
2363 SET_RING_HEAD(dev_priv, cur_read_ptr);
2364 dev_priv->ring.tail = cur_read_ptr;
2365}
2366
2367void r600_do_cp_stop(drm_radeon_private_t *dev_priv)
2368{
2369 uint32_t cp_me;
2370
2371 DRM_DEBUG("\n");
2372
2373 cp_me = 0xff | R600_CP_ME_HALT;
2374
2375 RADEON_WRITE(R600_CP_ME_CNTL, cp_me);
2376
2377 dev_priv->cp_running = 0;
2378}
2379
2380int r600_cp_dispatch_indirect(struct drm_device *dev,
2381 struct drm_buf *buf, int start, int end)
2382{
2383 drm_radeon_private_t *dev_priv = dev->dev_private;
2384 RING_LOCALS;
2385
2386 if (start != end) {
2387 unsigned long offset = (dev_priv->gart_buffers_offset
2388 + buf->offset + start);
2389 int dwords = (end - start + 3) / sizeof(u32);
2390
2391 DRM_DEBUG("dwords:%d\n", dwords);
2392 DRM_DEBUG("offset 0x%lx\n", offset);
2393
2394
2395 /* Indirect buffer data must be a multiple of 16 dwords.
2396 * pad the data with a Type-2 CP packet.
2397 */
2398 while (dwords & 0xf) {
2399 u32 *data = (u32 *)
2400 ((char *)dev->agp_buffer_map->handle
2401 + buf->offset + start);
2402 data[dwords++] = RADEON_CP_PACKET2;
2403 }
2404
2405 /* Fire off the indirect buffer */
2406 BEGIN_RING(4);
2407 OUT_RING(CP_PACKET3(R600_IT_INDIRECT_BUFFER, 2));
2408 OUT_RING((offset & 0xfffffffc));
2409 OUT_RING((upper_32_bits(offset) & 0xff));
2410 OUT_RING(dwords);
2411 ADVANCE_RING();
2412 }
2413
2414 return 0;
2415}
2416
2417void r600_cp_dispatch_swap(struct drm_device *dev, struct drm_file *file_priv)
2418{
2419 drm_radeon_private_t *dev_priv = dev->dev_private;
2420 struct drm_master *master = file_priv->master;
2421 struct drm_radeon_master_private *master_priv = master->driver_priv;
2422 drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv;
2423 int nbox = sarea_priv->nbox;
2424 struct drm_clip_rect *pbox = sarea_priv->boxes;
2425 int i, cpp, src_pitch, dst_pitch;
2426 uint64_t src, dst;
2427 RING_LOCALS;
2428 DRM_DEBUG("\n");
2429
2430 if (dev_priv->color_fmt == RADEON_COLOR_FORMAT_ARGB8888)
2431 cpp = 4;
2432 else
2433 cpp = 2;
2434
2435 if (sarea_priv->pfCurrentPage == 0) {
2436 src_pitch = dev_priv->back_pitch;
2437 dst_pitch = dev_priv->front_pitch;
2438 src = dev_priv->back_offset + dev_priv->fb_location;
2439 dst = dev_priv->front_offset + dev_priv->fb_location;
2440 } else {
2441 src_pitch = dev_priv->front_pitch;
2442 dst_pitch = dev_priv->back_pitch;
2443 src = dev_priv->front_offset + dev_priv->fb_location;
2444 dst = dev_priv->back_offset + dev_priv->fb_location;
2445 }
2446
2447 if (r600_prepare_blit_copy(dev, file_priv)) {
2448 DRM_ERROR("unable to allocate vertex buffer for swap buffer\n");
2449 return;
2450 }
2451 for (i = 0; i < nbox; i++) {
2452 int x = pbox[i].x1;
2453 int y = pbox[i].y1;
2454 int w = pbox[i].x2 - x;
2455 int h = pbox[i].y2 - y;
2456
2457 DRM_DEBUG("%d,%d-%d,%d\n", x, y, w, h);
2458
2459 r600_blit_swap(dev,
2460 src, dst,
2461 x, y, x, y, w, h,
2462 src_pitch, dst_pitch, cpp);
2463 }
2464 r600_done_blit_copy(dev);
2465
2466 /* Increment the frame counter. The client-side 3D driver must
2467 * throttle the framerate by waiting for this value before
2468 * performing the swapbuffer ioctl.
2469 */
2470 sarea_priv->last_frame++;
2471
2472 BEGIN_RING(3);
2473 R600_FRAME_AGE(sarea_priv->last_frame);
2474 ADVANCE_RING();
2475}
2476
2477int r600_cp_dispatch_texture(struct drm_device *dev,
2478 struct drm_file *file_priv,
2479 drm_radeon_texture_t *tex,
2480 drm_radeon_tex_image_t *image)
2481{
2482 drm_radeon_private_t *dev_priv = dev->dev_private;
2483 struct drm_buf *buf;
2484 u32 *buffer;
2485 const u8 __user *data;
2486 unsigned int size, pass_size;
2487 u64 src_offset, dst_offset;
2488
2489 if (!radeon_check_offset(dev_priv, tex->offset)) {
2490 DRM_ERROR("Invalid destination offset\n");
2491 return -EINVAL;
2492 }
2493
2494 /* this might fail for zero-sized uploads - are those illegal? */
2495 if (!radeon_check_offset(dev_priv, tex->offset + tex->height * tex->pitch - 1)) {
2496 DRM_ERROR("Invalid final destination offset\n");
2497 return -EINVAL;
2498 }
2499
2500 size = tex->height * tex->pitch;
2501
2502 if (size == 0)
2503 return 0;
2504
2505 dst_offset = tex->offset;
2506
2507 if (r600_prepare_blit_copy(dev, file_priv)) {
2508 DRM_ERROR("unable to allocate vertex buffer for swap buffer\n");
2509 return -EAGAIN;
2510 }
2511 do {
2512 data = (const u8 __user *)image->data;
2513 pass_size = size;
2514
2515 buf = radeon_freelist_get(dev);
2516 if (!buf) {
2517 DRM_DEBUG("EAGAIN\n");
2518 if (copy_to_user(tex->image, image, sizeof(*image)))
2519 return -EFAULT;
2520 return -EAGAIN;
2521 }
2522
2523 if (pass_size > buf->total)
2524 pass_size = buf->total;
2525
2526 /* Dispatch the indirect buffer.
2527 */
2528 buffer =
2529 (u32 *) ((char *)dev->agp_buffer_map->handle + buf->offset);
2530
2531 if (copy_from_user(buffer, data, pass_size)) {
2532 DRM_ERROR("EFAULT on pad, %d bytes\n", pass_size);
2533 return -EFAULT;
2534 }
2535
2536 buf->file_priv = file_priv;
2537 buf->used = pass_size;
2538 src_offset = dev_priv->gart_buffers_offset + buf->offset;
2539
2540 r600_blit_copy(dev, src_offset, dst_offset, pass_size);
2541
2542 radeon_cp_discard_buffer(dev, file_priv->master, buf);
2543
2544 /* Update the input parameters for next time */
2545 image->data = (const u8 __user *)image->data + pass_size;
2546 dst_offset += pass_size;
2547 size -= pass_size;
2548 } while (size > 0);
2549 r600_done_blit_copy(dev);
2550
2551 return 0;
2552}
2553
2554/*
2555 * Legacy cs ioctl
2556 */
2557static u32 radeon_cs_id_get(struct drm_radeon_private *radeon)
2558{
2559 /* FIXME: check if wrap affect last reported wrap & sequence */
2560 radeon->cs_id_scnt = (radeon->cs_id_scnt + 1) & 0x00FFFFFF;
2561 if (!radeon->cs_id_scnt) {
2562 /* increment wrap counter */
2563 radeon->cs_id_wcnt += 0x01000000;
2564 /* valid sequence counter start at 1 */
2565 radeon->cs_id_scnt = 1;
2566 }
2567 return (radeon->cs_id_scnt | radeon->cs_id_wcnt);
2568}
2569
2570static void r600_cs_id_emit(drm_radeon_private_t *dev_priv, u32 *id)
2571{
2572 RING_LOCALS;
2573
2574 *id = radeon_cs_id_get(dev_priv);
2575
2576 /* SCRATCH 2 */
2577 BEGIN_RING(3);
2578 R600_CLEAR_AGE(*id);
2579 ADVANCE_RING();
2580 COMMIT_RING();
2581}
2582
2583static int r600_ib_get(struct drm_device *dev,
2584 struct drm_file *fpriv,
2585 struct drm_buf **buffer)
2586{
2587 struct drm_buf *buf;
2588
2589 *buffer = NULL;
2590 buf = radeon_freelist_get(dev);
2591 if (!buf) {
2592 return -EBUSY;
2593 }
2594 buf->file_priv = fpriv;
2595 *buffer = buf;
2596 return 0;
2597}
2598
2599static void r600_ib_free(struct drm_device *dev, struct drm_buf *buf,
2600 struct drm_file *fpriv, int l, int r)
2601{
2602 drm_radeon_private_t *dev_priv = dev->dev_private;
2603
2604 if (buf) {
2605 if (!r)
2606 r600_cp_dispatch_indirect(dev, buf, 0, l * 4);
2607 radeon_cp_discard_buffer(dev, fpriv->master, buf);
2608 COMMIT_RING();
2609 }
2610}
2611
2612int r600_cs_legacy_ioctl(struct drm_device *dev, void *data, struct drm_file *fpriv)
2613{
2614 struct drm_radeon_private *dev_priv = dev->dev_private;
2615 struct drm_radeon_cs *cs = data;
2616 struct drm_buf *buf;
2617 unsigned family;
2618 int l, r = 0;
2619 u32 *ib, cs_id = 0;
2620
2621 if (dev_priv == NULL) {
2622 DRM_ERROR("called with no initialization\n");
2623 return -EINVAL;
2624 }
2625 family = dev_priv->flags & RADEON_FAMILY_MASK;
2626 if (family < CHIP_R600) {
2627 DRM_ERROR("cs ioctl valid only for R6XX & R7XX in legacy mode\n");
2628 return -EINVAL;
2629 }
2630 mutex_lock(&dev_priv->cs_mutex);
2631 /* get ib */
2632 r = r600_ib_get(dev, fpriv, &buf);
2633 if (r) {
2634 DRM_ERROR("ib_get failed\n");
2635 goto out;
2636 }
2637 ib = dev->agp_buffer_map->handle + buf->offset;
2638 /* now parse command stream */
2639 r = r600_cs_legacy(dev, data, fpriv, family, ib, &l);
2640 if (r) {
2641 goto out;
2642 }
2643
2644out:
2645 r600_ib_free(dev, buf, fpriv, l, r);
2646 /* emit cs id sequence */
2647 r600_cs_id_emit(dev_priv, &cs_id);
2648 cs->cs_id = cs_id;
2649 mutex_unlock(&dev_priv->cs_mutex);
2650 return r;
2651}
2652
2653void r600_cs_legacy_get_tiling_conf(struct drm_device *dev, u32 *npipes, u32 *nbanks, u32 *group_size)
2654{
2655 struct drm_radeon_private *dev_priv = dev->dev_private;
2656
2657 *npipes = dev_priv->r600_npipes;
2658 *nbanks = dev_priv->r600_nbanks;
2659 *group_size = dev_priv->r600_group_size;
2660}
diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c
index acc1f99c84d9..2f36fa1576e0 100644
--- a/drivers/gpu/drm/radeon/r600_cs.c
+++ b/drivers/gpu/drm/radeon/r600_cs.c
@@ -2328,101 +2328,6 @@ int r600_cs_parse(struct radeon_cs_parser *p)
2328 return 0; 2328 return 0;
2329} 2329}
2330 2330
2331#ifdef CONFIG_DRM_RADEON_UMS
2332
2333/**
2334 * cs_parser_fini() - clean parser states
2335 * @parser: parser structure holding parsing context.
2336 * @error: error number
2337 *
2338 * If error is set than unvalidate buffer, otherwise just free memory
2339 * used by parsing context.
2340 **/
2341static void r600_cs_parser_fini(struct radeon_cs_parser *parser, int error)
2342{
2343 unsigned i;
2344
2345 kfree(parser->relocs);
2346 for (i = 0; i < parser->nchunks; i++)
2347 drm_free_large(parser->chunks[i].kdata);
2348 kfree(parser->chunks);
2349 kfree(parser->chunks_array);
2350}
2351
2352static int r600_cs_parser_relocs_legacy(struct radeon_cs_parser *p)
2353{
2354 if (p->chunk_relocs == NULL) {
2355 return 0;
2356 }
2357 p->relocs = kzalloc(sizeof(struct radeon_bo_list), GFP_KERNEL);
2358 if (p->relocs == NULL) {
2359 return -ENOMEM;
2360 }
2361 return 0;
2362}
2363
2364int r600_cs_legacy(struct drm_device *dev, void *data, struct drm_file *filp,
2365 unsigned family, u32 *ib, int *l)
2366{
2367 struct radeon_cs_parser parser;
2368 struct radeon_cs_chunk *ib_chunk;
2369 struct r600_cs_track *track;
2370 int r;
2371
2372 /* initialize tracker */
2373 track = kzalloc(sizeof(*track), GFP_KERNEL);
2374 if (track == NULL)
2375 return -ENOMEM;
2376 r600_cs_track_init(track);
2377 r600_cs_legacy_get_tiling_conf(dev, &track->npipes, &track->nbanks, &track->group_size);
2378 /* initialize parser */
2379 memset(&parser, 0, sizeof(struct radeon_cs_parser));
2380 parser.filp = filp;
2381 parser.dev = &dev->pdev->dev;
2382 parser.rdev = NULL;
2383 parser.family = family;
2384 parser.track = track;
2385 parser.ib.ptr = ib;
2386 r = radeon_cs_parser_init(&parser, data);
2387 if (r) {
2388 DRM_ERROR("Failed to initialize parser !\n");
2389 r600_cs_parser_fini(&parser, r);
2390 return r;
2391 }
2392 r = r600_cs_parser_relocs_legacy(&parser);
2393 if (r) {
2394 DRM_ERROR("Failed to parse relocation !\n");
2395 r600_cs_parser_fini(&parser, r);
2396 return r;
2397 }
2398 /* Copy the packet into the IB, the parser will read from the
2399 * input memory (cached) and write to the IB (which can be
2400 * uncached). */
2401 ib_chunk = parser.chunk_ib;
2402 parser.ib.length_dw = ib_chunk->length_dw;
2403 *l = parser.ib.length_dw;
2404 if (copy_from_user(ib, ib_chunk->user_ptr, ib_chunk->length_dw * 4)) {
2405 r = -EFAULT;
2406 r600_cs_parser_fini(&parser, r);
2407 return r;
2408 }
2409 r = r600_cs_parse(&parser);
2410 if (r) {
2411 DRM_ERROR("Invalid command stream !\n");
2412 r600_cs_parser_fini(&parser, r);
2413 return r;
2414 }
2415 r600_cs_parser_fini(&parser, r);
2416 return r;
2417}
2418
2419void r600_cs_legacy_init(void)
2420{
2421 r600_nomm = 1;
2422}
2423
2424#endif
2425
2426/* 2331/*
2427 * DMA 2332 * DMA
2428 */ 2333 */
diff --git a/drivers/gpu/drm/radeon/radeon_cp.c b/drivers/gpu/drm/radeon/radeon_cp.c
deleted file mode 100644
index 500287eff55d..000000000000
--- a/drivers/gpu/drm/radeon/radeon_cp.c
+++ /dev/null
@@ -1,2243 +0,0 @@
1/* radeon_cp.c -- CP support for Radeon -*- linux-c -*- */
2/*
3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5 * Copyright 2007 Advanced Micro Devices, Inc.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 *
27 * Authors:
28 * Kevin E. Martin <martin@valinux.com>
29 * Gareth Hughes <gareth@valinux.com>
30 *
31 * ------------------------ This file is DEPRECATED! -------------------------
32 */
33
34#include <linux/module.h>
35
36#include <drm/drmP.h>
37#include <drm/radeon_drm.h>
38#include "radeon_drv.h"
39#include "r300_reg.h"
40
41#define RADEON_FIFO_DEBUG 0
42
43/* Firmware Names */
44#define FIRMWARE_R100 "radeon/R100_cp.bin"
45#define FIRMWARE_R200 "radeon/R200_cp.bin"
46#define FIRMWARE_R300 "radeon/R300_cp.bin"
47#define FIRMWARE_R420 "radeon/R420_cp.bin"
48#define FIRMWARE_RS690 "radeon/RS690_cp.bin"
49#define FIRMWARE_RS600 "radeon/RS600_cp.bin"
50#define FIRMWARE_R520 "radeon/R520_cp.bin"
51
52MODULE_FIRMWARE(FIRMWARE_R100);
53MODULE_FIRMWARE(FIRMWARE_R200);
54MODULE_FIRMWARE(FIRMWARE_R300);
55MODULE_FIRMWARE(FIRMWARE_R420);
56MODULE_FIRMWARE(FIRMWARE_RS690);
57MODULE_FIRMWARE(FIRMWARE_RS600);
58MODULE_FIRMWARE(FIRMWARE_R520);
59
60static int radeon_do_cleanup_cp(struct drm_device * dev);
61static void radeon_do_cp_start(drm_radeon_private_t * dev_priv);
62
63u32 radeon_read_ring_rptr(drm_radeon_private_t *dev_priv, u32 off)
64{
65 u32 val;
66
67 if (dev_priv->flags & RADEON_IS_AGP) {
68 val = DRM_READ32(dev_priv->ring_rptr, off);
69 } else {
70 val = *(((volatile u32 *)
71 dev_priv->ring_rptr->handle) +
72 (off / sizeof(u32)));
73 val = le32_to_cpu(val);
74 }
75 return val;
76}
77
78u32 radeon_get_ring_head(drm_radeon_private_t *dev_priv)
79{
80 if (dev_priv->writeback_works)
81 return radeon_read_ring_rptr(dev_priv, 0);
82 else {
83 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
84 return RADEON_READ(R600_CP_RB_RPTR);
85 else
86 return RADEON_READ(RADEON_CP_RB_RPTR);
87 }
88}
89
90void radeon_write_ring_rptr(drm_radeon_private_t *dev_priv, u32 off, u32 val)
91{
92 if (dev_priv->flags & RADEON_IS_AGP)
93 DRM_WRITE32(dev_priv->ring_rptr, off, val);
94 else
95 *(((volatile u32 *) dev_priv->ring_rptr->handle) +
96 (off / sizeof(u32))) = cpu_to_le32(val);
97}
98
99void radeon_set_ring_head(drm_radeon_private_t *dev_priv, u32 val)
100{
101 radeon_write_ring_rptr(dev_priv, 0, val);
102}
103
104u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index)
105{
106 if (dev_priv->writeback_works) {
107 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
108 return radeon_read_ring_rptr(dev_priv,
109 R600_SCRATCHOFF(index));
110 else
111 return radeon_read_ring_rptr(dev_priv,
112 RADEON_SCRATCHOFF(index));
113 } else {
114 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
115 return RADEON_READ(R600_SCRATCH_REG0 + 4*index);
116 else
117 return RADEON_READ(RADEON_SCRATCH_REG0 + 4*index);
118 }
119}
120
121static u32 R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
122{
123 u32 ret;
124 RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff));
125 ret = RADEON_READ(R520_MC_IND_DATA);
126 RADEON_WRITE(R520_MC_IND_INDEX, 0);
127 return ret;
128}
129
130static u32 RS480_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
131{
132 u32 ret;
133 RADEON_WRITE(RS480_NB_MC_INDEX, addr & 0xff);
134 ret = RADEON_READ(RS480_NB_MC_DATA);
135 RADEON_WRITE(RS480_NB_MC_INDEX, 0xff);
136 return ret;
137}
138
139static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
140{
141 u32 ret;
142 RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK));
143 ret = RADEON_READ(RS690_MC_DATA);
144 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_MASK);
145 return ret;
146}
147
148static u32 RS600_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
149{
150 u32 ret;
151 RADEON_WRITE(RS600_MC_INDEX, ((addr & RS600_MC_ADDR_MASK) |
152 RS600_MC_IND_CITF_ARB0));
153 ret = RADEON_READ(RS600_MC_DATA);
154 return ret;
155}
156
157static u32 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
158{
159 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
160 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
161 return RS690_READ_MCIND(dev_priv, addr);
162 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
163 return RS600_READ_MCIND(dev_priv, addr);
164 else
165 return RS480_READ_MCIND(dev_priv, addr);
166}
167
168u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
169{
170
171 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
172 return RADEON_READ(R700_MC_VM_FB_LOCATION);
173 else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
174 return RADEON_READ(R600_MC_VM_FB_LOCATION);
175 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
176 return R500_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION);
177 else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
178 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
179 return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION);
180 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
181 return RS600_READ_MCIND(dev_priv, RS600_MC_FB_LOCATION);
182 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
183 return R500_READ_MCIND(dev_priv, R520_MC_FB_LOCATION);
184 else
185 return RADEON_READ(RADEON_MC_FB_LOCATION);
186}
187
188static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
189{
190 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
191 RADEON_WRITE(R700_MC_VM_FB_LOCATION, fb_loc);
192 else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
193 RADEON_WRITE(R600_MC_VM_FB_LOCATION, fb_loc);
194 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
195 R500_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc);
196 else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
197 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
198 RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc);
199 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
200 RS600_WRITE_MCIND(RS600_MC_FB_LOCATION, fb_loc);
201 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
202 R500_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc);
203 else
204 RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc);
205}
206
207void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc)
208{
209 /*R6xx/R7xx: AGP_TOP and BOT are actually 18 bits each */
210 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) {
211 RADEON_WRITE(R700_MC_VM_AGP_BOT, agp_loc & 0xffff); /* FIX ME */
212 RADEON_WRITE(R700_MC_VM_AGP_TOP, (agp_loc >> 16) & 0xffff);
213 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
214 RADEON_WRITE(R600_MC_VM_AGP_BOT, agp_loc & 0xffff); /* FIX ME */
215 RADEON_WRITE(R600_MC_VM_AGP_TOP, (agp_loc >> 16) & 0xffff);
216 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
217 R500_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc);
218 else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
219 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
220 RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc);
221 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
222 RS600_WRITE_MCIND(RS600_MC_AGP_LOCATION, agp_loc);
223 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
224 R500_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc);
225 else
226 RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc);
227}
228
229void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base)
230{
231 u32 agp_base_hi = upper_32_bits(agp_base);
232 u32 agp_base_lo = agp_base & 0xffffffff;
233 u32 r6xx_agp_base = (agp_base >> 22) & 0x3ffff;
234
235 /* R6xx/R7xx must be aligned to a 4MB boundary */
236 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
237 RADEON_WRITE(R700_MC_VM_AGP_BASE, r6xx_agp_base);
238 else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
239 RADEON_WRITE(R600_MC_VM_AGP_BASE, r6xx_agp_base);
240 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) {
241 R500_WRITE_MCIND(RV515_MC_AGP_BASE, agp_base_lo);
242 R500_WRITE_MCIND(RV515_MC_AGP_BASE_2, agp_base_hi);
243 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
244 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
245 RS690_WRITE_MCIND(RS690_MC_AGP_BASE, agp_base_lo);
246 RS690_WRITE_MCIND(RS690_MC_AGP_BASE_2, agp_base_hi);
247 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) {
248 RS600_WRITE_MCIND(RS600_AGP_BASE, agp_base_lo);
249 RS600_WRITE_MCIND(RS600_AGP_BASE_2, agp_base_hi);
250 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) {
251 R500_WRITE_MCIND(R520_MC_AGP_BASE, agp_base_lo);
252 R500_WRITE_MCIND(R520_MC_AGP_BASE_2, agp_base_hi);
253 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
254 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
255 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
256 RADEON_WRITE(RS480_AGP_BASE_2, agp_base_hi);
257 } else {
258 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
259 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R200)
260 RADEON_WRITE(RADEON_AGP_BASE_2, agp_base_hi);
261 }
262}
263
264void radeon_enable_bm(struct drm_radeon_private *dev_priv)
265{
266 u32 tmp;
267 /* Turn on bus mastering */
268 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
269 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
270 /* rs600/rs690/rs740 */
271 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
272 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
273 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV350) ||
274 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
275 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
276 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
277 /* r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
278 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
279 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
280 } /* PCIE cards appears to not need this */
281}
282
283static int RADEON_READ_PLL(struct drm_device * dev, int addr)
284{
285 drm_radeon_private_t *dev_priv = dev->dev_private;
286
287 RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
288 return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
289}
290
291static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
292{
293 RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff);
294 return RADEON_READ(RADEON_PCIE_DATA);
295}
296
297#if RADEON_FIFO_DEBUG
298static void radeon_status(drm_radeon_private_t * dev_priv)
299{
300 printk("%s:\n", __func__);
301 printk("RBBM_STATUS = 0x%08x\n",
302 (unsigned int)RADEON_READ(RADEON_RBBM_STATUS));
303 printk("CP_RB_RTPR = 0x%08x\n",
304 (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR));
305 printk("CP_RB_WTPR = 0x%08x\n",
306 (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR));
307 printk("AIC_CNTL = 0x%08x\n",
308 (unsigned int)RADEON_READ(RADEON_AIC_CNTL));
309 printk("AIC_STAT = 0x%08x\n",
310 (unsigned int)RADEON_READ(RADEON_AIC_STAT));
311 printk("AIC_PT_BASE = 0x%08x\n",
312 (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE));
313 printk("TLB_ADDR = 0x%08x\n",
314 (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR));
315 printk("TLB_DATA = 0x%08x\n",
316 (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA));
317}
318#endif
319
320/* ================================================================
321 * Engine, FIFO control
322 */
323
324static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
325{
326 u32 tmp;
327 int i;
328
329 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
330
331 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) {
332 tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT);
333 tmp |= RADEON_RB3D_DC_FLUSH_ALL;
334 RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);
335
336 for (i = 0; i < dev_priv->usec_timeout; i++) {
337 if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT)
338 & RADEON_RB3D_DC_BUSY)) {
339 return 0;
340 }
341 DRM_UDELAY(1);
342 }
343 } else {
344 /* don't flush or purge cache here or lockup */
345 return 0;
346 }
347
348#if RADEON_FIFO_DEBUG
349 DRM_ERROR("failed!\n");
350 radeon_status(dev_priv);
351#endif
352 return -EBUSY;
353}
354
355static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries)
356{
357 int i;
358
359 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
360
361 for (i = 0; i < dev_priv->usec_timeout; i++) {
362 int slots = (RADEON_READ(RADEON_RBBM_STATUS)
363 & RADEON_RBBM_FIFOCNT_MASK);
364 if (slots >= entries)
365 return 0;
366 DRM_UDELAY(1);
367 }
368 DRM_DEBUG("wait for fifo failed status : 0x%08X 0x%08X\n",
369 RADEON_READ(RADEON_RBBM_STATUS),
370 RADEON_READ(R300_VAP_CNTL_STATUS));
371
372#if RADEON_FIFO_DEBUG
373 DRM_ERROR("failed!\n");
374 radeon_status(dev_priv);
375#endif
376 return -EBUSY;
377}
378
379static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
380{
381 int i, ret;
382
383 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
384
385 ret = radeon_do_wait_for_fifo(dev_priv, 64);
386 if (ret)
387 return ret;
388
389 for (i = 0; i < dev_priv->usec_timeout; i++) {
390 if (!(RADEON_READ(RADEON_RBBM_STATUS)
391 & RADEON_RBBM_ACTIVE)) {
392 radeon_do_pixcache_flush(dev_priv);
393 return 0;
394 }
395 DRM_UDELAY(1);
396 }
397 DRM_DEBUG("wait idle failed status : 0x%08X 0x%08X\n",
398 RADEON_READ(RADEON_RBBM_STATUS),
399 RADEON_READ(R300_VAP_CNTL_STATUS));
400
401#if RADEON_FIFO_DEBUG
402 DRM_ERROR("failed!\n");
403 radeon_status(dev_priv);
404#endif
405 return -EBUSY;
406}
407
408static void radeon_init_pipes(struct drm_device *dev)
409{
410 drm_radeon_private_t *dev_priv = dev->dev_private;
411 uint32_t gb_tile_config, gb_pipe_sel = 0;
412
413 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) {
414 uint32_t z_pipe_sel = RADEON_READ(RV530_GB_PIPE_SELECT2);
415 if ((z_pipe_sel & 3) == 3)
416 dev_priv->num_z_pipes = 2;
417 else
418 dev_priv->num_z_pipes = 1;
419 } else
420 dev_priv->num_z_pipes = 1;
421
422 /* RS4xx/RS6xx/R4xx/R5xx */
423 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R420) {
424 gb_pipe_sel = RADEON_READ(R400_GB_PIPE_SELECT);
425 dev_priv->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1;
426 /* SE cards have 1 pipe */
427 if ((dev->pdev->device == 0x5e4c) ||
428 (dev->pdev->device == 0x5e4f))
429 dev_priv->num_gb_pipes = 1;
430 } else {
431 /* R3xx */
432 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300 &&
433 dev->pdev->device != 0x4144) ||
434 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350 &&
435 dev->pdev->device != 0x4148)) {
436 dev_priv->num_gb_pipes = 2;
437 } else {
438 /* RV3xx/R300 AD/R350 AH */
439 dev_priv->num_gb_pipes = 1;
440 }
441 }
442 DRM_INFO("Num pipes: %d\n", dev_priv->num_gb_pipes);
443
444 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 /*| R300_SUBPIXEL_1_16*/);
445
446 switch (dev_priv->num_gb_pipes) {
447 case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break;
448 case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break;
449 case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break;
450 default:
451 case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break;
452 }
453
454 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) {
455 RADEON_WRITE_PLL(R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4));
456 RADEON_WRITE(R300_SU_REG_DEST, ((1 << dev_priv->num_gb_pipes) - 1));
457 }
458 RADEON_WRITE(R300_GB_TILE_CONFIG, gb_tile_config);
459 radeon_do_wait_for_idle(dev_priv);
460 RADEON_WRITE(R300_DST_PIPE_CONFIG, RADEON_READ(R300_DST_PIPE_CONFIG) | R300_PIPE_AUTO_CONFIG);
461 RADEON_WRITE(R300_RB2D_DSTCACHE_MODE, (RADEON_READ(R300_RB2D_DSTCACHE_MODE) |
462 R300_DC_AUTOFLUSH_ENABLE |
463 R300_DC_DC_DISABLE_IGNORE_PE));
464
465
466}
467
468/* ================================================================
469 * CP control, initialization
470 */
471
472/* Load the microcode for the CP */
473static int radeon_cp_init_microcode(drm_radeon_private_t *dev_priv)
474{
475 struct platform_device *pdev;
476 const char *fw_name = NULL;
477 int err;
478
479 DRM_DEBUG("\n");
480
481 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
482 err = IS_ERR(pdev);
483 if (err) {
484 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
485 return -EINVAL;
486 }
487
488 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R100) ||
489 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV100) ||
490 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV200) ||
491 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS100) ||
492 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS200)) {
493 DRM_INFO("Loading R100 Microcode\n");
494 fw_name = FIRMWARE_R100;
495 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R200) ||
496 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV250) ||
497 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV280) ||
498 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS300)) {
499 DRM_INFO("Loading R200 Microcode\n");
500 fw_name = FIRMWARE_R200;
501 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
502 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350) ||
503 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV350) ||
504 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV380) ||
505 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
506 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
507 DRM_INFO("Loading R300 Microcode\n");
508 fw_name = FIRMWARE_R300;
509 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
510 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R423) ||
511 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV410)) {
512 DRM_INFO("Loading R400 Microcode\n");
513 fw_name = FIRMWARE_R420;
514 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
515 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
516 DRM_INFO("Loading RS690/RS740 Microcode\n");
517 fw_name = FIRMWARE_RS690;
518 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) {
519 DRM_INFO("Loading RS600 Microcode\n");
520 fw_name = FIRMWARE_RS600;
521 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) ||
522 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R520) ||
523 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) ||
524 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R580) ||
525 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV560) ||
526 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV570)) {
527 DRM_INFO("Loading R500 Microcode\n");
528 fw_name = FIRMWARE_R520;
529 }
530
531 err = request_firmware(&dev_priv->me_fw, fw_name, &pdev->dev);
532 platform_device_unregister(pdev);
533 if (err) {
534 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
535 fw_name);
536 } else if (dev_priv->me_fw->size % 8) {
537 printk(KERN_ERR
538 "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
539 dev_priv->me_fw->size, fw_name);
540 err = -EINVAL;
541 release_firmware(dev_priv->me_fw);
542 dev_priv->me_fw = NULL;
543 }
544 return err;
545}
546
547static void radeon_cp_load_microcode(drm_radeon_private_t *dev_priv)
548{
549 const __be32 *fw_data;
550 int i, size;
551
552 radeon_do_wait_for_idle(dev_priv);
553
554 if (dev_priv->me_fw) {
555 size = dev_priv->me_fw->size / 4;
556 fw_data = (const __be32 *)&dev_priv->me_fw->data[0];
557 RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
558 for (i = 0; i < size; i += 2) {
559 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
560 be32_to_cpup(&fw_data[i]));
561 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
562 be32_to_cpup(&fw_data[i + 1]));
563 }
564 }
565}
566
567/* Flush any pending commands to the CP. This should only be used just
568 * prior to a wait for idle, as it informs the engine that the command
569 * stream is ending.
570 */
571static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv)
572{
573 DRM_DEBUG("\n");
574#if 0
575 u32 tmp;
576
577 tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31);
578 RADEON_WRITE(RADEON_CP_RB_WPTR, tmp);
579#endif
580}
581
582/* Wait for the CP to go idle.
583 */
584int radeon_do_cp_idle(drm_radeon_private_t * dev_priv)
585{
586 RING_LOCALS;
587 DRM_DEBUG("\n");
588
589 BEGIN_RING(6);
590
591 RADEON_PURGE_CACHE();
592 RADEON_PURGE_ZCACHE();
593 RADEON_WAIT_UNTIL_IDLE();
594
595 ADVANCE_RING();
596 COMMIT_RING();
597
598 return radeon_do_wait_for_idle(dev_priv);
599}
600
601/* Start the Command Processor.
602 */
603static void radeon_do_cp_start(drm_radeon_private_t * dev_priv)
604{
605 RING_LOCALS;
606 DRM_DEBUG("\n");
607
608 radeon_do_wait_for_idle(dev_priv);
609
610 RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode);
611
612 dev_priv->cp_running = 1;
613
614 /* on r420, any DMA from CP to system memory while 2D is active
615 * can cause a hang. workaround is to queue a CP RESYNC token
616 */
617 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) {
618 BEGIN_RING(3);
619 OUT_RING(CP_PACKET0(R300_CP_RESYNC_ADDR, 1));
620 OUT_RING(5); /* scratch reg 5 */
621 OUT_RING(0xdeadbeef);
622 ADVANCE_RING();
623 COMMIT_RING();
624 }
625
626 BEGIN_RING(8);
627 /* isync can only be written through cp on r5xx write it here */
628 OUT_RING(CP_PACKET0(RADEON_ISYNC_CNTL, 0));
629 OUT_RING(RADEON_ISYNC_ANY2D_IDLE3D |
630 RADEON_ISYNC_ANY3D_IDLE2D |
631 RADEON_ISYNC_WAIT_IDLEGUI |
632 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
633 RADEON_PURGE_CACHE();
634 RADEON_PURGE_ZCACHE();
635 RADEON_WAIT_UNTIL_IDLE();
636 ADVANCE_RING();
637 COMMIT_RING();
638
639 dev_priv->track_flush |= RADEON_FLUSH_EMITED | RADEON_PURGE_EMITED;
640}
641
642/* Reset the Command Processor. This will not flush any pending
643 * commands, so you must wait for the CP command stream to complete
644 * before calling this routine.
645 */
646static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv)
647{
648 u32 cur_read_ptr;
649 DRM_DEBUG("\n");
650
651 cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
652 RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
653 SET_RING_HEAD(dev_priv, cur_read_ptr);
654 dev_priv->ring.tail = cur_read_ptr;
655}
656
657/* Stop the Command Processor. This will not flush any pending
658 * commands, so you must flush the command stream and wait for the CP
659 * to go idle before calling this routine.
660 */
661static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
662{
663 RING_LOCALS;
664 DRM_DEBUG("\n");
665
666 /* finish the pending CP_RESYNC token */
667 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) {
668 BEGIN_RING(2);
669 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
670 OUT_RING(R300_RB3D_DC_FINISH);
671 ADVANCE_RING();
672 COMMIT_RING();
673 radeon_do_wait_for_idle(dev_priv);
674 }
675
676 RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS);
677
678 dev_priv->cp_running = 0;
679}
680
681/* Reset the engine. This will stop the CP if it is running.
682 */
683static int radeon_do_engine_reset(struct drm_device * dev)
684{
685 drm_radeon_private_t *dev_priv = dev->dev_private;
686 u32 clock_cntl_index = 0, mclk_cntl = 0, rbbm_soft_reset;
687 DRM_DEBUG("\n");
688
689 radeon_do_pixcache_flush(dev_priv);
690
691 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
692 /* may need something similar for newer chips */
693 clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
694 mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL);
695
696 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl |
697 RADEON_FORCEON_MCLKA |
698 RADEON_FORCEON_MCLKB |
699 RADEON_FORCEON_YCLKA |
700 RADEON_FORCEON_YCLKB |
701 RADEON_FORCEON_MC |
702 RADEON_FORCEON_AIC));
703 }
704
705 rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
706
707 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
708 RADEON_SOFT_RESET_CP |
709 RADEON_SOFT_RESET_HI |
710 RADEON_SOFT_RESET_SE |
711 RADEON_SOFT_RESET_RE |
712 RADEON_SOFT_RESET_PP |
713 RADEON_SOFT_RESET_E2 |
714 RADEON_SOFT_RESET_RB));
715 RADEON_READ(RADEON_RBBM_SOFT_RESET);
716 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
717 ~(RADEON_SOFT_RESET_CP |
718 RADEON_SOFT_RESET_HI |
719 RADEON_SOFT_RESET_SE |
720 RADEON_SOFT_RESET_RE |
721 RADEON_SOFT_RESET_PP |
722 RADEON_SOFT_RESET_E2 |
723 RADEON_SOFT_RESET_RB)));
724 RADEON_READ(RADEON_RBBM_SOFT_RESET);
725
726 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
727 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl);
728 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
729 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
730 }
731
732 /* setup the raster pipes */
733 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R300)
734 radeon_init_pipes(dev);
735
736 /* Reset the CP ring */
737 radeon_do_cp_reset(dev_priv);
738
739 /* The CP is no longer running after an engine reset */
740 dev_priv->cp_running = 0;
741
742 /* Reset any pending vertex, indirect buffers */
743 radeon_freelist_reset(dev);
744
745 return 0;
746}
747
748static void radeon_cp_init_ring_buffer(struct drm_device * dev,
749 drm_radeon_private_t *dev_priv,
750 struct drm_file *file_priv)
751{
752 struct drm_radeon_master_private *master_priv;
753 u32 ring_start, cur_read_ptr;
754
755 /* Initialize the memory controller. With new memory map, the fb location
756 * is not changed, it should have been properly initialized already. Part
757 * of the problem is that the code below is bogus, assuming the GART is
758 * always appended to the fb which is not necessarily the case
759 */
760 if (!dev_priv->new_memmap)
761 radeon_write_fb_location(dev_priv,
762 ((dev_priv->gart_vm_start - 1) & 0xffff0000)
763 | (dev_priv->fb_location >> 16));
764
765#if IS_ENABLED(CONFIG_AGP)
766 if (dev_priv->flags & RADEON_IS_AGP) {
767 radeon_write_agp_base(dev_priv, dev->agp->base);
768
769 radeon_write_agp_location(dev_priv,
770 (((dev_priv->gart_vm_start - 1 +
771 dev_priv->gart_size) & 0xffff0000) |
772 (dev_priv->gart_vm_start >> 16)));
773
774 ring_start = (dev_priv->cp_ring->offset
775 - dev->agp->base
776 + dev_priv->gart_vm_start);
777 } else
778#endif
779 ring_start = (dev_priv->cp_ring->offset
780 - (unsigned long)dev->sg->virtual
781 + dev_priv->gart_vm_start);
782
783 RADEON_WRITE(RADEON_CP_RB_BASE, ring_start);
784
785 /* Set the write pointer delay */
786 RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0);
787
788 /* Initialize the ring buffer's read and write pointers */
789 cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
790 RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
791 SET_RING_HEAD(dev_priv, cur_read_ptr);
792 dev_priv->ring.tail = cur_read_ptr;
793
794#if IS_ENABLED(CONFIG_AGP)
795 if (dev_priv->flags & RADEON_IS_AGP) {
796 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
797 dev_priv->ring_rptr->offset
798 - dev->agp->base + dev_priv->gart_vm_start);
799 } else
800#endif
801 {
802 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
803 dev_priv->ring_rptr->offset
804 - ((unsigned long) dev->sg->virtual)
805 + dev_priv->gart_vm_start);
806 }
807
808 /* Set ring buffer size */
809#ifdef __BIG_ENDIAN
810 RADEON_WRITE(RADEON_CP_RB_CNTL,
811 RADEON_BUF_SWAP_32BIT |
812 (dev_priv->ring.fetch_size_l2ow << 18) |
813 (dev_priv->ring.rptr_update_l2qw << 8) |
814 dev_priv->ring.size_l2qw);
815#else
816 RADEON_WRITE(RADEON_CP_RB_CNTL,
817 (dev_priv->ring.fetch_size_l2ow << 18) |
818 (dev_priv->ring.rptr_update_l2qw << 8) |
819 dev_priv->ring.size_l2qw);
820#endif
821
822
823 /* Initialize the scratch register pointer. This will cause
824 * the scratch register values to be written out to memory
825 * whenever they are updated.
826 *
827 * We simply put this behind the ring read pointer, this works
828 * with PCI GART as well as (whatever kind of) AGP GART
829 */
830 RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR)
831 + RADEON_SCRATCH_REG_OFFSET);
832
833 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);
834
835 radeon_enable_bm(dev_priv);
836
837 radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(0), 0);
838 RADEON_WRITE(RADEON_LAST_FRAME_REG, 0);
839
840 radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1), 0);
841 RADEON_WRITE(RADEON_LAST_DISPATCH_REG, 0);
842
843 radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(2), 0);
844 RADEON_WRITE(RADEON_LAST_CLEAR_REG, 0);
845
846 /* reset sarea copies of these */
847 master_priv = file_priv->master->driver_priv;
848 if (master_priv->sarea_priv) {
849 master_priv->sarea_priv->last_frame = 0;
850 master_priv->sarea_priv->last_dispatch = 0;
851 master_priv->sarea_priv->last_clear = 0;
852 }
853
854 radeon_do_wait_for_idle(dev_priv);
855
856 /* Sync everything up */
857 RADEON_WRITE(RADEON_ISYNC_CNTL,
858 (RADEON_ISYNC_ANY2D_IDLE3D |
859 RADEON_ISYNC_ANY3D_IDLE2D |
860 RADEON_ISYNC_WAIT_IDLEGUI |
861 RADEON_ISYNC_CPSCRATCH_IDLEGUI));
862
863}
864
865static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
866{
867 u32 tmp;
868
869 /* Start with assuming that writeback doesn't work */
870 dev_priv->writeback_works = 0;
871
872 /* Writeback doesn't seem to work everywhere, test it here and possibly
873 * enable it if it appears to work
874 */
875 radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1), 0);
876
877 RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef);
878
879 for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
880 u32 val;
881
882 val = radeon_read_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1));
883 if (val == 0xdeadbeef)
884 break;
885 DRM_UDELAY(1);
886 }
887
888 if (tmp < dev_priv->usec_timeout) {
889 dev_priv->writeback_works = 1;
890 DRM_INFO("writeback test succeeded in %d usecs\n", tmp);
891 } else {
892 dev_priv->writeback_works = 0;
893 DRM_INFO("writeback test failed\n");
894 }
895 if (radeon_no_wb == 1) {
896 dev_priv->writeback_works = 0;
897 DRM_INFO("writeback forced off\n");
898 }
899
900 if (!dev_priv->writeback_works) {
901 /* Disable writeback to avoid unnecessary bus master transfer */
902 RADEON_WRITE(RADEON_CP_RB_CNTL, RADEON_READ(RADEON_CP_RB_CNTL) |
903 RADEON_RB_NO_UPDATE);
904 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0);
905 }
906}
907
908/* Enable or disable IGP GART on the chip */
909static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
910{
911 u32 temp;
912
913 if (on) {
914 DRM_DEBUG("programming igp gart %08X %08lX %08X\n",
915 dev_priv->gart_vm_start,
916 (long)dev_priv->gart_info.bus_addr,
917 dev_priv->gart_size);
918
919 temp = IGP_READ_MCIND(dev_priv, RS480_MC_MISC_CNTL);
920 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
921 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
922 IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, (RS480_GART_INDEX_REG_EN |
923 RS690_BLOCK_GFX_D3_EN));
924 else
925 IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN);
926
927 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
928 RS480_VA_SIZE_32MB));
929
930 temp = IGP_READ_MCIND(dev_priv, RS480_GART_FEATURE_ID);
931 IGP_WRITE_MCIND(RS480_GART_FEATURE_ID, (RS480_HANG_EN |
932 RS480_TLB_ENABLE |
933 RS480_GTW_LAC_EN |
934 RS480_1LEVEL_GART));
935
936 temp = dev_priv->gart_info.bus_addr & 0xfffff000;
937 temp |= (upper_32_bits(dev_priv->gart_info.bus_addr) & 0xff) << 4;
938 IGP_WRITE_MCIND(RS480_GART_BASE, temp);
939
940 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_MODE_CNTL);
941 IGP_WRITE_MCIND(RS480_AGP_MODE_CNTL, ((1 << RS480_REQ_TYPE_SNOOP_SHIFT) |
942 RS480_REQ_TYPE_SNOOP_DIS));
943
944 radeon_write_agp_base(dev_priv, dev_priv->gart_vm_start);
945
946 dev_priv->gart_size = 32*1024*1024;
947 temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) &
948 0xffff0000) | (dev_priv->gart_vm_start >> 16));
949
950 radeon_write_agp_location(dev_priv, temp);
951
952 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_ADDRESS_SPACE_SIZE);
953 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
954 RS480_VA_SIZE_32MB));
955
956 do {
957 temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
958 if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
959 break;
960 DRM_UDELAY(1);
961 } while (1);
962
963 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL,
964 RS480_GART_CACHE_INVALIDATE);
965
966 do {
967 temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
968 if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
969 break;
970 DRM_UDELAY(1);
971 } while (1);
972
973 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 0);
974 } else {
975 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, 0);
976 }
977}
978
979/* Enable or disable IGP GART on the chip */
980static void rs600_set_igpgart(drm_radeon_private_t *dev_priv, int on)
981{
982 u32 temp;
983 int i;
984
985 if (on) {
986 DRM_DEBUG("programming igp gart %08X %08lX %08X\n",
987 dev_priv->gart_vm_start,
988 (long)dev_priv->gart_info.bus_addr,
989 dev_priv->gart_size);
990
991 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, (RS600_EFFECTIVE_L2_CACHE_SIZE(6) |
992 RS600_EFFECTIVE_L2_QUEUE_SIZE(6)));
993
994 for (i = 0; i < 19; i++)
995 IGP_WRITE_MCIND(RS600_MC_PT0_CLIENT0_CNTL + i,
996 (RS600_ENABLE_TRANSLATION_MODE_OVERRIDE |
997 RS600_SYSTEM_ACCESS_MODE_IN_SYS |
998 RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASSTHROUGH |
999 RS600_EFFECTIVE_L1_CACHE_SIZE(3) |
1000 RS600_ENABLE_FRAGMENT_PROCESSING |
1001 RS600_EFFECTIVE_L1_QUEUE_SIZE(3)));
1002
1003 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_CNTL, (RS600_ENABLE_PAGE_TABLE |
1004 RS600_PAGE_TABLE_TYPE_FLAT));
1005
1006 /* disable all other contexts */
1007 for (i = 1; i < 8; i++)
1008 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_CNTL + i, 0);
1009
1010 /* setup the page table aperture */
1011 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_BASE_ADDR,
1012 dev_priv->gart_info.bus_addr);
1013 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_START_ADDR,
1014 dev_priv->gart_vm_start);
1015 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_END_ADDR,
1016 (dev_priv->gart_vm_start + dev_priv->gart_size - 1));
1017 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0);
1018
1019 /* setup the system aperture */
1020 IGP_WRITE_MCIND(RS600_MC_PT0_SYSTEM_APERTURE_LOW_ADDR,
1021 dev_priv->gart_vm_start);
1022 IGP_WRITE_MCIND(RS600_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR,
1023 (dev_priv->gart_vm_start + dev_priv->gart_size - 1));
1024
1025 /* enable page tables */
1026 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
1027 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, (temp | RS600_ENABLE_PT));
1028
1029 temp = IGP_READ_MCIND(dev_priv, RS600_MC_CNTL1);
1030 IGP_WRITE_MCIND(RS600_MC_CNTL1, (temp | RS600_ENABLE_PAGE_TABLES));
1031
1032 /* invalidate the cache */
1033 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
1034
1035 temp &= ~(RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE);
1036 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp);
1037 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
1038
1039 temp |= RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE;
1040 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp);
1041 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
1042
1043 temp &= ~(RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE);
1044 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp);
1045 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
1046
1047 } else {
1048 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, 0);
1049 temp = IGP_READ_MCIND(dev_priv, RS600_MC_CNTL1);
1050 temp &= ~RS600_ENABLE_PAGE_TABLES;
1051 IGP_WRITE_MCIND(RS600_MC_CNTL1, temp);
1052 }
1053}
1054
1055static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
1056{
1057 u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL);
1058 if (on) {
1059
1060 DRM_DEBUG("programming pcie %08X %08lX %08X\n",
1061 dev_priv->gart_vm_start,
1062 (long)dev_priv->gart_info.bus_addr,
1063 dev_priv->gart_size);
1064 RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO,
1065 dev_priv->gart_vm_start);
1066 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE,
1067 dev_priv->gart_info.bus_addr);
1068 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO,
1069 dev_priv->gart_vm_start);
1070 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO,
1071 dev_priv->gart_vm_start +
1072 dev_priv->gart_size - 1);
1073
1074 radeon_write_agp_location(dev_priv, 0xffffffc0); /* ?? */
1075
1076 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
1077 RADEON_PCIE_TX_GART_EN);
1078 } else {
1079 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
1080 tmp & ~RADEON_PCIE_TX_GART_EN);
1081 }
1082}
1083
1084/* Enable or disable PCI GART on the chip */
1085static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
1086{
1087 u32 tmp;
1088
1089 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
1090 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740) ||
1091 (dev_priv->flags & RADEON_IS_IGPGART)) {
1092 radeon_set_igpgart(dev_priv, on);
1093 return;
1094 }
1095
1096 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) {
1097 rs600_set_igpgart(dev_priv, on);
1098 return;
1099 }
1100
1101 if (dev_priv->flags & RADEON_IS_PCIE) {
1102 radeon_set_pciegart(dev_priv, on);
1103 return;
1104 }
1105
1106 tmp = RADEON_READ(RADEON_AIC_CNTL);
1107
1108 if (on) {
1109 RADEON_WRITE(RADEON_AIC_CNTL,
1110 tmp | RADEON_PCIGART_TRANSLATE_EN);
1111
1112 /* set PCI GART page-table base address
1113 */
1114 RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr);
1115
1116 /* set address range for PCI address translate
1117 */
1118 RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start);
1119 RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
1120 + dev_priv->gart_size - 1);
1121
1122 /* Turn off AGP aperture -- is this required for PCI GART?
1123 */
1124 radeon_write_agp_location(dev_priv, 0xffffffc0);
1125 RADEON_WRITE(RADEON_AGP_COMMAND, 0); /* clear AGP_COMMAND */
1126 } else {
1127 RADEON_WRITE(RADEON_AIC_CNTL,
1128 tmp & ~RADEON_PCIGART_TRANSLATE_EN);
1129 }
1130}
1131
1132static int radeon_setup_pcigart_surface(drm_radeon_private_t *dev_priv)
1133{
1134 struct drm_ati_pcigart_info *gart_info = &dev_priv->gart_info;
1135 struct radeon_virt_surface *vp;
1136 int i;
1137
1138 for (i = 0; i < RADEON_MAX_SURFACES * 2; i++) {
1139 if (!dev_priv->virt_surfaces[i].file_priv ||
1140 dev_priv->virt_surfaces[i].file_priv == PCIGART_FILE_PRIV)
1141 break;
1142 }
1143 if (i >= 2 * RADEON_MAX_SURFACES)
1144 return -ENOMEM;
1145 vp = &dev_priv->virt_surfaces[i];
1146
1147 for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1148 struct radeon_surface *sp = &dev_priv->surfaces[i];
1149 if (sp->refcount)
1150 continue;
1151
1152 vp->surface_index = i;
1153 vp->lower = gart_info->bus_addr;
1154 vp->upper = vp->lower + gart_info->table_size;
1155 vp->flags = 0;
1156 vp->file_priv = PCIGART_FILE_PRIV;
1157
1158 sp->refcount = 1;
1159 sp->lower = vp->lower;
1160 sp->upper = vp->upper;
1161 sp->flags = 0;
1162
1163 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, sp->flags);
1164 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND + 16 * i, sp->lower);
1165 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND + 16 * i, sp->upper);
1166 return 0;
1167 }
1168
1169 return -ENOMEM;
1170}
1171
1172static int radeon_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init,
1173 struct drm_file *file_priv)
1174{
1175 drm_radeon_private_t *dev_priv = dev->dev_private;
1176 struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv;
1177
1178 DRM_DEBUG("\n");
1179
1180 /* if we require new memory map but we don't have it fail */
1181 if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
1182 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
1183 radeon_do_cleanup_cp(dev);
1184 return -EINVAL;
1185 }
1186
1187 if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) {
1188 DRM_DEBUG("Forcing AGP card to PCI mode\n");
1189 dev_priv->flags &= ~RADEON_IS_AGP;
1190 } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE))
1191 && !init->is_pci) {
1192 DRM_DEBUG("Restoring AGP flag\n");
1193 dev_priv->flags |= RADEON_IS_AGP;
1194 }
1195
1196 if ((!(dev_priv->flags & RADEON_IS_AGP)) && !dev->sg) {
1197 DRM_ERROR("PCI GART memory not allocated!\n");
1198 radeon_do_cleanup_cp(dev);
1199 return -EINVAL;
1200 }
1201
1202 dev_priv->usec_timeout = init->usec_timeout;
1203 if (dev_priv->usec_timeout < 1 ||
1204 dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
1205 DRM_DEBUG("TIMEOUT problem!\n");
1206 radeon_do_cleanup_cp(dev);
1207 return -EINVAL;
1208 }
1209
1210 /* Enable vblank on CRTC1 for older X servers
1211 */
1212 dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
1213
1214 switch(init->func) {
1215 case RADEON_INIT_R200_CP:
1216 dev_priv->microcode_version = UCODE_R200;
1217 break;
1218 case RADEON_INIT_R300_CP:
1219 dev_priv->microcode_version = UCODE_R300;
1220 break;
1221 default:
1222 dev_priv->microcode_version = UCODE_R100;
1223 }
1224
1225 dev_priv->do_boxes = 0;
1226 dev_priv->cp_mode = init->cp_mode;
1227
1228 /* We don't support anything other than bus-mastering ring mode,
1229 * but the ring can be in either AGP or PCI space for the ring
1230 * read pointer.
1231 */
1232 if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
1233 (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
1234 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
1235 radeon_do_cleanup_cp(dev);
1236 return -EINVAL;
1237 }
1238
1239 switch (init->fb_bpp) {
1240 case 16:
1241 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
1242 break;
1243 case 32:
1244 default:
1245 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
1246 break;
1247 }
1248 dev_priv->front_offset = init->front_offset;
1249 dev_priv->front_pitch = init->front_pitch;
1250 dev_priv->back_offset = init->back_offset;
1251 dev_priv->back_pitch = init->back_pitch;
1252
1253 switch (init->depth_bpp) {
1254 case 16:
1255 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
1256 break;
1257 case 32:
1258 default:
1259 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
1260 break;
1261 }
1262 dev_priv->depth_offset = init->depth_offset;
1263 dev_priv->depth_pitch = init->depth_pitch;
1264
1265 /* Hardware state for depth clears. Remove this if/when we no
1266 * longer clear the depth buffer with a 3D rectangle. Hard-code
1267 * all values to prevent unwanted 3D state from slipping through
1268 * and screwing with the clear operation.
1269 */
1270 dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
1271 (dev_priv->color_fmt << 10) |
1272 (dev_priv->microcode_version ==
1273 UCODE_R100 ? RADEON_ZBLOCK16 : 0));
1274
1275 dev_priv->depth_clear.rb3d_zstencilcntl =
1276 (dev_priv->depth_fmt |
1277 RADEON_Z_TEST_ALWAYS |
1278 RADEON_STENCIL_TEST_ALWAYS |
1279 RADEON_STENCIL_S_FAIL_REPLACE |
1280 RADEON_STENCIL_ZPASS_REPLACE |
1281 RADEON_STENCIL_ZFAIL_REPLACE | RADEON_Z_WRITE_ENABLE);
1282
1283 dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
1284 RADEON_BFACE_SOLID |
1285 RADEON_FFACE_SOLID |
1286 RADEON_FLAT_SHADE_VTX_LAST |
1287 RADEON_DIFFUSE_SHADE_FLAT |
1288 RADEON_ALPHA_SHADE_FLAT |
1289 RADEON_SPECULAR_SHADE_FLAT |
1290 RADEON_FOG_SHADE_FLAT |
1291 RADEON_VTX_PIX_CENTER_OGL |
1292 RADEON_ROUND_MODE_TRUNC |
1293 RADEON_ROUND_PREC_8TH_PIX);
1294
1295
1296 dev_priv->ring_offset = init->ring_offset;
1297 dev_priv->ring_rptr_offset = init->ring_rptr_offset;
1298 dev_priv->buffers_offset = init->buffers_offset;
1299 dev_priv->gart_textures_offset = init->gart_textures_offset;
1300
1301 master_priv->sarea = drm_legacy_getsarea(dev);
1302 if (!master_priv->sarea) {
1303 DRM_ERROR("could not find sarea!\n");
1304 radeon_do_cleanup_cp(dev);
1305 return -EINVAL;
1306 }
1307
1308 dev_priv->cp_ring = drm_legacy_findmap(dev, init->ring_offset);
1309 if (!dev_priv->cp_ring) {
1310 DRM_ERROR("could not find cp ring region!\n");
1311 radeon_do_cleanup_cp(dev);
1312 return -EINVAL;
1313 }
1314 dev_priv->ring_rptr = drm_legacy_findmap(dev, init->ring_rptr_offset);
1315 if (!dev_priv->ring_rptr) {
1316 DRM_ERROR("could not find ring read pointer!\n");
1317 radeon_do_cleanup_cp(dev);
1318 return -EINVAL;
1319 }
1320 dev->agp_buffer_token = init->buffers_offset;
1321 dev->agp_buffer_map = drm_legacy_findmap(dev, init->buffers_offset);
1322 if (!dev->agp_buffer_map) {
1323 DRM_ERROR("could not find dma buffer region!\n");
1324 radeon_do_cleanup_cp(dev);
1325 return -EINVAL;
1326 }
1327
1328 if (init->gart_textures_offset) {
1329 dev_priv->gart_textures =
1330 drm_legacy_findmap(dev, init->gart_textures_offset);
1331 if (!dev_priv->gart_textures) {
1332 DRM_ERROR("could not find GART texture region!\n");
1333 radeon_do_cleanup_cp(dev);
1334 return -EINVAL;
1335 }
1336 }
1337
1338#if IS_ENABLED(CONFIG_AGP)
1339 if (dev_priv->flags & RADEON_IS_AGP) {
1340 drm_legacy_ioremap_wc(dev_priv->cp_ring, dev);
1341 drm_legacy_ioremap_wc(dev_priv->ring_rptr, dev);
1342 drm_legacy_ioremap_wc(dev->agp_buffer_map, dev);
1343 if (!dev_priv->cp_ring->handle ||
1344 !dev_priv->ring_rptr->handle ||
1345 !dev->agp_buffer_map->handle) {
1346 DRM_ERROR("could not find ioremap agp regions!\n");
1347 radeon_do_cleanup_cp(dev);
1348 return -EINVAL;
1349 }
1350 } else
1351#endif
1352 {
1353 dev_priv->cp_ring->handle =
1354 (void *)(unsigned long)dev_priv->cp_ring->offset;
1355 dev_priv->ring_rptr->handle =
1356 (void *)(unsigned long)dev_priv->ring_rptr->offset;
1357 dev->agp_buffer_map->handle =
1358 (void *)(unsigned long)dev->agp_buffer_map->offset;
1359
1360 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
1361 dev_priv->cp_ring->handle);
1362 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
1363 dev_priv->ring_rptr->handle);
1364 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
1365 dev->agp_buffer_map->handle);
1366 }
1367
1368 dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 16;
1369 dev_priv->fb_size =
1370 ((radeon_read_fb_location(dev_priv) & 0xffff0000u) + 0x10000)
1371 - dev_priv->fb_location;
1372
1373 dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
1374 ((dev_priv->front_offset
1375 + dev_priv->fb_location) >> 10));
1376
1377 dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
1378 ((dev_priv->back_offset
1379 + dev_priv->fb_location) >> 10));
1380
1381 dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
1382 ((dev_priv->depth_offset
1383 + dev_priv->fb_location) >> 10));
1384
1385 dev_priv->gart_size = init->gart_size;
1386
1387 /* New let's set the memory map ... */
1388 if (dev_priv->new_memmap) {
1389 u32 base = 0;
1390
1391 DRM_INFO("Setting GART location based on new memory map\n");
1392
1393 /* If using AGP, try to locate the AGP aperture at the same
1394 * location in the card and on the bus, though we have to
1395 * align it down.
1396 */
1397#if IS_ENABLED(CONFIG_AGP)
1398 if (dev_priv->flags & RADEON_IS_AGP) {
1399 base = dev->agp->base;
1400 /* Check if valid */
1401 if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location &&
1402 base < (dev_priv->fb_location + dev_priv->fb_size - 1)) {
1403 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n",
1404 dev->agp->base);
1405 base = 0;
1406 }
1407 }
1408#endif
1409 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */
1410 if (base == 0) {
1411 base = dev_priv->fb_location + dev_priv->fb_size;
1412 if (base < dev_priv->fb_location ||
1413 ((base + dev_priv->gart_size) & 0xfffffffful) < base)
1414 base = dev_priv->fb_location
1415 - dev_priv->gart_size;
1416 }
1417 dev_priv->gart_vm_start = base & 0xffc00000u;
1418 if (dev_priv->gart_vm_start != base)
1419 DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
1420 base, dev_priv->gart_vm_start);
1421 } else {
1422 DRM_INFO("Setting GART location based on old memory map\n");
1423 dev_priv->gart_vm_start = dev_priv->fb_location +
1424 RADEON_READ(RADEON_CONFIG_APER_SIZE);
1425 }
1426
1427#if IS_ENABLED(CONFIG_AGP)
1428 if (dev_priv->flags & RADEON_IS_AGP)
1429 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1430 - dev->agp->base
1431 + dev_priv->gart_vm_start);
1432 else
1433#endif
1434 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1435 - (unsigned long)dev->sg->virtual
1436 + dev_priv->gart_vm_start);
1437
1438 DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
1439 DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start);
1440 DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n",
1441 dev_priv->gart_buffers_offset);
1442
1443 dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
1444 dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
1445 + init->ring_size / sizeof(u32));
1446 dev_priv->ring.size = init->ring_size;
1447 dev_priv->ring.size_l2qw = order_base_2(init->ring_size / 8);
1448
1449 dev_priv->ring.rptr_update = /* init->rptr_update */ 4096;
1450 dev_priv->ring.rptr_update_l2qw = order_base_2( /* init->rptr_update */ 4096 / 8);
1451
1452 dev_priv->ring.fetch_size = /* init->fetch_size */ 32;
1453 dev_priv->ring.fetch_size_l2ow = order_base_2( /* init->fetch_size */ 32 / 16);
1454 dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
1455
1456 dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1457
1458#if IS_ENABLED(CONFIG_AGP)
1459 if (dev_priv->flags & RADEON_IS_AGP) {
1460 /* Turn off PCI GART */
1461 radeon_set_pcigart(dev_priv, 0);
1462 } else
1463#endif
1464 {
1465 u32 sctrl;
1466 int ret;
1467
1468 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
1469 /* if we have an offset set from userspace */
1470 if (dev_priv->pcigart_offset_set) {
1471 dev_priv->gart_info.bus_addr =
1472 (resource_size_t)dev_priv->pcigart_offset + dev_priv->fb_location;
1473 dev_priv->gart_info.mapping.offset =
1474 dev_priv->pcigart_offset + dev_priv->fb_aper_offset;
1475 dev_priv->gart_info.mapping.size =
1476 dev_priv->gart_info.table_size;
1477
1478 drm_legacy_ioremap_wc(&dev_priv->gart_info.mapping, dev);
1479 dev_priv->gart_info.addr =
1480 dev_priv->gart_info.mapping.handle;
1481
1482 if (dev_priv->flags & RADEON_IS_PCIE)
1483 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCIE;
1484 else
1485 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1486 dev_priv->gart_info.gart_table_location =
1487 DRM_ATI_GART_FB;
1488
1489 DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
1490 dev_priv->gart_info.addr,
1491 dev_priv->pcigart_offset);
1492 } else {
1493 if (dev_priv->flags & RADEON_IS_IGPGART)
1494 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_IGP;
1495 else
1496 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1497 dev_priv->gart_info.gart_table_location =
1498 DRM_ATI_GART_MAIN;
1499 dev_priv->gart_info.addr = NULL;
1500 dev_priv->gart_info.bus_addr = 0;
1501 if (dev_priv->flags & RADEON_IS_PCIE) {
1502 DRM_ERROR
1503 ("Cannot use PCI Express without GART in FB memory\n");
1504 radeon_do_cleanup_cp(dev);
1505 return -EINVAL;
1506 }
1507 }
1508
1509 sctrl = RADEON_READ(RADEON_SURFACE_CNTL);
1510 RADEON_WRITE(RADEON_SURFACE_CNTL, 0);
1511 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
1512 ret = r600_page_table_init(dev);
1513 else
1514 ret = drm_ati_pcigart_init(dev, &dev_priv->gart_info);
1515 RADEON_WRITE(RADEON_SURFACE_CNTL, sctrl);
1516
1517 if (!ret) {
1518 DRM_ERROR("failed to init PCI GART!\n");
1519 radeon_do_cleanup_cp(dev);
1520 return -ENOMEM;
1521 }
1522
1523 ret = radeon_setup_pcigart_surface(dev_priv);
1524 if (ret) {
1525 DRM_ERROR("failed to setup GART surface!\n");
1526 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
1527 r600_page_table_cleanup(dev, &dev_priv->gart_info);
1528 else
1529 drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info);
1530 radeon_do_cleanup_cp(dev);
1531 return ret;
1532 }
1533
1534 /* Turn on PCI GART */
1535 radeon_set_pcigart(dev_priv, 1);
1536 }
1537
1538 if (!dev_priv->me_fw) {
1539 int err = radeon_cp_init_microcode(dev_priv);
1540 if (err) {
1541 DRM_ERROR("Failed to load firmware!\n");
1542 radeon_do_cleanup_cp(dev);
1543 return err;
1544 }
1545 }
1546 radeon_cp_load_microcode(dev_priv);
1547 radeon_cp_init_ring_buffer(dev, dev_priv, file_priv);
1548
1549 dev_priv->last_buf = 0;
1550
1551 radeon_do_engine_reset(dev);
1552 radeon_test_writeback(dev_priv);
1553
1554 return 0;
1555}
1556
1557static int radeon_do_cleanup_cp(struct drm_device * dev)
1558{
1559 drm_radeon_private_t *dev_priv = dev->dev_private;
1560 DRM_DEBUG("\n");
1561
1562 /* Make sure interrupts are disabled here because the uninstall ioctl
1563 * may not have been called from userspace and after dev_private
1564 * is freed, it's too late.
1565 */
1566 if (dev->irq_enabled)
1567 drm_irq_uninstall(dev);
1568
1569#if IS_ENABLED(CONFIG_AGP)
1570 if (dev_priv->flags & RADEON_IS_AGP) {
1571 if (dev_priv->cp_ring != NULL) {
1572 drm_legacy_ioremapfree(dev_priv->cp_ring, dev);
1573 dev_priv->cp_ring = NULL;
1574 }
1575 if (dev_priv->ring_rptr != NULL) {
1576 drm_legacy_ioremapfree(dev_priv->ring_rptr, dev);
1577 dev_priv->ring_rptr = NULL;
1578 }
1579 if (dev->agp_buffer_map != NULL) {
1580 drm_legacy_ioremapfree(dev->agp_buffer_map, dev);
1581 dev->agp_buffer_map = NULL;
1582 }
1583 } else
1584#endif
1585 {
1586
1587 if (dev_priv->gart_info.bus_addr) {
1588 /* Turn off PCI GART */
1589 radeon_set_pcigart(dev_priv, 0);
1590 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
1591 r600_page_table_cleanup(dev, &dev_priv->gart_info);
1592 else {
1593 if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info))
1594 DRM_ERROR("failed to cleanup PCI GART!\n");
1595 }
1596 }
1597
1598 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB)
1599 {
1600 drm_legacy_ioremapfree(&dev_priv->gart_info.mapping, dev);
1601 dev_priv->gart_info.addr = NULL;
1602 }
1603 }
1604 /* only clear to the start of flags */
1605 memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1606
1607 return 0;
1608}
1609
1610/* This code will reinit the Radeon CP hardware after a resume from disc.
1611 * AFAIK, it would be very difficult to pickle the state at suspend time, so
1612 * here we make sure that all Radeon hardware initialisation is re-done without
1613 * affecting running applications.
1614 *
1615 * Charl P. Botha <http://cpbotha.net>
1616 */
1617static int radeon_do_resume_cp(struct drm_device *dev, struct drm_file *file_priv)
1618{
1619 drm_radeon_private_t *dev_priv = dev->dev_private;
1620
1621 if (!dev_priv) {
1622 DRM_ERROR("Called with no initialization\n");
1623 return -EINVAL;
1624 }
1625
1626 DRM_DEBUG("Starting radeon_do_resume_cp()\n");
1627
1628#if IS_ENABLED(CONFIG_AGP)
1629 if (dev_priv->flags & RADEON_IS_AGP) {
1630 /* Turn off PCI GART */
1631 radeon_set_pcigart(dev_priv, 0);
1632 } else
1633#endif
1634 {
1635 /* Turn on PCI GART */
1636 radeon_set_pcigart(dev_priv, 1);
1637 }
1638
1639 radeon_cp_load_microcode(dev_priv);
1640 radeon_cp_init_ring_buffer(dev, dev_priv, file_priv);
1641
1642 dev_priv->have_z_offset = 0;
1643 radeon_do_engine_reset(dev);
1644 radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1);
1645
1646 DRM_DEBUG("radeon_do_resume_cp() complete\n");
1647
1648 return 0;
1649}
1650
1651int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
1652{
1653 drm_radeon_private_t *dev_priv = dev->dev_private;
1654 drm_radeon_init_t *init = data;
1655
1656 LOCK_TEST_WITH_RETURN(dev, file_priv);
1657
1658 if (init->func == RADEON_INIT_R300_CP)
1659 r300_init_reg_flags(dev);
1660
1661 switch (init->func) {
1662 case RADEON_INIT_CP:
1663 case RADEON_INIT_R200_CP:
1664 case RADEON_INIT_R300_CP:
1665 return radeon_do_init_cp(dev, init, file_priv);
1666 case RADEON_INIT_R600_CP:
1667 return r600_do_init_cp(dev, init, file_priv);
1668 case RADEON_CLEANUP_CP:
1669 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1670 return r600_do_cleanup_cp(dev);
1671 else
1672 return radeon_do_cleanup_cp(dev);
1673 }
1674
1675 return -EINVAL;
1676}
1677
1678int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv)
1679{
1680 drm_radeon_private_t *dev_priv = dev->dev_private;
1681 DRM_DEBUG("\n");
1682
1683 LOCK_TEST_WITH_RETURN(dev, file_priv);
1684
1685 if (dev_priv->cp_running) {
1686 DRM_DEBUG("while CP running\n");
1687 return 0;
1688 }
1689 if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) {
1690 DRM_DEBUG("called with bogus CP mode (%d)\n",
1691 dev_priv->cp_mode);
1692 return 0;
1693 }
1694
1695 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1696 r600_do_cp_start(dev_priv);
1697 else
1698 radeon_do_cp_start(dev_priv);
1699
1700 return 0;
1701}
1702
1703/* Stop the CP. The engine must have been idled before calling this
1704 * routine.
1705 */
1706int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv)
1707{
1708 drm_radeon_private_t *dev_priv = dev->dev_private;
1709 drm_radeon_cp_stop_t *stop = data;
1710 int ret;
1711 DRM_DEBUG("\n");
1712
1713 LOCK_TEST_WITH_RETURN(dev, file_priv);
1714
1715 if (!dev_priv->cp_running)
1716 return 0;
1717
1718 /* Flush any pending CP commands. This ensures any outstanding
1719 * commands are exectuted by the engine before we turn it off.
1720 */
1721 if (stop->flush) {
1722 radeon_do_cp_flush(dev_priv);
1723 }
1724
1725 /* If we fail to make the engine go idle, we return an error
1726 * code so that the DRM ioctl wrapper can try again.
1727 */
1728 if (stop->idle) {
1729 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1730 ret = r600_do_cp_idle(dev_priv);
1731 else
1732 ret = radeon_do_cp_idle(dev_priv);
1733 if (ret)
1734 return ret;
1735 }
1736
1737 /* Finally, we can turn off the CP. If the engine isn't idle,
1738 * we will get some dropped triangles as they won't be fully
1739 * rendered before the CP is shut down.
1740 */
1741 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1742 r600_do_cp_stop(dev_priv);
1743 else
1744 radeon_do_cp_stop(dev_priv);
1745
1746 /* Reset the engine */
1747 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1748 r600_do_engine_reset(dev);
1749 else
1750 radeon_do_engine_reset(dev);
1751
1752 return 0;
1753}
1754
1755void radeon_do_release(struct drm_device * dev)
1756{
1757 drm_radeon_private_t *dev_priv = dev->dev_private;
1758 int i, ret;
1759
1760 if (dev_priv) {
1761 if (dev_priv->cp_running) {
1762 /* Stop the cp */
1763 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
1764 while ((ret = r600_do_cp_idle(dev_priv)) != 0) {
1765 DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1766#ifdef __linux__
1767 schedule();
1768#else
1769 tsleep(&ret, PZERO, "rdnrel", 1);
1770#endif
1771 }
1772 } else {
1773 while ((ret = radeon_do_cp_idle(dev_priv)) != 0) {
1774 DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1775#ifdef __linux__
1776 schedule();
1777#else
1778 tsleep(&ret, PZERO, "rdnrel", 1);
1779#endif
1780 }
1781 }
1782 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
1783 r600_do_cp_stop(dev_priv);
1784 r600_do_engine_reset(dev);
1785 } else {
1786 radeon_do_cp_stop(dev_priv);
1787 radeon_do_engine_reset(dev);
1788 }
1789 }
1790
1791 if ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_R600) {
1792 /* Disable *all* interrupts */
1793 if (dev_priv->mmio) /* remove this after permanent addmaps */
1794 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
1795
1796 if (dev_priv->mmio) { /* remove all surfaces */
1797 for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1798 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, 0);
1799 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND +
1800 16 * i, 0);
1801 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND +
1802 16 * i, 0);
1803 }
1804 }
1805 }
1806
1807 /* Free memory heap structures */
1808 radeon_mem_takedown(&(dev_priv->gart_heap));
1809 radeon_mem_takedown(&(dev_priv->fb_heap));
1810
1811 /* deallocate kernel resources */
1812 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1813 r600_do_cleanup_cp(dev);
1814 else
1815 radeon_do_cleanup_cp(dev);
1816 release_firmware(dev_priv->me_fw);
1817 dev_priv->me_fw = NULL;
1818 release_firmware(dev_priv->pfp_fw);
1819 dev_priv->pfp_fw = NULL;
1820 }
1821}
1822
1823/* Just reset the CP ring. Called as part of an X Server engine reset.
1824 */
1825int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1826{
1827 drm_radeon_private_t *dev_priv = dev->dev_private;
1828 DRM_DEBUG("\n");
1829
1830 LOCK_TEST_WITH_RETURN(dev, file_priv);
1831
1832 if (!dev_priv) {
1833 DRM_DEBUG("called before init done\n");
1834 return -EINVAL;
1835 }
1836
1837 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1838 r600_do_cp_reset(dev_priv);
1839 else
1840 radeon_do_cp_reset(dev_priv);
1841
1842 /* The CP is no longer running after an engine reset */
1843 dev_priv->cp_running = 0;
1844
1845 return 0;
1846}
1847
1848int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv)
1849{
1850 drm_radeon_private_t *dev_priv = dev->dev_private;
1851 DRM_DEBUG("\n");
1852
1853 LOCK_TEST_WITH_RETURN(dev, file_priv);
1854
1855 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1856 return r600_do_cp_idle(dev_priv);
1857 else
1858 return radeon_do_cp_idle(dev_priv);
1859}
1860
1861/* Added by Charl P. Botha to call radeon_do_resume_cp().
1862 */
1863int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv)
1864{
1865 drm_radeon_private_t *dev_priv = dev->dev_private;
1866 DRM_DEBUG("\n");
1867
1868 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1869 return r600_do_resume_cp(dev, file_priv);
1870 else
1871 return radeon_do_resume_cp(dev, file_priv);
1872}
1873
1874int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1875{
1876 drm_radeon_private_t *dev_priv = dev->dev_private;
1877 DRM_DEBUG("\n");
1878
1879 LOCK_TEST_WITH_RETURN(dev, file_priv);
1880
1881 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1882 return r600_do_engine_reset(dev);
1883 else
1884 return radeon_do_engine_reset(dev);
1885}
1886
1887/* ================================================================
1888 * Fullscreen mode
1889 */
1890
1891/* KW: Deprecated to say the least:
1892 */
1893int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv)
1894{
1895 return 0;
1896}
1897
1898/* ================================================================
1899 * Freelist management
1900 */
1901
1902/* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through
1903 * bufs until freelist code is used. Note this hides a problem with
1904 * the scratch register * (used to keep track of last buffer
1905 * completed) being written to before * the last buffer has actually
1906 * completed rendering.
1907 *
1908 * KW: It's also a good way to find free buffers quickly.
1909 *
1910 * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
1911 * sleep. However, bugs in older versions of radeon_accel.c mean that
1912 * we essentially have to do this, else old clients will break.
1913 *
1914 * However, it does leave open a potential deadlock where all the
1915 * buffers are held by other clients, which can't release them because
1916 * they can't get the lock.
1917 */
1918
1919struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1920{
1921 struct drm_device_dma *dma = dev->dma;
1922 drm_radeon_private_t *dev_priv = dev->dev_private;
1923 drm_radeon_buf_priv_t *buf_priv;
1924 struct drm_buf *buf;
1925 int i, t;
1926 int start;
1927
1928 if (++dev_priv->last_buf >= dma->buf_count)
1929 dev_priv->last_buf = 0;
1930
1931 start = dev_priv->last_buf;
1932
1933 for (t = 0; t < dev_priv->usec_timeout; t++) {
1934 u32 done_age = GET_SCRATCH(dev_priv, 1);
1935 DRM_DEBUG("done_age = %d\n", done_age);
1936 for (i = 0; i < dma->buf_count; i++) {
1937 buf = dma->buflist[start];
1938 buf_priv = buf->dev_private;
1939 if (buf->file_priv == NULL || (buf->pending &&
1940 buf_priv->age <=
1941 done_age)) {
1942 dev_priv->stats.requested_bufs++;
1943 buf->pending = 0;
1944 return buf;
1945 }
1946 if (++start >= dma->buf_count)
1947 start = 0;
1948 }
1949
1950 if (t) {
1951 DRM_UDELAY(1);
1952 dev_priv->stats.freelist_loops++;
1953 }
1954 }
1955
1956 return NULL;
1957}
1958
1959void radeon_freelist_reset(struct drm_device * dev)
1960{
1961 struct drm_device_dma *dma = dev->dma;
1962 drm_radeon_private_t *dev_priv = dev->dev_private;
1963 int i;
1964
1965 dev_priv->last_buf = 0;
1966 for (i = 0; i < dma->buf_count; i++) {
1967 struct drm_buf *buf = dma->buflist[i];
1968 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
1969 buf_priv->age = 0;
1970 }
1971}
1972
1973/* ================================================================
1974 * CP command submission
1975 */
1976
1977int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n)
1978{
1979 drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
1980 int i;
1981 u32 last_head = GET_RING_HEAD(dev_priv);
1982
1983 for (i = 0; i < dev_priv->usec_timeout; i++) {
1984 u32 head = GET_RING_HEAD(dev_priv);
1985
1986 ring->space = (head - ring->tail) * sizeof(u32);
1987 if (ring->space <= 0)
1988 ring->space += ring->size;
1989 if (ring->space > n)
1990 return 0;
1991
1992 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
1993
1994 if (head != last_head)
1995 i = 0;
1996 last_head = head;
1997
1998 DRM_UDELAY(1);
1999 }
2000
2001 /* FIXME: This return value is ignored in the BEGIN_RING macro! */
2002#if RADEON_FIFO_DEBUG
2003 radeon_status(dev_priv);
2004 DRM_ERROR("failed!\n");
2005#endif
2006 return -EBUSY;
2007}
2008
2009static int radeon_cp_get_buffers(struct drm_device *dev,
2010 struct drm_file *file_priv,
2011 struct drm_dma * d)
2012{
2013 int i;
2014 struct drm_buf *buf;
2015
2016 for (i = d->granted_count; i < d->request_count; i++) {
2017 buf = radeon_freelist_get(dev);
2018 if (!buf)
2019 return -EBUSY; /* NOTE: broken client */
2020
2021 buf->file_priv = file_priv;
2022
2023 if (copy_to_user(&d->request_indices[i], &buf->idx,
2024 sizeof(buf->idx)))
2025 return -EFAULT;
2026 if (copy_to_user(&d->request_sizes[i], &buf->total,
2027 sizeof(buf->total)))
2028 return -EFAULT;
2029
2030 d->granted_count++;
2031 }
2032 return 0;
2033}
2034
2035int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv)
2036{
2037 struct drm_device_dma *dma = dev->dma;
2038 int ret = 0;
2039 struct drm_dma *d = data;
2040
2041 LOCK_TEST_WITH_RETURN(dev, file_priv);
2042
2043 /* Please don't send us buffers.
2044 */
2045 if (d->send_count != 0) {
2046 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
2047 DRM_CURRENTPID, d->send_count);
2048 return -EINVAL;
2049 }
2050
2051 /* We'll send you buffers.
2052 */
2053 if (d->request_count < 0 || d->request_count > dma->buf_count) {
2054 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
2055 DRM_CURRENTPID, d->request_count, dma->buf_count);
2056 return -EINVAL;
2057 }
2058
2059 d->granted_count = 0;
2060
2061 if (d->request_count) {
2062 ret = radeon_cp_get_buffers(dev, file_priv, d);
2063 }
2064
2065 return ret;
2066}
2067
2068int radeon_driver_load(struct drm_device *dev, unsigned long flags)
2069{
2070 drm_radeon_private_t *dev_priv;
2071 int ret = 0;
2072
2073 dev_priv = kzalloc(sizeof(drm_radeon_private_t), GFP_KERNEL);
2074 if (dev_priv == NULL)
2075 return -ENOMEM;
2076
2077 dev->dev_private = (void *)dev_priv;
2078 dev_priv->flags = flags;
2079
2080 switch (flags & RADEON_FAMILY_MASK) {
2081 case CHIP_R100:
2082 case CHIP_RV200:
2083 case CHIP_R200:
2084 case CHIP_R300:
2085 case CHIP_R350:
2086 case CHIP_R420:
2087 case CHIP_R423:
2088 case CHIP_RV410:
2089 case CHIP_RV515:
2090 case CHIP_R520:
2091 case CHIP_RV570:
2092 case CHIP_R580:
2093 dev_priv->flags |= RADEON_HAS_HIERZ;
2094 break;
2095 default:
2096 /* all other chips have no hierarchical z buffer */
2097 break;
2098 }
2099
2100 pci_set_master(dev->pdev);
2101
2102 if (drm_pci_device_is_agp(dev))
2103 dev_priv->flags |= RADEON_IS_AGP;
2104 else if (pci_is_pcie(dev->pdev))
2105 dev_priv->flags |= RADEON_IS_PCIE;
2106 else
2107 dev_priv->flags |= RADEON_IS_PCI;
2108
2109 ret = drm_legacy_addmap(dev, pci_resource_start(dev->pdev, 2),
2110 pci_resource_len(dev->pdev, 2), _DRM_REGISTERS,
2111 _DRM_READ_ONLY | _DRM_DRIVER, &dev_priv->mmio);
2112 if (ret != 0)
2113 return ret;
2114
2115 ret = drm_vblank_init(dev, 2);
2116 if (ret) {
2117 radeon_driver_unload(dev);
2118 return ret;
2119 }
2120
2121 DRM_DEBUG("%s card detected\n",
2122 ((dev_priv->flags & RADEON_IS_AGP) ? "AGP" : (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI"))));
2123 return ret;
2124}
2125
2126int radeon_master_create(struct drm_device *dev, struct drm_master *master)
2127{
2128 struct drm_radeon_master_private *master_priv;
2129 unsigned long sareapage;
2130 int ret;
2131
2132 master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL);
2133 if (!master_priv)
2134 return -ENOMEM;
2135
2136 /* prebuild the SAREA */
2137 sareapage = max_t(unsigned long, SAREA_MAX, PAGE_SIZE);
2138 ret = drm_legacy_addmap(dev, 0, sareapage, _DRM_SHM, _DRM_CONTAINS_LOCK,
2139 &master_priv->sarea);
2140 if (ret) {
2141 DRM_ERROR("SAREA setup failed\n");
2142 kfree(master_priv);
2143 return ret;
2144 }
2145 master_priv->sarea_priv = master_priv->sarea->handle + sizeof(struct drm_sarea);
2146 master_priv->sarea_priv->pfCurrentPage = 0;
2147
2148 master->driver_priv = master_priv;
2149 return 0;
2150}
2151
2152void radeon_master_destroy(struct drm_device *dev, struct drm_master *master)
2153{
2154 struct drm_radeon_master_private *master_priv = master->driver_priv;
2155
2156 if (!master_priv)
2157 return;
2158
2159 if (master_priv->sarea_priv &&
2160 master_priv->sarea_priv->pfCurrentPage != 0)
2161 radeon_cp_dispatch_flip(dev, master);
2162
2163 master_priv->sarea_priv = NULL;
2164 if (master_priv->sarea)
2165 drm_legacy_rmmap_locked(dev, master_priv->sarea);
2166
2167 kfree(master_priv);
2168
2169 master->driver_priv = NULL;
2170}
2171
2172/* Create mappings for registers and framebuffer so userland doesn't necessarily
2173 * have to find them.
2174 */
2175int radeon_driver_firstopen(struct drm_device *dev)
2176{
2177 int ret;
2178 drm_local_map_t *map;
2179 drm_radeon_private_t *dev_priv = dev->dev_private;
2180
2181 dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE;
2182
2183 dev_priv->fb_aper_offset = pci_resource_start(dev->pdev, 0);
2184 ret = drm_legacy_addmap(dev, dev_priv->fb_aper_offset,
2185 pci_resource_len(dev->pdev, 0),
2186 _DRM_FRAME_BUFFER, _DRM_WRITE_COMBINING, &map);
2187 if (ret != 0)
2188 return ret;
2189
2190 return 0;
2191}
2192
2193int radeon_driver_unload(struct drm_device *dev)
2194{
2195 drm_radeon_private_t *dev_priv = dev->dev_private;
2196
2197 DRM_DEBUG("\n");
2198
2199 drm_legacy_rmmap(dev, dev_priv->mmio);
2200
2201 kfree(dev_priv);
2202
2203 dev->dev_private = NULL;
2204 return 0;
2205}
2206
2207void radeon_commit_ring(drm_radeon_private_t *dev_priv)
2208{
2209 int i;
2210 u32 *ring;
2211 int tail_aligned;
2212
2213 /* check if the ring is padded out to 16-dword alignment */
2214
2215 tail_aligned = dev_priv->ring.tail & (RADEON_RING_ALIGN-1);
2216 if (tail_aligned) {
2217 int num_p2 = RADEON_RING_ALIGN - tail_aligned;
2218
2219 ring = dev_priv->ring.start;
2220 /* pad with some CP_PACKET2 */
2221 for (i = 0; i < num_p2; i++)
2222 ring[dev_priv->ring.tail + i] = CP_PACKET2();
2223
2224 dev_priv->ring.tail += i;
2225
2226 dev_priv->ring.space -= num_p2 * sizeof(u32);
2227 }
2228
2229 dev_priv->ring.tail &= dev_priv->ring.tail_mask;
2230
2231 mb();
2232 GET_RING_HEAD( dev_priv );
2233
2234 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
2235 RADEON_WRITE(R600_CP_RB_WPTR, dev_priv->ring.tail);
2236 /* read from PCI bus to ensure correct posting */
2237 RADEON_READ(R600_CP_RB_RPTR);
2238 } else {
2239 RADEON_WRITE(RADEON_CP_RB_WPTR, dev_priv->ring.tail);
2240 /* read from PCI bus to ensure correct posting */
2241 RADEON_READ(RADEON_CP_RB_RPTR);
2242 }
2243}
diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c
index 5b6a6f5b3619..e266ffc520d2 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.c
+++ b/drivers/gpu/drm/radeon/radeon_drv.c
@@ -291,88 +291,6 @@ static struct pci_device_id pciidlist[] = {
291 291
292MODULE_DEVICE_TABLE(pci, pciidlist); 292MODULE_DEVICE_TABLE(pci, pciidlist);
293 293
294#ifdef CONFIG_DRM_RADEON_UMS
295
296static int radeon_suspend(struct drm_device *dev, pm_message_t state)
297{
298 drm_radeon_private_t *dev_priv = dev->dev_private;
299
300 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
301 return 0;
302
303 /* Disable *all* interrupts */
304 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600)
305 RADEON_WRITE(R500_DxMODE_INT_MASK, 0);
306 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
307 return 0;
308}
309
310static int radeon_resume(struct drm_device *dev)
311{
312 drm_radeon_private_t *dev_priv = dev->dev_private;
313
314 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
315 return 0;
316
317 /* Restore interrupt registers */
318 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600)
319 RADEON_WRITE(R500_DxMODE_INT_MASK, dev_priv->r500_disp_irq_reg);
320 RADEON_WRITE(RADEON_GEN_INT_CNTL, dev_priv->irq_enable_reg);
321 return 0;
322}
323
324
325static const struct file_operations radeon_driver_old_fops = {
326 .owner = THIS_MODULE,
327 .open = drm_open,
328 .release = drm_release,
329 .unlocked_ioctl = drm_ioctl,
330 .mmap = drm_legacy_mmap,
331 .poll = drm_poll,
332 .read = drm_read,
333#ifdef CONFIG_COMPAT
334 .compat_ioctl = radeon_compat_ioctl,
335#endif
336 .llseek = noop_llseek,
337};
338
339static struct drm_driver driver_old = {
340 .driver_features =
341 DRIVER_USE_AGP | DRIVER_PCI_DMA | DRIVER_SG |
342 DRIVER_HAVE_IRQ | DRIVER_HAVE_DMA | DRIVER_IRQ_SHARED,
343 .dev_priv_size = sizeof(drm_radeon_buf_priv_t),
344 .load = radeon_driver_load,
345 .firstopen = radeon_driver_firstopen,
346 .open = radeon_driver_open,
347 .preclose = radeon_driver_preclose,
348 .postclose = radeon_driver_postclose,
349 .lastclose = radeon_driver_lastclose,
350 .set_busid = drm_pci_set_busid,
351 .unload = radeon_driver_unload,
352 .suspend = radeon_suspend,
353 .resume = radeon_resume,
354 .get_vblank_counter = radeon_get_vblank_counter,
355 .enable_vblank = radeon_enable_vblank,
356 .disable_vblank = radeon_disable_vblank,
357 .master_create = radeon_master_create,
358 .master_destroy = radeon_master_destroy,
359 .irq_preinstall = radeon_driver_irq_preinstall,
360 .irq_postinstall = radeon_driver_irq_postinstall,
361 .irq_uninstall = radeon_driver_irq_uninstall,
362 .irq_handler = radeon_driver_irq_handler,
363 .ioctls = radeon_ioctls,
364 .dma_ioctl = radeon_cp_buffers,
365 .fops = &radeon_driver_old_fops,
366 .name = DRIVER_NAME,
367 .desc = DRIVER_DESC,
368 .date = DRIVER_DATE,
369 .major = DRIVER_MAJOR,
370 .minor = DRIVER_MINOR,
371 .patchlevel = DRIVER_PATCHLEVEL,
372};
373
374#endif
375
376static struct drm_driver kms_driver; 294static struct drm_driver kms_driver;
377 295
378static int radeon_kick_out_firmware_fb(struct pci_dev *pdev) 296static int radeon_kick_out_firmware_fb(struct pci_dev *pdev)
@@ -619,13 +537,6 @@ static struct drm_driver kms_driver = {
619static struct drm_driver *driver; 537static struct drm_driver *driver;
620static struct pci_driver *pdriver; 538static struct pci_driver *pdriver;
621 539
622#ifdef CONFIG_DRM_RADEON_UMS
623static struct pci_driver radeon_pci_driver = {
624 .name = DRIVER_NAME,
625 .id_table = pciidlist,
626};
627#endif
628
629static struct pci_driver radeon_kms_pci_driver = { 540static struct pci_driver radeon_kms_pci_driver = {
630 .name = DRIVER_NAME, 541 .name = DRIVER_NAME,
631 .id_table = pciidlist, 542 .id_table = pciidlist,
@@ -655,16 +566,8 @@ static int __init radeon_init(void)
655 radeon_register_atpx_handler(); 566 radeon_register_atpx_handler();
656 567
657 } else { 568 } else {
658#ifdef CONFIG_DRM_RADEON_UMS
659 DRM_INFO("radeon userspace modesetting enabled.\n");
660 driver = &driver_old;
661 pdriver = &radeon_pci_driver;
662 driver->driver_features &= ~DRIVER_MODESET;
663 driver->num_ioctls = radeon_max_ioctl;
664#else
665 DRM_ERROR("No UMS support in radeon module!\n"); 569 DRM_ERROR("No UMS support in radeon module!\n");
666 return -EINVAL; 570 return -EINVAL;
667#endif
668 } 571 }
669 572
670 radeon_kfd_init(); 573 radeon_kfd_init();
diff --git a/drivers/gpu/drm/radeon/radeon_drv.h b/drivers/gpu/drm/radeon/radeon_drv.h
index 0caafc7a6e17..afef2d9fccd8 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.h
+++ b/drivers/gpu/drm/radeon/radeon_drv.h
@@ -119,2052 +119,4 @@
119long radeon_drm_ioctl(struct file *filp, 119long radeon_drm_ioctl(struct file *filp,
120 unsigned int cmd, unsigned long arg); 120 unsigned int cmd, unsigned long arg);
121 121
122/* The rest of the file is DEPRECATED! */
123#ifdef CONFIG_DRM_RADEON_UMS
124
125enum radeon_cp_microcode_version {
126 UCODE_R100,
127 UCODE_R200,
128 UCODE_R300,
129};
130
131typedef struct drm_radeon_freelist {
132 unsigned int age;
133 struct drm_buf *buf;
134 struct drm_radeon_freelist *next;
135 struct drm_radeon_freelist *prev;
136} drm_radeon_freelist_t;
137
138typedef struct drm_radeon_ring_buffer {
139 u32 *start;
140 u32 *end;
141 int size;
142 int size_l2qw;
143
144 int rptr_update; /* Double Words */
145 int rptr_update_l2qw; /* log2 Quad Words */
146
147 int fetch_size; /* Double Words */
148 int fetch_size_l2ow; /* log2 Oct Words */
149
150 u32 tail;
151 u32 tail_mask;
152 int space;
153
154 int high_mark;
155} drm_radeon_ring_buffer_t;
156
157typedef struct drm_radeon_depth_clear_t {
158 u32 rb3d_cntl;
159 u32 rb3d_zstencilcntl;
160 u32 se_cntl;
161} drm_radeon_depth_clear_t;
162
163struct drm_radeon_driver_file_fields {
164 int64_t radeon_fb_delta;
165};
166
167struct mem_block {
168 struct mem_block *next;
169 struct mem_block *prev;
170 int start;
171 int size;
172 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
173};
174
175struct radeon_surface {
176 int refcount;
177 u32 lower;
178 u32 upper;
179 u32 flags;
180};
181
182struct radeon_virt_surface {
183 int surface_index;
184 u32 lower;
185 u32 upper;
186 u32 flags;
187 struct drm_file *file_priv;
188#define PCIGART_FILE_PRIV ((void *) -1L)
189};
190
191#define RADEON_FLUSH_EMITED (1 << 0)
192#define RADEON_PURGE_EMITED (1 << 1)
193
194struct drm_radeon_master_private {
195 drm_local_map_t *sarea;
196 drm_radeon_sarea_t *sarea_priv;
197};
198
199typedef struct drm_radeon_private {
200 drm_radeon_ring_buffer_t ring;
201
202 u32 fb_location;
203 u32 fb_size;
204 int new_memmap;
205
206 int gart_size;
207 u32 gart_vm_start;
208 unsigned long gart_buffers_offset;
209
210 int cp_mode;
211 int cp_running;
212
213 drm_radeon_freelist_t *head;
214 drm_radeon_freelist_t *tail;
215 int last_buf;
216 int writeback_works;
217
218 int usec_timeout;
219
220 int microcode_version;
221
222 struct {
223 u32 boxes;
224 int freelist_timeouts;
225 int freelist_loops;
226 int requested_bufs;
227 int last_frame_reads;
228 int last_clear_reads;
229 int clears;
230 int texture_uploads;
231 } stats;
232
233 int do_boxes;
234 int page_flipping;
235
236 u32 color_fmt;
237 unsigned int front_offset;
238 unsigned int front_pitch;
239 unsigned int back_offset;
240 unsigned int back_pitch;
241
242 u32 depth_fmt;
243 unsigned int depth_offset;
244 unsigned int depth_pitch;
245
246 u32 front_pitch_offset;
247 u32 back_pitch_offset;
248 u32 depth_pitch_offset;
249
250 drm_radeon_depth_clear_t depth_clear;
251
252 unsigned long ring_offset;
253 unsigned long ring_rptr_offset;
254 unsigned long buffers_offset;
255 unsigned long gart_textures_offset;
256
257 drm_local_map_t *sarea;
258 drm_local_map_t *cp_ring;
259 drm_local_map_t *ring_rptr;
260 drm_local_map_t *gart_textures;
261
262 struct mem_block *gart_heap;
263 struct mem_block *fb_heap;
264
265 /* SW interrupt */
266 wait_queue_head_t swi_queue;
267 atomic_t swi_emitted;
268 int vblank_crtc;
269 uint32_t irq_enable_reg;
270 uint32_t r500_disp_irq_reg;
271
272 struct radeon_surface surfaces[RADEON_MAX_SURFACES];
273 struct radeon_virt_surface virt_surfaces[2 * RADEON_MAX_SURFACES];
274
275 unsigned long pcigart_offset;
276 unsigned int pcigart_offset_set;
277 struct drm_ati_pcigart_info gart_info;
278
279 u32 scratch_ages[5];
280
281 int have_z_offset;
282
283 /* starting from here on, data is preserved across an open */
284 uint32_t flags; /* see radeon_chip_flags */
285 resource_size_t fb_aper_offset;
286
287 int num_gb_pipes;
288 int num_z_pipes;
289 int track_flush;
290 drm_local_map_t *mmio;
291
292 /* r6xx/r7xx pipe/shader config */
293 int r600_max_pipes;
294 int r600_max_tile_pipes;
295 int r600_max_simds;
296 int r600_max_backends;
297 int r600_max_gprs;
298 int r600_max_threads;
299 int r600_max_stack_entries;
300 int r600_max_hw_contexts;
301 int r600_max_gs_threads;
302 int r600_sx_max_export_size;
303 int r600_sx_max_export_pos_size;
304 int r600_sx_max_export_smx_size;
305 int r600_sq_num_cf_insts;
306 int r700_sx_num_of_sets;
307 int r700_sc_prim_fifo_size;
308 int r700_sc_hiz_tile_fifo_size;
309 int r700_sc_earlyz_tile_fifo_fize;
310 int r600_group_size;
311 int r600_npipes;
312 int r600_nbanks;
313
314 struct mutex cs_mutex;
315 u32 cs_id_scnt;
316 u32 cs_id_wcnt;
317 /* r6xx/r7xx drm blit vertex buffer */
318 struct drm_buf *blit_vb;
319
320 /* firmware */
321 const struct firmware *me_fw, *pfp_fw;
322} drm_radeon_private_t;
323
324typedef struct drm_radeon_buf_priv {
325 u32 age;
326} drm_radeon_buf_priv_t;
327
328struct drm_buffer;
329
330typedef struct drm_radeon_kcmd_buffer {
331 int bufsz;
332 struct drm_buffer *buffer;
333 int nbox;
334 struct drm_clip_rect __user *boxes;
335} drm_radeon_kcmd_buffer_t;
336
337extern int radeon_no_wb;
338extern struct drm_ioctl_desc radeon_ioctls[];
339extern int radeon_max_ioctl;
340
341extern u32 radeon_get_ring_head(drm_radeon_private_t *dev_priv);
342extern void radeon_set_ring_head(drm_radeon_private_t *dev_priv, u32 val);
343
344#define GET_RING_HEAD(dev_priv) radeon_get_ring_head(dev_priv)
345#define SET_RING_HEAD(dev_priv, val) radeon_set_ring_head(dev_priv, val)
346
347/* Check whether the given hardware address is inside the framebuffer or the
348 * GART area.
349 */
350static __inline__ int radeon_check_offset(drm_radeon_private_t *dev_priv,
351 u64 off)
352{
353 u32 fb_start = dev_priv->fb_location;
354 u32 fb_end = fb_start + dev_priv->fb_size - 1;
355 u32 gart_start = dev_priv->gart_vm_start;
356 u32 gart_end = gart_start + dev_priv->gart_size - 1;
357
358 return ((off >= fb_start && off <= fb_end) ||
359 (off >= gart_start && off <= gart_end));
360}
361
362/* radeon_state.c */
363extern void radeon_cp_discard_buffer(struct drm_device *dev, struct drm_master *master, struct drm_buf *buf);
364
365 /* radeon_cp.c */
366extern int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv);
367extern int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv);
368extern int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv);
369extern int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv);
370extern int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv);
371extern int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv);
372extern int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv);
373extern int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv);
374extern int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv);
375extern u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv);
376extern void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc);
377extern void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base);
378
379extern void radeon_freelist_reset(struct drm_device * dev);
380extern struct drm_buf *radeon_freelist_get(struct drm_device * dev);
381
382extern int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n);
383
384extern int radeon_do_cp_idle(drm_radeon_private_t * dev_priv);
385
386extern int radeon_driver_preinit(struct drm_device *dev, unsigned long flags);
387extern int radeon_presetup(struct drm_device *dev);
388extern int radeon_driver_postcleanup(struct drm_device *dev);
389
390extern int radeon_mem_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv);
391extern int radeon_mem_free(struct drm_device *dev, void *data, struct drm_file *file_priv);
392extern int radeon_mem_init_heap(struct drm_device *dev, void *data, struct drm_file *file_priv);
393extern void radeon_mem_takedown(struct mem_block **heap);
394extern void radeon_mem_release(struct drm_file *file_priv,
395 struct mem_block *heap);
396
397extern void radeon_enable_bm(struct drm_radeon_private *dev_priv);
398extern u32 radeon_read_ring_rptr(drm_radeon_private_t *dev_priv, u32 off);
399extern void radeon_write_ring_rptr(drm_radeon_private_t *dev_priv, u32 off, u32 val);
400
401 /* radeon_irq.c */
402extern void radeon_irq_set_state(struct drm_device *dev, u32 mask, int state);
403extern int radeon_irq_emit(struct drm_device *dev, void *data, struct drm_file *file_priv);
404extern int radeon_irq_wait(struct drm_device *dev, void *data, struct drm_file *file_priv);
405
406extern void radeon_do_release(struct drm_device * dev);
407extern u32 radeon_get_vblank_counter(struct drm_device *dev, unsigned int pipe);
408extern int radeon_enable_vblank(struct drm_device *dev, unsigned int pipe);
409extern void radeon_disable_vblank(struct drm_device *dev, unsigned int pipe);
410extern irqreturn_t radeon_driver_irq_handler(int irq, void *arg);
411extern void radeon_driver_irq_preinstall(struct drm_device * dev);
412extern int radeon_driver_irq_postinstall(struct drm_device *dev);
413extern void radeon_driver_irq_uninstall(struct drm_device * dev);
414extern void radeon_enable_interrupt(struct drm_device *dev);
415extern int radeon_vblank_crtc_get(struct drm_device *dev);
416extern int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value);
417
418extern int radeon_driver_load(struct drm_device *dev, unsigned long flags);
419extern int radeon_driver_unload(struct drm_device *dev);
420extern int radeon_driver_firstopen(struct drm_device *dev);
421extern void radeon_driver_preclose(struct drm_device *dev,
422 struct drm_file *file_priv);
423extern void radeon_driver_postclose(struct drm_device *dev,
424 struct drm_file *file_priv);
425extern void radeon_driver_lastclose(struct drm_device * dev);
426extern int radeon_driver_open(struct drm_device *dev,
427 struct drm_file *file_priv);
428extern long radeon_compat_ioctl(struct file *filp, unsigned int cmd,
429 unsigned long arg);
430
431extern int radeon_master_create(struct drm_device *dev, struct drm_master *master);
432extern void radeon_master_destroy(struct drm_device *dev, struct drm_master *master);
433extern void radeon_cp_dispatch_flip(struct drm_device *dev, struct drm_master *master);
434/* r300_cmdbuf.c */
435extern void r300_init_reg_flags(struct drm_device *dev);
436
437extern int r300_do_cp_cmdbuf(struct drm_device *dev,
438 struct drm_file *file_priv,
439 drm_radeon_kcmd_buffer_t *cmdbuf);
440
441/* r600_cp.c */
442extern int r600_do_engine_reset(struct drm_device *dev);
443extern int r600_do_cleanup_cp(struct drm_device *dev);
444extern int r600_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init,
445 struct drm_file *file_priv);
446extern int r600_do_resume_cp(struct drm_device *dev, struct drm_file *file_priv);
447extern int r600_do_cp_idle(drm_radeon_private_t *dev_priv);
448extern void r600_do_cp_start(drm_radeon_private_t *dev_priv);
449extern void r600_do_cp_reset(drm_radeon_private_t *dev_priv);
450extern void r600_do_cp_stop(drm_radeon_private_t *dev_priv);
451extern int r600_cp_dispatch_indirect(struct drm_device *dev,
452 struct drm_buf *buf, int start, int end);
453extern int r600_page_table_init(struct drm_device *dev);
454extern void r600_page_table_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info);
455extern int r600_cs_legacy_ioctl(struct drm_device *dev, void *data, struct drm_file *fpriv);
456extern void r600_cp_dispatch_swap(struct drm_device *dev, struct drm_file *file_priv);
457extern int r600_cp_dispatch_texture(struct drm_device *dev,
458 struct drm_file *file_priv,
459 drm_radeon_texture_t *tex,
460 drm_radeon_tex_image_t *image);
461/* r600_blit.c */
462extern int r600_prepare_blit_copy(struct drm_device *dev, struct drm_file *file_priv);
463extern void r600_done_blit_copy(struct drm_device *dev);
464extern void r600_blit_copy(struct drm_device *dev,
465 uint64_t src_gpu_addr, uint64_t dst_gpu_addr,
466 int size_bytes);
467extern void r600_blit_swap(struct drm_device *dev,
468 uint64_t src_gpu_addr, uint64_t dst_gpu_addr,
469 int sx, int sy, int dx, int dy,
470 int w, int h, int src_pitch, int dst_pitch, int cpp);
471
472/* Flags for stats.boxes
473 */
474#define RADEON_BOX_DMA_IDLE 0x1
475#define RADEON_BOX_RING_FULL 0x2
476#define RADEON_BOX_FLIP 0x4
477#define RADEON_BOX_WAIT_IDLE 0x8
478#define RADEON_BOX_TEXTURE_LOAD 0x10
479
480/* Register definitions, register access macros and drmAddMap constants
481 * for Radeon kernel driver.
482 */
483#define RADEON_MM_INDEX 0x0000
484#define RADEON_MM_DATA 0x0004
485
486#define RADEON_AGP_COMMAND 0x0f60
487#define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config */
488# define RADEON_AGP_ENABLE (1<<8)
489#define RADEON_AUX_SCISSOR_CNTL 0x26f0
490# define RADEON_EXCLUSIVE_SCISSOR_0 (1 << 24)
491# define RADEON_EXCLUSIVE_SCISSOR_1 (1 << 25)
492# define RADEON_EXCLUSIVE_SCISSOR_2 (1 << 26)
493# define RADEON_SCISSOR_0_ENABLE (1 << 28)
494# define RADEON_SCISSOR_1_ENABLE (1 << 29)
495# define RADEON_SCISSOR_2_ENABLE (1 << 30)
496
497/*
498 * PCIE radeons (rv370/rv380, rv410, r423/r430/r480, r5xx)
499 * don't have an explicit bus mastering disable bit. It's handled
500 * by the PCI D-states. PMI_BM_DIS disables D-state bus master
501 * handling, not bus mastering itself.
502 */
503#define RADEON_BUS_CNTL 0x0030
504/* r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
505# define RADEON_BUS_MASTER_DIS (1 << 6)
506/* rs600/rs690/rs740 */
507# define RS600_BUS_MASTER_DIS (1 << 14)
508# define RS600_MSI_REARM (1 << 20)
509/* see RS400_MSI_REARM in AIC_CNTL for rs480 */
510
511#define RADEON_BUS_CNTL1 0x0034
512# define RADEON_PMI_BM_DIS (1 << 2)
513# define RADEON_PMI_INT_DIS (1 << 3)
514
515#define RV370_BUS_CNTL 0x004c
516# define RV370_PMI_BM_DIS (1 << 5)
517# define RV370_PMI_INT_DIS (1 << 6)
518
519#define RADEON_MSI_REARM_EN 0x0160
520/* rv370/rv380, rv410, r423/r430/r480, r5xx */
521# define RV370_MSI_REARM_EN (1 << 0)
522
523#define RADEON_CLOCK_CNTL_DATA 0x000c
524# define RADEON_PLL_WR_EN (1 << 7)
525#define RADEON_CLOCK_CNTL_INDEX 0x0008
526#define RADEON_CONFIG_APER_SIZE 0x0108
527#define RADEON_CONFIG_MEMSIZE 0x00f8
528#define RADEON_CRTC_OFFSET 0x0224
529#define RADEON_CRTC_OFFSET_CNTL 0x0228
530# define RADEON_CRTC_TILE_EN (1 << 15)
531# define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16)
532#define RADEON_CRTC2_OFFSET 0x0324
533#define RADEON_CRTC2_OFFSET_CNTL 0x0328
534
535#define RADEON_PCIE_INDEX 0x0030
536#define RADEON_PCIE_DATA 0x0034
537#define RADEON_PCIE_TX_GART_CNTL 0x10
538# define RADEON_PCIE_TX_GART_EN (1 << 0)
539# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0 << 1)
540# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1 << 1)
541# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3 << 1)
542# define RADEON_PCIE_TX_GART_MODE_32_128_CACHE (0 << 3)
543# define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE (1 << 3)
544# define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN (1 << 5)
545# define RADEON_PCIE_TX_GART_INVALIDATE_TLB (1 << 8)
546#define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11
547#define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12
548#define RADEON_PCIE_TX_GART_BASE 0x13
549#define RADEON_PCIE_TX_GART_START_LO 0x14
550#define RADEON_PCIE_TX_GART_START_HI 0x15
551#define RADEON_PCIE_TX_GART_END_LO 0x16
552#define RADEON_PCIE_TX_GART_END_HI 0x17
553
554#define RS480_NB_MC_INDEX 0x168
555# define RS480_NB_MC_IND_WR_EN (1 << 8)
556#define RS480_NB_MC_DATA 0x16c
557
558#define RS690_MC_INDEX 0x78
559# define RS690_MC_INDEX_MASK 0x1ff
560# define RS690_MC_INDEX_WR_EN (1 << 9)
561# define RS690_MC_INDEX_WR_ACK 0x7f
562#define RS690_MC_DATA 0x7c
563
564/* MC indirect registers */
565#define RS480_MC_MISC_CNTL 0x18
566# define RS480_DISABLE_GTW (1 << 1)
567/* switch between MCIND GART and MM GART registers. 0 = mmgart, 1 = mcind gart */
568# define RS480_GART_INDEX_REG_EN (1 << 12)
569# define RS690_BLOCK_GFX_D3_EN (1 << 14)
570#define RS480_K8_FB_LOCATION 0x1e
571#define RS480_GART_FEATURE_ID 0x2b
572# define RS480_HANG_EN (1 << 11)
573# define RS480_TLB_ENABLE (1 << 18)
574# define RS480_P2P_ENABLE (1 << 19)
575# define RS480_GTW_LAC_EN (1 << 25)
576# define RS480_2LEVEL_GART (0 << 30)
577# define RS480_1LEVEL_GART (1 << 30)
578# define RS480_PDC_EN (1 << 31)
579#define RS480_GART_BASE 0x2c
580#define RS480_GART_CACHE_CNTRL 0x2e
581# define RS480_GART_CACHE_INVALIDATE (1 << 0) /* wait for it to clear */
582#define RS480_AGP_ADDRESS_SPACE_SIZE 0x38
583# define RS480_GART_EN (1 << 0)
584# define RS480_VA_SIZE_32MB (0 << 1)
585# define RS480_VA_SIZE_64MB (1 << 1)
586# define RS480_VA_SIZE_128MB (2 << 1)
587# define RS480_VA_SIZE_256MB (3 << 1)
588# define RS480_VA_SIZE_512MB (4 << 1)
589# define RS480_VA_SIZE_1GB (5 << 1)
590# define RS480_VA_SIZE_2GB (6 << 1)
591#define RS480_AGP_MODE_CNTL 0x39
592# define RS480_POST_GART_Q_SIZE (1 << 18)
593# define RS480_NONGART_SNOOP (1 << 19)
594# define RS480_AGP_RD_BUF_SIZE (1 << 20)
595# define RS480_REQ_TYPE_SNOOP_SHIFT 22
596# define RS480_REQ_TYPE_SNOOP_MASK 0x3
597# define RS480_REQ_TYPE_SNOOP_DIS (1 << 24)
598#define RS480_MC_MISC_UMA_CNTL 0x5f
599#define RS480_MC_MCLK_CNTL 0x7a
600#define RS480_MC_UMA_DUALCH_CNTL 0x86
601
602#define RS690_MC_FB_LOCATION 0x100
603#define RS690_MC_AGP_LOCATION 0x101
604#define RS690_MC_AGP_BASE 0x102
605#define RS690_MC_AGP_BASE_2 0x103
606
607#define RS600_MC_INDEX 0x70
608# define RS600_MC_ADDR_MASK 0xffff
609# define RS600_MC_IND_SEQ_RBS_0 (1 << 16)
610# define RS600_MC_IND_SEQ_RBS_1 (1 << 17)
611# define RS600_MC_IND_SEQ_RBS_2 (1 << 18)
612# define RS600_MC_IND_SEQ_RBS_3 (1 << 19)
613# define RS600_MC_IND_AIC_RBS (1 << 20)
614# define RS600_MC_IND_CITF_ARB0 (1 << 21)
615# define RS600_MC_IND_CITF_ARB1 (1 << 22)
616# define RS600_MC_IND_WR_EN (1 << 23)
617#define RS600_MC_DATA 0x74
618
619#define RS600_MC_STATUS 0x0
620# define RS600_MC_IDLE (1 << 1)
621#define RS600_MC_FB_LOCATION 0x4
622#define RS600_MC_AGP_LOCATION 0x5
623#define RS600_AGP_BASE 0x6
624#define RS600_AGP_BASE_2 0x7
625#define RS600_MC_CNTL1 0x9
626# define RS600_ENABLE_PAGE_TABLES (1 << 26)
627#define RS600_MC_PT0_CNTL 0x100
628# define RS600_ENABLE_PT (1 << 0)
629# define RS600_EFFECTIVE_L2_CACHE_SIZE(x) ((x) << 15)
630# define RS600_EFFECTIVE_L2_QUEUE_SIZE(x) ((x) << 21)
631# define RS600_INVALIDATE_ALL_L1_TLBS (1 << 28)
632# define RS600_INVALIDATE_L2_CACHE (1 << 29)
633#define RS600_MC_PT0_CONTEXT0_CNTL 0x102
634# define RS600_ENABLE_PAGE_TABLE (1 << 0)
635# define RS600_PAGE_TABLE_TYPE_FLAT (0 << 1)
636#define RS600_MC_PT0_SYSTEM_APERTURE_LOW_ADDR 0x112
637#define RS600_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR 0x114
638#define RS600_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR 0x11c
639#define RS600_MC_PT0_CONTEXT0_FLAT_BASE_ADDR 0x12c
640#define RS600_MC_PT0_CONTEXT0_FLAT_START_ADDR 0x13c
641#define RS600_MC_PT0_CONTEXT0_FLAT_END_ADDR 0x14c
642#define RS600_MC_PT0_CLIENT0_CNTL 0x16c
643# define RS600_ENABLE_TRANSLATION_MODE_OVERRIDE (1 << 0)
644# define RS600_TRANSLATION_MODE_OVERRIDE (1 << 1)
645# define RS600_SYSTEM_ACCESS_MODE_MASK (3 << 8)
646# define RS600_SYSTEM_ACCESS_MODE_PA_ONLY (0 << 8)
647# define RS600_SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 8)
648# define RS600_SYSTEM_ACCESS_MODE_IN_SYS (2 << 8)
649# define RS600_SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 8)
650# define RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASSTHROUGH (0 << 10)
651# define RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE (1 << 10)
652# define RS600_EFFECTIVE_L1_CACHE_SIZE(x) ((x) << 11)
653# define RS600_ENABLE_FRAGMENT_PROCESSING (1 << 14)
654# define RS600_EFFECTIVE_L1_QUEUE_SIZE(x) ((x) << 15)
655# define RS600_INVALIDATE_L1_TLB (1 << 20)
656
657#define R520_MC_IND_INDEX 0x70
658#define R520_MC_IND_WR_EN (1 << 24)
659#define R520_MC_IND_DATA 0x74
660
661#define RV515_MC_FB_LOCATION 0x01
662#define RV515_MC_AGP_LOCATION 0x02
663#define RV515_MC_AGP_BASE 0x03
664#define RV515_MC_AGP_BASE_2 0x04
665
666#define R520_MC_FB_LOCATION 0x04
667#define R520_MC_AGP_LOCATION 0x05
668#define R520_MC_AGP_BASE 0x06
669#define R520_MC_AGP_BASE_2 0x07
670
671#define RADEON_MPP_TB_CONFIG 0x01c0
672#define RADEON_MEM_CNTL 0x0140
673#define RADEON_MEM_SDRAM_MODE_REG 0x0158
674#define RADEON_AGP_BASE_2 0x015c /* r200+ only */
675#define RS480_AGP_BASE_2 0x0164
676#define RADEON_AGP_BASE 0x0170
677
678/* pipe config regs */
679#define R400_GB_PIPE_SELECT 0x402c
680#define RV530_GB_PIPE_SELECT2 0x4124
681#define R500_DYN_SCLK_PWMEM_PIPE 0x000d /* PLL */
682#define R300_GB_TILE_CONFIG 0x4018
683# define R300_ENABLE_TILING (1 << 0)
684# define R300_PIPE_COUNT_RV350 (0 << 1)
685# define R300_PIPE_COUNT_R300 (3 << 1)
686# define R300_PIPE_COUNT_R420_3P (6 << 1)
687# define R300_PIPE_COUNT_R420 (7 << 1)
688# define R300_TILE_SIZE_8 (0 << 4)
689# define R300_TILE_SIZE_16 (1 << 4)
690# define R300_TILE_SIZE_32 (2 << 4)
691# define R300_SUBPIXEL_1_12 (0 << 16)
692# define R300_SUBPIXEL_1_16 (1 << 16)
693#define R300_DST_PIPE_CONFIG 0x170c
694# define R300_PIPE_AUTO_CONFIG (1 << 31)
695#define R300_RB2D_DSTCACHE_MODE 0x3428
696# define R300_DC_AUTOFLUSH_ENABLE (1 << 8)
697# define R300_DC_DC_DISABLE_IGNORE_PE (1 << 17)
698
699#define RADEON_RB3D_COLOROFFSET 0x1c40
700#define RADEON_RB3D_COLORPITCH 0x1c48
701
702#define RADEON_SRC_X_Y 0x1590
703
704#define RADEON_DP_GUI_MASTER_CNTL 0x146c
705# define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0)
706# define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1)
707# define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4)
708# define RADEON_GMC_BRUSH_NONE (15 << 4)
709# define RADEON_GMC_DST_16BPP (4 << 8)
710# define RADEON_GMC_DST_24BPP (5 << 8)
711# define RADEON_GMC_DST_32BPP (6 << 8)
712# define RADEON_GMC_DST_DATATYPE_SHIFT 8
713# define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12)
714# define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24)
715# define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24)
716# define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28)
717# define RADEON_GMC_WR_MSK_DIS (1 << 30)
718# define RADEON_ROP3_S 0x00cc0000
719# define RADEON_ROP3_P 0x00f00000
720#define RADEON_DP_WRITE_MASK 0x16cc
721#define RADEON_SRC_PITCH_OFFSET 0x1428
722#define RADEON_DST_PITCH_OFFSET 0x142c
723#define RADEON_DST_PITCH_OFFSET_C 0x1c80
724# define RADEON_DST_TILE_LINEAR (0 << 30)
725# define RADEON_DST_TILE_MACRO (1 << 30)
726# define RADEON_DST_TILE_MICRO (2 << 30)
727# define RADEON_DST_TILE_BOTH (3 << 30)
728
729#define RADEON_SCRATCH_REG0 0x15e0
730#define RADEON_SCRATCH_REG1 0x15e4
731#define RADEON_SCRATCH_REG2 0x15e8
732#define RADEON_SCRATCH_REG3 0x15ec
733#define RADEON_SCRATCH_REG4 0x15f0
734#define RADEON_SCRATCH_REG5 0x15f4
735#define RADEON_SCRATCH_UMSK 0x0770
736#define RADEON_SCRATCH_ADDR 0x0774
737
738#define RADEON_SCRATCHOFF( x ) (RADEON_SCRATCH_REG_OFFSET + 4*(x))
739
740extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index);
741
742#define GET_SCRATCH(dev_priv, x) radeon_get_scratch(dev_priv, x)
743
744#define R600_SCRATCH_REG0 0x8500
745#define R600_SCRATCH_REG1 0x8504
746#define R600_SCRATCH_REG2 0x8508
747#define R600_SCRATCH_REG3 0x850c
748#define R600_SCRATCH_REG4 0x8510
749#define R600_SCRATCH_REG5 0x8514
750#define R600_SCRATCH_REG6 0x8518
751#define R600_SCRATCH_REG7 0x851c
752#define R600_SCRATCH_UMSK 0x8540
753#define R600_SCRATCH_ADDR 0x8544
754
755#define R600_SCRATCHOFF(x) (R600_SCRATCH_REG_OFFSET + 4*(x))
756
757#define RADEON_GEN_INT_CNTL 0x0040
758# define RADEON_CRTC_VBLANK_MASK (1 << 0)
759# define RADEON_CRTC2_VBLANK_MASK (1 << 9)
760# define RADEON_GUI_IDLE_INT_ENABLE (1 << 19)
761# define RADEON_SW_INT_ENABLE (1 << 25)
762
763#define RADEON_GEN_INT_STATUS 0x0044
764# define RADEON_CRTC_VBLANK_STAT (1 << 0)
765# define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0)
766# define RADEON_CRTC2_VBLANK_STAT (1 << 9)
767# define RADEON_CRTC2_VBLANK_STAT_ACK (1 << 9)
768# define RADEON_GUI_IDLE_INT_TEST_ACK (1 << 19)
769# define RADEON_SW_INT_TEST (1 << 25)
770# define RADEON_SW_INT_TEST_ACK (1 << 25)
771# define RADEON_SW_INT_FIRE (1 << 26)
772# define R500_DISPLAY_INT_STATUS (1 << 0)
773
774#define RADEON_HOST_PATH_CNTL 0x0130
775# define RADEON_HDP_SOFT_RESET (1 << 26)
776# define RADEON_HDP_WC_TIMEOUT_MASK (7 << 28)
777# define RADEON_HDP_WC_TIMEOUT_28BCLK (7 << 28)
778
779#define RADEON_ISYNC_CNTL 0x1724
780# define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0)
781# define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1)
782# define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2)
783# define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3)
784# define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4)
785# define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5)
786
787#define RADEON_RBBM_GUICNTL 0x172c
788# define RADEON_HOST_DATA_SWAP_NONE (0 << 0)
789# define RADEON_HOST_DATA_SWAP_16BIT (1 << 0)
790# define RADEON_HOST_DATA_SWAP_32BIT (2 << 0)
791# define RADEON_HOST_DATA_SWAP_HDW (3 << 0)
792
793#define RADEON_MC_AGP_LOCATION 0x014c
794#define RADEON_MC_FB_LOCATION 0x0148
795#define RADEON_MCLK_CNTL 0x0012
796# define RADEON_FORCEON_MCLKA (1 << 16)
797# define RADEON_FORCEON_MCLKB (1 << 17)
798# define RADEON_FORCEON_YCLKA (1 << 18)
799# define RADEON_FORCEON_YCLKB (1 << 19)
800# define RADEON_FORCEON_MC (1 << 20)
801# define RADEON_FORCEON_AIC (1 << 21)
802
803#define RADEON_PP_BORDER_COLOR_0 0x1d40
804#define RADEON_PP_BORDER_COLOR_1 0x1d44
805#define RADEON_PP_BORDER_COLOR_2 0x1d48
806#define RADEON_PP_CNTL 0x1c38
807# define RADEON_SCISSOR_ENABLE (1 << 1)
808#define RADEON_PP_LUM_MATRIX 0x1d00
809#define RADEON_PP_MISC 0x1c14
810#define RADEON_PP_ROT_MATRIX_0 0x1d58
811#define RADEON_PP_TXFILTER_0 0x1c54
812#define RADEON_PP_TXOFFSET_0 0x1c5c
813#define RADEON_PP_TXFILTER_1 0x1c6c
814#define RADEON_PP_TXFILTER_2 0x1c84
815
816#define R300_RB2D_DSTCACHE_CTLSTAT 0x342c /* use R300_DSTCACHE_CTLSTAT */
817#define R300_DSTCACHE_CTLSTAT 0x1714
818# define R300_RB2D_DC_FLUSH (3 << 0)
819# define R300_RB2D_DC_FREE (3 << 2)
820# define R300_RB2D_DC_FLUSH_ALL 0xf
821# define R300_RB2D_DC_BUSY (1 << 31)
822#define RADEON_RB3D_CNTL 0x1c3c
823# define RADEON_ALPHA_BLEND_ENABLE (1 << 0)
824# define RADEON_PLANE_MASK_ENABLE (1 << 1)
825# define RADEON_DITHER_ENABLE (1 << 2)
826# define RADEON_ROUND_ENABLE (1 << 3)
827# define RADEON_SCALE_DITHER_ENABLE (1 << 4)
828# define RADEON_DITHER_INIT (1 << 5)
829# define RADEON_ROP_ENABLE (1 << 6)
830# define RADEON_STENCIL_ENABLE (1 << 7)
831# define RADEON_Z_ENABLE (1 << 8)
832# define RADEON_ZBLOCK16 (1 << 15)
833#define RADEON_RB3D_DEPTHOFFSET 0x1c24
834#define RADEON_RB3D_DEPTHCLEARVALUE 0x3230
835#define RADEON_RB3D_DEPTHPITCH 0x1c28
836#define RADEON_RB3D_PLANEMASK 0x1d84
837#define RADEON_RB3D_STENCILREFMASK 0x1d7c
838#define RADEON_RB3D_ZCACHE_MODE 0x3250
839#define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254
840# define RADEON_RB3D_ZC_FLUSH (1 << 0)
841# define RADEON_RB3D_ZC_FREE (1 << 2)
842# define RADEON_RB3D_ZC_FLUSH_ALL 0x5
843# define RADEON_RB3D_ZC_BUSY (1 << 31)
844#define R300_ZB_ZCACHE_CTLSTAT 0x4f18
845# define R300_ZC_FLUSH (1 << 0)
846# define R300_ZC_FREE (1 << 1)
847# define R300_ZC_BUSY (1 << 31)
848#define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325c
849# define RADEON_RB3D_DC_FLUSH (3 << 0)
850# define RADEON_RB3D_DC_FREE (3 << 2)
851# define RADEON_RB3D_DC_FLUSH_ALL 0xf
852# define RADEON_RB3D_DC_BUSY (1 << 31)
853#define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c
854# define R300_RB3D_DC_FLUSH (2 << 0)
855# define R300_RB3D_DC_FREE (2 << 2)
856# define R300_RB3D_DC_FINISH (1 << 4)
857#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
858# define RADEON_Z_TEST_MASK (7 << 4)
859# define RADEON_Z_TEST_ALWAYS (7 << 4)
860# define RADEON_Z_HIERARCHY_ENABLE (1 << 8)
861# define RADEON_STENCIL_TEST_ALWAYS (7 << 12)
862# define RADEON_STENCIL_S_FAIL_REPLACE (2 << 16)
863# define RADEON_STENCIL_ZPASS_REPLACE (2 << 20)
864# define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24)
865# define RADEON_Z_COMPRESSION_ENABLE (1 << 28)
866# define RADEON_FORCE_Z_DIRTY (1 << 29)
867# define RADEON_Z_WRITE_ENABLE (1 << 30)
868# define RADEON_Z_DECOMPRESSION_ENABLE (1 << 31)
869#define RADEON_RBBM_SOFT_RESET 0x00f0
870# define RADEON_SOFT_RESET_CP (1 << 0)
871# define RADEON_SOFT_RESET_HI (1 << 1)
872# define RADEON_SOFT_RESET_SE (1 << 2)
873# define RADEON_SOFT_RESET_RE (1 << 3)
874# define RADEON_SOFT_RESET_PP (1 << 4)
875# define RADEON_SOFT_RESET_E2 (1 << 5)
876# define RADEON_SOFT_RESET_RB (1 << 6)
877# define RADEON_SOFT_RESET_HDP (1 << 7)
878/*
879 * 6:0 Available slots in the FIFO
880 * 8 Host Interface active
881 * 9 CP request active
882 * 10 FIFO request active
883 * 11 Host Interface retry active
884 * 12 CP retry active
885 * 13 FIFO retry active
886 * 14 FIFO pipeline busy
887 * 15 Event engine busy
888 * 16 CP command stream busy
889 * 17 2D engine busy
890 * 18 2D portion of render backend busy
891 * 20 3D setup engine busy
892 * 26 GA engine busy
893 * 27 CBA 2D engine busy
894 * 31 2D engine busy or 3D engine busy or FIFO not empty or CP busy or
895 * command stream queue not empty or Ring Buffer not empty
896 */
897#define RADEON_RBBM_STATUS 0x0e40
898/* Same as the previous RADEON_RBBM_STATUS; this is a mirror of that register. */
899/* #define RADEON_RBBM_STATUS 0x1740 */
900/* bits 6:0 are dword slots available in the cmd fifo */
901# define RADEON_RBBM_FIFOCNT_MASK 0x007f
902# define RADEON_HIRQ_ON_RBB (1 << 8)
903# define RADEON_CPRQ_ON_RBB (1 << 9)
904# define RADEON_CFRQ_ON_RBB (1 << 10)
905# define RADEON_HIRQ_IN_RTBUF (1 << 11)
906# define RADEON_CPRQ_IN_RTBUF (1 << 12)
907# define RADEON_CFRQ_IN_RTBUF (1 << 13)
908# define RADEON_PIPE_BUSY (1 << 14)
909# define RADEON_ENG_EV_BUSY (1 << 15)
910# define RADEON_CP_CMDSTRM_BUSY (1 << 16)
911# define RADEON_E2_BUSY (1 << 17)
912# define RADEON_RB2D_BUSY (1 << 18)
913# define RADEON_RB3D_BUSY (1 << 19) /* not used on r300 */
914# define RADEON_VAP_BUSY (1 << 20)
915# define RADEON_RE_BUSY (1 << 21) /* not used on r300 */
916# define RADEON_TAM_BUSY (1 << 22) /* not used on r300 */
917# define RADEON_TDM_BUSY (1 << 23) /* not used on r300 */
918# define RADEON_PB_BUSY (1 << 24) /* not used on r300 */
919# define RADEON_TIM_BUSY (1 << 25) /* not used on r300 */
920# define RADEON_GA_BUSY (1 << 26)
921# define RADEON_CBA2D_BUSY (1 << 27)
922# define RADEON_RBBM_ACTIVE (1 << 31)
923#define RADEON_RE_LINE_PATTERN 0x1cd0
924#define RADEON_RE_MISC 0x26c4
925#define RADEON_RE_TOP_LEFT 0x26c0
926#define RADEON_RE_WIDTH_HEIGHT 0x1c44
927#define RADEON_RE_STIPPLE_ADDR 0x1cc8
928#define RADEON_RE_STIPPLE_DATA 0x1ccc
929
930#define RADEON_SCISSOR_TL_0 0x1cd8
931#define RADEON_SCISSOR_BR_0 0x1cdc
932#define RADEON_SCISSOR_TL_1 0x1ce0
933#define RADEON_SCISSOR_BR_1 0x1ce4
934#define RADEON_SCISSOR_TL_2 0x1ce8
935#define RADEON_SCISSOR_BR_2 0x1cec
936#define RADEON_SE_COORD_FMT 0x1c50
937#define RADEON_SE_CNTL 0x1c4c
938# define RADEON_FFACE_CULL_CW (0 << 0)
939# define RADEON_BFACE_SOLID (3 << 1)
940# define RADEON_FFACE_SOLID (3 << 3)
941# define RADEON_FLAT_SHADE_VTX_LAST (3 << 6)
942# define RADEON_DIFFUSE_SHADE_FLAT (1 << 8)
943# define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8)
944# define RADEON_ALPHA_SHADE_FLAT (1 << 10)
945# define RADEON_ALPHA_SHADE_GOURAUD (2 << 10)
946# define RADEON_SPECULAR_SHADE_FLAT (1 << 12)
947# define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12)
948# define RADEON_FOG_SHADE_FLAT (1 << 14)
949# define RADEON_FOG_SHADE_GOURAUD (2 << 14)
950# define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24)
951# define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25)
952# define RADEON_VTX_PIX_CENTER_OGL (1 << 27)
953# define RADEON_ROUND_MODE_TRUNC (0 << 28)
954# define RADEON_ROUND_PREC_8TH_PIX (1 << 30)
955#define RADEON_SE_CNTL_STATUS 0x2140
956#define RADEON_SE_LINE_WIDTH 0x1db8
957#define RADEON_SE_VPORT_XSCALE 0x1d98
958#define RADEON_SE_ZBIAS_FACTOR 0x1db0
959#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210
960#define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254
961#define RADEON_SE_TCL_VECTOR_INDX_REG 0x2200
962# define RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT 16
963# define RADEON_VEC_INDX_DWORD_COUNT_SHIFT 28
964#define RADEON_SE_TCL_VECTOR_DATA_REG 0x2204
965#define RADEON_SE_TCL_SCALAR_INDX_REG 0x2208
966# define RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT 16
967#define RADEON_SE_TCL_SCALAR_DATA_REG 0x220C
968#define RADEON_SURFACE_ACCESS_FLAGS 0x0bf8
969#define RADEON_SURFACE_ACCESS_CLR 0x0bfc
970#define RADEON_SURFACE_CNTL 0x0b00
971# define RADEON_SURF_TRANSLATION_DIS (1 << 8)
972# define RADEON_NONSURF_AP0_SWP_MASK (3 << 20)
973# define RADEON_NONSURF_AP0_SWP_LITTLE (0 << 20)
974# define RADEON_NONSURF_AP0_SWP_BIG16 (1 << 20)
975# define RADEON_NONSURF_AP0_SWP_BIG32 (2 << 20)
976# define RADEON_NONSURF_AP1_SWP_MASK (3 << 22)
977# define RADEON_NONSURF_AP1_SWP_LITTLE (0 << 22)
978# define RADEON_NONSURF_AP1_SWP_BIG16 (1 << 22)
979# define RADEON_NONSURF_AP1_SWP_BIG32 (2 << 22)
980#define RADEON_SURFACE0_INFO 0x0b0c
981# define RADEON_SURF_PITCHSEL_MASK (0x1ff << 0)
982# define RADEON_SURF_TILE_MODE_MASK (3 << 16)
983# define RADEON_SURF_TILE_MODE_MACRO (0 << 16)
984# define RADEON_SURF_TILE_MODE_MICRO (1 << 16)
985# define RADEON_SURF_TILE_MODE_32BIT_Z (2 << 16)
986# define RADEON_SURF_TILE_MODE_16BIT_Z (3 << 16)
987#define RADEON_SURFACE0_LOWER_BOUND 0x0b04
988#define RADEON_SURFACE0_UPPER_BOUND 0x0b08
989# define RADEON_SURF_ADDRESS_FIXED_MASK (0x3ff << 0)
990#define RADEON_SURFACE1_INFO 0x0b1c
991#define RADEON_SURFACE1_LOWER_BOUND 0x0b14
992#define RADEON_SURFACE1_UPPER_BOUND 0x0b18
993#define RADEON_SURFACE2_INFO 0x0b2c
994#define RADEON_SURFACE2_LOWER_BOUND 0x0b24
995#define RADEON_SURFACE2_UPPER_BOUND 0x0b28
996#define RADEON_SURFACE3_INFO 0x0b3c
997#define RADEON_SURFACE3_LOWER_BOUND 0x0b34
998#define RADEON_SURFACE3_UPPER_BOUND 0x0b38
999#define RADEON_SURFACE4_INFO 0x0b4c
1000#define RADEON_SURFACE4_LOWER_BOUND 0x0b44
1001#define RADEON_SURFACE4_UPPER_BOUND 0x0b48
1002#define RADEON_SURFACE5_INFO 0x0b5c
1003#define RADEON_SURFACE5_LOWER_BOUND 0x0b54
1004#define RADEON_SURFACE5_UPPER_BOUND 0x0b58
1005#define RADEON_SURFACE6_INFO 0x0b6c
1006#define RADEON_SURFACE6_LOWER_BOUND 0x0b64
1007#define RADEON_SURFACE6_UPPER_BOUND 0x0b68
1008#define RADEON_SURFACE7_INFO 0x0b7c
1009#define RADEON_SURFACE7_LOWER_BOUND 0x0b74
1010#define RADEON_SURFACE7_UPPER_BOUND 0x0b78
1011#define RADEON_SW_SEMAPHORE 0x013c
1012
1013#define RADEON_WAIT_UNTIL 0x1720
1014# define RADEON_WAIT_CRTC_PFLIP (1 << 0)
1015# define RADEON_WAIT_2D_IDLE (1 << 14)
1016# define RADEON_WAIT_3D_IDLE (1 << 15)
1017# define RADEON_WAIT_2D_IDLECLEAN (1 << 16)
1018# define RADEON_WAIT_3D_IDLECLEAN (1 << 17)
1019# define RADEON_WAIT_HOST_IDLECLEAN (1 << 18)
1020
1021#define RADEON_RB3D_ZMASKOFFSET 0x3234
1022#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
1023# define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0)
1024# define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0)
1025
1026/* CP registers */
1027#define RADEON_CP_ME_RAM_ADDR 0x07d4
1028#define RADEON_CP_ME_RAM_RADDR 0x07d8
1029#define RADEON_CP_ME_RAM_DATAH 0x07dc
1030#define RADEON_CP_ME_RAM_DATAL 0x07e0
1031
1032#define RADEON_CP_RB_BASE 0x0700
1033#define RADEON_CP_RB_CNTL 0x0704
1034# define RADEON_BUF_SWAP_32BIT (2 << 16)
1035# define RADEON_RB_NO_UPDATE (1 << 27)
1036# define RADEON_RB_RPTR_WR_ENA (1 << 31)
1037#define RADEON_CP_RB_RPTR_ADDR 0x070c
1038#define RADEON_CP_RB_RPTR 0x0710
1039#define RADEON_CP_RB_WPTR 0x0714
1040
1041#define RADEON_CP_RB_WPTR_DELAY 0x0718
1042# define RADEON_PRE_WRITE_TIMER_SHIFT 0
1043# define RADEON_PRE_WRITE_LIMIT_SHIFT 23
1044
1045#define RADEON_CP_IB_BASE 0x0738
1046
1047#define RADEON_CP_CSQ_CNTL 0x0740
1048# define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0)
1049# define RADEON_CSQ_PRIDIS_INDDIS (0 << 28)
1050# define RADEON_CSQ_PRIPIO_INDDIS (1 << 28)
1051# define RADEON_CSQ_PRIBM_INDDIS (2 << 28)
1052# define RADEON_CSQ_PRIPIO_INDBM (3 << 28)
1053# define RADEON_CSQ_PRIBM_INDBM (4 << 28)
1054# define RADEON_CSQ_PRIPIO_INDPIO (15 << 28)
1055
1056#define R300_CP_RESYNC_ADDR 0x0778
1057#define R300_CP_RESYNC_DATA 0x077c
1058
1059#define RADEON_AIC_CNTL 0x01d0
1060# define RADEON_PCIGART_TRANSLATE_EN (1 << 0)
1061# define RS400_MSI_REARM (1 << 3)
1062#define RADEON_AIC_STAT 0x01d4
1063#define RADEON_AIC_PT_BASE 0x01d8
1064#define RADEON_AIC_LO_ADDR 0x01dc
1065#define RADEON_AIC_HI_ADDR 0x01e0
1066#define RADEON_AIC_TLB_ADDR 0x01e4
1067#define RADEON_AIC_TLB_DATA 0x01e8
1068
1069/* CP command packets */
1070#define RADEON_CP_PACKET0 0x00000000
1071# define RADEON_ONE_REG_WR (1 << 15)
1072#define RADEON_CP_PACKET1 0x40000000
1073#define RADEON_CP_PACKET2 0x80000000
1074#define RADEON_CP_PACKET3 0xC0000000
1075# define RADEON_CP_NOP 0x00001000
1076# define RADEON_CP_NEXT_CHAR 0x00001900
1077# define RADEON_CP_PLY_NEXTSCAN 0x00001D00
1078# define RADEON_CP_SET_SCISSORS 0x00001E00
1079 /* GEN_INDX_PRIM is unsupported starting with R300 */
1080# define RADEON_3D_RNDR_GEN_INDX_PRIM 0x00002300
1081# define RADEON_WAIT_FOR_IDLE 0x00002600
1082# define RADEON_3D_DRAW_VBUF 0x00002800
1083# define RADEON_3D_DRAW_IMMD 0x00002900
1084# define RADEON_3D_DRAW_INDX 0x00002A00
1085# define RADEON_CP_LOAD_PALETTE 0x00002C00
1086# define RADEON_3D_LOAD_VBPNTR 0x00002F00
1087# define RADEON_MPEG_IDCT_MACROBLOCK 0x00003000
1088# define RADEON_MPEG_IDCT_MACROBLOCK_REV 0x00003100
1089# define RADEON_3D_CLEAR_ZMASK 0x00003200
1090# define RADEON_CP_INDX_BUFFER 0x00003300
1091# define RADEON_CP_3D_DRAW_VBUF_2 0x00003400
1092# define RADEON_CP_3D_DRAW_IMMD_2 0x00003500
1093# define RADEON_CP_3D_DRAW_INDX_2 0x00003600
1094# define RADEON_3D_CLEAR_HIZ 0x00003700
1095# define RADEON_CP_3D_CLEAR_CMASK 0x00003802
1096# define RADEON_CNTL_HOSTDATA_BLT 0x00009400
1097# define RADEON_CNTL_PAINT_MULTI 0x00009A00
1098# define RADEON_CNTL_BITBLT_MULTI 0x00009B00
1099# define RADEON_CNTL_SET_SCISSORS 0xC0001E00
1100
1101# define R600_IT_INDIRECT_BUFFER_END 0x00001700
1102# define R600_IT_SET_PREDICATION 0x00002000
1103# define R600_IT_REG_RMW 0x00002100
1104# define R600_IT_COND_EXEC 0x00002200
1105# define R600_IT_PRED_EXEC 0x00002300
1106# define R600_IT_START_3D_CMDBUF 0x00002400
1107# define R600_IT_DRAW_INDEX_2 0x00002700
1108# define R600_IT_CONTEXT_CONTROL 0x00002800
1109# define R600_IT_DRAW_INDEX_IMMD_BE 0x00002900
1110# define R600_IT_INDEX_TYPE 0x00002A00
1111# define R600_IT_DRAW_INDEX 0x00002B00
1112# define R600_IT_DRAW_INDEX_AUTO 0x00002D00
1113# define R600_IT_DRAW_INDEX_IMMD 0x00002E00
1114# define R600_IT_NUM_INSTANCES 0x00002F00
1115# define R600_IT_STRMOUT_BUFFER_UPDATE 0x00003400
1116# define R600_IT_INDIRECT_BUFFER_MP 0x00003800
1117# define R600_IT_MEM_SEMAPHORE 0x00003900
1118# define R600_IT_MPEG_INDEX 0x00003A00
1119# define R600_IT_WAIT_REG_MEM 0x00003C00
1120# define R600_IT_MEM_WRITE 0x00003D00
1121# define R600_IT_INDIRECT_BUFFER 0x00003200
1122# define R600_IT_SURFACE_SYNC 0x00004300
1123# define R600_CB0_DEST_BASE_ENA (1 << 6)
1124# define R600_TC_ACTION_ENA (1 << 23)
1125# define R600_VC_ACTION_ENA (1 << 24)
1126# define R600_CB_ACTION_ENA (1 << 25)
1127# define R600_DB_ACTION_ENA (1 << 26)
1128# define R600_SH_ACTION_ENA (1 << 27)
1129# define R600_SMX_ACTION_ENA (1 << 28)
1130# define R600_IT_ME_INITIALIZE 0x00004400
1131# define R600_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16)
1132# define R600_IT_COND_WRITE 0x00004500
1133# define R600_IT_EVENT_WRITE 0x00004600
1134# define R600_IT_EVENT_WRITE_EOP 0x00004700
1135# define R600_IT_ONE_REG_WRITE 0x00005700
1136# define R600_IT_SET_CONFIG_REG 0x00006800
1137# define R600_SET_CONFIG_REG_OFFSET 0x00008000
1138# define R600_SET_CONFIG_REG_END 0x0000ac00
1139# define R600_IT_SET_CONTEXT_REG 0x00006900
1140# define R600_SET_CONTEXT_REG_OFFSET 0x00028000
1141# define R600_SET_CONTEXT_REG_END 0x00029000
1142# define R600_IT_SET_ALU_CONST 0x00006A00
1143# define R600_SET_ALU_CONST_OFFSET 0x00030000
1144# define R600_SET_ALU_CONST_END 0x00032000
1145# define R600_IT_SET_BOOL_CONST 0x00006B00
1146# define R600_SET_BOOL_CONST_OFFSET 0x0003e380
1147# define R600_SET_BOOL_CONST_END 0x00040000
1148# define R600_IT_SET_LOOP_CONST 0x00006C00
1149# define R600_SET_LOOP_CONST_OFFSET 0x0003e200
1150# define R600_SET_LOOP_CONST_END 0x0003e380
1151# define R600_IT_SET_RESOURCE 0x00006D00
1152# define R600_SET_RESOURCE_OFFSET 0x00038000
1153# define R600_SET_RESOURCE_END 0x0003c000
1154# define R600_SQ_TEX_VTX_INVALID_TEXTURE 0x0
1155# define R600_SQ_TEX_VTX_INVALID_BUFFER 0x1
1156# define R600_SQ_TEX_VTX_VALID_TEXTURE 0x2
1157# define R600_SQ_TEX_VTX_VALID_BUFFER 0x3
1158# define R600_IT_SET_SAMPLER 0x00006E00
1159# define R600_SET_SAMPLER_OFFSET 0x0003c000
1160# define R600_SET_SAMPLER_END 0x0003cff0
1161# define R600_IT_SET_CTL_CONST 0x00006F00
1162# define R600_SET_CTL_CONST_OFFSET 0x0003cff0
1163# define R600_SET_CTL_CONST_END 0x0003e200
1164# define R600_IT_SURFACE_BASE_UPDATE 0x00007300
1165
1166#define RADEON_CP_PACKET_MASK 0xC0000000
1167#define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000
1168#define RADEON_CP_PACKET0_REG_MASK 0x000007ff
1169#define RADEON_CP_PACKET1_REG0_MASK 0x000007ff
1170#define RADEON_CP_PACKET1_REG1_MASK 0x003ff800
1171
1172#define RADEON_VTX_Z_PRESENT (1 << 31)
1173#define RADEON_VTX_PKCOLOR_PRESENT (1 << 3)
1174
1175#define RADEON_PRIM_TYPE_NONE (0 << 0)
1176#define RADEON_PRIM_TYPE_POINT (1 << 0)
1177#define RADEON_PRIM_TYPE_LINE (2 << 0)
1178#define RADEON_PRIM_TYPE_LINE_STRIP (3 << 0)
1179#define RADEON_PRIM_TYPE_TRI_LIST (4 << 0)
1180#define RADEON_PRIM_TYPE_TRI_FAN (5 << 0)
1181#define RADEON_PRIM_TYPE_TRI_STRIP (6 << 0)
1182#define RADEON_PRIM_TYPE_TRI_TYPE2 (7 << 0)
1183#define RADEON_PRIM_TYPE_RECT_LIST (8 << 0)
1184#define RADEON_PRIM_TYPE_3VRT_POINT_LIST (9 << 0)
1185#define RADEON_PRIM_TYPE_3VRT_LINE_LIST (10 << 0)
1186#define RADEON_PRIM_TYPE_MASK 0xf
1187#define RADEON_PRIM_WALK_IND (1 << 4)
1188#define RADEON_PRIM_WALK_LIST (2 << 4)
1189#define RADEON_PRIM_WALK_RING (3 << 4)
1190#define RADEON_COLOR_ORDER_BGRA (0 << 6)
1191#define RADEON_COLOR_ORDER_RGBA (1 << 6)
1192#define RADEON_MAOS_ENABLE (1 << 7)
1193#define RADEON_VTX_FMT_R128_MODE (0 << 8)
1194#define RADEON_VTX_FMT_RADEON_MODE (1 << 8)
1195#define RADEON_NUM_VERTICES_SHIFT 16
1196
1197#define RADEON_COLOR_FORMAT_CI8 2
1198#define RADEON_COLOR_FORMAT_ARGB1555 3
1199#define RADEON_COLOR_FORMAT_RGB565 4
1200#define RADEON_COLOR_FORMAT_ARGB8888 6
1201#define RADEON_COLOR_FORMAT_RGB332 7
1202#define RADEON_COLOR_FORMAT_RGB8 9
1203#define RADEON_COLOR_FORMAT_ARGB4444 15
1204
1205#define RADEON_TXFORMAT_I8 0
1206#define RADEON_TXFORMAT_AI88 1
1207#define RADEON_TXFORMAT_RGB332 2
1208#define RADEON_TXFORMAT_ARGB1555 3
1209#define RADEON_TXFORMAT_RGB565 4
1210#define RADEON_TXFORMAT_ARGB4444 5
1211#define RADEON_TXFORMAT_ARGB8888 6
1212#define RADEON_TXFORMAT_RGBA8888 7
1213#define RADEON_TXFORMAT_Y8 8
1214#define RADEON_TXFORMAT_VYUY422 10
1215#define RADEON_TXFORMAT_YVYU422 11
1216#define RADEON_TXFORMAT_DXT1 12
1217#define RADEON_TXFORMAT_DXT23 14
1218#define RADEON_TXFORMAT_DXT45 15
1219
1220#define R200_PP_TXCBLEND_0 0x2f00
1221#define R200_PP_TXCBLEND_1 0x2f10
1222#define R200_PP_TXCBLEND_2 0x2f20
1223#define R200_PP_TXCBLEND_3 0x2f30
1224#define R200_PP_TXCBLEND_4 0x2f40
1225#define R200_PP_TXCBLEND_5 0x2f50
1226#define R200_PP_TXCBLEND_6 0x2f60
1227#define R200_PP_TXCBLEND_7 0x2f70
1228#define R200_SE_TCL_LIGHT_MODEL_CTL_0 0x2268
1229#define R200_PP_TFACTOR_0 0x2ee0
1230#define R200_SE_VTX_FMT_0 0x2088
1231#define R200_SE_VAP_CNTL 0x2080
1232#define R200_SE_TCL_MATRIX_SEL_0 0x2230
1233#define R200_SE_TCL_TEX_PROC_CTL_2 0x22a8
1234#define R200_SE_TCL_UCP_VERT_BLEND_CTL 0x22c0
1235#define R200_PP_TXFILTER_5 0x2ca0
1236#define R200_PP_TXFILTER_4 0x2c80
1237#define R200_PP_TXFILTER_3 0x2c60
1238#define R200_PP_TXFILTER_2 0x2c40
1239#define R200_PP_TXFILTER_1 0x2c20
1240#define R200_PP_TXFILTER_0 0x2c00
1241#define R200_PP_TXOFFSET_5 0x2d78
1242#define R200_PP_TXOFFSET_4 0x2d60
1243#define R200_PP_TXOFFSET_3 0x2d48
1244#define R200_PP_TXOFFSET_2 0x2d30
1245#define R200_PP_TXOFFSET_1 0x2d18
1246#define R200_PP_TXOFFSET_0 0x2d00
1247
1248#define R200_PP_CUBIC_FACES_0 0x2c18
1249#define R200_PP_CUBIC_FACES_1 0x2c38
1250#define R200_PP_CUBIC_FACES_2 0x2c58
1251#define R200_PP_CUBIC_FACES_3 0x2c78
1252#define R200_PP_CUBIC_FACES_4 0x2c98
1253#define R200_PP_CUBIC_FACES_5 0x2cb8
1254#define R200_PP_CUBIC_OFFSET_F1_0 0x2d04
1255#define R200_PP_CUBIC_OFFSET_F2_0 0x2d08
1256#define R200_PP_CUBIC_OFFSET_F3_0 0x2d0c
1257#define R200_PP_CUBIC_OFFSET_F4_0 0x2d10
1258#define R200_PP_CUBIC_OFFSET_F5_0 0x2d14
1259#define R200_PP_CUBIC_OFFSET_F1_1 0x2d1c
1260#define R200_PP_CUBIC_OFFSET_F2_1 0x2d20
1261#define R200_PP_CUBIC_OFFSET_F3_1 0x2d24
1262#define R200_PP_CUBIC_OFFSET_F4_1 0x2d28
1263#define R200_PP_CUBIC_OFFSET_F5_1 0x2d2c
1264#define R200_PP_CUBIC_OFFSET_F1_2 0x2d34
1265#define R200_PP_CUBIC_OFFSET_F2_2 0x2d38
1266#define R200_PP_CUBIC_OFFSET_F3_2 0x2d3c
1267#define R200_PP_CUBIC_OFFSET_F4_2 0x2d40
1268#define R200_PP_CUBIC_OFFSET_F5_2 0x2d44
1269#define R200_PP_CUBIC_OFFSET_F1_3 0x2d4c
1270#define R200_PP_CUBIC_OFFSET_F2_3 0x2d50
1271#define R200_PP_CUBIC_OFFSET_F3_3 0x2d54
1272#define R200_PP_CUBIC_OFFSET_F4_3 0x2d58
1273#define R200_PP_CUBIC_OFFSET_F5_3 0x2d5c
1274#define R200_PP_CUBIC_OFFSET_F1_4 0x2d64
1275#define R200_PP_CUBIC_OFFSET_F2_4 0x2d68
1276#define R200_PP_CUBIC_OFFSET_F3_4 0x2d6c
1277#define R200_PP_CUBIC_OFFSET_F4_4 0x2d70
1278#define R200_PP_CUBIC_OFFSET_F5_4 0x2d74
1279#define R200_PP_CUBIC_OFFSET_F1_5 0x2d7c
1280#define R200_PP_CUBIC_OFFSET_F2_5 0x2d80
1281#define R200_PP_CUBIC_OFFSET_F3_5 0x2d84
1282#define R200_PP_CUBIC_OFFSET_F4_5 0x2d88
1283#define R200_PP_CUBIC_OFFSET_F5_5 0x2d8c
1284
1285#define R200_RE_AUX_SCISSOR_CNTL 0x26f0
1286#define R200_SE_VTE_CNTL 0x20b0
1287#define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250
1288#define R200_PP_TAM_DEBUG3 0x2d9c
1289#define R200_PP_CNTL_X 0x2cc4
1290#define R200_SE_VAP_CNTL_STATUS 0x2140
1291#define R200_RE_SCISSOR_TL_0 0x1cd8
1292#define R200_RE_SCISSOR_TL_1 0x1ce0
1293#define R200_RE_SCISSOR_TL_2 0x1ce8
1294#define R200_RB3D_DEPTHXY_OFFSET 0x1d60
1295#define R200_RE_AUX_SCISSOR_CNTL 0x26f0
1296#define R200_SE_VTX_STATE_CNTL 0x2180
1297#define R200_RE_POINTSIZE 0x2648
1298#define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0 0x2254
1299
1300#define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */
1301#define RADEON_PP_TEX_SIZE_1 0x1d0c
1302#define RADEON_PP_TEX_SIZE_2 0x1d14
1303
1304#define RADEON_PP_CUBIC_FACES_0 0x1d24
1305#define RADEON_PP_CUBIC_FACES_1 0x1d28
1306#define RADEON_PP_CUBIC_FACES_2 0x1d2c
1307#define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */
1308#define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00
1309#define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14
1310
1311#define RADEON_SE_TCL_STATE_FLUSH 0x2284
1312
1313#define SE_VAP_CNTL__TCL_ENA_MASK 0x00000001
1314#define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK 0x00010000
1315#define SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT 0x00000012
1316#define SE_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100
1317#define SE_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200
1318#define SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK 0x00000001
1319#define SE_VTX_FMT_0__VTX_W0_PRESENT_MASK 0x00000002
1320#define SE_VTX_FMT_0__VTX_COLOR_0_FMT__SHIFT 0x0000000b
1321#define R200_3D_DRAW_IMMD_2 0xC0003500
1322#define R200_SE_VTX_FMT_1 0x208c
1323#define R200_RE_CNTL 0x1c50
1324
1325#define R200_RB3D_BLENDCOLOR 0x3218
1326
1327#define R200_SE_TCL_POINT_SPRITE_CNTL 0x22c4
1328
1329#define R200_PP_TRI_PERF 0x2cf8
1330
1331#define R200_PP_AFS_0 0x2f80
1332#define R200_PP_AFS_1 0x2f00 /* same as txcblend_0 */
1333
1334#define R200_VAP_PVS_CNTL_1 0x22D0
1335
1336#define RADEON_CRTC_CRNT_FRAME 0x0214
1337#define RADEON_CRTC2_CRNT_FRAME 0x0314
1338
1339#define R500_D1CRTC_STATUS 0x609c
1340#define R500_D2CRTC_STATUS 0x689c
1341#define R500_CRTC_V_BLANK (1<<0)
1342
1343#define R500_D1CRTC_FRAME_COUNT 0x60a4
1344#define R500_D2CRTC_FRAME_COUNT 0x68a4
1345
1346#define R500_D1MODE_V_COUNTER 0x6530
1347#define R500_D2MODE_V_COUNTER 0x6d30
1348
1349#define R500_D1MODE_VBLANK_STATUS 0x6534
1350#define R500_D2MODE_VBLANK_STATUS 0x6d34
1351#define R500_VBLANK_OCCURED (1<<0)
1352#define R500_VBLANK_ACK (1<<4)
1353#define R500_VBLANK_STAT (1<<12)
1354#define R500_VBLANK_INT (1<<16)
1355
1356#define R500_DxMODE_INT_MASK 0x6540
1357#define R500_D1MODE_INT_MASK (1<<0)
1358#define R500_D2MODE_INT_MASK (1<<8)
1359
1360#define R500_DISP_INTERRUPT_STATUS 0x7edc
1361#define R500_D1_VBLANK_INTERRUPT (1 << 4)
1362#define R500_D2_VBLANK_INTERRUPT (1 << 5)
1363
1364/* R6xx/R7xx registers */
1365#define R600_MC_VM_FB_LOCATION 0x2180
1366#define R600_MC_VM_AGP_TOP 0x2184
1367#define R600_MC_VM_AGP_BOT 0x2188
1368#define R600_MC_VM_AGP_BASE 0x218c
1369#define R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2190
1370#define R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194
1371#define R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198
1372
1373#define R700_MC_VM_FB_LOCATION 0x2024
1374#define R700_MC_VM_AGP_TOP 0x2028
1375#define R700_MC_VM_AGP_BOT 0x202c
1376#define R700_MC_VM_AGP_BASE 0x2030
1377#define R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034
1378#define R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038
1379#define R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203c
1380
1381#define R600_MCD_RD_A_CNTL 0x219c
1382#define R600_MCD_RD_B_CNTL 0x21a0
1383
1384#define R600_MCD_WR_A_CNTL 0x21a4
1385#define R600_MCD_WR_B_CNTL 0x21a8
1386
1387#define R600_MCD_RD_SYS_CNTL 0x2200
1388#define R600_MCD_WR_SYS_CNTL 0x2214
1389
1390#define R600_MCD_RD_GFX_CNTL 0x21fc
1391#define R600_MCD_RD_HDP_CNTL 0x2204
1392#define R600_MCD_RD_PDMA_CNTL 0x2208
1393#define R600_MCD_RD_SEM_CNTL 0x220c
1394#define R600_MCD_WR_GFX_CNTL 0x2210
1395#define R600_MCD_WR_HDP_CNTL 0x2218
1396#define R600_MCD_WR_PDMA_CNTL 0x221c
1397#define R600_MCD_WR_SEM_CNTL 0x2220
1398
1399# define R600_MCD_L1_TLB (1 << 0)
1400# define R600_MCD_L1_FRAG_PROC (1 << 1)
1401# define R600_MCD_L1_STRICT_ORDERING (1 << 2)
1402
1403# define R600_MCD_SYSTEM_ACCESS_MODE_MASK (3 << 6)
1404# define R600_MCD_SYSTEM_ACCESS_MODE_PA_ONLY (0 << 6)
1405# define R600_MCD_SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 6)
1406# define R600_MCD_SYSTEM_ACCESS_MODE_IN_SYS (2 << 6)
1407# define R600_MCD_SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 6)
1408
1409# define R600_MCD_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 8)
1410# define R600_MCD_SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE (1 << 8)
1411
1412# define R600_MCD_SEMAPHORE_MODE (1 << 10)
1413# define R600_MCD_WAIT_L2_QUERY (1 << 11)
1414# define R600_MCD_EFFECTIVE_L1_TLB_SIZE(x) ((x) << 12)
1415# define R600_MCD_EFFECTIVE_L1_QUEUE_SIZE(x) ((x) << 15)
1416
1417#define R700_MC_VM_MD_L1_TLB0_CNTL 0x2654
1418#define R700_MC_VM_MD_L1_TLB1_CNTL 0x2658
1419#define R700_MC_VM_MD_L1_TLB2_CNTL 0x265c
1420
1421#define R700_MC_VM_MB_L1_TLB0_CNTL 0x2234
1422#define R700_MC_VM_MB_L1_TLB1_CNTL 0x2238
1423#define R700_MC_VM_MB_L1_TLB2_CNTL 0x223c
1424#define R700_MC_VM_MB_L1_TLB3_CNTL 0x2240
1425
1426# define R700_ENABLE_L1_TLB (1 << 0)
1427# define R700_ENABLE_L1_FRAGMENT_PROCESSING (1 << 1)
1428# define R700_SYSTEM_ACCESS_MODE_IN_SYS (2 << 3)
1429# define R700_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5)
1430# define R700_EFFECTIVE_L1_TLB_SIZE(x) ((x) << 15)
1431# define R700_EFFECTIVE_L1_QUEUE_SIZE(x) ((x) << 18)
1432
1433#define R700_MC_ARB_RAMCFG 0x2760
1434# define R700_NOOFBANK_SHIFT 0
1435# define R700_NOOFBANK_MASK 0x3
1436# define R700_NOOFRANK_SHIFT 2
1437# define R700_NOOFRANK_MASK 0x1
1438# define R700_NOOFROWS_SHIFT 3
1439# define R700_NOOFROWS_MASK 0x7
1440# define R700_NOOFCOLS_SHIFT 6
1441# define R700_NOOFCOLS_MASK 0x3
1442# define R700_CHANSIZE_SHIFT 8
1443# define R700_CHANSIZE_MASK 0x1
1444# define R700_BURSTLENGTH_SHIFT 9
1445# define R700_BURSTLENGTH_MASK 0x1
1446#define R600_RAMCFG 0x2408
1447# define R600_NOOFBANK_SHIFT 0
1448# define R600_NOOFBANK_MASK 0x1
1449# define R600_NOOFRANK_SHIFT 1
1450# define R600_NOOFRANK_MASK 0x1
1451# define R600_NOOFROWS_SHIFT 2
1452# define R600_NOOFROWS_MASK 0x7
1453# define R600_NOOFCOLS_SHIFT 5
1454# define R600_NOOFCOLS_MASK 0x3
1455# define R600_CHANSIZE_SHIFT 7
1456# define R600_CHANSIZE_MASK 0x1
1457# define R600_BURSTLENGTH_SHIFT 8
1458# define R600_BURSTLENGTH_MASK 0x1
1459
1460#define R600_VM_L2_CNTL 0x1400
1461# define R600_VM_L2_CACHE_EN (1 << 0)
1462# define R600_VM_L2_FRAG_PROC (1 << 1)
1463# define R600_VM_ENABLE_PTE_CACHE_LRU_W (1 << 9)
1464# define R600_VM_L2_CNTL_QUEUE_SIZE(x) ((x) << 13)
1465# define R700_VM_L2_CNTL_QUEUE_SIZE(x) ((x) << 14)
1466
1467#define R600_VM_L2_CNTL2 0x1404
1468# define R600_VM_L2_CNTL2_INVALIDATE_ALL_L1_TLBS (1 << 0)
1469# define R600_VM_L2_CNTL2_INVALIDATE_L2_CACHE (1 << 1)
1470#define R600_VM_L2_CNTL3 0x1408
1471# define R600_VM_L2_CNTL3_BANK_SELECT_0(x) ((x) << 0)
1472# define R600_VM_L2_CNTL3_BANK_SELECT_1(x) ((x) << 5)
1473# define R600_VM_L2_CNTL3_CACHE_UPDATE_MODE(x) ((x) << 10)
1474# define R700_VM_L2_CNTL3_BANK_SELECT(x) ((x) << 0)
1475# define R700_VM_L2_CNTL3_CACHE_UPDATE_MODE(x) ((x) << 6)
1476
1477#define R600_VM_L2_STATUS 0x140c
1478
1479#define R600_VM_CONTEXT0_CNTL 0x1410
1480# define R600_VM_ENABLE_CONTEXT (1 << 0)
1481# define R600_VM_PAGE_TABLE_DEPTH_FLAT (0 << 1)
1482
1483#define R600_VM_CONTEXT0_CNTL2 0x1430
1484#define R600_VM_CONTEXT0_REQUEST_RESPONSE 0x1470
1485#define R600_VM_CONTEXT0_INVALIDATION_LOW_ADDR 0x1490
1486#define R600_VM_CONTEXT0_INVALIDATION_HIGH_ADDR 0x14b0
1487#define R600_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x1574
1488#define R600_VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x1594
1489#define R600_VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x15b4
1490
1491#define R700_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153c
1492#define R700_VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155c
1493#define R700_VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157c
1494
1495#define R600_HDP_HOST_PATH_CNTL 0x2c00
1496
1497#define R600_GRBM_CNTL 0x8000
1498# define R600_GRBM_READ_TIMEOUT(x) ((x) << 0)
1499
1500#define R600_GRBM_STATUS 0x8010
1501# define R600_CMDFIFO_AVAIL_MASK 0x1f
1502# define R700_CMDFIFO_AVAIL_MASK 0xf
1503# define R600_GUI_ACTIVE (1 << 31)
1504#define R600_GRBM_STATUS2 0x8014
1505#define R600_GRBM_SOFT_RESET 0x8020
1506# define R600_SOFT_RESET_CP (1 << 0)
1507#define R600_WAIT_UNTIL 0x8040
1508
1509#define R600_CP_SEM_WAIT_TIMER 0x85bc
1510#define R600_CP_ME_CNTL 0x86d8
1511# define R600_CP_ME_HALT (1 << 28)
1512#define R600_CP_QUEUE_THRESHOLDS 0x8760
1513# define R600_ROQ_IB1_START(x) ((x) << 0)
1514# define R600_ROQ_IB2_START(x) ((x) << 8)
1515#define R600_CP_MEQ_THRESHOLDS 0x8764
1516# define R700_STQ_SPLIT(x) ((x) << 0)
1517# define R600_MEQ_END(x) ((x) << 16)
1518# define R600_ROQ_END(x) ((x) << 24)
1519#define R600_CP_PERFMON_CNTL 0x87fc
1520#define R600_CP_RB_BASE 0xc100
1521#define R600_CP_RB_CNTL 0xc104
1522# define R600_RB_BUFSZ(x) ((x) << 0)
1523# define R600_RB_BLKSZ(x) ((x) << 8)
1524# define R600_BUF_SWAP_32BIT (2 << 16)
1525# define R600_RB_NO_UPDATE (1 << 27)
1526# define R600_RB_RPTR_WR_ENA (1 << 31)
1527#define R600_CP_RB_RPTR_WR 0xc108
1528#define R600_CP_RB_RPTR_ADDR 0xc10c
1529#define R600_CP_RB_RPTR_ADDR_HI 0xc110
1530#define R600_CP_RB_WPTR 0xc114
1531#define R600_CP_RB_WPTR_ADDR 0xc118
1532#define R600_CP_RB_WPTR_ADDR_HI 0xc11c
1533#define R600_CP_RB_RPTR 0x8700
1534#define R600_CP_RB_WPTR_DELAY 0x8704
1535#define R600_CP_PFP_UCODE_ADDR 0xc150
1536#define R600_CP_PFP_UCODE_DATA 0xc154
1537#define R600_CP_ME_RAM_RADDR 0xc158
1538#define R600_CP_ME_RAM_WADDR 0xc15c
1539#define R600_CP_ME_RAM_DATA 0xc160
1540#define R600_CP_DEBUG 0xc1fc
1541
1542#define R600_PA_CL_ENHANCE 0x8a14
1543# define R600_CLIP_VTX_REORDER_ENA (1 << 0)
1544# define R600_NUM_CLIP_SEQ(x) ((x) << 1)
1545#define R600_PA_SC_LINE_STIPPLE_STATE 0x8b10
1546#define R600_PA_SC_MULTI_CHIP_CNTL 0x8b20
1547#define R700_PA_SC_FORCE_EOV_MAX_CNTS 0x8b24
1548# define R700_FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0)
1549# define R700_FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16)
1550#define R600_PA_SC_AA_SAMPLE_LOCS_2S 0x8b40
1551#define R600_PA_SC_AA_SAMPLE_LOCS_4S 0x8b44
1552#define R600_PA_SC_AA_SAMPLE_LOCS_8S_WD0 0x8b48
1553#define R600_PA_SC_AA_SAMPLE_LOCS_8S_WD1 0x8b4c
1554# define R600_S0_X(x) ((x) << 0)
1555# define R600_S0_Y(x) ((x) << 4)
1556# define R600_S1_X(x) ((x) << 8)
1557# define R600_S1_Y(x) ((x) << 12)
1558# define R600_S2_X(x) ((x) << 16)
1559# define R600_S2_Y(x) ((x) << 20)
1560# define R600_S3_X(x) ((x) << 24)
1561# define R600_S3_Y(x) ((x) << 28)
1562# define R600_S4_X(x) ((x) << 0)
1563# define R600_S4_Y(x) ((x) << 4)
1564# define R600_S5_X(x) ((x) << 8)
1565# define R600_S5_Y(x) ((x) << 12)
1566# define R600_S6_X(x) ((x) << 16)
1567# define R600_S6_Y(x) ((x) << 20)
1568# define R600_S7_X(x) ((x) << 24)
1569# define R600_S7_Y(x) ((x) << 28)
1570#define R600_PA_SC_FIFO_SIZE 0x8bd0
1571# define R600_SC_PRIM_FIFO_SIZE(x) ((x) << 0)
1572# define R600_SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 8)
1573# define R600_SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 16)
1574#define R700_PA_SC_FIFO_SIZE_R7XX 0x8bcc
1575# define R700_SC_PRIM_FIFO_SIZE(x) ((x) << 0)
1576# define R700_SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12)
1577# define R700_SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20)
1578#define R600_PA_SC_ENHANCE 0x8bf0
1579# define R600_FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0)
1580# define R600_FORCE_EOV_MAX_TILE_CNT(x) ((x) << 12)
1581#define R600_PA_SC_CLIPRECT_RULE 0x2820c
1582#define R700_PA_SC_EDGERULE 0x28230
1583#define R600_PA_SC_LINE_STIPPLE 0x28a0c
1584#define R600_PA_SC_MODE_CNTL 0x28a4c
1585#define R600_PA_SC_AA_CONFIG 0x28c04
1586
1587#define R600_SX_EXPORT_BUFFER_SIZES 0x900c
1588# define R600_COLOR_BUFFER_SIZE(x) ((x) << 0)
1589# define R600_POSITION_BUFFER_SIZE(x) ((x) << 8)
1590# define R600_SMX_BUFFER_SIZE(x) ((x) << 16)
1591#define R600_SX_DEBUG_1 0x9054
1592# define R600_SMX_EVENT_RELEASE (1 << 0)
1593# define R600_ENABLE_NEW_SMX_ADDRESS (1 << 16)
1594#define R700_SX_DEBUG_1 0x9058
1595# define R700_ENABLE_NEW_SMX_ADDRESS (1 << 16)
1596#define R600_SX_MISC 0x28350
1597
1598#define R600_DB_DEBUG 0x9830
1599# define R600_PREZ_MUST_WAIT_FOR_POSTZ_DONE (1 << 31)
1600#define R600_DB_WATERMARKS 0x9838
1601# define R600_DEPTH_FREE(x) ((x) << 0)
1602# define R600_DEPTH_FLUSH(x) ((x) << 5)
1603# define R600_DEPTH_PENDING_FREE(x) ((x) << 15)
1604# define R600_DEPTH_CACHELINE_FREE(x) ((x) << 20)
1605#define R700_DB_DEBUG3 0x98b0
1606# define R700_DB_CLK_OFF_DELAY(x) ((x) << 11)
1607#define RV700_DB_DEBUG4 0x9b8c
1608# define RV700_DISABLE_TILE_COVERED_FOR_PS_ITER (1 << 6)
1609
1610#define R600_VGT_CACHE_INVALIDATION 0x88c4
1611# define R600_CACHE_INVALIDATION(x) ((x) << 0)
1612# define R600_VC_ONLY 0
1613# define R600_TC_ONLY 1
1614# define R600_VC_AND_TC 2
1615# define R700_AUTO_INVLD_EN(x) ((x) << 6)
1616# define R700_NO_AUTO 0
1617# define R700_ES_AUTO 1
1618# define R700_GS_AUTO 2
1619# define R700_ES_AND_GS_AUTO 3
1620#define R600_VGT_GS_PER_ES 0x88c8
1621#define R600_VGT_ES_PER_GS 0x88cc
1622#define R600_VGT_GS_PER_VS 0x88e8
1623#define R600_VGT_GS_VERTEX_REUSE 0x88d4
1624#define R600_VGT_NUM_INSTANCES 0x8974
1625#define R600_VGT_STRMOUT_EN 0x28ab0
1626#define R600_VGT_EVENT_INITIATOR 0x28a90
1627# define R600_CACHE_FLUSH_AND_INV_EVENT (0x16 << 0)
1628#define R600_VGT_VERTEX_REUSE_BLOCK_CNTL 0x28c58
1629# define R600_VTX_REUSE_DEPTH_MASK 0xff
1630#define R600_VGT_OUT_DEALLOC_CNTL 0x28c5c
1631# define R600_DEALLOC_DIST_MASK 0x7f
1632
1633#define R600_CB_COLOR0_BASE 0x28040
1634#define R600_CB_COLOR1_BASE 0x28044
1635#define R600_CB_COLOR2_BASE 0x28048
1636#define R600_CB_COLOR3_BASE 0x2804c
1637#define R600_CB_COLOR4_BASE 0x28050
1638#define R600_CB_COLOR5_BASE 0x28054
1639#define R600_CB_COLOR6_BASE 0x28058
1640#define R600_CB_COLOR7_BASE 0x2805c
1641#define R600_CB_COLOR7_FRAG 0x280fc
1642
1643#define R600_CB_COLOR0_SIZE 0x28060
1644#define R600_CB_COLOR0_VIEW 0x28080
1645#define R600_CB_COLOR0_INFO 0x280a0
1646#define R600_CB_COLOR0_TILE 0x280c0
1647#define R600_CB_COLOR0_FRAG 0x280e0
1648#define R600_CB_COLOR0_MASK 0x28100
1649
1650#define AVIVO_D1MODE_VLINE_START_END 0x6538
1651#define AVIVO_D2MODE_VLINE_START_END 0x6d38
1652#define R600_CP_COHER_BASE 0x85f8
1653#define R600_DB_DEPTH_BASE 0x2800c
1654#define R600_SQ_PGM_START_FS 0x28894
1655#define R600_SQ_PGM_START_ES 0x28880
1656#define R600_SQ_PGM_START_VS 0x28858
1657#define R600_SQ_PGM_RESOURCES_VS 0x28868
1658#define R600_SQ_PGM_CF_OFFSET_VS 0x288d0
1659#define R600_SQ_PGM_START_GS 0x2886c
1660#define R600_SQ_PGM_START_PS 0x28840
1661#define R600_SQ_PGM_RESOURCES_PS 0x28850
1662#define R600_SQ_PGM_EXPORTS_PS 0x28854
1663#define R600_SQ_PGM_CF_OFFSET_PS 0x288cc
1664#define R600_VGT_DMA_BASE 0x287e8
1665#define R600_VGT_DMA_BASE_HI 0x287e4
1666#define R600_VGT_STRMOUT_BASE_OFFSET_0 0x28b10
1667#define R600_VGT_STRMOUT_BASE_OFFSET_1 0x28b14
1668#define R600_VGT_STRMOUT_BASE_OFFSET_2 0x28b18
1669#define R600_VGT_STRMOUT_BASE_OFFSET_3 0x28b1c
1670#define R600_VGT_STRMOUT_BASE_OFFSET_HI_0 0x28b44
1671#define R600_VGT_STRMOUT_BASE_OFFSET_HI_1 0x28b48
1672#define R600_VGT_STRMOUT_BASE_OFFSET_HI_2 0x28b4c
1673#define R600_VGT_STRMOUT_BASE_OFFSET_HI_3 0x28b50
1674#define R600_VGT_STRMOUT_BUFFER_BASE_0 0x28ad8
1675#define R600_VGT_STRMOUT_BUFFER_BASE_1 0x28ae8
1676#define R600_VGT_STRMOUT_BUFFER_BASE_2 0x28af8
1677#define R600_VGT_STRMOUT_BUFFER_BASE_3 0x28b08
1678#define R600_VGT_STRMOUT_BUFFER_OFFSET_0 0x28adc
1679#define R600_VGT_STRMOUT_BUFFER_OFFSET_1 0x28aec
1680#define R600_VGT_STRMOUT_BUFFER_OFFSET_2 0x28afc
1681#define R600_VGT_STRMOUT_BUFFER_OFFSET_3 0x28b0c
1682
1683#define R600_VGT_PRIMITIVE_TYPE 0x8958
1684
1685#define R600_PA_SC_SCREEN_SCISSOR_TL 0x28030
1686#define R600_PA_SC_GENERIC_SCISSOR_TL 0x28240
1687#define R600_PA_SC_WINDOW_SCISSOR_TL 0x28204
1688
1689#define R600_TC_CNTL 0x9608
1690# define R600_TC_L2_SIZE(x) ((x) << 5)
1691# define R600_L2_DISABLE_LATE_HIT (1 << 9)
1692
1693#define R600_ARB_POP 0x2418
1694# define R600_ENABLE_TC128 (1 << 30)
1695#define R600_ARB_GDEC_RD_CNTL 0x246c
1696
1697#define R600_TA_CNTL_AUX 0x9508
1698# define R600_DISABLE_CUBE_WRAP (1 << 0)
1699# define R600_DISABLE_CUBE_ANISO (1 << 1)
1700# define R700_GETLOD_SELECT(x) ((x) << 2)
1701# define R600_SYNC_GRADIENT (1 << 24)
1702# define R600_SYNC_WALKER (1 << 25)
1703# define R600_SYNC_ALIGNER (1 << 26)
1704# define R600_BILINEAR_PRECISION_6_BIT (0 << 31)
1705# define R600_BILINEAR_PRECISION_8_BIT (1 << 31)
1706
1707#define R700_TCP_CNTL 0x9610
1708
1709#define R600_SMX_DC_CTL0 0xa020
1710# define R700_USE_HASH_FUNCTION (1 << 0)
1711# define R700_CACHE_DEPTH(x) ((x) << 1)
1712# define R700_FLUSH_ALL_ON_EVENT (1 << 10)
1713# define R700_STALL_ON_EVENT (1 << 11)
1714#define R700_SMX_EVENT_CTL 0xa02c
1715# define R700_ES_FLUSH_CTL(x) ((x) << 0)
1716# define R700_GS_FLUSH_CTL(x) ((x) << 3)
1717# define R700_ACK_FLUSH_CTL(x) ((x) << 6)
1718# define R700_SYNC_FLUSH_CTL (1 << 8)
1719
1720#define R600_SQ_CONFIG 0x8c00
1721# define R600_VC_ENABLE (1 << 0)
1722# define R600_EXPORT_SRC_C (1 << 1)
1723# define R600_DX9_CONSTS (1 << 2)
1724# define R600_ALU_INST_PREFER_VECTOR (1 << 3)
1725# define R600_DX10_CLAMP (1 << 4)
1726# define R600_CLAUSE_SEQ_PRIO(x) ((x) << 8)
1727# define R600_PS_PRIO(x) ((x) << 24)
1728# define R600_VS_PRIO(x) ((x) << 26)
1729# define R600_GS_PRIO(x) ((x) << 28)
1730# define R600_ES_PRIO(x) ((x) << 30)
1731#define R600_SQ_GPR_RESOURCE_MGMT_1 0x8c04
1732# define R600_NUM_PS_GPRS(x) ((x) << 0)
1733# define R600_NUM_VS_GPRS(x) ((x) << 16)
1734# define R700_DYN_GPR_ENABLE (1 << 27)
1735# define R600_NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28)
1736#define R600_SQ_GPR_RESOURCE_MGMT_2 0x8c08
1737# define R600_NUM_GS_GPRS(x) ((x) << 0)
1738# define R600_NUM_ES_GPRS(x) ((x) << 16)
1739#define R600_SQ_THREAD_RESOURCE_MGMT 0x8c0c
1740# define R600_NUM_PS_THREADS(x) ((x) << 0)
1741# define R600_NUM_VS_THREADS(x) ((x) << 8)
1742# define R600_NUM_GS_THREADS(x) ((x) << 16)
1743# define R600_NUM_ES_THREADS(x) ((x) << 24)
1744#define R600_SQ_STACK_RESOURCE_MGMT_1 0x8c10
1745# define R600_NUM_PS_STACK_ENTRIES(x) ((x) << 0)
1746# define R600_NUM_VS_STACK_ENTRIES(x) ((x) << 16)
1747#define R600_SQ_STACK_RESOURCE_MGMT_2 0x8c14
1748# define R600_NUM_GS_STACK_ENTRIES(x) ((x) << 0)
1749# define R600_NUM_ES_STACK_ENTRIES(x) ((x) << 16)
1750#define R600_SQ_MS_FIFO_SIZES 0x8cf0
1751# define R600_CACHE_FIFO_SIZE(x) ((x) << 0)
1752# define R600_FETCH_FIFO_HIWATER(x) ((x) << 8)
1753# define R600_DONE_FIFO_HIWATER(x) ((x) << 16)
1754# define R600_ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24)
1755#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_0 0x8db0
1756# define R700_SIMDA_RING0(x) ((x) << 0)
1757# define R700_SIMDA_RING1(x) ((x) << 8)
1758# define R700_SIMDB_RING0(x) ((x) << 16)
1759# define R700_SIMDB_RING1(x) ((x) << 24)
1760#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_1 0x8db4
1761#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_2 0x8db8
1762#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_3 0x8dbc
1763#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_4 0x8dc0
1764#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_5 0x8dc4
1765#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_6 0x8dc8
1766#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_7 0x8dcc
1767
1768#define R600_SPI_PS_IN_CONTROL_0 0x286cc
1769# define R600_NUM_INTERP(x) ((x) << 0)
1770# define R600_POSITION_ENA (1 << 8)
1771# define R600_POSITION_CENTROID (1 << 9)
1772# define R600_POSITION_ADDR(x) ((x) << 10)
1773# define R600_PARAM_GEN(x) ((x) << 15)
1774# define R600_PARAM_GEN_ADDR(x) ((x) << 19)
1775# define R600_BARYC_SAMPLE_CNTL(x) ((x) << 26)
1776# define R600_PERSP_GRADIENT_ENA (1 << 28)
1777# define R600_LINEAR_GRADIENT_ENA (1 << 29)
1778# define R600_POSITION_SAMPLE (1 << 30)
1779# define R600_BARYC_AT_SAMPLE_ENA (1 << 31)
1780#define R600_SPI_PS_IN_CONTROL_1 0x286d0
1781# define R600_GEN_INDEX_PIX (1 << 0)
1782# define R600_GEN_INDEX_PIX_ADDR(x) ((x) << 1)
1783# define R600_FRONT_FACE_ENA (1 << 8)
1784# define R600_FRONT_FACE_CHAN(x) ((x) << 9)
1785# define R600_FRONT_FACE_ALL_BITS (1 << 11)
1786# define R600_FRONT_FACE_ADDR(x) ((x) << 12)
1787# define R600_FOG_ADDR(x) ((x) << 17)
1788# define R600_FIXED_PT_POSITION_ENA (1 << 24)
1789# define R600_FIXED_PT_POSITION_ADDR(x) ((x) << 25)
1790# define R700_POSITION_ULC (1 << 30)
1791#define R600_SPI_INPUT_Z 0x286d8
1792
1793#define R600_SPI_CONFIG_CNTL 0x9100
1794# define R600_GPR_WRITE_PRIORITY(x) ((x) << 0)
1795# define R600_DISABLE_INTERP_1 (1 << 5)
1796#define R600_SPI_CONFIG_CNTL_1 0x913c
1797# define R600_VTX_DONE_DELAY(x) ((x) << 0)
1798# define R600_INTERP_ONE_PRIM_PER_ROW (1 << 4)
1799
1800#define R600_GB_TILING_CONFIG 0x98f0
1801# define R600_PIPE_TILING(x) ((x) << 1)
1802# define R600_BANK_TILING(x) ((x) << 4)
1803# define R600_GROUP_SIZE(x) ((x) << 6)
1804# define R600_ROW_TILING(x) ((x) << 8)
1805# define R600_BANK_SWAPS(x) ((x) << 11)
1806# define R600_SAMPLE_SPLIT(x) ((x) << 14)
1807# define R600_BACKEND_MAP(x) ((x) << 16)
1808#define R600_DCP_TILING_CONFIG 0x6ca0
1809#define R600_HDP_TILING_CONFIG 0x2f3c
1810
1811#define R600_CC_RB_BACKEND_DISABLE 0x98f4
1812#define R700_CC_SYS_RB_BACKEND_DISABLE 0x3f88
1813# define R600_BACKEND_DISABLE(x) ((x) << 16)
1814
1815#define R600_CC_GC_SHADER_PIPE_CONFIG 0x8950
1816#define R600_GC_USER_SHADER_PIPE_CONFIG 0x8954
1817# define R600_INACTIVE_QD_PIPES(x) ((x) << 8)
1818# define R600_INACTIVE_QD_PIPES_MASK (0xff << 8)
1819# define R600_INACTIVE_SIMDS(x) ((x) << 16)
1820# define R600_INACTIVE_SIMDS_MASK (0xff << 16)
1821
1822#define R700_CGTS_SYS_TCC_DISABLE 0x3f90
1823#define R700_CGTS_USER_SYS_TCC_DISABLE 0x3f94
1824#define R700_CGTS_TCC_DISABLE 0x9148
1825#define R700_CGTS_USER_TCC_DISABLE 0x914c
1826
1827/* Constants */
1828#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
1829
1830#define RADEON_LAST_FRAME_REG RADEON_SCRATCH_REG0
1831#define RADEON_LAST_DISPATCH_REG RADEON_SCRATCH_REG1
1832#define RADEON_LAST_CLEAR_REG RADEON_SCRATCH_REG2
1833#define RADEON_LAST_SWI_REG RADEON_SCRATCH_REG3
1834#define RADEON_LAST_DISPATCH 1
1835
1836#define R600_LAST_FRAME_REG R600_SCRATCH_REG0
1837#define R600_LAST_DISPATCH_REG R600_SCRATCH_REG1
1838#define R600_LAST_CLEAR_REG R600_SCRATCH_REG2
1839#define R600_LAST_SWI_REG R600_SCRATCH_REG3
1840
1841#define RADEON_MAX_VB_AGE 0x7fffffff
1842#define RADEON_MAX_VB_VERTS (0xffff)
1843
1844#define RADEON_RING_HIGH_MARK 128
1845
1846#define RADEON_PCIGART_TABLE_SIZE (32*1024)
1847
1848#define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) )
1849#define RADEON_WRITE(reg, val) \
1850do { \
1851 if (reg < 0x10000) { \
1852 DRM_WRITE32(dev_priv->mmio, (reg), (val)); \
1853 } else { \
1854 DRM_WRITE32(dev_priv->mmio, RADEON_MM_INDEX, (reg)); \
1855 DRM_WRITE32(dev_priv->mmio, RADEON_MM_DATA, (val)); \
1856 } \
1857} while (0)
1858#define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) )
1859#define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) )
1860
1861#define RADEON_WRITE_PLL(addr, val) \
1862do { \
1863 RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, \
1864 ((addr) & 0x1f) | RADEON_PLL_WR_EN ); \
1865 RADEON_WRITE(RADEON_CLOCK_CNTL_DATA, (val)); \
1866} while (0)
1867
1868#define RADEON_WRITE_PCIE(addr, val) \
1869do { \
1870 RADEON_WRITE8(RADEON_PCIE_INDEX, \
1871 ((addr) & 0xff)); \
1872 RADEON_WRITE(RADEON_PCIE_DATA, (val)); \
1873} while (0)
1874
1875#define R500_WRITE_MCIND(addr, val) \
1876do { \
1877 RADEON_WRITE(R520_MC_IND_INDEX, 0xff0000 | ((addr) & 0xff)); \
1878 RADEON_WRITE(R520_MC_IND_DATA, (val)); \
1879 RADEON_WRITE(R520_MC_IND_INDEX, 0); \
1880} while (0)
1881
1882#define RS480_WRITE_MCIND(addr, val) \
1883do { \
1884 RADEON_WRITE(RS480_NB_MC_INDEX, \
1885 ((addr) & 0xff) | RS480_NB_MC_IND_WR_EN); \
1886 RADEON_WRITE(RS480_NB_MC_DATA, (val)); \
1887 RADEON_WRITE(RS480_NB_MC_INDEX, 0xff); \
1888} while (0)
1889
1890#define RS690_WRITE_MCIND(addr, val) \
1891do { \
1892 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_EN | ((addr) & RS690_MC_INDEX_MASK)); \
1893 RADEON_WRITE(RS690_MC_DATA, val); \
1894 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK); \
1895} while (0)
1896
1897#define RS600_WRITE_MCIND(addr, val) \
1898do { \
1899 RADEON_WRITE(RS600_MC_INDEX, RS600_MC_IND_WR_EN | RS600_MC_IND_CITF_ARB0 | ((addr) & RS600_MC_ADDR_MASK)); \
1900 RADEON_WRITE(RS600_MC_DATA, val); \
1901} while (0)
1902
1903#define IGP_WRITE_MCIND(addr, val) \
1904do { \
1905 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || \
1906 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) \
1907 RS690_WRITE_MCIND(addr, val); \
1908 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) \
1909 RS600_WRITE_MCIND(addr, val); \
1910 else \
1911 RS480_WRITE_MCIND(addr, val); \
1912} while (0)
1913
1914#define CP_PACKET0( reg, n ) \
1915 (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2))
1916#define CP_PACKET0_TABLE( reg, n ) \
1917 (RADEON_CP_PACKET0 | RADEON_ONE_REG_WR | ((n) << 16) | ((reg) >> 2))
1918#define CP_PACKET1( reg0, reg1 ) \
1919 (RADEON_CP_PACKET1 | (((reg1) >> 2) << 15) | ((reg0) >> 2))
1920#define CP_PACKET2() \
1921 (RADEON_CP_PACKET2)
1922#define CP_PACKET3( pkt, n ) \
1923 (RADEON_CP_PACKET3 | (pkt) | ((n) << 16))
1924
1925/* ================================================================
1926 * Engine control helper macros
1927 */
1928
1929#define RADEON_WAIT_UNTIL_2D_IDLE() do { \
1930 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1931 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
1932 RADEON_WAIT_HOST_IDLECLEAN) ); \
1933} while (0)
1934
1935#define RADEON_WAIT_UNTIL_3D_IDLE() do { \
1936 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1937 OUT_RING( (RADEON_WAIT_3D_IDLECLEAN | \
1938 RADEON_WAIT_HOST_IDLECLEAN) ); \
1939} while (0)
1940
1941#define RADEON_WAIT_UNTIL_IDLE() do { \
1942 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1943 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
1944 RADEON_WAIT_3D_IDLECLEAN | \
1945 RADEON_WAIT_HOST_IDLECLEAN) ); \
1946} while (0)
1947
1948#define RADEON_WAIT_UNTIL_PAGE_FLIPPED() do { \
1949 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
1950 OUT_RING( RADEON_WAIT_CRTC_PFLIP ); \
1951} while (0)
1952
1953#define RADEON_FLUSH_CACHE() do { \
1954 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
1955 OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \
1956 OUT_RING(RADEON_RB3D_DC_FLUSH); \
1957 } else { \
1958 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \
1959 OUT_RING(R300_RB3D_DC_FLUSH); \
1960 } \
1961} while (0)
1962
1963#define RADEON_PURGE_CACHE() do { \
1964 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
1965 OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \
1966 OUT_RING(RADEON_RB3D_DC_FLUSH | RADEON_RB3D_DC_FREE); \
1967 } else { \
1968 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \
1969 OUT_RING(R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE); \
1970 } \
1971} while (0)
1972
1973#define RADEON_FLUSH_ZCACHE() do { \
1974 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
1975 OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \
1976 OUT_RING(RADEON_RB3D_ZC_FLUSH); \
1977 } else { \
1978 OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0)); \
1979 OUT_RING(R300_ZC_FLUSH); \
1980 } \
1981} while (0)
1982
1983#define RADEON_PURGE_ZCACHE() do { \
1984 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
1985 OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \
1986 OUT_RING(RADEON_RB3D_ZC_FLUSH | RADEON_RB3D_ZC_FREE); \
1987 } else { \
1988 OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0)); \
1989 OUT_RING(R300_ZC_FLUSH | R300_ZC_FREE); \
1990 } \
1991} while (0)
1992
1993/* ================================================================
1994 * Misc helper macros
1995 */
1996
1997/* Perfbox functionality only.
1998 */
1999#define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \
2000do { \
2001 if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE)) { \
2002 u32 head = GET_RING_HEAD( dev_priv ); \
2003 if (head == dev_priv->ring.tail) \
2004 dev_priv->stats.boxes |= RADEON_BOX_DMA_IDLE; \
2005 } \
2006} while (0)
2007
2008#define VB_AGE_TEST_WITH_RETURN( dev_priv ) \
2009do { \
2010 struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv; \
2011 drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv; \
2012 if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) { \
2013 int __ret; \
2014 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) \
2015 __ret = r600_do_cp_idle(dev_priv); \
2016 else \
2017 __ret = radeon_do_cp_idle(dev_priv); \
2018 if ( __ret ) return __ret; \
2019 sarea_priv->last_dispatch = 0; \
2020 radeon_freelist_reset( dev ); \
2021 } \
2022} while (0)
2023
2024#define RADEON_DISPATCH_AGE( age ) do { \
2025 OUT_RING( CP_PACKET0( RADEON_LAST_DISPATCH_REG, 0 ) ); \
2026 OUT_RING( age ); \
2027} while (0)
2028
2029#define RADEON_FRAME_AGE( age ) do { \
2030 OUT_RING( CP_PACKET0( RADEON_LAST_FRAME_REG, 0 ) ); \
2031 OUT_RING( age ); \
2032} while (0)
2033
2034#define RADEON_CLEAR_AGE( age ) do { \
2035 OUT_RING( CP_PACKET0( RADEON_LAST_CLEAR_REG, 0 ) ); \
2036 OUT_RING( age ); \
2037} while (0)
2038
2039#define R600_DISPATCH_AGE(age) do { \
2040 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); \
2041 OUT_RING((R600_LAST_DISPATCH_REG - R600_SET_CONFIG_REG_OFFSET) >> 2); \
2042 OUT_RING(age); \
2043} while (0)
2044
2045#define R600_FRAME_AGE(age) do { \
2046 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); \
2047 OUT_RING((R600_LAST_FRAME_REG - R600_SET_CONFIG_REG_OFFSET) >> 2); \
2048 OUT_RING(age); \
2049} while (0)
2050
2051#define R600_CLEAR_AGE(age) do { \
2052 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); \
2053 OUT_RING((R600_LAST_CLEAR_REG - R600_SET_CONFIG_REG_OFFSET) >> 2); \
2054 OUT_RING(age); \
2055} while (0)
2056
2057/* ================================================================
2058 * Ring control
2059 */
2060
2061#define RADEON_VERBOSE 0
2062
2063#define RING_LOCALS int write, _nr, _align_nr; unsigned int mask; u32 *ring;
2064
2065#define RADEON_RING_ALIGN 16
2066
2067#define BEGIN_RING( n ) do { \
2068 if ( RADEON_VERBOSE ) { \
2069 DRM_INFO( "BEGIN_RING( %d )\n", (n)); \
2070 } \
2071 _align_nr = RADEON_RING_ALIGN - ((dev_priv->ring.tail + n) & (RADEON_RING_ALIGN-1)); \
2072 _align_nr += n; \
2073 if (dev_priv->ring.space <= (_align_nr * sizeof(u32))) { \
2074 COMMIT_RING(); \
2075 radeon_wait_ring( dev_priv, _align_nr * sizeof(u32)); \
2076 } \
2077 _nr = n; dev_priv->ring.space -= (n) * sizeof(u32); \
2078 ring = dev_priv->ring.start; \
2079 write = dev_priv->ring.tail; \
2080 mask = dev_priv->ring.tail_mask; \
2081} while (0)
2082
2083#define ADVANCE_RING() do { \
2084 if ( RADEON_VERBOSE ) { \
2085 DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \
2086 write, dev_priv->ring.tail ); \
2087 } \
2088 if (((dev_priv->ring.tail + _nr) & mask) != write) { \
2089 DRM_ERROR( \
2090 "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \
2091 ((dev_priv->ring.tail + _nr) & mask), \
2092 write, __LINE__); \
2093 } else \
2094 dev_priv->ring.tail = write; \
2095} while (0)
2096
2097extern void radeon_commit_ring(drm_radeon_private_t *dev_priv);
2098
2099#define COMMIT_RING() do { \
2100 radeon_commit_ring(dev_priv); \
2101 } while(0)
2102
2103#define OUT_RING( x ) do { \
2104 if ( RADEON_VERBOSE ) { \
2105 DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \
2106 (unsigned int)(x), write ); \
2107 } \
2108 ring[write++] = (x); \
2109 write &= mask; \
2110} while (0)
2111
2112#define OUT_RING_REG( reg, val ) do { \
2113 OUT_RING( CP_PACKET0( reg, 0 ) ); \
2114 OUT_RING( val ); \
2115} while (0)
2116
2117#define OUT_RING_TABLE( tab, sz ) do { \
2118 int _size = (sz); \
2119 int *_tab = (int *)(tab); \
2120 \
2121 if (write + _size > mask) { \
2122 int _i = (mask+1) - write; \
2123 _size -= _i; \
2124 while (_i > 0 ) { \
2125 *(int *)(ring + write) = *_tab++; \
2126 write++; \
2127 _i--; \
2128 } \
2129 write = 0; \
2130 _tab += _i; \
2131 } \
2132 while (_size > 0) { \
2133 *(ring + write) = *_tab++; \
2134 write++; \
2135 _size--; \
2136 } \
2137 write &= mask; \
2138} while (0)
2139
2140/**
2141 * Copy given number of dwords from drm buffer to the ring buffer.
2142 */
2143#define OUT_RING_DRM_BUFFER(buf, sz) do { \
2144 int _size = (sz) * 4; \
2145 struct drm_buffer *_buf = (buf); \
2146 int _part_size; \
2147 while (_size > 0) { \
2148 _part_size = _size; \
2149 \
2150 if (write + _part_size/4 > mask) \
2151 _part_size = ((mask + 1) - write)*4; \
2152 \
2153 if (drm_buffer_index(_buf) + _part_size > PAGE_SIZE) \
2154 _part_size = PAGE_SIZE - drm_buffer_index(_buf);\
2155 \
2156 \
2157 \
2158 memcpy(ring + write, &_buf->data[drm_buffer_page(_buf)] \
2159 [drm_buffer_index(_buf)], _part_size); \
2160 \
2161 _size -= _part_size; \
2162 write = (write + _part_size/4) & mask; \
2163 drm_buffer_advance(_buf, _part_size); \
2164 } \
2165} while (0)
2166
2167
2168#endif /* CONFIG_DRM_RADEON_UMS */
2169
2170#endif /* __RADEON_DRV_H__ */ 122#endif /* __RADEON_DRV_H__ */
diff --git a/drivers/gpu/drm/radeon/radeon_irq.c b/drivers/gpu/drm/radeon/radeon_irq.c
deleted file mode 100644
index 688afb62f7c4..000000000000
--- a/drivers/gpu/drm/radeon/radeon_irq.c
+++ /dev/null
@@ -1,402 +0,0 @@
1/* radeon_irq.c -- IRQ handling for radeon -*- linux-c -*- */
2/*
3 * Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
4 *
5 * The Weather Channel (TM) funded Tungsten Graphics to develop the
6 * initial release of the Radeon 8500 driver under the XFree86 license.
7 * This notice must be preserved.
8 *
9 * Permission is hereby granted, free of charge, to any person obtaining a
10 * copy of this software and associated documentation files (the "Software"),
11 * to deal in the Software without restriction, including without limitation
12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
13 * and/or sell copies of the Software, and to permit persons to whom the
14 * Software is furnished to do so, subject to the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the next
17 * paragraph) shall be included in all copies or substantial portions of the
18 * Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
24 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
25 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
26 * DEALINGS IN THE SOFTWARE.
27 *
28 * Authors:
29 * Keith Whitwell <keith@tungstengraphics.com>
30 * Michel D�zer <michel@daenzer.net>
31 *
32 * ------------------------ This file is DEPRECATED! -------------------------
33 */
34
35#include <drm/drmP.h>
36#include <drm/radeon_drm.h>
37#include "radeon_drv.h"
38
39void radeon_irq_set_state(struct drm_device *dev, u32 mask, int state)
40{
41 drm_radeon_private_t *dev_priv = dev->dev_private;
42
43 if (state)
44 dev_priv->irq_enable_reg |= mask;
45 else
46 dev_priv->irq_enable_reg &= ~mask;
47
48 if (dev->irq_enabled)
49 RADEON_WRITE(RADEON_GEN_INT_CNTL, dev_priv->irq_enable_reg);
50}
51
52static void r500_vbl_irq_set_state(struct drm_device *dev, u32 mask, int state)
53{
54 drm_radeon_private_t *dev_priv = dev->dev_private;
55
56 if (state)
57 dev_priv->r500_disp_irq_reg |= mask;
58 else
59 dev_priv->r500_disp_irq_reg &= ~mask;
60
61 if (dev->irq_enabled)
62 RADEON_WRITE(R500_DxMODE_INT_MASK, dev_priv->r500_disp_irq_reg);
63}
64
65int radeon_enable_vblank(struct drm_device *dev, unsigned int pipe)
66{
67 drm_radeon_private_t *dev_priv = dev->dev_private;
68
69 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) {
70 switch (pipe) {
71 case 0:
72 r500_vbl_irq_set_state(dev, R500_D1MODE_INT_MASK, 1);
73 break;
74 case 1:
75 r500_vbl_irq_set_state(dev, R500_D2MODE_INT_MASK, 1);
76 break;
77 default:
78 DRM_ERROR("tried to enable vblank on non-existent crtc %u\n",
79 pipe);
80 return -EINVAL;
81 }
82 } else {
83 switch (pipe) {
84 case 0:
85 radeon_irq_set_state(dev, RADEON_CRTC_VBLANK_MASK, 1);
86 break;
87 case 1:
88 radeon_irq_set_state(dev, RADEON_CRTC2_VBLANK_MASK, 1);
89 break;
90 default:
91 DRM_ERROR("tried to enable vblank on non-existent crtc %u\n",
92 pipe);
93 return -EINVAL;
94 }
95 }
96
97 return 0;
98}
99
100void radeon_disable_vblank(struct drm_device *dev, unsigned int pipe)
101{
102 drm_radeon_private_t *dev_priv = dev->dev_private;
103
104 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) {
105 switch (pipe) {
106 case 0:
107 r500_vbl_irq_set_state(dev, R500_D1MODE_INT_MASK, 0);
108 break;
109 case 1:
110 r500_vbl_irq_set_state(dev, R500_D2MODE_INT_MASK, 0);
111 break;
112 default:
113 DRM_ERROR("tried to enable vblank on non-existent crtc %u\n",
114 pipe);
115 break;
116 }
117 } else {
118 switch (pipe) {
119 case 0:
120 radeon_irq_set_state(dev, RADEON_CRTC_VBLANK_MASK, 0);
121 break;
122 case 1:
123 radeon_irq_set_state(dev, RADEON_CRTC2_VBLANK_MASK, 0);
124 break;
125 default:
126 DRM_ERROR("tried to enable vblank on non-existent crtc %u\n",
127 pipe);
128 break;
129 }
130 }
131}
132
133static u32 radeon_acknowledge_irqs(drm_radeon_private_t *dev_priv, u32 *r500_disp_int)
134{
135 u32 irqs = RADEON_READ(RADEON_GEN_INT_STATUS);
136 u32 irq_mask = RADEON_SW_INT_TEST;
137
138 *r500_disp_int = 0;
139 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) {
140 /* vbl interrupts in a different place */
141
142 if (irqs & R500_DISPLAY_INT_STATUS) {
143 /* if a display interrupt */
144 u32 disp_irq;
145
146 disp_irq = RADEON_READ(R500_DISP_INTERRUPT_STATUS);
147
148 *r500_disp_int = disp_irq;
149 if (disp_irq & R500_D1_VBLANK_INTERRUPT)
150 RADEON_WRITE(R500_D1MODE_VBLANK_STATUS, R500_VBLANK_ACK);
151 if (disp_irq & R500_D2_VBLANK_INTERRUPT)
152 RADEON_WRITE(R500_D2MODE_VBLANK_STATUS, R500_VBLANK_ACK);
153 }
154 irq_mask |= R500_DISPLAY_INT_STATUS;
155 } else
156 irq_mask |= RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT;
157
158 irqs &= irq_mask;
159
160 if (irqs)
161 RADEON_WRITE(RADEON_GEN_INT_STATUS, irqs);
162
163 return irqs;
164}
165
166/* Interrupts - Used for device synchronization and flushing in the
167 * following circumstances:
168 *
169 * - Exclusive FB access with hw idle:
170 * - Wait for GUI Idle (?) interrupt, then do normal flush.
171 *
172 * - Frame throttling, NV_fence:
173 * - Drop marker irq's into command stream ahead of time.
174 * - Wait on irq's with lock *not held*
175 * - Check each for termination condition
176 *
177 * - Internally in cp_getbuffer, etc:
178 * - as above, but wait with lock held???
179 *
180 * NOTE: These functions are misleadingly named -- the irq's aren't
181 * tied to dma at all, this is just a hangover from dri prehistory.
182 */
183
184irqreturn_t radeon_driver_irq_handler(int irq, void *arg)
185{
186 struct drm_device *dev = (struct drm_device *) arg;
187 drm_radeon_private_t *dev_priv =
188 (drm_radeon_private_t *) dev->dev_private;
189 u32 stat;
190 u32 r500_disp_int;
191
192 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
193 return IRQ_NONE;
194
195 /* Only consider the bits we're interested in - others could be used
196 * outside the DRM
197 */
198 stat = radeon_acknowledge_irqs(dev_priv, &r500_disp_int);
199 if (!stat)
200 return IRQ_NONE;
201
202 stat &= dev_priv->irq_enable_reg;
203
204 /* SW interrupt */
205 if (stat & RADEON_SW_INT_TEST)
206 wake_up(&dev_priv->swi_queue);
207
208 /* VBLANK interrupt */
209 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) {
210 if (r500_disp_int & R500_D1_VBLANK_INTERRUPT)
211 drm_handle_vblank(dev, 0);
212 if (r500_disp_int & R500_D2_VBLANK_INTERRUPT)
213 drm_handle_vblank(dev, 1);
214 } else {
215 if (stat & RADEON_CRTC_VBLANK_STAT)
216 drm_handle_vblank(dev, 0);
217 if (stat & RADEON_CRTC2_VBLANK_STAT)
218 drm_handle_vblank(dev, 1);
219 }
220 return IRQ_HANDLED;
221}
222
223static int radeon_emit_irq(struct drm_device * dev)
224{
225 drm_radeon_private_t *dev_priv = dev->dev_private;
226 unsigned int ret;
227 RING_LOCALS;
228
229 atomic_inc(&dev_priv->swi_emitted);
230 ret = atomic_read(&dev_priv->swi_emitted);
231
232 BEGIN_RING(4);
233 OUT_RING_REG(RADEON_LAST_SWI_REG, ret);
234 OUT_RING_REG(RADEON_GEN_INT_STATUS, RADEON_SW_INT_FIRE);
235 ADVANCE_RING();
236 COMMIT_RING();
237
238 return ret;
239}
240
241static int radeon_wait_irq(struct drm_device * dev, int swi_nr)
242{
243 drm_radeon_private_t *dev_priv =
244 (drm_radeon_private_t *) dev->dev_private;
245 int ret = 0;
246
247 if (RADEON_READ(RADEON_LAST_SWI_REG) >= swi_nr)
248 return 0;
249
250 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
251
252 DRM_WAIT_ON(ret, dev_priv->swi_queue, 3 * HZ,
253 RADEON_READ(RADEON_LAST_SWI_REG) >= swi_nr);
254
255 return ret;
256}
257
258u32 radeon_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
259{
260 drm_radeon_private_t *dev_priv = dev->dev_private;
261
262 if (!dev_priv) {
263 DRM_ERROR("called with no initialization\n");
264 return -EINVAL;
265 }
266
267 if (pipe > 1) {
268 DRM_ERROR("Invalid crtc %u\n", pipe);
269 return -EINVAL;
270 }
271
272 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) {
273 if (pipe == 0)
274 return RADEON_READ(R500_D1CRTC_FRAME_COUNT);
275 else
276 return RADEON_READ(R500_D2CRTC_FRAME_COUNT);
277 } else {
278 if (pipe == 0)
279 return RADEON_READ(RADEON_CRTC_CRNT_FRAME);
280 else
281 return RADEON_READ(RADEON_CRTC2_CRNT_FRAME);
282 }
283}
284
285/* Needs the lock as it touches the ring.
286 */
287int radeon_irq_emit(struct drm_device *dev, void *data, struct drm_file *file_priv)
288{
289 drm_radeon_private_t *dev_priv = dev->dev_private;
290 drm_radeon_irq_emit_t *emit = data;
291 int result;
292
293 if (!dev_priv) {
294 DRM_ERROR("called with no initialization\n");
295 return -EINVAL;
296 }
297
298 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
299 return -EINVAL;
300
301 LOCK_TEST_WITH_RETURN(dev, file_priv);
302
303 result = radeon_emit_irq(dev);
304
305 if (copy_to_user(emit->irq_seq, &result, sizeof(int))) {
306 DRM_ERROR("copy_to_user\n");
307 return -EFAULT;
308 }
309
310 return 0;
311}
312
313/* Doesn't need the hardware lock.
314 */
315int radeon_irq_wait(struct drm_device *dev, void *data, struct drm_file *file_priv)
316{
317 drm_radeon_private_t *dev_priv = dev->dev_private;
318 drm_radeon_irq_wait_t *irqwait = data;
319
320 if (!dev_priv) {
321 DRM_ERROR("called with no initialization\n");
322 return -EINVAL;
323 }
324
325 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
326 return -EINVAL;
327
328 return radeon_wait_irq(dev, irqwait->irq_seq);
329}
330
331/* drm_dma.h hooks
332*/
333void radeon_driver_irq_preinstall(struct drm_device * dev)
334{
335 drm_radeon_private_t *dev_priv =
336 (drm_radeon_private_t *) dev->dev_private;
337 u32 dummy;
338
339 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
340 return;
341
342 /* Disable *all* interrupts */
343 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600)
344 RADEON_WRITE(R500_DxMODE_INT_MASK, 0);
345 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
346
347 /* Clear bits if they're already high */
348 radeon_acknowledge_irqs(dev_priv, &dummy);
349}
350
351int radeon_driver_irq_postinstall(struct drm_device *dev)
352{
353 drm_radeon_private_t *dev_priv =
354 (drm_radeon_private_t *) dev->dev_private;
355
356 atomic_set(&dev_priv->swi_emitted, 0);
357 init_waitqueue_head(&dev_priv->swi_queue);
358
359 dev->max_vblank_count = 0x001fffff;
360
361 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
362 return 0;
363
364 radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1);
365
366 return 0;
367}
368
369void radeon_driver_irq_uninstall(struct drm_device * dev)
370{
371 drm_radeon_private_t *dev_priv =
372 (drm_radeon_private_t *) dev->dev_private;
373 if (!dev_priv)
374 return;
375
376 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
377 return;
378
379 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600)
380 RADEON_WRITE(R500_DxMODE_INT_MASK, 0);
381 /* Disable *all* interrupts */
382 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
383}
384
385
386int radeon_vblank_crtc_get(struct drm_device *dev)
387{
388 drm_radeon_private_t *dev_priv = (drm_radeon_private_t *) dev->dev_private;
389
390 return dev_priv->vblank_crtc;
391}
392
393int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value)
394{
395 drm_radeon_private_t *dev_priv = (drm_radeon_private_t *) dev->dev_private;
396 if (value & ~(DRM_RADEON_VBLANK_CRTC1 | DRM_RADEON_VBLANK_CRTC2)) {
397 DRM_ERROR("called with invalid crtc 0x%x\n", (unsigned int)value);
398 return -EINVAL;
399 }
400 dev_priv->vblank_crtc = (unsigned int)value;
401 return 0;
402}
diff --git a/drivers/gpu/drm/radeon/radeon_mem.c b/drivers/gpu/drm/radeon/radeon_mem.c
deleted file mode 100644
index 146d253f1131..000000000000
--- a/drivers/gpu/drm/radeon/radeon_mem.c
+++ /dev/null
@@ -1,302 +0,0 @@
1/* radeon_mem.c -- Simple GART/fb memory manager for radeon -*- linux-c -*- */
2/*
3 * Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
4 *
5 * The Weather Channel (TM) funded Tungsten Graphics to develop the
6 * initial release of the Radeon 8500 driver under the XFree86 license.
7 * This notice must be preserved.
8 *
9 * Permission is hereby granted, free of charge, to any person obtaining a
10 * copy of this software and associated documentation files (the "Software"),
11 * to deal in the Software without restriction, including without limitation
12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
13 * and/or sell copies of the Software, and to permit persons to whom the
14 * Software is furnished to do so, subject to the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the next
17 * paragraph) shall be included in all copies or substantial portions of the
18 * Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
24 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
25 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
26 * DEALINGS IN THE SOFTWARE.
27 *
28 * Authors:
29 * Keith Whitwell <keith@tungstengraphics.com>
30 *
31 * ------------------------ This file is DEPRECATED! -------------------------
32 */
33
34#include <drm/drmP.h>
35#include <drm/radeon_drm.h>
36#include "radeon_drv.h"
37
38/* Very simple allocator for GART memory, working on a static range
39 * already mapped into each client's address space.
40 */
41
42static struct mem_block *split_block(struct mem_block *p, int start, int size,
43 struct drm_file *file_priv)
44{
45 /* Maybe cut off the start of an existing block */
46 if (start > p->start) {
47 struct mem_block *newblock = kmalloc(sizeof(*newblock),
48 GFP_KERNEL);
49 if (!newblock)
50 goto out;
51 newblock->start = start;
52 newblock->size = p->size - (start - p->start);
53 newblock->file_priv = NULL;
54 newblock->next = p->next;
55 newblock->prev = p;
56 p->next->prev = newblock;
57 p->next = newblock;
58 p->size -= newblock->size;
59 p = newblock;
60 }
61
62 /* Maybe cut off the end of an existing block */
63 if (size < p->size) {
64 struct mem_block *newblock = kmalloc(sizeof(*newblock),
65 GFP_KERNEL);
66 if (!newblock)
67 goto out;
68 newblock->start = start + size;
69 newblock->size = p->size - size;
70 newblock->file_priv = NULL;
71 newblock->next = p->next;
72 newblock->prev = p;
73 p->next->prev = newblock;
74 p->next = newblock;
75 p->size = size;
76 }
77
78 out:
79 /* Our block is in the middle */
80 p->file_priv = file_priv;
81 return p;
82}
83
84static struct mem_block *alloc_block(struct mem_block *heap, int size,
85 int align2, struct drm_file *file_priv)
86{
87 struct mem_block *p;
88 int mask = (1 << align2) - 1;
89
90 list_for_each(p, heap) {
91 int start = (p->start + mask) & ~mask;
92 if (p->file_priv == NULL && start + size <= p->start + p->size)
93 return split_block(p, start, size, file_priv);
94 }
95
96 return NULL;
97}
98
99static struct mem_block *find_block(struct mem_block *heap, int start)
100{
101 struct mem_block *p;
102
103 list_for_each(p, heap)
104 if (p->start == start)
105 return p;
106
107 return NULL;
108}
109
110static void free_block(struct mem_block *p)
111{
112 p->file_priv = NULL;
113
114 /* Assumes a single contiguous range. Needs a special file_priv in
115 * 'heap' to stop it being subsumed.
116 */
117 if (p->next->file_priv == NULL) {
118 struct mem_block *q = p->next;
119 p->size += q->size;
120 p->next = q->next;
121 p->next->prev = p;
122 kfree(q);
123 }
124
125 if (p->prev->file_priv == NULL) {
126 struct mem_block *q = p->prev;
127 q->size += p->size;
128 q->next = p->next;
129 q->next->prev = q;
130 kfree(p);
131 }
132}
133
134/* Initialize. How to check for an uninitialized heap?
135 */
136static int init_heap(struct mem_block **heap, int start, int size)
137{
138 struct mem_block *blocks = kmalloc(sizeof(*blocks), GFP_KERNEL);
139
140 if (!blocks)
141 return -ENOMEM;
142
143 *heap = kzalloc(sizeof(**heap), GFP_KERNEL);
144 if (!*heap) {
145 kfree(blocks);
146 return -ENOMEM;
147 }
148
149 blocks->start = start;
150 blocks->size = size;
151 blocks->file_priv = NULL;
152 blocks->next = blocks->prev = *heap;
153
154 (*heap)->file_priv = (struct drm_file *) - 1;
155 (*heap)->next = (*heap)->prev = blocks;
156 return 0;
157}
158
159/* Free all blocks associated with the releasing file.
160 */
161void radeon_mem_release(struct drm_file *file_priv, struct mem_block *heap)
162{
163 struct mem_block *p;
164
165 if (!heap || !heap->next)
166 return;
167
168 list_for_each(p, heap) {
169 if (p->file_priv == file_priv)
170 p->file_priv = NULL;
171 }
172
173 /* Assumes a single contiguous range. Needs a special file_priv in
174 * 'heap' to stop it being subsumed.
175 */
176 list_for_each(p, heap) {
177 while (p->file_priv == NULL && p->next->file_priv == NULL) {
178 struct mem_block *q = p->next;
179 p->size += q->size;
180 p->next = q->next;
181 p->next->prev = p;
182 kfree(q);
183 }
184 }
185}
186
187/* Shutdown.
188 */
189void radeon_mem_takedown(struct mem_block **heap)
190{
191 struct mem_block *p;
192
193 if (!*heap)
194 return;
195
196 for (p = (*heap)->next; p != *heap;) {
197 struct mem_block *q = p;
198 p = p->next;
199 kfree(q);
200 }
201
202 kfree(*heap);
203 *heap = NULL;
204}
205
206/* IOCTL HANDLERS */
207
208static struct mem_block **get_heap(drm_radeon_private_t * dev_priv, int region)
209{
210 switch (region) {
211 case RADEON_MEM_REGION_GART:
212 return &dev_priv->gart_heap;
213 case RADEON_MEM_REGION_FB:
214 return &dev_priv->fb_heap;
215 default:
216 return NULL;
217 }
218}
219
220int radeon_mem_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv)
221{
222 drm_radeon_private_t *dev_priv = dev->dev_private;
223 drm_radeon_mem_alloc_t *alloc = data;
224 struct mem_block *block, **heap;
225
226 if (!dev_priv) {
227 DRM_ERROR("called with no initialization\n");
228 return -EINVAL;
229 }
230
231 heap = get_heap(dev_priv, alloc->region);
232 if (!heap || !*heap)
233 return -EFAULT;
234
235 /* Make things easier on ourselves: all allocations at least
236 * 4k aligned.
237 */
238 if (alloc->alignment < 12)
239 alloc->alignment = 12;
240
241 block = alloc_block(*heap, alloc->size, alloc->alignment, file_priv);
242
243 if (!block)
244 return -ENOMEM;
245
246 if (copy_to_user(alloc->region_offset, &block->start,
247 sizeof(int))) {
248 DRM_ERROR("copy_to_user\n");
249 return -EFAULT;
250 }
251
252 return 0;
253}
254
255int radeon_mem_free(struct drm_device *dev, void *data, struct drm_file *file_priv)
256{
257 drm_radeon_private_t *dev_priv = dev->dev_private;
258 drm_radeon_mem_free_t *memfree = data;
259 struct mem_block *block, **heap;
260
261 if (!dev_priv) {
262 DRM_ERROR("called with no initialization\n");
263 return -EINVAL;
264 }
265
266 heap = get_heap(dev_priv, memfree->region);
267 if (!heap || !*heap)
268 return -EFAULT;
269
270 block = find_block(*heap, memfree->region_offset);
271 if (!block)
272 return -EFAULT;
273
274 if (block->file_priv != file_priv)
275 return -EPERM;
276
277 free_block(block);
278 return 0;
279}
280
281int radeon_mem_init_heap(struct drm_device *dev, void *data, struct drm_file *file_priv)
282{
283 drm_radeon_private_t *dev_priv = dev->dev_private;
284 drm_radeon_mem_init_heap_t *initheap = data;
285 struct mem_block **heap;
286
287 if (!dev_priv) {
288 DRM_ERROR("called with no initialization\n");
289 return -EINVAL;
290 }
291
292 heap = get_heap(dev_priv, initheap->region);
293 if (!heap)
294 return -EFAULT;
295
296 if (*heap) {
297 DRM_ERROR("heap already initialized?");
298 return -EFAULT;
299 }
300
301 return init_heap(heap, initheap->start, initheap->size);
302}
diff --git a/drivers/gpu/drm/radeon/radeon_state.c b/drivers/gpu/drm/radeon/radeon_state.c
deleted file mode 100644
index 15aee723db77..000000000000
--- a/drivers/gpu/drm/radeon/radeon_state.c
+++ /dev/null
@@ -1,3261 +0,0 @@
1/* radeon_state.c -- State support for Radeon -*- linux-c -*- */
2/*
3 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Gareth Hughes <gareth@valinux.com>
27 * Kevin E. Martin <martin@valinux.com>
28 *
29 * ------------------------ This file is DEPRECATED! -------------------------
30 */
31
32#include <drm/drmP.h>
33#include <drm/radeon_drm.h>
34#include "radeon_drv.h"
35#include "drm_buffer.h"
36
37/* ================================================================
38 * Helper functions for client state checking and fixup
39 */
40
41static __inline__ int radeon_check_and_fixup_offset(drm_radeon_private_t *
42 dev_priv,
43 struct drm_file * file_priv,
44 u32 *offset)
45{
46 u64 off = *offset;
47 u32 fb_end = dev_priv->fb_location + dev_priv->fb_size - 1;
48 struct drm_radeon_driver_file_fields *radeon_priv;
49
50 /* Hrm ... the story of the offset ... So this function converts
51 * the various ideas of what userland clients might have for an
52 * offset in the card address space into an offset into the card
53 * address space :) So with a sane client, it should just keep
54 * the value intact and just do some boundary checking. However,
55 * not all clients are sane. Some older clients pass us 0 based
56 * offsets relative to the start of the framebuffer and some may
57 * assume the AGP aperture it appended to the framebuffer, so we
58 * try to detect those cases and fix them up.
59 *
60 * Note: It might be a good idea here to make sure the offset lands
61 * in some "allowed" area to protect things like the PCIE GART...
62 */
63
64 /* First, the best case, the offset already lands in either the
65 * framebuffer or the GART mapped space
66 */
67 if (radeon_check_offset(dev_priv, off))
68 return 0;
69
70 /* Ok, that didn't happen... now check if we have a zero based
71 * offset that fits in the framebuffer + gart space, apply the
72 * magic offset we get from SETPARAM or calculated from fb_location
73 */
74 if (off < (dev_priv->fb_size + dev_priv->gart_size)) {
75 radeon_priv = file_priv->driver_priv;
76 off += radeon_priv->radeon_fb_delta;
77 }
78
79 /* Finally, assume we aimed at a GART offset if beyond the fb */
80 if (off > fb_end)
81 off = off - fb_end - 1 + dev_priv->gart_vm_start;
82
83 /* Now recheck and fail if out of bounds */
84 if (radeon_check_offset(dev_priv, off)) {
85 DRM_DEBUG("offset fixed up to 0x%x\n", (unsigned int)off);
86 *offset = off;
87 return 0;
88 }
89 return -EINVAL;
90}
91
92static __inline__ int radeon_check_and_fixup_packets(drm_radeon_private_t *
93 dev_priv,
94 struct drm_file *file_priv,
95 int id, struct drm_buffer *buf)
96{
97 u32 *data;
98 switch (id) {
99
100 case RADEON_EMIT_PP_MISC:
101 data = drm_buffer_pointer_to_dword(buf,
102 (RADEON_RB3D_DEPTHOFFSET - RADEON_PP_MISC) / 4);
103
104 if (radeon_check_and_fixup_offset(dev_priv, file_priv, data)) {
105 DRM_ERROR("Invalid depth buffer offset\n");
106 return -EINVAL;
107 }
108 dev_priv->have_z_offset = 1;
109 break;
110
111 case RADEON_EMIT_PP_CNTL:
112 data = drm_buffer_pointer_to_dword(buf,
113 (RADEON_RB3D_COLOROFFSET - RADEON_PP_CNTL) / 4);
114
115 if (radeon_check_and_fixup_offset(dev_priv, file_priv, data)) {
116 DRM_ERROR("Invalid colour buffer offset\n");
117 return -EINVAL;
118 }
119 break;
120
121 case R200_EMIT_PP_TXOFFSET_0:
122 case R200_EMIT_PP_TXOFFSET_1:
123 case R200_EMIT_PP_TXOFFSET_2:
124 case R200_EMIT_PP_TXOFFSET_3:
125 case R200_EMIT_PP_TXOFFSET_4:
126 case R200_EMIT_PP_TXOFFSET_5:
127 data = drm_buffer_pointer_to_dword(buf, 0);
128 if (radeon_check_and_fixup_offset(dev_priv, file_priv, data)) {
129 DRM_ERROR("Invalid R200 texture offset\n");
130 return -EINVAL;
131 }
132 break;
133
134 case RADEON_EMIT_PP_TXFILTER_0:
135 case RADEON_EMIT_PP_TXFILTER_1:
136 case RADEON_EMIT_PP_TXFILTER_2:
137 data = drm_buffer_pointer_to_dword(buf,
138 (RADEON_PP_TXOFFSET_0 - RADEON_PP_TXFILTER_0) / 4);
139 if (radeon_check_and_fixup_offset(dev_priv, file_priv, data)) {
140 DRM_ERROR("Invalid R100 texture offset\n");
141 return -EINVAL;
142 }
143 break;
144
145 case R200_EMIT_PP_CUBIC_OFFSETS_0:
146 case R200_EMIT_PP_CUBIC_OFFSETS_1:
147 case R200_EMIT_PP_CUBIC_OFFSETS_2:
148 case R200_EMIT_PP_CUBIC_OFFSETS_3:
149 case R200_EMIT_PP_CUBIC_OFFSETS_4:
150 case R200_EMIT_PP_CUBIC_OFFSETS_5:{
151 int i;
152 for (i = 0; i < 5; i++) {
153 data = drm_buffer_pointer_to_dword(buf, i);
154 if (radeon_check_and_fixup_offset(dev_priv,
155 file_priv,
156 data)) {
157 DRM_ERROR
158 ("Invalid R200 cubic texture offset\n");
159 return -EINVAL;
160 }
161 }
162 break;
163 }
164
165 case RADEON_EMIT_PP_CUBIC_OFFSETS_T0:
166 case RADEON_EMIT_PP_CUBIC_OFFSETS_T1:
167 case RADEON_EMIT_PP_CUBIC_OFFSETS_T2:{
168 int i;
169 for (i = 0; i < 5; i++) {
170 data = drm_buffer_pointer_to_dword(buf, i);
171 if (radeon_check_and_fixup_offset(dev_priv,
172 file_priv,
173 data)) {
174 DRM_ERROR
175 ("Invalid R100 cubic texture offset\n");
176 return -EINVAL;
177 }
178 }
179 }
180 break;
181
182 case R200_EMIT_VAP_CTL:{
183 RING_LOCALS;
184 BEGIN_RING(2);
185 OUT_RING_REG(RADEON_SE_TCL_STATE_FLUSH, 0);
186 ADVANCE_RING();
187 }
188 break;
189
190 case RADEON_EMIT_RB3D_COLORPITCH:
191 case RADEON_EMIT_RE_LINE_PATTERN:
192 case RADEON_EMIT_SE_LINE_WIDTH:
193 case RADEON_EMIT_PP_LUM_MATRIX:
194 case RADEON_EMIT_PP_ROT_MATRIX_0:
195 case RADEON_EMIT_RB3D_STENCILREFMASK:
196 case RADEON_EMIT_SE_VPORT_XSCALE:
197 case RADEON_EMIT_SE_CNTL:
198 case RADEON_EMIT_SE_CNTL_STATUS:
199 case RADEON_EMIT_RE_MISC:
200 case RADEON_EMIT_PP_BORDER_COLOR_0:
201 case RADEON_EMIT_PP_BORDER_COLOR_1:
202 case RADEON_EMIT_PP_BORDER_COLOR_2:
203 case RADEON_EMIT_SE_ZBIAS_FACTOR:
204 case RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT:
205 case RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED:
206 case R200_EMIT_PP_TXCBLEND_0:
207 case R200_EMIT_PP_TXCBLEND_1:
208 case R200_EMIT_PP_TXCBLEND_2:
209 case R200_EMIT_PP_TXCBLEND_3:
210 case R200_EMIT_PP_TXCBLEND_4:
211 case R200_EMIT_PP_TXCBLEND_5:
212 case R200_EMIT_PP_TXCBLEND_6:
213 case R200_EMIT_PP_TXCBLEND_7:
214 case R200_EMIT_TCL_LIGHT_MODEL_CTL_0:
215 case R200_EMIT_TFACTOR_0:
216 case R200_EMIT_VTX_FMT_0:
217 case R200_EMIT_MATRIX_SELECT_0:
218 case R200_EMIT_TEX_PROC_CTL_2:
219 case R200_EMIT_TCL_UCP_VERT_BLEND_CTL:
220 case R200_EMIT_PP_TXFILTER_0:
221 case R200_EMIT_PP_TXFILTER_1:
222 case R200_EMIT_PP_TXFILTER_2:
223 case R200_EMIT_PP_TXFILTER_3:
224 case R200_EMIT_PP_TXFILTER_4:
225 case R200_EMIT_PP_TXFILTER_5:
226 case R200_EMIT_VTE_CNTL:
227 case R200_EMIT_OUTPUT_VTX_COMP_SEL:
228 case R200_EMIT_PP_TAM_DEBUG3:
229 case R200_EMIT_PP_CNTL_X:
230 case R200_EMIT_RB3D_DEPTHXY_OFFSET:
231 case R200_EMIT_RE_AUX_SCISSOR_CNTL:
232 case R200_EMIT_RE_SCISSOR_TL_0:
233 case R200_EMIT_RE_SCISSOR_TL_1:
234 case R200_EMIT_RE_SCISSOR_TL_2:
235 case R200_EMIT_SE_VAP_CNTL_STATUS:
236 case R200_EMIT_SE_VTX_STATE_CNTL:
237 case R200_EMIT_RE_POINTSIZE:
238 case R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0:
239 case R200_EMIT_PP_CUBIC_FACES_0:
240 case R200_EMIT_PP_CUBIC_FACES_1:
241 case R200_EMIT_PP_CUBIC_FACES_2:
242 case R200_EMIT_PP_CUBIC_FACES_3:
243 case R200_EMIT_PP_CUBIC_FACES_4:
244 case R200_EMIT_PP_CUBIC_FACES_5:
245 case RADEON_EMIT_PP_TEX_SIZE_0:
246 case RADEON_EMIT_PP_TEX_SIZE_1:
247 case RADEON_EMIT_PP_TEX_SIZE_2:
248 case R200_EMIT_RB3D_BLENDCOLOR:
249 case R200_EMIT_TCL_POINT_SPRITE_CNTL:
250 case RADEON_EMIT_PP_CUBIC_FACES_0:
251 case RADEON_EMIT_PP_CUBIC_FACES_1:
252 case RADEON_EMIT_PP_CUBIC_FACES_2:
253 case R200_EMIT_PP_TRI_PERF_CNTL:
254 case R200_EMIT_PP_AFS_0:
255 case R200_EMIT_PP_AFS_1:
256 case R200_EMIT_ATF_TFACTOR:
257 case R200_EMIT_PP_TXCTLALL_0:
258 case R200_EMIT_PP_TXCTLALL_1:
259 case R200_EMIT_PP_TXCTLALL_2:
260 case R200_EMIT_PP_TXCTLALL_3:
261 case R200_EMIT_PP_TXCTLALL_4:
262 case R200_EMIT_PP_TXCTLALL_5:
263 case R200_EMIT_VAP_PVS_CNTL:
264 /* These packets don't contain memory offsets */
265 break;
266
267 default:
268 DRM_ERROR("Unknown state packet ID %d\n", id);
269 return -EINVAL;
270 }
271
272 return 0;
273}
274
275static int radeon_check_and_fixup_packet3(drm_radeon_private_t *
276 dev_priv,
277 struct drm_file *file_priv,
278 drm_radeon_kcmd_buffer_t *
279 cmdbuf,
280 unsigned int *cmdsz)
281{
282 u32 *cmd = drm_buffer_pointer_to_dword(cmdbuf->buffer, 0);
283 u32 offset, narrays;
284 int count, i, k;
285
286 count = ((*cmd & RADEON_CP_PACKET_COUNT_MASK) >> 16);
287 *cmdsz = 2 + count;
288
289 if ((*cmd & 0xc0000000) != RADEON_CP_PACKET3) {
290 DRM_ERROR("Not a type 3 packet\n");
291 return -EINVAL;
292 }
293
294 if (4 * *cmdsz > drm_buffer_unprocessed(cmdbuf->buffer)) {
295 DRM_ERROR("Packet size larger than size of data provided\n");
296 return -EINVAL;
297 }
298
299 switch (*cmd & 0xff00) {
300 /* XXX Are there old drivers needing other packets? */
301
302 case RADEON_3D_DRAW_IMMD:
303 case RADEON_3D_DRAW_VBUF:
304 case RADEON_3D_DRAW_INDX:
305 case RADEON_WAIT_FOR_IDLE:
306 case RADEON_CP_NOP:
307 case RADEON_3D_CLEAR_ZMASK:
308/* case RADEON_CP_NEXT_CHAR:
309 case RADEON_CP_PLY_NEXTSCAN:
310 case RADEON_CP_SET_SCISSORS: */ /* probably safe but will never need them? */
311 /* these packets are safe */
312 break;
313
314 case RADEON_CP_3D_DRAW_IMMD_2:
315 case RADEON_CP_3D_DRAW_VBUF_2:
316 case RADEON_CP_3D_DRAW_INDX_2:
317 case RADEON_3D_CLEAR_HIZ:
318 /* safe but r200 only */
319 if (dev_priv->microcode_version != UCODE_R200) {
320 DRM_ERROR("Invalid 3d packet for r100-class chip\n");
321 return -EINVAL;
322 }
323 break;
324
325 case RADEON_3D_LOAD_VBPNTR:
326
327 if (count > 18) { /* 12 arrays max */
328 DRM_ERROR("Too large payload in 3D_LOAD_VBPNTR (count=%d)\n",
329 count);
330 return -EINVAL;
331 }
332
333 /* carefully check packet contents */
334 cmd = drm_buffer_pointer_to_dword(cmdbuf->buffer, 1);
335
336 narrays = *cmd & ~0xc000;
337 k = 0;
338 i = 2;
339 while ((k < narrays) && (i < (count + 2))) {
340 i++; /* skip attribute field */
341 cmd = drm_buffer_pointer_to_dword(cmdbuf->buffer, i);
342 if (radeon_check_and_fixup_offset(dev_priv, file_priv,
343 cmd)) {
344 DRM_ERROR
345 ("Invalid offset (k=%d i=%d) in 3D_LOAD_VBPNTR packet.\n",
346 k, i);
347 return -EINVAL;
348 }
349 k++;
350 i++;
351 if (k == narrays)
352 break;
353 /* have one more to process, they come in pairs */
354 cmd = drm_buffer_pointer_to_dword(cmdbuf->buffer, i);
355
356 if (radeon_check_and_fixup_offset(dev_priv,
357 file_priv, cmd))
358 {
359 DRM_ERROR
360 ("Invalid offset (k=%d i=%d) in 3D_LOAD_VBPNTR packet.\n",
361 k, i);
362 return -EINVAL;
363 }
364 k++;
365 i++;
366 }
367 /* do the counts match what we expect ? */
368 if ((k != narrays) || (i != (count + 2))) {
369 DRM_ERROR
370 ("Malformed 3D_LOAD_VBPNTR packet (k=%d i=%d narrays=%d count+1=%d).\n",
371 k, i, narrays, count + 1);
372 return -EINVAL;
373 }
374 break;
375
376 case RADEON_3D_RNDR_GEN_INDX_PRIM:
377 if (dev_priv->microcode_version != UCODE_R100) {
378 DRM_ERROR("Invalid 3d packet for r200-class chip\n");
379 return -EINVAL;
380 }
381
382 cmd = drm_buffer_pointer_to_dword(cmdbuf->buffer, 1);
383 if (radeon_check_and_fixup_offset(dev_priv, file_priv, cmd)) {
384 DRM_ERROR("Invalid rndr_gen_indx offset\n");
385 return -EINVAL;
386 }
387 break;
388
389 case RADEON_CP_INDX_BUFFER:
390 if (dev_priv->microcode_version != UCODE_R200) {
391 DRM_ERROR("Invalid 3d packet for r100-class chip\n");
392 return -EINVAL;
393 }
394
395 cmd = drm_buffer_pointer_to_dword(cmdbuf->buffer, 1);
396 if ((*cmd & 0x8000ffff) != 0x80000810) {
397 DRM_ERROR("Invalid indx_buffer reg address %08X\n", *cmd);
398 return -EINVAL;
399 }
400 cmd = drm_buffer_pointer_to_dword(cmdbuf->buffer, 2);
401 if (radeon_check_and_fixup_offset(dev_priv, file_priv, cmd)) {
402 DRM_ERROR("Invalid indx_buffer offset is %08X\n", *cmd);
403 return -EINVAL;
404 }
405 break;
406
407 case RADEON_CNTL_HOSTDATA_BLT:
408 case RADEON_CNTL_PAINT_MULTI:
409 case RADEON_CNTL_BITBLT_MULTI:
410 /* MSB of opcode: next DWORD GUI_CNTL */
411 cmd = drm_buffer_pointer_to_dword(cmdbuf->buffer, 1);
412 if (*cmd & (RADEON_GMC_SRC_PITCH_OFFSET_CNTL
413 | RADEON_GMC_DST_PITCH_OFFSET_CNTL)) {
414 u32 *cmd2 = drm_buffer_pointer_to_dword(cmdbuf->buffer, 2);
415 offset = *cmd2 << 10;
416 if (radeon_check_and_fixup_offset
417 (dev_priv, file_priv, &offset)) {
418 DRM_ERROR("Invalid first packet offset\n");
419 return -EINVAL;
420 }
421 *cmd2 = (*cmd2 & 0xffc00000) | offset >> 10;
422 }
423
424 if ((*cmd & RADEON_GMC_SRC_PITCH_OFFSET_CNTL) &&
425 (*cmd & RADEON_GMC_DST_PITCH_OFFSET_CNTL)) {
426 u32 *cmd3 = drm_buffer_pointer_to_dword(cmdbuf->buffer, 3);
427 offset = *cmd3 << 10;
428 if (radeon_check_and_fixup_offset
429 (dev_priv, file_priv, &offset)) {
430 DRM_ERROR("Invalid second packet offset\n");
431 return -EINVAL;
432 }
433 *cmd3 = (*cmd3 & 0xffc00000) | offset >> 10;
434 }
435 break;
436
437 default:
438 DRM_ERROR("Invalid packet type %x\n", *cmd & 0xff00);
439 return -EINVAL;
440 }
441
442 return 0;
443}
444
445/* ================================================================
446 * CP hardware state programming functions
447 */
448
449static void radeon_emit_clip_rect(drm_radeon_private_t * dev_priv,
450 struct drm_clip_rect * box)
451{
452 RING_LOCALS;
453
454 DRM_DEBUG(" box: x1=%d y1=%d x2=%d y2=%d\n",
455 box->x1, box->y1, box->x2, box->y2);
456
457 BEGIN_RING(4);
458 OUT_RING(CP_PACKET0(RADEON_RE_TOP_LEFT, 0));
459 OUT_RING((box->y1 << 16) | box->x1);
460 OUT_RING(CP_PACKET0(RADEON_RE_WIDTH_HEIGHT, 0));
461 OUT_RING(((box->y2 - 1) << 16) | (box->x2 - 1));
462 ADVANCE_RING();
463}
464
465/* Emit 1.1 state
466 */
467static int radeon_emit_state(drm_radeon_private_t * dev_priv,
468 struct drm_file *file_priv,
469 drm_radeon_context_regs_t * ctx,
470 drm_radeon_texture_regs_t * tex,
471 unsigned int dirty)
472{
473 RING_LOCALS;
474 DRM_DEBUG("dirty=0x%08x\n", dirty);
475
476 if (dirty & RADEON_UPLOAD_CONTEXT) {
477 if (radeon_check_and_fixup_offset(dev_priv, file_priv,
478 &ctx->rb3d_depthoffset)) {
479 DRM_ERROR("Invalid depth buffer offset\n");
480 return -EINVAL;
481 }
482
483 if (radeon_check_and_fixup_offset(dev_priv, file_priv,
484 &ctx->rb3d_coloroffset)) {
485 DRM_ERROR("Invalid depth buffer offset\n");
486 return -EINVAL;
487 }
488
489 BEGIN_RING(14);
490 OUT_RING(CP_PACKET0(RADEON_PP_MISC, 6));
491 OUT_RING(ctx->pp_misc);
492 OUT_RING(ctx->pp_fog_color);
493 OUT_RING(ctx->re_solid_color);
494 OUT_RING(ctx->rb3d_blendcntl);
495 OUT_RING(ctx->rb3d_depthoffset);
496 OUT_RING(ctx->rb3d_depthpitch);
497 OUT_RING(ctx->rb3d_zstencilcntl);
498 OUT_RING(CP_PACKET0(RADEON_PP_CNTL, 2));
499 OUT_RING(ctx->pp_cntl);
500 OUT_RING(ctx->rb3d_cntl);
501 OUT_RING(ctx->rb3d_coloroffset);
502 OUT_RING(CP_PACKET0(RADEON_RB3D_COLORPITCH, 0));
503 OUT_RING(ctx->rb3d_colorpitch);
504 ADVANCE_RING();
505 }
506
507 if (dirty & RADEON_UPLOAD_VERTFMT) {
508 BEGIN_RING(2);
509 OUT_RING(CP_PACKET0(RADEON_SE_COORD_FMT, 0));
510 OUT_RING(ctx->se_coord_fmt);
511 ADVANCE_RING();
512 }
513
514 if (dirty & RADEON_UPLOAD_LINE) {
515 BEGIN_RING(5);
516 OUT_RING(CP_PACKET0(RADEON_RE_LINE_PATTERN, 1));
517 OUT_RING(ctx->re_line_pattern);
518 OUT_RING(ctx->re_line_state);
519 OUT_RING(CP_PACKET0(RADEON_SE_LINE_WIDTH, 0));
520 OUT_RING(ctx->se_line_width);
521 ADVANCE_RING();
522 }
523
524 if (dirty & RADEON_UPLOAD_BUMPMAP) {
525 BEGIN_RING(5);
526 OUT_RING(CP_PACKET0(RADEON_PP_LUM_MATRIX, 0));
527 OUT_RING(ctx->pp_lum_matrix);
528 OUT_RING(CP_PACKET0(RADEON_PP_ROT_MATRIX_0, 1));
529 OUT_RING(ctx->pp_rot_matrix_0);
530 OUT_RING(ctx->pp_rot_matrix_1);
531 ADVANCE_RING();
532 }
533
534 if (dirty & RADEON_UPLOAD_MASKS) {
535 BEGIN_RING(4);
536 OUT_RING(CP_PACKET0(RADEON_RB3D_STENCILREFMASK, 2));
537 OUT_RING(ctx->rb3d_stencilrefmask);
538 OUT_RING(ctx->rb3d_ropcntl);
539 OUT_RING(ctx->rb3d_planemask);
540 ADVANCE_RING();
541 }
542
543 if (dirty & RADEON_UPLOAD_VIEWPORT) {
544 BEGIN_RING(7);
545 OUT_RING(CP_PACKET0(RADEON_SE_VPORT_XSCALE, 5));
546 OUT_RING(ctx->se_vport_xscale);
547 OUT_RING(ctx->se_vport_xoffset);
548 OUT_RING(ctx->se_vport_yscale);
549 OUT_RING(ctx->se_vport_yoffset);
550 OUT_RING(ctx->se_vport_zscale);
551 OUT_RING(ctx->se_vport_zoffset);
552 ADVANCE_RING();
553 }
554
555 if (dirty & RADEON_UPLOAD_SETUP) {
556 BEGIN_RING(4);
557 OUT_RING(CP_PACKET0(RADEON_SE_CNTL, 0));
558 OUT_RING(ctx->se_cntl);
559 OUT_RING(CP_PACKET0(RADEON_SE_CNTL_STATUS, 0));
560 OUT_RING(ctx->se_cntl_status);
561 ADVANCE_RING();
562 }
563
564 if (dirty & RADEON_UPLOAD_MISC) {
565 BEGIN_RING(2);
566 OUT_RING(CP_PACKET0(RADEON_RE_MISC, 0));
567 OUT_RING(ctx->re_misc);
568 ADVANCE_RING();
569 }
570
571 if (dirty & RADEON_UPLOAD_TEX0) {
572 if (radeon_check_and_fixup_offset(dev_priv, file_priv,
573 &tex[0].pp_txoffset)) {
574 DRM_ERROR("Invalid texture offset for unit 0\n");
575 return -EINVAL;
576 }
577
578 BEGIN_RING(9);
579 OUT_RING(CP_PACKET0(RADEON_PP_TXFILTER_0, 5));
580 OUT_RING(tex[0].pp_txfilter);
581 OUT_RING(tex[0].pp_txformat);
582 OUT_RING(tex[0].pp_txoffset);
583 OUT_RING(tex[0].pp_txcblend);
584 OUT_RING(tex[0].pp_txablend);
585 OUT_RING(tex[0].pp_tfactor);
586 OUT_RING(CP_PACKET0(RADEON_PP_BORDER_COLOR_0, 0));
587 OUT_RING(tex[0].pp_border_color);
588 ADVANCE_RING();
589 }
590
591 if (dirty & RADEON_UPLOAD_TEX1) {
592 if (radeon_check_and_fixup_offset(dev_priv, file_priv,
593 &tex[1].pp_txoffset)) {
594 DRM_ERROR("Invalid texture offset for unit 1\n");
595 return -EINVAL;
596 }
597
598 BEGIN_RING(9);
599 OUT_RING(CP_PACKET0(RADEON_PP_TXFILTER_1, 5));
600 OUT_RING(tex[1].pp_txfilter);
601 OUT_RING(tex[1].pp_txformat);
602 OUT_RING(tex[1].pp_txoffset);
603 OUT_RING(tex[1].pp_txcblend);
604 OUT_RING(tex[1].pp_txablend);
605 OUT_RING(tex[1].pp_tfactor);
606 OUT_RING(CP_PACKET0(RADEON_PP_BORDER_COLOR_1, 0));
607 OUT_RING(tex[1].pp_border_color);
608 ADVANCE_RING();
609 }
610
611 if (dirty & RADEON_UPLOAD_TEX2) {
612 if (radeon_check_and_fixup_offset(dev_priv, file_priv,
613 &tex[2].pp_txoffset)) {
614 DRM_ERROR("Invalid texture offset for unit 2\n");
615 return -EINVAL;
616 }
617
618 BEGIN_RING(9);
619 OUT_RING(CP_PACKET0(RADEON_PP_TXFILTER_2, 5));
620 OUT_RING(tex[2].pp_txfilter);
621 OUT_RING(tex[2].pp_txformat);
622 OUT_RING(tex[2].pp_txoffset);
623 OUT_RING(tex[2].pp_txcblend);
624 OUT_RING(tex[2].pp_txablend);
625 OUT_RING(tex[2].pp_tfactor);
626 OUT_RING(CP_PACKET0(RADEON_PP_BORDER_COLOR_2, 0));
627 OUT_RING(tex[2].pp_border_color);
628 ADVANCE_RING();
629 }
630
631 return 0;
632}
633
634/* Emit 1.2 state
635 */
636static int radeon_emit_state2(drm_radeon_private_t * dev_priv,
637 struct drm_file *file_priv,
638 drm_radeon_state_t * state)
639{
640 RING_LOCALS;
641
642 if (state->dirty & RADEON_UPLOAD_ZBIAS) {
643 BEGIN_RING(3);
644 OUT_RING(CP_PACKET0(RADEON_SE_ZBIAS_FACTOR, 1));
645 OUT_RING(state->context2.se_zbias_factor);
646 OUT_RING(state->context2.se_zbias_constant);
647 ADVANCE_RING();
648 }
649
650 return radeon_emit_state(dev_priv, file_priv, &state->context,
651 state->tex, state->dirty);
652}
653
654/* New (1.3) state mechanism. 3 commands (packet, scalar, vector) in
655 * 1.3 cmdbuffers allow all previous state to be updated as well as
656 * the tcl scalar and vector areas.
657 */
658static struct {
659 int start;
660 int len;
661 const char *name;
662} packet[RADEON_MAX_STATE_PACKETS] = {
663 {RADEON_PP_MISC, 7, "RADEON_PP_MISC"},
664 {RADEON_PP_CNTL, 3, "RADEON_PP_CNTL"},
665 {RADEON_RB3D_COLORPITCH, 1, "RADEON_RB3D_COLORPITCH"},
666 {RADEON_RE_LINE_PATTERN, 2, "RADEON_RE_LINE_PATTERN"},
667 {RADEON_SE_LINE_WIDTH, 1, "RADEON_SE_LINE_WIDTH"},
668 {RADEON_PP_LUM_MATRIX, 1, "RADEON_PP_LUM_MATRIX"},
669 {RADEON_PP_ROT_MATRIX_0, 2, "RADEON_PP_ROT_MATRIX_0"},
670 {RADEON_RB3D_STENCILREFMASK, 3, "RADEON_RB3D_STENCILREFMASK"},
671 {RADEON_SE_VPORT_XSCALE, 6, "RADEON_SE_VPORT_XSCALE"},
672 {RADEON_SE_CNTL, 2, "RADEON_SE_CNTL"},
673 {RADEON_SE_CNTL_STATUS, 1, "RADEON_SE_CNTL_STATUS"},
674 {RADEON_RE_MISC, 1, "RADEON_RE_MISC"},
675 {RADEON_PP_TXFILTER_0, 6, "RADEON_PP_TXFILTER_0"},
676 {RADEON_PP_BORDER_COLOR_0, 1, "RADEON_PP_BORDER_COLOR_0"},
677 {RADEON_PP_TXFILTER_1, 6, "RADEON_PP_TXFILTER_1"},
678 {RADEON_PP_BORDER_COLOR_1, 1, "RADEON_PP_BORDER_COLOR_1"},
679 {RADEON_PP_TXFILTER_2, 6, "RADEON_PP_TXFILTER_2"},
680 {RADEON_PP_BORDER_COLOR_2, 1, "RADEON_PP_BORDER_COLOR_2"},
681 {RADEON_SE_ZBIAS_FACTOR, 2, "RADEON_SE_ZBIAS_FACTOR"},
682 {RADEON_SE_TCL_OUTPUT_VTX_FMT, 11, "RADEON_SE_TCL_OUTPUT_VTX_FMT"},
683 {RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED, 17,
684 "RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED"},
685 {R200_PP_TXCBLEND_0, 4, "R200_PP_TXCBLEND_0"},
686 {R200_PP_TXCBLEND_1, 4, "R200_PP_TXCBLEND_1"},
687 {R200_PP_TXCBLEND_2, 4, "R200_PP_TXCBLEND_2"},
688 {R200_PP_TXCBLEND_3, 4, "R200_PP_TXCBLEND_3"},
689 {R200_PP_TXCBLEND_4, 4, "R200_PP_TXCBLEND_4"},
690 {R200_PP_TXCBLEND_5, 4, "R200_PP_TXCBLEND_5"},
691 {R200_PP_TXCBLEND_6, 4, "R200_PP_TXCBLEND_6"},
692 {R200_PP_TXCBLEND_7, 4, "R200_PP_TXCBLEND_7"},
693 {R200_SE_TCL_LIGHT_MODEL_CTL_0, 6, "R200_SE_TCL_LIGHT_MODEL_CTL_0"},
694 {R200_PP_TFACTOR_0, 6, "R200_PP_TFACTOR_0"},
695 {R200_SE_VTX_FMT_0, 4, "R200_SE_VTX_FMT_0"},
696 {R200_SE_VAP_CNTL, 1, "R200_SE_VAP_CNTL"},
697 {R200_SE_TCL_MATRIX_SEL_0, 5, "R200_SE_TCL_MATRIX_SEL_0"},
698 {R200_SE_TCL_TEX_PROC_CTL_2, 5, "R200_SE_TCL_TEX_PROC_CTL_2"},
699 {R200_SE_TCL_UCP_VERT_BLEND_CTL, 1, "R200_SE_TCL_UCP_VERT_BLEND_CTL"},
700 {R200_PP_TXFILTER_0, 6, "R200_PP_TXFILTER_0"},
701 {R200_PP_TXFILTER_1, 6, "R200_PP_TXFILTER_1"},
702 {R200_PP_TXFILTER_2, 6, "R200_PP_TXFILTER_2"},
703 {R200_PP_TXFILTER_3, 6, "R200_PP_TXFILTER_3"},
704 {R200_PP_TXFILTER_4, 6, "R200_PP_TXFILTER_4"},
705 {R200_PP_TXFILTER_5, 6, "R200_PP_TXFILTER_5"},
706 {R200_PP_TXOFFSET_0, 1, "R200_PP_TXOFFSET_0"},
707 {R200_PP_TXOFFSET_1, 1, "R200_PP_TXOFFSET_1"},
708 {R200_PP_TXOFFSET_2, 1, "R200_PP_TXOFFSET_2"},
709 {R200_PP_TXOFFSET_3, 1, "R200_PP_TXOFFSET_3"},
710 {R200_PP_TXOFFSET_4, 1, "R200_PP_TXOFFSET_4"},
711 {R200_PP_TXOFFSET_5, 1, "R200_PP_TXOFFSET_5"},
712 {R200_SE_VTE_CNTL, 1, "R200_SE_VTE_CNTL"},
713 {R200_SE_TCL_OUTPUT_VTX_COMP_SEL, 1,
714 "R200_SE_TCL_OUTPUT_VTX_COMP_SEL"},
715 {R200_PP_TAM_DEBUG3, 1, "R200_PP_TAM_DEBUG3"},
716 {R200_PP_CNTL_X, 1, "R200_PP_CNTL_X"},
717 {R200_RB3D_DEPTHXY_OFFSET, 1, "R200_RB3D_DEPTHXY_OFFSET"},
718 {R200_RE_AUX_SCISSOR_CNTL, 1, "R200_RE_AUX_SCISSOR_CNTL"},
719 {R200_RE_SCISSOR_TL_0, 2, "R200_RE_SCISSOR_TL_0"},
720 {R200_RE_SCISSOR_TL_1, 2, "R200_RE_SCISSOR_TL_1"},
721 {R200_RE_SCISSOR_TL_2, 2, "R200_RE_SCISSOR_TL_2"},
722 {R200_SE_VAP_CNTL_STATUS, 1, "R200_SE_VAP_CNTL_STATUS"},
723 {R200_SE_VTX_STATE_CNTL, 1, "R200_SE_VTX_STATE_CNTL"},
724 {R200_RE_POINTSIZE, 1, "R200_RE_POINTSIZE"},
725 {R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0, 4,
726 "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0"},
727 {R200_PP_CUBIC_FACES_0, 1, "R200_PP_CUBIC_FACES_0"}, /* 61 */
728 {R200_PP_CUBIC_OFFSET_F1_0, 5, "R200_PP_CUBIC_OFFSET_F1_0"}, /* 62 */
729 {R200_PP_CUBIC_FACES_1, 1, "R200_PP_CUBIC_FACES_1"},
730 {R200_PP_CUBIC_OFFSET_F1_1, 5, "R200_PP_CUBIC_OFFSET_F1_1"},
731 {R200_PP_CUBIC_FACES_2, 1, "R200_PP_CUBIC_FACES_2"},
732 {R200_PP_CUBIC_OFFSET_F1_2, 5, "R200_PP_CUBIC_OFFSET_F1_2"},
733 {R200_PP_CUBIC_FACES_3, 1, "R200_PP_CUBIC_FACES_3"},
734 {R200_PP_CUBIC_OFFSET_F1_3, 5, "R200_PP_CUBIC_OFFSET_F1_3"},
735 {R200_PP_CUBIC_FACES_4, 1, "R200_PP_CUBIC_FACES_4"},
736 {R200_PP_CUBIC_OFFSET_F1_4, 5, "R200_PP_CUBIC_OFFSET_F1_4"},
737 {R200_PP_CUBIC_FACES_5, 1, "R200_PP_CUBIC_FACES_5"},
738 {R200_PP_CUBIC_OFFSET_F1_5, 5, "R200_PP_CUBIC_OFFSET_F1_5"},
739 {RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0"},
740 {RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1"},
741 {RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_2"},
742 {R200_RB3D_BLENDCOLOR, 3, "R200_RB3D_BLENDCOLOR"},
743 {R200_SE_TCL_POINT_SPRITE_CNTL, 1, "R200_SE_TCL_POINT_SPRITE_CNTL"},
744 {RADEON_PP_CUBIC_FACES_0, 1, "RADEON_PP_CUBIC_FACES_0"},
745 {RADEON_PP_CUBIC_OFFSET_T0_0, 5, "RADEON_PP_CUBIC_OFFSET_T0_0"},
746 {RADEON_PP_CUBIC_FACES_1, 1, "RADEON_PP_CUBIC_FACES_1"},
747 {RADEON_PP_CUBIC_OFFSET_T1_0, 5, "RADEON_PP_CUBIC_OFFSET_T1_0"},
748 {RADEON_PP_CUBIC_FACES_2, 1, "RADEON_PP_CUBIC_FACES_2"},
749 {RADEON_PP_CUBIC_OFFSET_T2_0, 5, "RADEON_PP_CUBIC_OFFSET_T2_0"},
750 {R200_PP_TRI_PERF, 2, "R200_PP_TRI_PERF"},
751 {R200_PP_AFS_0, 32, "R200_PP_AFS_0"}, /* 85 */
752 {R200_PP_AFS_1, 32, "R200_PP_AFS_1"},
753 {R200_PP_TFACTOR_0, 8, "R200_ATF_TFACTOR"},
754 {R200_PP_TXFILTER_0, 8, "R200_PP_TXCTLALL_0"},
755 {R200_PP_TXFILTER_1, 8, "R200_PP_TXCTLALL_1"},
756 {R200_PP_TXFILTER_2, 8, "R200_PP_TXCTLALL_2"},
757 {R200_PP_TXFILTER_3, 8, "R200_PP_TXCTLALL_3"},
758 {R200_PP_TXFILTER_4, 8, "R200_PP_TXCTLALL_4"},
759 {R200_PP_TXFILTER_5, 8, "R200_PP_TXCTLALL_5"},
760 {R200_VAP_PVS_CNTL_1, 2, "R200_VAP_PVS_CNTL"},
761};
762
763/* ================================================================
764 * Performance monitoring functions
765 */
766
767static void radeon_clear_box(drm_radeon_private_t * dev_priv,
768 struct drm_radeon_master_private *master_priv,
769 int x, int y, int w, int h, int r, int g, int b)
770{
771 u32 color;
772 RING_LOCALS;
773
774 x += master_priv->sarea_priv->boxes[0].x1;
775 y += master_priv->sarea_priv->boxes[0].y1;
776
777 switch (dev_priv->color_fmt) {
778 case RADEON_COLOR_FORMAT_RGB565:
779 color = (((r & 0xf8) << 8) |
780 ((g & 0xfc) << 3) | ((b & 0xf8) >> 3));
781 break;
782 case RADEON_COLOR_FORMAT_ARGB8888:
783 default:
784 color = (((0xff) << 24) | (r << 16) | (g << 8) | b);
785 break;
786 }
787
788 BEGIN_RING(4);
789 RADEON_WAIT_UNTIL_3D_IDLE();
790 OUT_RING(CP_PACKET0(RADEON_DP_WRITE_MASK, 0));
791 OUT_RING(0xffffffff);
792 ADVANCE_RING();
793
794 BEGIN_RING(6);
795
796 OUT_RING(CP_PACKET3(RADEON_CNTL_PAINT_MULTI, 4));
797 OUT_RING(RADEON_GMC_DST_PITCH_OFFSET_CNTL |
798 RADEON_GMC_BRUSH_SOLID_COLOR |
799 (dev_priv->color_fmt << 8) |
800 RADEON_GMC_SRC_DATATYPE_COLOR |
801 RADEON_ROP3_P | RADEON_GMC_CLR_CMP_CNTL_DIS);
802
803 if (master_priv->sarea_priv->pfCurrentPage == 1) {
804 OUT_RING(dev_priv->front_pitch_offset);
805 } else {
806 OUT_RING(dev_priv->back_pitch_offset);
807 }
808
809 OUT_RING(color);
810
811 OUT_RING((x << 16) | y);
812 OUT_RING((w << 16) | h);
813
814 ADVANCE_RING();
815}
816
817static void radeon_cp_performance_boxes(drm_radeon_private_t *dev_priv, struct drm_radeon_master_private *master_priv)
818{
819 /* Collapse various things into a wait flag -- trying to
820 * guess if userspase slept -- better just to have them tell us.
821 */
822 if (dev_priv->stats.last_frame_reads > 1 ||
823 dev_priv->stats.last_clear_reads > dev_priv->stats.clears) {
824 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
825 }
826
827 if (dev_priv->stats.freelist_loops) {
828 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
829 }
830
831 /* Purple box for page flipping
832 */
833 if (dev_priv->stats.boxes & RADEON_BOX_FLIP)
834 radeon_clear_box(dev_priv, master_priv, 4, 4, 8, 8, 255, 0, 255);
835
836 /* Red box if we have to wait for idle at any point
837 */
838 if (dev_priv->stats.boxes & RADEON_BOX_WAIT_IDLE)
839 radeon_clear_box(dev_priv, master_priv, 16, 4, 8, 8, 255, 0, 0);
840
841 /* Blue box: lost context?
842 */
843
844 /* Yellow box for texture swaps
845 */
846 if (dev_priv->stats.boxes & RADEON_BOX_TEXTURE_LOAD)
847 radeon_clear_box(dev_priv, master_priv, 40, 4, 8, 8, 255, 255, 0);
848
849 /* Green box if hardware never idles (as far as we can tell)
850 */
851 if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE))
852 radeon_clear_box(dev_priv, master_priv, 64, 4, 8, 8, 0, 255, 0);
853
854 /* Draw bars indicating number of buffers allocated
855 * (not a great measure, easily confused)
856 */
857 if (dev_priv->stats.requested_bufs) {
858 if (dev_priv->stats.requested_bufs > 100)
859 dev_priv->stats.requested_bufs = 100;
860
861 radeon_clear_box(dev_priv, master_priv, 4, 16,
862 dev_priv->stats.requested_bufs, 4,
863 196, 128, 128);
864 }
865
866 memset(&dev_priv->stats, 0, sizeof(dev_priv->stats));
867
868}
869
870/* ================================================================
871 * CP command dispatch functions
872 */
873
874static void radeon_cp_dispatch_clear(struct drm_device * dev,
875 struct drm_master *master,
876 drm_radeon_clear_t * clear,
877 drm_radeon_clear_rect_t * depth_boxes)
878{
879 drm_radeon_private_t *dev_priv = dev->dev_private;
880 struct drm_radeon_master_private *master_priv = master->driver_priv;
881 drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv;
882 drm_radeon_depth_clear_t *depth_clear = &dev_priv->depth_clear;
883 int nbox = sarea_priv->nbox;
884 struct drm_clip_rect *pbox = sarea_priv->boxes;
885 unsigned int flags = clear->flags;
886 u32 rb3d_cntl = 0, rb3d_stencilrefmask = 0;
887 int i;
888 RING_LOCALS;
889 DRM_DEBUG("flags = 0x%x\n", flags);
890
891 dev_priv->stats.clears++;
892
893 if (sarea_priv->pfCurrentPage == 1) {
894 unsigned int tmp = flags;
895
896 flags &= ~(RADEON_FRONT | RADEON_BACK);
897 if (tmp & RADEON_FRONT)
898 flags |= RADEON_BACK;
899 if (tmp & RADEON_BACK)
900 flags |= RADEON_FRONT;
901 }
902 if (flags & (RADEON_DEPTH|RADEON_STENCIL)) {
903 if (!dev_priv->have_z_offset) {
904 printk_once(KERN_ERR "radeon: illegal depth clear request. Buggy mesa detected - please update.\n");
905 flags &= ~(RADEON_DEPTH | RADEON_STENCIL);
906 }
907 }
908
909 if (flags & (RADEON_FRONT | RADEON_BACK)) {
910
911 BEGIN_RING(4);
912
913 /* Ensure the 3D stream is idle before doing a
914 * 2D fill to clear the front or back buffer.
915 */
916 RADEON_WAIT_UNTIL_3D_IDLE();
917
918 OUT_RING(CP_PACKET0(RADEON_DP_WRITE_MASK, 0));
919 OUT_RING(clear->color_mask);
920
921 ADVANCE_RING();
922
923 /* Make sure we restore the 3D state next time.
924 */
925 sarea_priv->ctx_owner = 0;
926
927 for (i = 0; i < nbox; i++) {
928 int x = pbox[i].x1;
929 int y = pbox[i].y1;
930 int w = pbox[i].x2 - x;
931 int h = pbox[i].y2 - y;
932
933 DRM_DEBUG("%d,%d-%d,%d flags 0x%x\n",
934 x, y, w, h, flags);
935
936 if (flags & RADEON_FRONT) {
937 BEGIN_RING(6);
938
939 OUT_RING(CP_PACKET3
940 (RADEON_CNTL_PAINT_MULTI, 4));
941 OUT_RING(RADEON_GMC_DST_PITCH_OFFSET_CNTL |
942 RADEON_GMC_BRUSH_SOLID_COLOR |
943 (dev_priv->
944 color_fmt << 8) |
945 RADEON_GMC_SRC_DATATYPE_COLOR |
946 RADEON_ROP3_P |
947 RADEON_GMC_CLR_CMP_CNTL_DIS);
948
949 OUT_RING(dev_priv->front_pitch_offset);
950 OUT_RING(clear->clear_color);
951
952 OUT_RING((x << 16) | y);
953 OUT_RING((w << 16) | h);
954
955 ADVANCE_RING();
956 }
957
958 if (flags & RADEON_BACK) {
959 BEGIN_RING(6);
960
961 OUT_RING(CP_PACKET3
962 (RADEON_CNTL_PAINT_MULTI, 4));
963 OUT_RING(RADEON_GMC_DST_PITCH_OFFSET_CNTL |
964 RADEON_GMC_BRUSH_SOLID_COLOR |
965 (dev_priv->
966 color_fmt << 8) |
967 RADEON_GMC_SRC_DATATYPE_COLOR |
968 RADEON_ROP3_P |
969 RADEON_GMC_CLR_CMP_CNTL_DIS);
970
971 OUT_RING(dev_priv->back_pitch_offset);
972 OUT_RING(clear->clear_color);
973
974 OUT_RING((x << 16) | y);
975 OUT_RING((w << 16) | h);
976
977 ADVANCE_RING();
978 }
979 }
980 }
981
982 /* hyper z clear */
983 /* no docs available, based on reverse engineering by Stephane Marchesin */
984 if ((flags & (RADEON_DEPTH | RADEON_STENCIL))
985 && (flags & RADEON_CLEAR_FASTZ)) {
986
987 int i;
988 int depthpixperline =
989 dev_priv->depth_fmt ==
990 RADEON_DEPTH_FORMAT_16BIT_INT_Z ? (dev_priv->depth_pitch /
991 2) : (dev_priv->
992 depth_pitch / 4);
993
994 u32 clearmask;
995
996 u32 tempRB3D_DEPTHCLEARVALUE = clear->clear_depth |
997 ((clear->depth_mask & 0xff) << 24);
998
999 /* Make sure we restore the 3D state next time.
1000 * we haven't touched any "normal" state - still need this?
1001 */
1002 sarea_priv->ctx_owner = 0;
1003
1004 if ((dev_priv->flags & RADEON_HAS_HIERZ)
1005 && (flags & RADEON_USE_HIERZ)) {
1006 /* FIXME : reverse engineer that for Rx00 cards */
1007 /* FIXME : the mask supposedly contains low-res z values. So can't set
1008 just to the max (0xff? or actually 0x3fff?), need to take z clear
1009 value into account? */
1010 /* pattern seems to work for r100, though get slight
1011 rendering errors with glxgears. If hierz is not enabled for r100,
1012 only 4 bits which indicate clear (15,16,31,32, all zero) matter, the
1013 other ones are ignored, and the same clear mask can be used. That's
1014 very different behaviour than R200 which needs different clear mask
1015 and different number of tiles to clear if hierz is enabled or not !?!
1016 */
1017 clearmask = (0xff << 22) | (0xff << 6) | 0x003f003f;
1018 } else {
1019 /* clear mask : chooses the clearing pattern.
1020 rv250: could be used to clear only parts of macrotiles
1021 (but that would get really complicated...)?
1022 bit 0 and 1 (either or both of them ?!?!) are used to
1023 not clear tile (or maybe one of the bits indicates if the tile is
1024 compressed or not), bit 2 and 3 to not clear tile 1,...,.
1025 Pattern is as follows:
1026 | 0,1 | 4,5 | 8,9 |12,13|16,17|20,21|24,25|28,29|
1027 bits -------------------------------------------------
1028 | 2,3 | 6,7 |10,11|14,15|18,19|22,23|26,27|30,31|
1029 rv100: clearmask covers 2x8 4x1 tiles, but one clear still
1030 covers 256 pixels ?!?
1031 */
1032 clearmask = 0x0;
1033 }
1034
1035 BEGIN_RING(8);
1036 RADEON_WAIT_UNTIL_2D_IDLE();
1037 OUT_RING_REG(RADEON_RB3D_DEPTHCLEARVALUE,
1038 tempRB3D_DEPTHCLEARVALUE);
1039 /* what offset is this exactly ? */
1040 OUT_RING_REG(RADEON_RB3D_ZMASKOFFSET, 0);
1041 /* need ctlstat, otherwise get some strange black flickering */
1042 OUT_RING_REG(RADEON_RB3D_ZCACHE_CTLSTAT,
1043 RADEON_RB3D_ZC_FLUSH_ALL);
1044 ADVANCE_RING();
1045
1046 for (i = 0; i < nbox; i++) {
1047 int tileoffset, nrtilesx, nrtilesy, j;
1048 /* it looks like r200 needs rv-style clears, at least if hierz is not enabled? */
1049 if ((dev_priv->flags & RADEON_HAS_HIERZ)
1050 && !(dev_priv->microcode_version == UCODE_R200)) {
1051 /* FIXME : figure this out for r200 (when hierz is enabled). Or
1052 maybe r200 actually doesn't need to put the low-res z value into
1053 the tile cache like r100, but just needs to clear the hi-level z-buffer?
1054 Works for R100, both with hierz and without.
1055 R100 seems to operate on 2x1 8x8 tiles, but...
1056 odd: offset/nrtiles need to be 64 pix (4 block) aligned? Potentially
1057 problematic with resolutions which are not 64 pix aligned? */
1058 tileoffset =
1059 ((pbox[i].y1 >> 3) * depthpixperline +
1060 pbox[i].x1) >> 6;
1061 nrtilesx =
1062 ((pbox[i].x2 & ~63) -
1063 (pbox[i].x1 & ~63)) >> 4;
1064 nrtilesy =
1065 (pbox[i].y2 >> 3) - (pbox[i].y1 >> 3);
1066 for (j = 0; j <= nrtilesy; j++) {
1067 BEGIN_RING(4);
1068 OUT_RING(CP_PACKET3
1069 (RADEON_3D_CLEAR_ZMASK, 2));
1070 /* first tile */
1071 OUT_RING(tileoffset * 8);
1072 /* the number of tiles to clear */
1073 OUT_RING(nrtilesx + 4);
1074 /* clear mask : chooses the clearing pattern. */
1075 OUT_RING(clearmask);
1076 ADVANCE_RING();
1077 tileoffset += depthpixperline >> 6;
1078 }
1079 } else if (dev_priv->microcode_version == UCODE_R200) {
1080 /* works for rv250. */
1081 /* find first macro tile (8x2 4x4 z-pixels on rv250) */
1082 tileoffset =
1083 ((pbox[i].y1 >> 3) * depthpixperline +
1084 pbox[i].x1) >> 5;
1085 nrtilesx =
1086 (pbox[i].x2 >> 5) - (pbox[i].x1 >> 5);
1087 nrtilesy =
1088 (pbox[i].y2 >> 3) - (pbox[i].y1 >> 3);
1089 for (j = 0; j <= nrtilesy; j++) {
1090 BEGIN_RING(4);
1091 OUT_RING(CP_PACKET3
1092 (RADEON_3D_CLEAR_ZMASK, 2));
1093 /* first tile */
1094 /* judging by the first tile offset needed, could possibly
1095 directly address/clear 4x4 tiles instead of 8x2 * 4x4
1096 macro tiles, though would still need clear mask for
1097 right/bottom if truly 4x4 granularity is desired ? */
1098 OUT_RING(tileoffset * 16);
1099 /* the number of tiles to clear */
1100 OUT_RING(nrtilesx + 1);
1101 /* clear mask : chooses the clearing pattern. */
1102 OUT_RING(clearmask);
1103 ADVANCE_RING();
1104 tileoffset += depthpixperline >> 5;
1105 }
1106 } else { /* rv 100 */
1107 /* rv100 might not need 64 pix alignment, who knows */
1108 /* offsets are, hmm, weird */
1109 tileoffset =
1110 ((pbox[i].y1 >> 4) * depthpixperline +
1111 pbox[i].x1) >> 6;
1112 nrtilesx =
1113 ((pbox[i].x2 & ~63) -
1114 (pbox[i].x1 & ~63)) >> 4;
1115 nrtilesy =
1116 (pbox[i].y2 >> 4) - (pbox[i].y1 >> 4);
1117 for (j = 0; j <= nrtilesy; j++) {
1118 BEGIN_RING(4);
1119 OUT_RING(CP_PACKET3
1120 (RADEON_3D_CLEAR_ZMASK, 2));
1121 OUT_RING(tileoffset * 128);
1122 /* the number of tiles to clear */
1123 OUT_RING(nrtilesx + 4);
1124 /* clear mask : chooses the clearing pattern. */
1125 OUT_RING(clearmask);
1126 ADVANCE_RING();
1127 tileoffset += depthpixperline >> 6;
1128 }
1129 }
1130 }
1131
1132 /* TODO don't always clear all hi-level z tiles */
1133 if ((dev_priv->flags & RADEON_HAS_HIERZ)
1134 && (dev_priv->microcode_version == UCODE_R200)
1135 && (flags & RADEON_USE_HIERZ))
1136 /* r100 and cards without hierarchical z-buffer have no high-level z-buffer */
1137 /* FIXME : the mask supposedly contains low-res z values. So can't set
1138 just to the max (0xff? or actually 0x3fff?), need to take z clear
1139 value into account? */
1140 {
1141 BEGIN_RING(4);
1142 OUT_RING(CP_PACKET3(RADEON_3D_CLEAR_HIZ, 2));
1143 OUT_RING(0x0); /* First tile */
1144 OUT_RING(0x3cc0);
1145 OUT_RING((0xff << 22) | (0xff << 6) | 0x003f003f);
1146 ADVANCE_RING();
1147 }
1148 }
1149
1150 /* We have to clear the depth and/or stencil buffers by
1151 * rendering a quad into just those buffers. Thus, we have to
1152 * make sure the 3D engine is configured correctly.
1153 */
1154 else if ((dev_priv->microcode_version == UCODE_R200) &&
1155 (flags & (RADEON_DEPTH | RADEON_STENCIL))) {
1156
1157 int tempPP_CNTL;
1158 int tempRE_CNTL;
1159 int tempRB3D_CNTL;
1160 int tempRB3D_ZSTENCILCNTL;
1161 int tempRB3D_STENCILREFMASK;
1162 int tempRB3D_PLANEMASK;
1163 int tempSE_CNTL;
1164 int tempSE_VTE_CNTL;
1165 int tempSE_VTX_FMT_0;
1166 int tempSE_VTX_FMT_1;
1167 int tempSE_VAP_CNTL;
1168 int tempRE_AUX_SCISSOR_CNTL;
1169
1170 tempPP_CNTL = 0;
1171 tempRE_CNTL = 0;
1172
1173 tempRB3D_CNTL = depth_clear->rb3d_cntl;
1174
1175 tempRB3D_ZSTENCILCNTL = depth_clear->rb3d_zstencilcntl;
1176 tempRB3D_STENCILREFMASK = 0x0;
1177
1178 tempSE_CNTL = depth_clear->se_cntl;
1179
1180 /* Disable TCL */
1181
1182 tempSE_VAP_CNTL = ( /* SE_VAP_CNTL__FORCE_W_TO_ONE_MASK | */
1183 (0x9 <<
1184 SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT));
1185
1186 tempRB3D_PLANEMASK = 0x0;
1187
1188 tempRE_AUX_SCISSOR_CNTL = 0x0;
1189
1190 tempSE_VTE_CNTL =
1191 SE_VTE_CNTL__VTX_XY_FMT_MASK | SE_VTE_CNTL__VTX_Z_FMT_MASK;
1192
1193 /* Vertex format (X, Y, Z, W) */
1194 tempSE_VTX_FMT_0 =
1195 SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK |
1196 SE_VTX_FMT_0__VTX_W0_PRESENT_MASK;
1197 tempSE_VTX_FMT_1 = 0x0;
1198
1199 /*
1200 * Depth buffer specific enables
1201 */
1202 if (flags & RADEON_DEPTH) {
1203 /* Enable depth buffer */
1204 tempRB3D_CNTL |= RADEON_Z_ENABLE;
1205 } else {
1206 /* Disable depth buffer */
1207 tempRB3D_CNTL &= ~RADEON_Z_ENABLE;
1208 }
1209
1210 /*
1211 * Stencil buffer specific enables
1212 */
1213 if (flags & RADEON_STENCIL) {
1214 tempRB3D_CNTL |= RADEON_STENCIL_ENABLE;
1215 tempRB3D_STENCILREFMASK = clear->depth_mask;
1216 } else {
1217 tempRB3D_CNTL &= ~RADEON_STENCIL_ENABLE;
1218 tempRB3D_STENCILREFMASK = 0x00000000;
1219 }
1220
1221 if (flags & RADEON_USE_COMP_ZBUF) {
1222 tempRB3D_ZSTENCILCNTL |= RADEON_Z_COMPRESSION_ENABLE |
1223 RADEON_Z_DECOMPRESSION_ENABLE;
1224 }
1225 if (flags & RADEON_USE_HIERZ) {
1226 tempRB3D_ZSTENCILCNTL |= RADEON_Z_HIERARCHY_ENABLE;
1227 }
1228
1229 BEGIN_RING(26);
1230 RADEON_WAIT_UNTIL_2D_IDLE();
1231
1232 OUT_RING_REG(RADEON_PP_CNTL, tempPP_CNTL);
1233 OUT_RING_REG(R200_RE_CNTL, tempRE_CNTL);
1234 OUT_RING_REG(RADEON_RB3D_CNTL, tempRB3D_CNTL);
1235 OUT_RING_REG(RADEON_RB3D_ZSTENCILCNTL, tempRB3D_ZSTENCILCNTL);
1236 OUT_RING_REG(RADEON_RB3D_STENCILREFMASK,
1237 tempRB3D_STENCILREFMASK);
1238 OUT_RING_REG(RADEON_RB3D_PLANEMASK, tempRB3D_PLANEMASK);
1239 OUT_RING_REG(RADEON_SE_CNTL, tempSE_CNTL);
1240 OUT_RING_REG(R200_SE_VTE_CNTL, tempSE_VTE_CNTL);
1241 OUT_RING_REG(R200_SE_VTX_FMT_0, tempSE_VTX_FMT_0);
1242 OUT_RING_REG(R200_SE_VTX_FMT_1, tempSE_VTX_FMT_1);
1243 OUT_RING_REG(R200_SE_VAP_CNTL, tempSE_VAP_CNTL);
1244 OUT_RING_REG(R200_RE_AUX_SCISSOR_CNTL, tempRE_AUX_SCISSOR_CNTL);
1245 ADVANCE_RING();
1246
1247 /* Make sure we restore the 3D state next time.
1248 */
1249 sarea_priv->ctx_owner = 0;
1250
1251 for (i = 0; i < nbox; i++) {
1252
1253 /* Funny that this should be required --
1254 * sets top-left?
1255 */
1256 radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]);
1257
1258 BEGIN_RING(14);
1259 OUT_RING(CP_PACKET3(R200_3D_DRAW_IMMD_2, 12));
1260 OUT_RING((RADEON_PRIM_TYPE_RECT_LIST |
1261 RADEON_PRIM_WALK_RING |
1262 (3 << RADEON_NUM_VERTICES_SHIFT)));
1263 OUT_RING(depth_boxes[i].ui[CLEAR_X1]);
1264 OUT_RING(depth_boxes[i].ui[CLEAR_Y1]);
1265 OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]);
1266 OUT_RING(0x3f800000);
1267 OUT_RING(depth_boxes[i].ui[CLEAR_X1]);
1268 OUT_RING(depth_boxes[i].ui[CLEAR_Y2]);
1269 OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]);
1270 OUT_RING(0x3f800000);
1271 OUT_RING(depth_boxes[i].ui[CLEAR_X2]);
1272 OUT_RING(depth_boxes[i].ui[CLEAR_Y2]);
1273 OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]);
1274 OUT_RING(0x3f800000);
1275 ADVANCE_RING();
1276 }
1277 } else if ((flags & (RADEON_DEPTH | RADEON_STENCIL))) {
1278
1279 int tempRB3D_ZSTENCILCNTL = depth_clear->rb3d_zstencilcntl;
1280
1281 rb3d_cntl = depth_clear->rb3d_cntl;
1282
1283 if (flags & RADEON_DEPTH) {
1284 rb3d_cntl |= RADEON_Z_ENABLE;
1285 } else {
1286 rb3d_cntl &= ~RADEON_Z_ENABLE;
1287 }
1288
1289 if (flags & RADEON_STENCIL) {
1290 rb3d_cntl |= RADEON_STENCIL_ENABLE;
1291 rb3d_stencilrefmask = clear->depth_mask; /* misnamed field */
1292 } else {
1293 rb3d_cntl &= ~RADEON_STENCIL_ENABLE;
1294 rb3d_stencilrefmask = 0x00000000;
1295 }
1296
1297 if (flags & RADEON_USE_COMP_ZBUF) {
1298 tempRB3D_ZSTENCILCNTL |= RADEON_Z_COMPRESSION_ENABLE |
1299 RADEON_Z_DECOMPRESSION_ENABLE;
1300 }
1301 if (flags & RADEON_USE_HIERZ) {
1302 tempRB3D_ZSTENCILCNTL |= RADEON_Z_HIERARCHY_ENABLE;
1303 }
1304
1305 BEGIN_RING(13);
1306 RADEON_WAIT_UNTIL_2D_IDLE();
1307
1308 OUT_RING(CP_PACKET0(RADEON_PP_CNTL, 1));
1309 OUT_RING(0x00000000);
1310 OUT_RING(rb3d_cntl);
1311
1312 OUT_RING_REG(RADEON_RB3D_ZSTENCILCNTL, tempRB3D_ZSTENCILCNTL);
1313 OUT_RING_REG(RADEON_RB3D_STENCILREFMASK, rb3d_stencilrefmask);
1314 OUT_RING_REG(RADEON_RB3D_PLANEMASK, 0x00000000);
1315 OUT_RING_REG(RADEON_SE_CNTL, depth_clear->se_cntl);
1316 ADVANCE_RING();
1317
1318 /* Make sure we restore the 3D state next time.
1319 */
1320 sarea_priv->ctx_owner = 0;
1321
1322 for (i = 0; i < nbox; i++) {
1323
1324 /* Funny that this should be required --
1325 * sets top-left?
1326 */
1327 radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]);
1328
1329 BEGIN_RING(15);
1330
1331 OUT_RING(CP_PACKET3(RADEON_3D_DRAW_IMMD, 13));
1332 OUT_RING(RADEON_VTX_Z_PRESENT |
1333 RADEON_VTX_PKCOLOR_PRESENT);
1334 OUT_RING((RADEON_PRIM_TYPE_RECT_LIST |
1335 RADEON_PRIM_WALK_RING |
1336 RADEON_MAOS_ENABLE |
1337 RADEON_VTX_FMT_RADEON_MODE |
1338 (3 << RADEON_NUM_VERTICES_SHIFT)));
1339
1340 OUT_RING(depth_boxes[i].ui[CLEAR_X1]);
1341 OUT_RING(depth_boxes[i].ui[CLEAR_Y1]);
1342 OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]);
1343 OUT_RING(0x0);
1344
1345 OUT_RING(depth_boxes[i].ui[CLEAR_X1]);
1346 OUT_RING(depth_boxes[i].ui[CLEAR_Y2]);
1347 OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]);
1348 OUT_RING(0x0);
1349
1350 OUT_RING(depth_boxes[i].ui[CLEAR_X2]);
1351 OUT_RING(depth_boxes[i].ui[CLEAR_Y2]);
1352 OUT_RING(depth_boxes[i].ui[CLEAR_DEPTH]);
1353 OUT_RING(0x0);
1354
1355 ADVANCE_RING();
1356 }
1357 }
1358
1359 /* Increment the clear counter. The client-side 3D driver must
1360 * wait on this value before performing the clear ioctl. We
1361 * need this because the card's so damned fast...
1362 */
1363 sarea_priv->last_clear++;
1364
1365 BEGIN_RING(4);
1366
1367 RADEON_CLEAR_AGE(sarea_priv->last_clear);
1368 RADEON_WAIT_UNTIL_IDLE();
1369
1370 ADVANCE_RING();
1371}
1372
1373static void radeon_cp_dispatch_swap(struct drm_device *dev, struct drm_master *master)
1374{
1375 drm_radeon_private_t *dev_priv = dev->dev_private;
1376 struct drm_radeon_master_private *master_priv = master->driver_priv;
1377 drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv;
1378 int nbox = sarea_priv->nbox;
1379 struct drm_clip_rect *pbox = sarea_priv->boxes;
1380 int i;
1381 RING_LOCALS;
1382 DRM_DEBUG("\n");
1383
1384 /* Do some trivial performance monitoring...
1385 */
1386 if (dev_priv->do_boxes)
1387 radeon_cp_performance_boxes(dev_priv, master_priv);
1388
1389 /* Wait for the 3D stream to idle before dispatching the bitblt.
1390 * This will prevent data corruption between the two streams.
1391 */
1392 BEGIN_RING(2);
1393
1394 RADEON_WAIT_UNTIL_3D_IDLE();
1395
1396 ADVANCE_RING();
1397
1398 for (i = 0; i < nbox; i++) {
1399 int x = pbox[i].x1;
1400 int y = pbox[i].y1;
1401 int w = pbox[i].x2 - x;
1402 int h = pbox[i].y2 - y;
1403
1404 DRM_DEBUG("%d,%d-%d,%d\n", x, y, w, h);
1405
1406 BEGIN_RING(9);
1407
1408 OUT_RING(CP_PACKET0(RADEON_DP_GUI_MASTER_CNTL, 0));
1409 OUT_RING(RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
1410 RADEON_GMC_DST_PITCH_OFFSET_CNTL |
1411 RADEON_GMC_BRUSH_NONE |
1412 (dev_priv->color_fmt << 8) |
1413 RADEON_GMC_SRC_DATATYPE_COLOR |
1414 RADEON_ROP3_S |
1415 RADEON_DP_SRC_SOURCE_MEMORY |
1416 RADEON_GMC_CLR_CMP_CNTL_DIS | RADEON_GMC_WR_MSK_DIS);
1417
1418 /* Make this work even if front & back are flipped:
1419 */
1420 OUT_RING(CP_PACKET0(RADEON_SRC_PITCH_OFFSET, 1));
1421 if (sarea_priv->pfCurrentPage == 0) {
1422 OUT_RING(dev_priv->back_pitch_offset);
1423 OUT_RING(dev_priv->front_pitch_offset);
1424 } else {
1425 OUT_RING(dev_priv->front_pitch_offset);
1426 OUT_RING(dev_priv->back_pitch_offset);
1427 }
1428
1429 OUT_RING(CP_PACKET0(RADEON_SRC_X_Y, 2));
1430 OUT_RING((x << 16) | y);
1431 OUT_RING((x << 16) | y);
1432 OUT_RING((w << 16) | h);
1433
1434 ADVANCE_RING();
1435 }
1436
1437 /* Increment the frame counter. The client-side 3D driver must
1438 * throttle the framerate by waiting for this value before
1439 * performing the swapbuffer ioctl.
1440 */
1441 sarea_priv->last_frame++;
1442
1443 BEGIN_RING(4);
1444
1445 RADEON_FRAME_AGE(sarea_priv->last_frame);
1446 RADEON_WAIT_UNTIL_2D_IDLE();
1447
1448 ADVANCE_RING();
1449}
1450
1451void radeon_cp_dispatch_flip(struct drm_device *dev, struct drm_master *master)
1452{
1453 drm_radeon_private_t *dev_priv = dev->dev_private;
1454 struct drm_radeon_master_private *master_priv = master->driver_priv;
1455 struct drm_sarea *sarea = (struct drm_sarea *)master_priv->sarea->handle;
1456 int offset = (master_priv->sarea_priv->pfCurrentPage == 1)
1457 ? dev_priv->front_offset : dev_priv->back_offset;
1458 RING_LOCALS;
1459 DRM_DEBUG("pfCurrentPage=%d\n",
1460 master_priv->sarea_priv->pfCurrentPage);
1461
1462 /* Do some trivial performance monitoring...
1463 */
1464 if (dev_priv->do_boxes) {
1465 dev_priv->stats.boxes |= RADEON_BOX_FLIP;
1466 radeon_cp_performance_boxes(dev_priv, master_priv);
1467 }
1468
1469 /* Update the frame offsets for both CRTCs
1470 */
1471 BEGIN_RING(6);
1472
1473 RADEON_WAIT_UNTIL_3D_IDLE();
1474 OUT_RING_REG(RADEON_CRTC_OFFSET,
1475 ((sarea->frame.y * dev_priv->front_pitch +
1476 sarea->frame.x * (dev_priv->color_fmt - 2)) & ~7)
1477 + offset);
1478 OUT_RING_REG(RADEON_CRTC2_OFFSET, master_priv->sarea_priv->crtc2_base
1479 + offset);
1480
1481 ADVANCE_RING();
1482
1483 /* Increment the frame counter. The client-side 3D driver must
1484 * throttle the framerate by waiting for this value before
1485 * performing the swapbuffer ioctl.
1486 */
1487 master_priv->sarea_priv->last_frame++;
1488 master_priv->sarea_priv->pfCurrentPage =
1489 1 - master_priv->sarea_priv->pfCurrentPage;
1490
1491 BEGIN_RING(2);
1492
1493 RADEON_FRAME_AGE(master_priv->sarea_priv->last_frame);
1494
1495 ADVANCE_RING();
1496}
1497
1498static int bad_prim_vertex_nr(int primitive, int nr)
1499{
1500 switch (primitive & RADEON_PRIM_TYPE_MASK) {
1501 case RADEON_PRIM_TYPE_NONE:
1502 case RADEON_PRIM_TYPE_POINT:
1503 return nr < 1;
1504 case RADEON_PRIM_TYPE_LINE:
1505 return (nr & 1) || nr == 0;
1506 case RADEON_PRIM_TYPE_LINE_STRIP:
1507 return nr < 2;
1508 case RADEON_PRIM_TYPE_TRI_LIST:
1509 case RADEON_PRIM_TYPE_3VRT_POINT_LIST:
1510 case RADEON_PRIM_TYPE_3VRT_LINE_LIST:
1511 case RADEON_PRIM_TYPE_RECT_LIST:
1512 return nr % 3 || nr == 0;
1513 case RADEON_PRIM_TYPE_TRI_FAN:
1514 case RADEON_PRIM_TYPE_TRI_STRIP:
1515 return nr < 3;
1516 default:
1517 return 1;
1518 }
1519}
1520
1521typedef struct {
1522 unsigned int start;
1523 unsigned int finish;
1524 unsigned int prim;
1525 unsigned int numverts;
1526 unsigned int offset;
1527 unsigned int vc_format;
1528} drm_radeon_tcl_prim_t;
1529
1530static void radeon_cp_dispatch_vertex(struct drm_device * dev,
1531 struct drm_file *file_priv,
1532 struct drm_buf * buf,
1533 drm_radeon_tcl_prim_t * prim)
1534{
1535 drm_radeon_private_t *dev_priv = dev->dev_private;
1536 struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv;
1537 drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv;
1538 int offset = dev_priv->gart_buffers_offset + buf->offset + prim->start;
1539 int numverts = (int)prim->numverts;
1540 int nbox = sarea_priv->nbox;
1541 int i = 0;
1542 RING_LOCALS;
1543
1544 DRM_DEBUG("hwprim 0x%x vfmt 0x%x %d..%d %d verts\n",
1545 prim->prim,
1546 prim->vc_format, prim->start, prim->finish, prim->numverts);
1547
1548 if (bad_prim_vertex_nr(prim->prim, prim->numverts)) {
1549 DRM_ERROR("bad prim %x numverts %d\n",
1550 prim->prim, prim->numverts);
1551 return;
1552 }
1553
1554 do {
1555 /* Emit the next cliprect */
1556 if (i < nbox) {
1557 radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]);
1558 }
1559
1560 /* Emit the vertex buffer rendering commands */
1561 BEGIN_RING(5);
1562
1563 OUT_RING(CP_PACKET3(RADEON_3D_RNDR_GEN_INDX_PRIM, 3));
1564 OUT_RING(offset);
1565 OUT_RING(numverts);
1566 OUT_RING(prim->vc_format);
1567 OUT_RING(prim->prim | RADEON_PRIM_WALK_LIST |
1568 RADEON_COLOR_ORDER_RGBA |
1569 RADEON_VTX_FMT_RADEON_MODE |
1570 (numverts << RADEON_NUM_VERTICES_SHIFT));
1571
1572 ADVANCE_RING();
1573
1574 i++;
1575 } while (i < nbox);
1576}
1577
1578void radeon_cp_discard_buffer(struct drm_device *dev, struct drm_master *master, struct drm_buf *buf)
1579{
1580 drm_radeon_private_t *dev_priv = dev->dev_private;
1581 struct drm_radeon_master_private *master_priv = master->driver_priv;
1582 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
1583 RING_LOCALS;
1584
1585 buf_priv->age = ++master_priv->sarea_priv->last_dispatch;
1586
1587 /* Emit the vertex buffer age */
1588 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
1589 BEGIN_RING(3);
1590 R600_DISPATCH_AGE(buf_priv->age);
1591 ADVANCE_RING();
1592 } else {
1593 BEGIN_RING(2);
1594 RADEON_DISPATCH_AGE(buf_priv->age);
1595 ADVANCE_RING();
1596 }
1597
1598 buf->pending = 1;
1599 buf->used = 0;
1600}
1601
1602static void radeon_cp_dispatch_indirect(struct drm_device * dev,
1603 struct drm_buf * buf, int start, int end)
1604{
1605 drm_radeon_private_t *dev_priv = dev->dev_private;
1606 RING_LOCALS;
1607 DRM_DEBUG("buf=%d s=0x%x e=0x%x\n", buf->idx, start, end);
1608
1609 if (start != end) {
1610 int offset = (dev_priv->gart_buffers_offset
1611 + buf->offset + start);
1612 int dwords = (end - start + 3) / sizeof(u32);
1613
1614 /* Indirect buffer data must be an even number of
1615 * dwords, so if we've been given an odd number we must
1616 * pad the data with a Type-2 CP packet.
1617 */
1618 if (dwords & 1) {
1619 u32 *data = (u32 *)
1620 ((char *)dev->agp_buffer_map->handle
1621 + buf->offset + start);
1622 data[dwords++] = RADEON_CP_PACKET2;
1623 }
1624
1625 /* Fire off the indirect buffer */
1626 BEGIN_RING(3);
1627
1628 OUT_RING(CP_PACKET0(RADEON_CP_IB_BASE, 1));
1629 OUT_RING(offset);
1630 OUT_RING(dwords);
1631
1632 ADVANCE_RING();
1633 }
1634}
1635
1636static void radeon_cp_dispatch_indices(struct drm_device *dev,
1637 struct drm_master *master,
1638 struct drm_buf * elt_buf,
1639 drm_radeon_tcl_prim_t * prim)
1640{
1641 drm_radeon_private_t *dev_priv = dev->dev_private;
1642 struct drm_radeon_master_private *master_priv = master->driver_priv;
1643 drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv;
1644 int offset = dev_priv->gart_buffers_offset + prim->offset;
1645 u32 *data;
1646 int dwords;
1647 int i = 0;
1648 int start = prim->start + RADEON_INDEX_PRIM_OFFSET;
1649 int count = (prim->finish - start) / sizeof(u16);
1650 int nbox = sarea_priv->nbox;
1651
1652 DRM_DEBUG("hwprim 0x%x vfmt 0x%x %d..%d offset: %x nr %d\n",
1653 prim->prim,
1654 prim->vc_format,
1655 prim->start, prim->finish, prim->offset, prim->numverts);
1656
1657 if (bad_prim_vertex_nr(prim->prim, count)) {
1658 DRM_ERROR("bad prim %x count %d\n", prim->prim, count);
1659 return;
1660 }
1661
1662 if (start >= prim->finish || (prim->start & 0x7)) {
1663 DRM_ERROR("buffer prim %d\n", prim->prim);
1664 return;
1665 }
1666
1667 dwords = (prim->finish - prim->start + 3) / sizeof(u32);
1668
1669 data = (u32 *) ((char *)dev->agp_buffer_map->handle +
1670 elt_buf->offset + prim->start);
1671
1672 data[0] = CP_PACKET3(RADEON_3D_RNDR_GEN_INDX_PRIM, dwords - 2);
1673 data[1] = offset;
1674 data[2] = prim->numverts;
1675 data[3] = prim->vc_format;
1676 data[4] = (prim->prim |
1677 RADEON_PRIM_WALK_IND |
1678 RADEON_COLOR_ORDER_RGBA |
1679 RADEON_VTX_FMT_RADEON_MODE |
1680 (count << RADEON_NUM_VERTICES_SHIFT));
1681
1682 do {
1683 if (i < nbox)
1684 radeon_emit_clip_rect(dev_priv, &sarea_priv->boxes[i]);
1685
1686 radeon_cp_dispatch_indirect(dev, elt_buf,
1687 prim->start, prim->finish);
1688
1689 i++;
1690 } while (i < nbox);
1691
1692}
1693
1694#define RADEON_MAX_TEXTURE_SIZE RADEON_BUFFER_SIZE
1695
1696static int radeon_cp_dispatch_texture(struct drm_device * dev,
1697 struct drm_file *file_priv,
1698 drm_radeon_texture_t * tex,
1699 drm_radeon_tex_image_t * image)
1700{
1701 drm_radeon_private_t *dev_priv = dev->dev_private;
1702 struct drm_buf *buf;
1703 u32 format;
1704 u32 *buffer;
1705 const u8 __user *data;
1706 unsigned int size, dwords, tex_width, blit_width, spitch;
1707 u32 height;
1708 int i;
1709 u32 texpitch, microtile;
1710 u32 offset, byte_offset;
1711 RING_LOCALS;
1712
1713 if (radeon_check_and_fixup_offset(dev_priv, file_priv, &tex->offset)) {
1714 DRM_ERROR("Invalid destination offset\n");
1715 return -EINVAL;
1716 }
1717
1718 dev_priv->stats.boxes |= RADEON_BOX_TEXTURE_LOAD;
1719
1720 /* Flush the pixel cache. This ensures no pixel data gets mixed
1721 * up with the texture data from the host data blit, otherwise
1722 * part of the texture image may be corrupted.
1723 */
1724 BEGIN_RING(4);
1725 RADEON_FLUSH_CACHE();
1726 RADEON_WAIT_UNTIL_IDLE();
1727 ADVANCE_RING();
1728
1729 /* The compiler won't optimize away a division by a variable,
1730 * even if the only legal values are powers of two. Thus, we'll
1731 * use a shift instead.
1732 */
1733 switch (tex->format) {
1734 case RADEON_TXFORMAT_ARGB8888:
1735 case RADEON_TXFORMAT_RGBA8888:
1736 format = RADEON_COLOR_FORMAT_ARGB8888;
1737 tex_width = tex->width * 4;
1738 blit_width = image->width * 4;
1739 break;
1740 case RADEON_TXFORMAT_AI88:
1741 case RADEON_TXFORMAT_ARGB1555:
1742 case RADEON_TXFORMAT_RGB565:
1743 case RADEON_TXFORMAT_ARGB4444:
1744 case RADEON_TXFORMAT_VYUY422:
1745 case RADEON_TXFORMAT_YVYU422:
1746 format = RADEON_COLOR_FORMAT_RGB565;
1747 tex_width = tex->width * 2;
1748 blit_width = image->width * 2;
1749 break;
1750 case RADEON_TXFORMAT_I8:
1751 case RADEON_TXFORMAT_RGB332:
1752 format = RADEON_COLOR_FORMAT_CI8;
1753 tex_width = tex->width * 1;
1754 blit_width = image->width * 1;
1755 break;
1756 default:
1757 DRM_ERROR("invalid texture format %d\n", tex->format);
1758 return -EINVAL;
1759 }
1760 spitch = blit_width >> 6;
1761 if (spitch == 0 && image->height > 1)
1762 return -EINVAL;
1763
1764 texpitch = tex->pitch;
1765 if ((texpitch << 22) & RADEON_DST_TILE_MICRO) {
1766 microtile = 1;
1767 if (tex_width < 64) {
1768 texpitch &= ~(RADEON_DST_TILE_MICRO >> 22);
1769 /* we got tiled coordinates, untile them */
1770 image->x *= 2;
1771 }
1772 } else
1773 microtile = 0;
1774
1775 /* this might fail for zero-sized uploads - are those illegal? */
1776 if (!radeon_check_offset(dev_priv, tex->offset + image->height *
1777 blit_width - 1)) {
1778 DRM_ERROR("Invalid final destination offset\n");
1779 return -EINVAL;
1780 }
1781
1782 DRM_DEBUG("tex=%dx%d blit=%d\n", tex_width, tex->height, blit_width);
1783
1784 do {
1785 DRM_DEBUG("tex: ofs=0x%x p=%d f=%d x=%hd y=%hd w=%hd h=%hd\n",
1786 tex->offset >> 10, tex->pitch, tex->format,
1787 image->x, image->y, image->width, image->height);
1788
1789 /* Make a copy of some parameters in case we have to
1790 * update them for a multi-pass texture blit.
1791 */
1792 height = image->height;
1793 data = (const u8 __user *)image->data;
1794
1795 size = height * blit_width;
1796
1797 if (size > RADEON_MAX_TEXTURE_SIZE) {
1798 height = RADEON_MAX_TEXTURE_SIZE / blit_width;
1799 size = height * blit_width;
1800 } else if (size < 4 && size > 0) {
1801 size = 4;
1802 } else if (size == 0) {
1803 return 0;
1804 }
1805
1806 buf = radeon_freelist_get(dev);
1807 if (0 && !buf) {
1808 radeon_do_cp_idle(dev_priv);
1809 buf = radeon_freelist_get(dev);
1810 }
1811 if (!buf) {
1812 DRM_DEBUG("EAGAIN\n");
1813 if (copy_to_user(tex->image, image, sizeof(*image)))
1814 return -EFAULT;
1815 return -EAGAIN;
1816 }
1817
1818 /* Dispatch the indirect buffer.
1819 */
1820 buffer =
1821 (u32 *) ((char *)dev->agp_buffer_map->handle + buf->offset);
1822 dwords = size / 4;
1823
1824#define RADEON_COPY_MT(_buf, _data, _width) \
1825 do { \
1826 if (copy_from_user(_buf, _data, (_width))) {\
1827 DRM_ERROR("EFAULT on pad, %d bytes\n", (_width)); \
1828 return -EFAULT; \
1829 } \
1830 } while(0)
1831
1832 if (microtile) {
1833 /* texture micro tiling in use, minimum texture width is thus 16 bytes.
1834 however, we cannot use blitter directly for texture width < 64 bytes,
1835 since minimum tex pitch is 64 bytes and we need this to match
1836 the texture width, otherwise the blitter will tile it wrong.
1837 Thus, tiling manually in this case. Additionally, need to special
1838 case tex height = 1, since our actual image will have height 2
1839 and we need to ensure we don't read beyond the texture size
1840 from user space. */
1841 if (tex->height == 1) {
1842 if (tex_width >= 64 || tex_width <= 16) {
1843 RADEON_COPY_MT(buffer, data,
1844 (int)(tex_width * sizeof(u32)));
1845 } else if (tex_width == 32) {
1846 RADEON_COPY_MT(buffer, data, 16);
1847 RADEON_COPY_MT(buffer + 8,
1848 data + 16, 16);
1849 }
1850 } else if (tex_width >= 64 || tex_width == 16) {
1851 RADEON_COPY_MT(buffer, data,
1852 (int)(dwords * sizeof(u32)));
1853 } else if (tex_width < 16) {
1854 for (i = 0; i < tex->height; i++) {
1855 RADEON_COPY_MT(buffer, data, tex_width);
1856 buffer += 4;
1857 data += tex_width;
1858 }
1859 } else if (tex_width == 32) {
1860 /* TODO: make sure this works when not fitting in one buffer
1861 (i.e. 32bytes x 2048...) */
1862 for (i = 0; i < tex->height; i += 2) {
1863 RADEON_COPY_MT(buffer, data, 16);
1864 data += 16;
1865 RADEON_COPY_MT(buffer + 8, data, 16);
1866 data += 16;
1867 RADEON_COPY_MT(buffer + 4, data, 16);
1868 data += 16;
1869 RADEON_COPY_MT(buffer + 12, data, 16);
1870 data += 16;
1871 buffer += 16;
1872 }
1873 }
1874 } else {
1875 if (tex_width >= 32) {
1876 /* Texture image width is larger than the minimum, so we
1877 * can upload it directly.
1878 */
1879 RADEON_COPY_MT(buffer, data,
1880 (int)(dwords * sizeof(u32)));
1881 } else {
1882 /* Texture image width is less than the minimum, so we
1883 * need to pad out each image scanline to the minimum
1884 * width.
1885 */
1886 for (i = 0; i < tex->height; i++) {
1887 RADEON_COPY_MT(buffer, data, tex_width);
1888 buffer += 8;
1889 data += tex_width;
1890 }
1891 }
1892 }
1893
1894#undef RADEON_COPY_MT
1895 byte_offset = (image->y & ~2047) * blit_width;
1896 buf->file_priv = file_priv;
1897 buf->used = size;
1898 offset = dev_priv->gart_buffers_offset + buf->offset;
1899 BEGIN_RING(9);
1900 OUT_RING(CP_PACKET3(RADEON_CNTL_BITBLT_MULTI, 5));
1901 OUT_RING(RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
1902 RADEON_GMC_DST_PITCH_OFFSET_CNTL |
1903 RADEON_GMC_BRUSH_NONE |
1904 (format << 8) |
1905 RADEON_GMC_SRC_DATATYPE_COLOR |
1906 RADEON_ROP3_S |
1907 RADEON_DP_SRC_SOURCE_MEMORY |
1908 RADEON_GMC_CLR_CMP_CNTL_DIS | RADEON_GMC_WR_MSK_DIS);
1909 OUT_RING((spitch << 22) | (offset >> 10));
1910 OUT_RING((texpitch << 22) | ((tex->offset >> 10) + (byte_offset >> 10)));
1911 OUT_RING(0);
1912 OUT_RING((image->x << 16) | (image->y % 2048));
1913 OUT_RING((image->width << 16) | height);
1914 RADEON_WAIT_UNTIL_2D_IDLE();
1915 ADVANCE_RING();
1916 COMMIT_RING();
1917
1918 radeon_cp_discard_buffer(dev, file_priv->master, buf);
1919
1920 /* Update the input parameters for next time */
1921 image->y += height;
1922 image->height -= height;
1923 image->data = (const u8 __user *)image->data + size;
1924 } while (image->height > 0);
1925
1926 /* Flush the pixel cache after the blit completes. This ensures
1927 * the texture data is written out to memory before rendering
1928 * continues.
1929 */
1930 BEGIN_RING(4);
1931 RADEON_FLUSH_CACHE();
1932 RADEON_WAIT_UNTIL_2D_IDLE();
1933 ADVANCE_RING();
1934 COMMIT_RING();
1935
1936 return 0;
1937}
1938
1939static void radeon_cp_dispatch_stipple(struct drm_device * dev, u32 * stipple)
1940{
1941 drm_radeon_private_t *dev_priv = dev->dev_private;
1942 int i;
1943 RING_LOCALS;
1944 DRM_DEBUG("\n");
1945
1946 BEGIN_RING(35);
1947
1948 OUT_RING(CP_PACKET0(RADEON_RE_STIPPLE_ADDR, 0));
1949 OUT_RING(0x00000000);
1950
1951 OUT_RING(CP_PACKET0_TABLE(RADEON_RE_STIPPLE_DATA, 31));
1952 for (i = 0; i < 32; i++) {
1953 OUT_RING(stipple[i]);
1954 }
1955
1956 ADVANCE_RING();
1957}
1958
1959static void radeon_apply_surface_regs(int surf_index,
1960 drm_radeon_private_t *dev_priv)
1961{
1962 if (!dev_priv->mmio)
1963 return;
1964
1965 radeon_do_cp_idle(dev_priv);
1966
1967 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * surf_index,
1968 dev_priv->surfaces[surf_index].flags);
1969 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND + 16 * surf_index,
1970 dev_priv->surfaces[surf_index].lower);
1971 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND + 16 * surf_index,
1972 dev_priv->surfaces[surf_index].upper);
1973}
1974
1975/* Allocates a virtual surface
1976 * doesn't always allocate a real surface, will stretch an existing
1977 * surface when possible.
1978 *
1979 * Note that refcount can be at most 2, since during a free refcount=3
1980 * might mean we have to allocate a new surface which might not always
1981 * be available.
1982 * For example : we allocate three contiguous surfaces ABC. If B is
1983 * freed, we suddenly need two surfaces to store A and C, which might
1984 * not always be available.
1985 */
1986static int alloc_surface(drm_radeon_surface_alloc_t *new,
1987 drm_radeon_private_t *dev_priv,
1988 struct drm_file *file_priv)
1989{
1990 struct radeon_virt_surface *s;
1991 int i;
1992 int virt_surface_index;
1993 uint32_t new_upper, new_lower;
1994
1995 new_lower = new->address;
1996 new_upper = new_lower + new->size - 1;
1997
1998 /* sanity check */
1999 if ((new_lower >= new_upper) || (new->flags == 0) || (new->size == 0) ||
2000 ((new_upper & RADEON_SURF_ADDRESS_FIXED_MASK) !=
2001 RADEON_SURF_ADDRESS_FIXED_MASK)
2002 || ((new_lower & RADEON_SURF_ADDRESS_FIXED_MASK) != 0))
2003 return -1;
2004
2005 /* make sure there is no overlap with existing surfaces */
2006 for (i = 0; i < RADEON_MAX_SURFACES; i++) {
2007 if ((dev_priv->surfaces[i].refcount != 0) &&
2008 (((new_lower >= dev_priv->surfaces[i].lower) &&
2009 (new_lower < dev_priv->surfaces[i].upper)) ||
2010 ((new_lower < dev_priv->surfaces[i].lower) &&
2011 (new_upper > dev_priv->surfaces[i].lower)))) {
2012 return -1;
2013 }
2014 }
2015
2016 /* find a virtual surface */
2017 for (i = 0; i < 2 * RADEON_MAX_SURFACES; i++)
2018 if (dev_priv->virt_surfaces[i].file_priv == NULL)
2019 break;
2020 if (i == 2 * RADEON_MAX_SURFACES) {
2021 return -1;
2022 }
2023 virt_surface_index = i;
2024
2025 /* try to reuse an existing surface */
2026 for (i = 0; i < RADEON_MAX_SURFACES; i++) {
2027 /* extend before */
2028 if ((dev_priv->surfaces[i].refcount == 1) &&
2029 (new->flags == dev_priv->surfaces[i].flags) &&
2030 (new_upper + 1 == dev_priv->surfaces[i].lower)) {
2031 s = &(dev_priv->virt_surfaces[virt_surface_index]);
2032 s->surface_index = i;
2033 s->lower = new_lower;
2034 s->upper = new_upper;
2035 s->flags = new->flags;
2036 s->file_priv = file_priv;
2037 dev_priv->surfaces[i].refcount++;
2038 dev_priv->surfaces[i].lower = s->lower;
2039 radeon_apply_surface_regs(s->surface_index, dev_priv);
2040 return virt_surface_index;
2041 }
2042
2043 /* extend after */
2044 if ((dev_priv->surfaces[i].refcount == 1) &&
2045 (new->flags == dev_priv->surfaces[i].flags) &&
2046 (new_lower == dev_priv->surfaces[i].upper + 1)) {
2047 s = &(dev_priv->virt_surfaces[virt_surface_index]);
2048 s->surface_index = i;
2049 s->lower = new_lower;
2050 s->upper = new_upper;
2051 s->flags = new->flags;
2052 s->file_priv = file_priv;
2053 dev_priv->surfaces[i].refcount++;
2054 dev_priv->surfaces[i].upper = s->upper;
2055 radeon_apply_surface_regs(s->surface_index, dev_priv);
2056 return virt_surface_index;
2057 }
2058 }
2059
2060 /* okay, we need a new one */
2061 for (i = 0; i < RADEON_MAX_SURFACES; i++) {
2062 if (dev_priv->surfaces[i].refcount == 0) {
2063 s = &(dev_priv->virt_surfaces[virt_surface_index]);
2064 s->surface_index = i;
2065 s->lower = new_lower;
2066 s->upper = new_upper;
2067 s->flags = new->flags;
2068 s->file_priv = file_priv;
2069 dev_priv->surfaces[i].refcount = 1;
2070 dev_priv->surfaces[i].lower = s->lower;
2071 dev_priv->surfaces[i].upper = s->upper;
2072 dev_priv->surfaces[i].flags = s->flags;
2073 radeon_apply_surface_regs(s->surface_index, dev_priv);
2074 return virt_surface_index;
2075 }
2076 }
2077
2078 /* we didn't find anything */
2079 return -1;
2080}
2081
2082static int free_surface(struct drm_file *file_priv,
2083 drm_radeon_private_t * dev_priv,
2084 int lower)
2085{
2086 struct radeon_virt_surface *s;
2087 int i;
2088 /* find the virtual surface */
2089 for (i = 0; i < 2 * RADEON_MAX_SURFACES; i++) {
2090 s = &(dev_priv->virt_surfaces[i]);
2091 if (s->file_priv) {
2092 if ((lower == s->lower) && (file_priv == s->file_priv))
2093 {
2094 if (dev_priv->surfaces[s->surface_index].
2095 lower == s->lower)
2096 dev_priv->surfaces[s->surface_index].
2097 lower = s->upper;
2098
2099 if (dev_priv->surfaces[s->surface_index].
2100 upper == s->upper)
2101 dev_priv->surfaces[s->surface_index].
2102 upper = s->lower;
2103
2104 dev_priv->surfaces[s->surface_index].refcount--;
2105 if (dev_priv->surfaces[s->surface_index].
2106 refcount == 0)
2107 dev_priv->surfaces[s->surface_index].
2108 flags = 0;
2109 s->file_priv = NULL;
2110 radeon_apply_surface_regs(s->surface_index,
2111 dev_priv);
2112 return 0;
2113 }
2114 }
2115 }
2116 return 1;
2117}
2118
2119static void radeon_surfaces_release(struct drm_file *file_priv,
2120 drm_radeon_private_t * dev_priv)
2121{
2122 int i;
2123 for (i = 0; i < 2 * RADEON_MAX_SURFACES; i++) {
2124 if (dev_priv->virt_surfaces[i].file_priv == file_priv)
2125 free_surface(file_priv, dev_priv,
2126 dev_priv->virt_surfaces[i].lower);
2127 }
2128}
2129
2130/* ================================================================
2131 * IOCTL functions
2132 */
2133static int radeon_surface_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv)
2134{
2135 drm_radeon_private_t *dev_priv = dev->dev_private;
2136 drm_radeon_surface_alloc_t *alloc = data;
2137
2138 if (alloc_surface(alloc, dev_priv, file_priv) == -1)
2139 return -EINVAL;
2140 else
2141 return 0;
2142}
2143
2144static int radeon_surface_free(struct drm_device *dev, void *data, struct drm_file *file_priv)
2145{
2146 drm_radeon_private_t *dev_priv = dev->dev_private;
2147 drm_radeon_surface_free_t *memfree = data;
2148
2149 if (free_surface(file_priv, dev_priv, memfree->address))
2150 return -EINVAL;
2151 else
2152 return 0;
2153}
2154
2155static int radeon_cp_clear(struct drm_device *dev, void *data, struct drm_file *file_priv)
2156{
2157 drm_radeon_private_t *dev_priv = dev->dev_private;
2158 struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv;
2159 drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv;
2160 drm_radeon_clear_t *clear = data;
2161 drm_radeon_clear_rect_t depth_boxes[RADEON_NR_SAREA_CLIPRECTS];
2162 DRM_DEBUG("\n");
2163
2164 LOCK_TEST_WITH_RETURN(dev, file_priv);
2165
2166 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2167
2168 if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS)
2169 sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS;
2170
2171 if (copy_from_user(&depth_boxes, clear->depth_boxes,
2172 sarea_priv->nbox * sizeof(depth_boxes[0])))
2173 return -EFAULT;
2174
2175 radeon_cp_dispatch_clear(dev, file_priv->master, clear, depth_boxes);
2176
2177 COMMIT_RING();
2178 return 0;
2179}
2180
2181/* Not sure why this isn't set all the time:
2182 */
2183static int radeon_do_init_pageflip(struct drm_device *dev, struct drm_master *master)
2184{
2185 drm_radeon_private_t *dev_priv = dev->dev_private;
2186 struct drm_radeon_master_private *master_priv = master->driver_priv;
2187 RING_LOCALS;
2188
2189 DRM_DEBUG("\n");
2190
2191 BEGIN_RING(6);
2192 RADEON_WAIT_UNTIL_3D_IDLE();
2193 OUT_RING(CP_PACKET0(RADEON_CRTC_OFFSET_CNTL, 0));
2194 OUT_RING(RADEON_READ(RADEON_CRTC_OFFSET_CNTL) |
2195 RADEON_CRTC_OFFSET_FLIP_CNTL);
2196 OUT_RING(CP_PACKET0(RADEON_CRTC2_OFFSET_CNTL, 0));
2197 OUT_RING(RADEON_READ(RADEON_CRTC2_OFFSET_CNTL) |
2198 RADEON_CRTC_OFFSET_FLIP_CNTL);
2199 ADVANCE_RING();
2200
2201 dev_priv->page_flipping = 1;
2202
2203 if (master_priv->sarea_priv->pfCurrentPage != 1)
2204 master_priv->sarea_priv->pfCurrentPage = 0;
2205
2206 return 0;
2207}
2208
2209/* Swapping and flipping are different operations, need different ioctls.
2210 * They can & should be intermixed to support multiple 3d windows.
2211 */
2212static int radeon_cp_flip(struct drm_device *dev, void *data, struct drm_file *file_priv)
2213{
2214 drm_radeon_private_t *dev_priv = dev->dev_private;
2215 DRM_DEBUG("\n");
2216
2217 LOCK_TEST_WITH_RETURN(dev, file_priv);
2218
2219 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2220
2221 if (!dev_priv->page_flipping)
2222 radeon_do_init_pageflip(dev, file_priv->master);
2223
2224 radeon_cp_dispatch_flip(dev, file_priv->master);
2225
2226 COMMIT_RING();
2227 return 0;
2228}
2229
2230static int radeon_cp_swap(struct drm_device *dev, void *data, struct drm_file *file_priv)
2231{
2232 drm_radeon_private_t *dev_priv = dev->dev_private;
2233 struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv;
2234 drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv;
2235
2236 DRM_DEBUG("\n");
2237
2238 LOCK_TEST_WITH_RETURN(dev, file_priv);
2239
2240 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2241
2242 if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS)
2243 sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS;
2244
2245 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
2246 r600_cp_dispatch_swap(dev, file_priv);
2247 else
2248 radeon_cp_dispatch_swap(dev, file_priv->master);
2249 sarea_priv->ctx_owner = 0;
2250
2251 COMMIT_RING();
2252 return 0;
2253}
2254
2255static int radeon_cp_vertex(struct drm_device *dev, void *data, struct drm_file *file_priv)
2256{
2257 drm_radeon_private_t *dev_priv = dev->dev_private;
2258 struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv;
2259 drm_radeon_sarea_t *sarea_priv;
2260 struct drm_device_dma *dma = dev->dma;
2261 struct drm_buf *buf;
2262 drm_radeon_vertex_t *vertex = data;
2263 drm_radeon_tcl_prim_t prim;
2264
2265 LOCK_TEST_WITH_RETURN(dev, file_priv);
2266
2267 sarea_priv = master_priv->sarea_priv;
2268
2269 DRM_DEBUG("pid=%d index=%d count=%d discard=%d\n",
2270 DRM_CURRENTPID, vertex->idx, vertex->count, vertex->discard);
2271
2272 if (vertex->idx < 0 || vertex->idx >= dma->buf_count) {
2273 DRM_ERROR("buffer index %d (of %d max)\n",
2274 vertex->idx, dma->buf_count - 1);
2275 return -EINVAL;
2276 }
2277 if (vertex->prim < 0 || vertex->prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST) {
2278 DRM_ERROR("buffer prim %d\n", vertex->prim);
2279 return -EINVAL;
2280 }
2281
2282 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2283 VB_AGE_TEST_WITH_RETURN(dev_priv);
2284
2285 buf = dma->buflist[vertex->idx];
2286
2287 if (buf->file_priv != file_priv) {
2288 DRM_ERROR("process %d using buffer owned by %p\n",
2289 DRM_CURRENTPID, buf->file_priv);
2290 return -EINVAL;
2291 }
2292 if (buf->pending) {
2293 DRM_ERROR("sending pending buffer %d\n", vertex->idx);
2294 return -EINVAL;
2295 }
2296
2297 /* Build up a prim_t record:
2298 */
2299 if (vertex->count) {
2300 buf->used = vertex->count; /* not used? */
2301
2302 if (sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS) {
2303 if (radeon_emit_state(dev_priv, file_priv,
2304 &sarea_priv->context_state,
2305 sarea_priv->tex_state,
2306 sarea_priv->dirty)) {
2307 DRM_ERROR("radeon_emit_state failed\n");
2308 return -EINVAL;
2309 }
2310
2311 sarea_priv->dirty &= ~(RADEON_UPLOAD_TEX0IMAGES |
2312 RADEON_UPLOAD_TEX1IMAGES |
2313 RADEON_UPLOAD_TEX2IMAGES |
2314 RADEON_REQUIRE_QUIESCENCE);
2315 }
2316
2317 prim.start = 0;
2318 prim.finish = vertex->count; /* unused */
2319 prim.prim = vertex->prim;
2320 prim.numverts = vertex->count;
2321 prim.vc_format = sarea_priv->vc_format;
2322
2323 radeon_cp_dispatch_vertex(dev, file_priv, buf, &prim);
2324 }
2325
2326 if (vertex->discard) {
2327 radeon_cp_discard_buffer(dev, file_priv->master, buf);
2328 }
2329
2330 COMMIT_RING();
2331 return 0;
2332}
2333
2334static int radeon_cp_indices(struct drm_device *dev, void *data, struct drm_file *file_priv)
2335{
2336 drm_radeon_private_t *dev_priv = dev->dev_private;
2337 struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv;
2338 drm_radeon_sarea_t *sarea_priv;
2339 struct drm_device_dma *dma = dev->dma;
2340 struct drm_buf *buf;
2341 drm_radeon_indices_t *elts = data;
2342 drm_radeon_tcl_prim_t prim;
2343 int count;
2344
2345 LOCK_TEST_WITH_RETURN(dev, file_priv);
2346
2347 sarea_priv = master_priv->sarea_priv;
2348
2349 DRM_DEBUG("pid=%d index=%d start=%d end=%d discard=%d\n",
2350 DRM_CURRENTPID, elts->idx, elts->start, elts->end,
2351 elts->discard);
2352
2353 if (elts->idx < 0 || elts->idx >= dma->buf_count) {
2354 DRM_ERROR("buffer index %d (of %d max)\n",
2355 elts->idx, dma->buf_count - 1);
2356 return -EINVAL;
2357 }
2358 if (elts->prim < 0 || elts->prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST) {
2359 DRM_ERROR("buffer prim %d\n", elts->prim);
2360 return -EINVAL;
2361 }
2362
2363 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2364 VB_AGE_TEST_WITH_RETURN(dev_priv);
2365
2366 buf = dma->buflist[elts->idx];
2367
2368 if (buf->file_priv != file_priv) {
2369 DRM_ERROR("process %d using buffer owned by %p\n",
2370 DRM_CURRENTPID, buf->file_priv);
2371 return -EINVAL;
2372 }
2373 if (buf->pending) {
2374 DRM_ERROR("sending pending buffer %d\n", elts->idx);
2375 return -EINVAL;
2376 }
2377
2378 count = (elts->end - elts->start) / sizeof(u16);
2379 elts->start -= RADEON_INDEX_PRIM_OFFSET;
2380
2381 if (elts->start & 0x7) {
2382 DRM_ERROR("misaligned buffer 0x%x\n", elts->start);
2383 return -EINVAL;
2384 }
2385 if (elts->start < buf->used) {
2386 DRM_ERROR("no header 0x%x - 0x%x\n", elts->start, buf->used);
2387 return -EINVAL;
2388 }
2389
2390 buf->used = elts->end;
2391
2392 if (sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS) {
2393 if (radeon_emit_state(dev_priv, file_priv,
2394 &sarea_priv->context_state,
2395 sarea_priv->tex_state,
2396 sarea_priv->dirty)) {
2397 DRM_ERROR("radeon_emit_state failed\n");
2398 return -EINVAL;
2399 }
2400
2401 sarea_priv->dirty &= ~(RADEON_UPLOAD_TEX0IMAGES |
2402 RADEON_UPLOAD_TEX1IMAGES |
2403 RADEON_UPLOAD_TEX2IMAGES |
2404 RADEON_REQUIRE_QUIESCENCE);
2405 }
2406
2407 /* Build up a prim_t record:
2408 */
2409 prim.start = elts->start;
2410 prim.finish = elts->end;
2411 prim.prim = elts->prim;
2412 prim.offset = 0; /* offset from start of dma buffers */
2413 prim.numverts = RADEON_MAX_VB_VERTS; /* duh */
2414 prim.vc_format = sarea_priv->vc_format;
2415
2416 radeon_cp_dispatch_indices(dev, file_priv->master, buf, &prim);
2417 if (elts->discard) {
2418 radeon_cp_discard_buffer(dev, file_priv->master, buf);
2419 }
2420
2421 COMMIT_RING();
2422 return 0;
2423}
2424
2425static int radeon_cp_texture(struct drm_device *dev, void *data, struct drm_file *file_priv)
2426{
2427 drm_radeon_private_t *dev_priv = dev->dev_private;
2428 drm_radeon_texture_t *tex = data;
2429 drm_radeon_tex_image_t image;
2430 int ret;
2431
2432 LOCK_TEST_WITH_RETURN(dev, file_priv);
2433
2434 if (tex->image == NULL) {
2435 DRM_ERROR("null texture image!\n");
2436 return -EINVAL;
2437 }
2438
2439 if (copy_from_user(&image,
2440 (drm_radeon_tex_image_t __user *) tex->image,
2441 sizeof(image)))
2442 return -EFAULT;
2443
2444 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2445 VB_AGE_TEST_WITH_RETURN(dev_priv);
2446
2447 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
2448 ret = r600_cp_dispatch_texture(dev, file_priv, tex, &image);
2449 else
2450 ret = radeon_cp_dispatch_texture(dev, file_priv, tex, &image);
2451
2452 return ret;
2453}
2454
2455static int radeon_cp_stipple(struct drm_device *dev, void *data, struct drm_file *file_priv)
2456{
2457 drm_radeon_private_t *dev_priv = dev->dev_private;
2458 drm_radeon_stipple_t *stipple = data;
2459 u32 mask[32];
2460
2461 LOCK_TEST_WITH_RETURN(dev, file_priv);
2462
2463 if (copy_from_user(&mask, stipple->mask, 32 * sizeof(u32)))
2464 return -EFAULT;
2465
2466 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2467
2468 radeon_cp_dispatch_stipple(dev, mask);
2469
2470 COMMIT_RING();
2471 return 0;
2472}
2473
2474static int radeon_cp_indirect(struct drm_device *dev, void *data, struct drm_file *file_priv)
2475{
2476 drm_radeon_private_t *dev_priv = dev->dev_private;
2477 struct drm_device_dma *dma = dev->dma;
2478 struct drm_buf *buf;
2479 drm_radeon_indirect_t *indirect = data;
2480 RING_LOCALS;
2481
2482 LOCK_TEST_WITH_RETURN(dev, file_priv);
2483
2484 DRM_DEBUG("idx=%d s=%d e=%d d=%d\n",
2485 indirect->idx, indirect->start, indirect->end,
2486 indirect->discard);
2487
2488 if (indirect->idx < 0 || indirect->idx >= dma->buf_count) {
2489 DRM_ERROR("buffer index %d (of %d max)\n",
2490 indirect->idx, dma->buf_count - 1);
2491 return -EINVAL;
2492 }
2493
2494 buf = dma->buflist[indirect->idx];
2495
2496 if (buf->file_priv != file_priv) {
2497 DRM_ERROR("process %d using buffer owned by %p\n",
2498 DRM_CURRENTPID, buf->file_priv);
2499 return -EINVAL;
2500 }
2501 if (buf->pending) {
2502 DRM_ERROR("sending pending buffer %d\n", indirect->idx);
2503 return -EINVAL;
2504 }
2505
2506 if (indirect->start < buf->used) {
2507 DRM_ERROR("reusing indirect: start=0x%x actual=0x%x\n",
2508 indirect->start, buf->used);
2509 return -EINVAL;
2510 }
2511
2512 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2513 VB_AGE_TEST_WITH_RETURN(dev_priv);
2514
2515 buf->used = indirect->end;
2516
2517 /* Dispatch the indirect buffer full of commands from the
2518 * X server. This is insecure and is thus only available to
2519 * privileged clients.
2520 */
2521 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
2522 r600_cp_dispatch_indirect(dev, buf, indirect->start, indirect->end);
2523 else {
2524 /* Wait for the 3D stream to idle before the indirect buffer
2525 * containing 2D acceleration commands is processed.
2526 */
2527 BEGIN_RING(2);
2528 RADEON_WAIT_UNTIL_3D_IDLE();
2529 ADVANCE_RING();
2530 radeon_cp_dispatch_indirect(dev, buf, indirect->start, indirect->end);
2531 }
2532
2533 if (indirect->discard) {
2534 radeon_cp_discard_buffer(dev, file_priv->master, buf);
2535 }
2536
2537 COMMIT_RING();
2538 return 0;
2539}
2540
2541static int radeon_cp_vertex2(struct drm_device *dev, void *data, struct drm_file *file_priv)
2542{
2543 drm_radeon_private_t *dev_priv = dev->dev_private;
2544 struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv;
2545 drm_radeon_sarea_t *sarea_priv;
2546 struct drm_device_dma *dma = dev->dma;
2547 struct drm_buf *buf;
2548 drm_radeon_vertex2_t *vertex = data;
2549 int i;
2550 unsigned char laststate;
2551
2552 LOCK_TEST_WITH_RETURN(dev, file_priv);
2553
2554 sarea_priv = master_priv->sarea_priv;
2555
2556 DRM_DEBUG("pid=%d index=%d discard=%d\n",
2557 DRM_CURRENTPID, vertex->idx, vertex->discard);
2558
2559 if (vertex->idx < 0 || vertex->idx >= dma->buf_count) {
2560 DRM_ERROR("buffer index %d (of %d max)\n",
2561 vertex->idx, dma->buf_count - 1);
2562 return -EINVAL;
2563 }
2564
2565 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2566 VB_AGE_TEST_WITH_RETURN(dev_priv);
2567
2568 buf = dma->buflist[vertex->idx];
2569
2570 if (buf->file_priv != file_priv) {
2571 DRM_ERROR("process %d using buffer owned by %p\n",
2572 DRM_CURRENTPID, buf->file_priv);
2573 return -EINVAL;
2574 }
2575
2576 if (buf->pending) {
2577 DRM_ERROR("sending pending buffer %d\n", vertex->idx);
2578 return -EINVAL;
2579 }
2580
2581 if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS)
2582 return -EINVAL;
2583
2584 for (laststate = 0xff, i = 0; i < vertex->nr_prims; i++) {
2585 drm_radeon_prim_t prim;
2586 drm_radeon_tcl_prim_t tclprim;
2587
2588 if (copy_from_user(&prim, &vertex->prim[i], sizeof(prim)))
2589 return -EFAULT;
2590
2591 if (prim.stateidx != laststate) {
2592 drm_radeon_state_t state;
2593
2594 if (copy_from_user(&state,
2595 &vertex->state[prim.stateidx],
2596 sizeof(state)))
2597 return -EFAULT;
2598
2599 if (radeon_emit_state2(dev_priv, file_priv, &state)) {
2600 DRM_ERROR("radeon_emit_state2 failed\n");
2601 return -EINVAL;
2602 }
2603
2604 laststate = prim.stateidx;
2605 }
2606
2607 tclprim.start = prim.start;
2608 tclprim.finish = prim.finish;
2609 tclprim.prim = prim.prim;
2610 tclprim.vc_format = prim.vc_format;
2611
2612 if (prim.prim & RADEON_PRIM_WALK_IND) {
2613 tclprim.offset = prim.numverts * 64;
2614 tclprim.numverts = RADEON_MAX_VB_VERTS; /* duh */
2615
2616 radeon_cp_dispatch_indices(dev, file_priv->master, buf, &tclprim);
2617 } else {
2618 tclprim.numverts = prim.numverts;
2619 tclprim.offset = 0; /* not used */
2620
2621 radeon_cp_dispatch_vertex(dev, file_priv, buf, &tclprim);
2622 }
2623
2624 if (sarea_priv->nbox == 1)
2625 sarea_priv->nbox = 0;
2626 }
2627
2628 if (vertex->discard) {
2629 radeon_cp_discard_buffer(dev, file_priv->master, buf);
2630 }
2631
2632 COMMIT_RING();
2633 return 0;
2634}
2635
2636static int radeon_emit_packets(drm_radeon_private_t * dev_priv,
2637 struct drm_file *file_priv,
2638 drm_radeon_cmd_header_t header,
2639 drm_radeon_kcmd_buffer_t *cmdbuf)
2640{
2641 int id = (int)header.packet.packet_id;
2642 int sz, reg;
2643 RING_LOCALS;
2644
2645 if (id >= RADEON_MAX_STATE_PACKETS)
2646 return -EINVAL;
2647
2648 sz = packet[id].len;
2649 reg = packet[id].start;
2650
2651 if (sz * sizeof(u32) > drm_buffer_unprocessed(cmdbuf->buffer)) {
2652 DRM_ERROR("Packet size provided larger than data provided\n");
2653 return -EINVAL;
2654 }
2655
2656 if (radeon_check_and_fixup_packets(dev_priv, file_priv, id,
2657 cmdbuf->buffer)) {
2658 DRM_ERROR("Packet verification failed\n");
2659 return -EINVAL;
2660 }
2661
2662 BEGIN_RING(sz + 1);
2663 OUT_RING(CP_PACKET0(reg, (sz - 1)));
2664 OUT_RING_DRM_BUFFER(cmdbuf->buffer, sz);
2665 ADVANCE_RING();
2666
2667 return 0;
2668}
2669
2670static __inline__ int radeon_emit_scalars(drm_radeon_private_t *dev_priv,
2671 drm_radeon_cmd_header_t header,
2672 drm_radeon_kcmd_buffer_t *cmdbuf)
2673{
2674 int sz = header.scalars.count;
2675 int start = header.scalars.offset;
2676 int stride = header.scalars.stride;
2677 RING_LOCALS;
2678
2679 BEGIN_RING(3 + sz);
2680 OUT_RING(CP_PACKET0(RADEON_SE_TCL_SCALAR_INDX_REG, 0));
2681 OUT_RING(start | (stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT));
2682 OUT_RING(CP_PACKET0_TABLE(RADEON_SE_TCL_SCALAR_DATA_REG, sz - 1));
2683 OUT_RING_DRM_BUFFER(cmdbuf->buffer, sz);
2684 ADVANCE_RING();
2685 return 0;
2686}
2687
2688/* God this is ugly
2689 */
2690static __inline__ int radeon_emit_scalars2(drm_radeon_private_t *dev_priv,
2691 drm_radeon_cmd_header_t header,
2692 drm_radeon_kcmd_buffer_t *cmdbuf)
2693{
2694 int sz = header.scalars.count;
2695 int start = ((unsigned int)header.scalars.offset) + 0x100;
2696 int stride = header.scalars.stride;
2697 RING_LOCALS;
2698
2699 BEGIN_RING(3 + sz);
2700 OUT_RING(CP_PACKET0(RADEON_SE_TCL_SCALAR_INDX_REG, 0));
2701 OUT_RING(start | (stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT));
2702 OUT_RING(CP_PACKET0_TABLE(RADEON_SE_TCL_SCALAR_DATA_REG, sz - 1));
2703 OUT_RING_DRM_BUFFER(cmdbuf->buffer, sz);
2704 ADVANCE_RING();
2705 return 0;
2706}
2707
2708static __inline__ int radeon_emit_vectors(drm_radeon_private_t *dev_priv,
2709 drm_radeon_cmd_header_t header,
2710 drm_radeon_kcmd_buffer_t *cmdbuf)
2711{
2712 int sz = header.vectors.count;
2713 int start = header.vectors.offset;
2714 int stride = header.vectors.stride;
2715 RING_LOCALS;
2716
2717 BEGIN_RING(5 + sz);
2718 OUT_RING_REG(RADEON_SE_TCL_STATE_FLUSH, 0);
2719 OUT_RING(CP_PACKET0(RADEON_SE_TCL_VECTOR_INDX_REG, 0));
2720 OUT_RING(start | (stride << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT));
2721 OUT_RING(CP_PACKET0_TABLE(RADEON_SE_TCL_VECTOR_DATA_REG, (sz - 1)));
2722 OUT_RING_DRM_BUFFER(cmdbuf->buffer, sz);
2723 ADVANCE_RING();
2724
2725 return 0;
2726}
2727
2728static __inline__ int radeon_emit_veclinear(drm_radeon_private_t *dev_priv,
2729 drm_radeon_cmd_header_t header,
2730 drm_radeon_kcmd_buffer_t *cmdbuf)
2731{
2732 int sz = header.veclinear.count * 4;
2733 int start = header.veclinear.addr_lo | (header.veclinear.addr_hi << 8);
2734 RING_LOCALS;
2735
2736 if (!sz)
2737 return 0;
2738 if (sz * 4 > drm_buffer_unprocessed(cmdbuf->buffer))
2739 return -EINVAL;
2740
2741 BEGIN_RING(5 + sz);
2742 OUT_RING_REG(RADEON_SE_TCL_STATE_FLUSH, 0);
2743 OUT_RING(CP_PACKET0(RADEON_SE_TCL_VECTOR_INDX_REG, 0));
2744 OUT_RING(start | (1 << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT));
2745 OUT_RING(CP_PACKET0_TABLE(RADEON_SE_TCL_VECTOR_DATA_REG, (sz - 1)));
2746 OUT_RING_DRM_BUFFER(cmdbuf->buffer, sz);
2747 ADVANCE_RING();
2748
2749 return 0;
2750}
2751
2752static int radeon_emit_packet3(struct drm_device * dev,
2753 struct drm_file *file_priv,
2754 drm_radeon_kcmd_buffer_t *cmdbuf)
2755{
2756 drm_radeon_private_t *dev_priv = dev->dev_private;
2757 unsigned int cmdsz;
2758 int ret;
2759 RING_LOCALS;
2760
2761 DRM_DEBUG("\n");
2762
2763 if ((ret = radeon_check_and_fixup_packet3(dev_priv, file_priv,
2764 cmdbuf, &cmdsz))) {
2765 DRM_ERROR("Packet verification failed\n");
2766 return ret;
2767 }
2768
2769 BEGIN_RING(cmdsz);
2770 OUT_RING_DRM_BUFFER(cmdbuf->buffer, cmdsz);
2771 ADVANCE_RING();
2772
2773 return 0;
2774}
2775
2776static int radeon_emit_packet3_cliprect(struct drm_device *dev,
2777 struct drm_file *file_priv,
2778 drm_radeon_kcmd_buffer_t *cmdbuf,
2779 int orig_nbox)
2780{
2781 drm_radeon_private_t *dev_priv = dev->dev_private;
2782 struct drm_clip_rect box;
2783 unsigned int cmdsz;
2784 int ret;
2785 struct drm_clip_rect __user *boxes = cmdbuf->boxes;
2786 int i = 0;
2787 RING_LOCALS;
2788
2789 DRM_DEBUG("\n");
2790
2791 if ((ret = radeon_check_and_fixup_packet3(dev_priv, file_priv,
2792 cmdbuf, &cmdsz))) {
2793 DRM_ERROR("Packet verification failed\n");
2794 return ret;
2795 }
2796
2797 if (!orig_nbox)
2798 goto out;
2799
2800 do {
2801 if (i < cmdbuf->nbox) {
2802 if (copy_from_user(&box, &boxes[i], sizeof(box)))
2803 return -EFAULT;
2804 /* FIXME The second and subsequent times round
2805 * this loop, send a WAIT_UNTIL_3D_IDLE before
2806 * calling emit_clip_rect(). This fixes a
2807 * lockup on fast machines when sending
2808 * several cliprects with a cmdbuf, as when
2809 * waving a 2D window over a 3D
2810 * window. Something in the commands from user
2811 * space seems to hang the card when they're
2812 * sent several times in a row. That would be
2813 * the correct place to fix it but this works
2814 * around it until I can figure that out - Tim
2815 * Smith */
2816 if (i) {
2817 BEGIN_RING(2);
2818 RADEON_WAIT_UNTIL_3D_IDLE();
2819 ADVANCE_RING();
2820 }
2821 radeon_emit_clip_rect(dev_priv, &box);
2822 }
2823
2824 BEGIN_RING(cmdsz);
2825 OUT_RING_DRM_BUFFER(cmdbuf->buffer, cmdsz);
2826 ADVANCE_RING();
2827
2828 } while (++i < cmdbuf->nbox);
2829 if (cmdbuf->nbox == 1)
2830 cmdbuf->nbox = 0;
2831
2832 return 0;
2833 out:
2834 drm_buffer_advance(cmdbuf->buffer, cmdsz * 4);
2835 return 0;
2836}
2837
2838static int radeon_emit_wait(struct drm_device * dev, int flags)
2839{
2840 drm_radeon_private_t *dev_priv = dev->dev_private;
2841 RING_LOCALS;
2842
2843 DRM_DEBUG("%x\n", flags);
2844 switch (flags) {
2845 case RADEON_WAIT_2D:
2846 BEGIN_RING(2);
2847 RADEON_WAIT_UNTIL_2D_IDLE();
2848 ADVANCE_RING();
2849 break;
2850 case RADEON_WAIT_3D:
2851 BEGIN_RING(2);
2852 RADEON_WAIT_UNTIL_3D_IDLE();
2853 ADVANCE_RING();
2854 break;
2855 case RADEON_WAIT_2D | RADEON_WAIT_3D:
2856 BEGIN_RING(2);
2857 RADEON_WAIT_UNTIL_IDLE();
2858 ADVANCE_RING();
2859 break;
2860 default:
2861 return -EINVAL;
2862 }
2863
2864 return 0;
2865}
2866
2867static int radeon_cp_cmdbuf(struct drm_device *dev, void *data,
2868 struct drm_file *file_priv)
2869{
2870 drm_radeon_private_t *dev_priv = dev->dev_private;
2871 struct drm_device_dma *dma = dev->dma;
2872 struct drm_buf *buf = NULL;
2873 drm_radeon_cmd_header_t stack_header;
2874 int idx;
2875 drm_radeon_kcmd_buffer_t *cmdbuf = data;
2876 int orig_nbox;
2877
2878 LOCK_TEST_WITH_RETURN(dev, file_priv);
2879
2880 RING_SPACE_TEST_WITH_RETURN(dev_priv);
2881 VB_AGE_TEST_WITH_RETURN(dev_priv);
2882
2883 if (cmdbuf->bufsz > 64 * 1024 || cmdbuf->bufsz < 0) {
2884 return -EINVAL;
2885 }
2886
2887 /* Allocate an in-kernel area and copy in the cmdbuf. Do this to avoid
2888 * races between checking values and using those values in other code,
2889 * and simply to avoid a lot of function calls to copy in data.
2890 */
2891 if (cmdbuf->bufsz != 0) {
2892 int rv;
2893 void __user *buffer = cmdbuf->buffer;
2894 rv = drm_buffer_alloc(&cmdbuf->buffer, cmdbuf->bufsz);
2895 if (rv)
2896 return rv;
2897 rv = drm_buffer_copy_from_user(cmdbuf->buffer, buffer,
2898 cmdbuf->bufsz);
2899 if (rv) {
2900 drm_buffer_free(cmdbuf->buffer);
2901 return rv;
2902 }
2903 } else
2904 goto done;
2905
2906 orig_nbox = cmdbuf->nbox;
2907
2908 if (dev_priv->microcode_version == UCODE_R300) {
2909 int temp;
2910 temp = r300_do_cp_cmdbuf(dev, file_priv, cmdbuf);
2911
2912 drm_buffer_free(cmdbuf->buffer);
2913
2914 return temp;
2915 }
2916
2917 /* microcode_version != r300 */
2918 while (drm_buffer_unprocessed(cmdbuf->buffer) >= sizeof(stack_header)) {
2919
2920 drm_radeon_cmd_header_t *header;
2921 header = drm_buffer_read_object(cmdbuf->buffer,
2922 sizeof(stack_header), &stack_header);
2923
2924 switch (header->header.cmd_type) {
2925 case RADEON_CMD_PACKET:
2926 DRM_DEBUG("RADEON_CMD_PACKET\n");
2927 if (radeon_emit_packets
2928 (dev_priv, file_priv, *header, cmdbuf)) {
2929 DRM_ERROR("radeon_emit_packets failed\n");
2930 goto err;
2931 }
2932 break;
2933
2934 case RADEON_CMD_SCALARS:
2935 DRM_DEBUG("RADEON_CMD_SCALARS\n");
2936 if (radeon_emit_scalars(dev_priv, *header, cmdbuf)) {
2937 DRM_ERROR("radeon_emit_scalars failed\n");
2938 goto err;
2939 }
2940 break;
2941
2942 case RADEON_CMD_VECTORS:
2943 DRM_DEBUG("RADEON_CMD_VECTORS\n");
2944 if (radeon_emit_vectors(dev_priv, *header, cmdbuf)) {
2945 DRM_ERROR("radeon_emit_vectors failed\n");
2946 goto err;
2947 }
2948 break;
2949
2950 case RADEON_CMD_DMA_DISCARD:
2951 DRM_DEBUG("RADEON_CMD_DMA_DISCARD\n");
2952 idx = header->dma.buf_idx;
2953 if (idx < 0 || idx >= dma->buf_count) {
2954 DRM_ERROR("buffer index %d (of %d max)\n",
2955 idx, dma->buf_count - 1);
2956 goto err;
2957 }
2958
2959 buf = dma->buflist[idx];
2960 if (buf->file_priv != file_priv || buf->pending) {
2961 DRM_ERROR("bad buffer %p %p %d\n",
2962 buf->file_priv, file_priv,
2963 buf->pending);
2964 goto err;
2965 }
2966
2967 radeon_cp_discard_buffer(dev, file_priv->master, buf);
2968 break;
2969
2970 case RADEON_CMD_PACKET3:
2971 DRM_DEBUG("RADEON_CMD_PACKET3\n");
2972 if (radeon_emit_packet3(dev, file_priv, cmdbuf)) {
2973 DRM_ERROR("radeon_emit_packet3 failed\n");
2974 goto err;
2975 }
2976 break;
2977
2978 case RADEON_CMD_PACKET3_CLIP:
2979 DRM_DEBUG("RADEON_CMD_PACKET3_CLIP\n");
2980 if (radeon_emit_packet3_cliprect
2981 (dev, file_priv, cmdbuf, orig_nbox)) {
2982 DRM_ERROR("radeon_emit_packet3_clip failed\n");
2983 goto err;
2984 }
2985 break;
2986
2987 case RADEON_CMD_SCALARS2:
2988 DRM_DEBUG("RADEON_CMD_SCALARS2\n");
2989 if (radeon_emit_scalars2(dev_priv, *header, cmdbuf)) {
2990 DRM_ERROR("radeon_emit_scalars2 failed\n");
2991 goto err;
2992 }
2993 break;
2994
2995 case RADEON_CMD_WAIT:
2996 DRM_DEBUG("RADEON_CMD_WAIT\n");
2997 if (radeon_emit_wait(dev, header->wait.flags)) {
2998 DRM_ERROR("radeon_emit_wait failed\n");
2999 goto err;
3000 }
3001 break;
3002 case RADEON_CMD_VECLINEAR:
3003 DRM_DEBUG("RADEON_CMD_VECLINEAR\n");
3004 if (radeon_emit_veclinear(dev_priv, *header, cmdbuf)) {
3005 DRM_ERROR("radeon_emit_veclinear failed\n");
3006 goto err;
3007 }
3008 break;
3009
3010 default:
3011 DRM_ERROR("bad cmd_type %d at byte %d\n",
3012 header->header.cmd_type,
3013 cmdbuf->buffer->iterator);
3014 goto err;
3015 }
3016 }
3017
3018 drm_buffer_free(cmdbuf->buffer);
3019
3020 done:
3021 DRM_DEBUG("DONE\n");
3022 COMMIT_RING();
3023 return 0;
3024
3025 err:
3026 drm_buffer_free(cmdbuf->buffer);
3027 return -EINVAL;
3028}
3029
3030static int radeon_cp_getparam(struct drm_device *dev, void *data, struct drm_file *file_priv)
3031{
3032 drm_radeon_private_t *dev_priv = dev->dev_private;
3033 drm_radeon_getparam_t *param = data;
3034 int value;
3035
3036 DRM_DEBUG("pid=%d\n", DRM_CURRENTPID);
3037
3038 switch (param->param) {
3039 case RADEON_PARAM_GART_BUFFER_OFFSET:
3040 value = dev_priv->gart_buffers_offset;
3041 break;
3042 case RADEON_PARAM_LAST_FRAME:
3043 dev_priv->stats.last_frame_reads++;
3044 value = GET_SCRATCH(dev_priv, 0);
3045 break;
3046 case RADEON_PARAM_LAST_DISPATCH:
3047 value = GET_SCRATCH(dev_priv, 1);
3048 break;
3049 case RADEON_PARAM_LAST_CLEAR:
3050 dev_priv->stats.last_clear_reads++;
3051 value = GET_SCRATCH(dev_priv, 2);
3052 break;
3053 case RADEON_PARAM_IRQ_NR:
3054 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
3055 value = 0;
3056 else
3057 value = dev->pdev->irq;
3058 break;
3059 case RADEON_PARAM_GART_BASE:
3060 value = dev_priv->gart_vm_start;
3061 break;
3062 case RADEON_PARAM_REGISTER_HANDLE:
3063 value = dev_priv->mmio->offset;
3064 break;
3065 case RADEON_PARAM_STATUS_HANDLE:
3066 value = dev_priv->ring_rptr_offset;
3067 break;
3068#if BITS_PER_LONG == 32
3069 /*
3070 * This ioctl() doesn't work on 64-bit platforms because hw_lock is a
3071 * pointer which can't fit into an int-sized variable. According to
3072 * Michel Dänzer, the ioctl() is only used on embedded platforms, so
3073 * not supporting it shouldn't be a problem. If the same functionality
3074 * is needed on 64-bit platforms, a new ioctl() would have to be added,
3075 * so backwards-compatibility for the embedded platforms can be
3076 * maintained. --davidm 4-Feb-2004.
3077 */
3078 case RADEON_PARAM_SAREA_HANDLE:
3079 /* The lock is the first dword in the sarea. */
3080 /* no users of this parameter */
3081 break;
3082#endif
3083 case RADEON_PARAM_GART_TEX_HANDLE:
3084 value = dev_priv->gart_textures_offset;
3085 break;
3086 case RADEON_PARAM_SCRATCH_OFFSET:
3087 if (!dev_priv->writeback_works)
3088 return -EINVAL;
3089 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
3090 value = R600_SCRATCH_REG_OFFSET;
3091 else
3092 value = RADEON_SCRATCH_REG_OFFSET;
3093 break;
3094 case RADEON_PARAM_CARD_TYPE:
3095 if (dev_priv->flags & RADEON_IS_PCIE)
3096 value = RADEON_CARD_PCIE;
3097 else if (dev_priv->flags & RADEON_IS_AGP)
3098 value = RADEON_CARD_AGP;
3099 else
3100 value = RADEON_CARD_PCI;
3101 break;
3102 case RADEON_PARAM_VBLANK_CRTC:
3103 value = radeon_vblank_crtc_get(dev);
3104 break;
3105 case RADEON_PARAM_FB_LOCATION:
3106 value = radeon_read_fb_location(dev_priv);
3107 break;
3108 case RADEON_PARAM_NUM_GB_PIPES:
3109 value = dev_priv->num_gb_pipes;
3110 break;
3111 case RADEON_PARAM_NUM_Z_PIPES:
3112 value = dev_priv->num_z_pipes;
3113 break;
3114 default:
3115 DRM_DEBUG("Invalid parameter %d\n", param->param);
3116 return -EINVAL;
3117 }
3118
3119 if (copy_to_user(param->value, &value, sizeof(int))) {
3120 DRM_ERROR("copy_to_user\n");
3121 return -EFAULT;
3122 }
3123
3124 return 0;
3125}
3126
3127static int radeon_cp_setparam(struct drm_device *dev, void *data, struct drm_file *file_priv)
3128{
3129 drm_radeon_private_t *dev_priv = dev->dev_private;
3130 struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv;
3131 drm_radeon_setparam_t *sp = data;
3132 struct drm_radeon_driver_file_fields *radeon_priv;
3133
3134 switch (sp->param) {
3135 case RADEON_SETPARAM_FB_LOCATION:
3136 radeon_priv = file_priv->driver_priv;
3137 radeon_priv->radeon_fb_delta = dev_priv->fb_location -
3138 sp->value;
3139 break;
3140 case RADEON_SETPARAM_SWITCH_TILING:
3141 if (sp->value == 0) {
3142 DRM_DEBUG("color tiling disabled\n");
3143 dev_priv->front_pitch_offset &= ~RADEON_DST_TILE_MACRO;
3144 dev_priv->back_pitch_offset &= ~RADEON_DST_TILE_MACRO;
3145 if (master_priv->sarea_priv)
3146 master_priv->sarea_priv->tiling_enabled = 0;
3147 } else if (sp->value == 1) {
3148 DRM_DEBUG("color tiling enabled\n");
3149 dev_priv->front_pitch_offset |= RADEON_DST_TILE_MACRO;
3150 dev_priv->back_pitch_offset |= RADEON_DST_TILE_MACRO;
3151 if (master_priv->sarea_priv)
3152 master_priv->sarea_priv->tiling_enabled = 1;
3153 }
3154 break;
3155 case RADEON_SETPARAM_PCIGART_LOCATION:
3156 dev_priv->pcigart_offset = sp->value;
3157 dev_priv->pcigart_offset_set = 1;
3158 break;
3159 case RADEON_SETPARAM_NEW_MEMMAP:
3160 dev_priv->new_memmap = sp->value;
3161 break;
3162 case RADEON_SETPARAM_PCIGART_TABLE_SIZE:
3163 dev_priv->gart_info.table_size = sp->value;
3164 if (dev_priv->gart_info.table_size < RADEON_PCIGART_TABLE_SIZE)
3165 dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE;
3166 break;
3167 case RADEON_SETPARAM_VBLANK_CRTC:
3168 return radeon_vblank_crtc_set(dev, sp->value);
3169 break;
3170 default:
3171 DRM_DEBUG("Invalid parameter %d\n", sp->param);
3172 return -EINVAL;
3173 }
3174
3175 return 0;
3176}
3177
3178/* When a client dies:
3179 * - Check for and clean up flipped page state
3180 * - Free any alloced GART memory.
3181 * - Free any alloced radeon surfaces.
3182 *
3183 * DRM infrastructure takes care of reclaiming dma buffers.
3184 */
3185void radeon_driver_preclose(struct drm_device *dev, struct drm_file *file_priv)
3186{
3187 if (dev->dev_private) {
3188 drm_radeon_private_t *dev_priv = dev->dev_private;
3189 dev_priv->page_flipping = 0;
3190 radeon_mem_release(file_priv, dev_priv->gart_heap);
3191 radeon_mem_release(file_priv, dev_priv->fb_heap);
3192 radeon_surfaces_release(file_priv, dev_priv);
3193 }
3194}
3195
3196void radeon_driver_lastclose(struct drm_device *dev)
3197{
3198 radeon_surfaces_release(PCIGART_FILE_PRIV, dev->dev_private);
3199 radeon_do_release(dev);
3200}
3201
3202int radeon_driver_open(struct drm_device *dev, struct drm_file *file_priv)
3203{
3204 drm_radeon_private_t *dev_priv = dev->dev_private;
3205 struct drm_radeon_driver_file_fields *radeon_priv;
3206
3207 DRM_DEBUG("\n");
3208 radeon_priv = kmalloc(sizeof(*radeon_priv), GFP_KERNEL);
3209
3210 if (!radeon_priv)
3211 return -ENOMEM;
3212
3213 file_priv->driver_priv = radeon_priv;
3214
3215 if (dev_priv)
3216 radeon_priv->radeon_fb_delta = dev_priv->fb_location;
3217 else
3218 radeon_priv->radeon_fb_delta = 0;
3219 return 0;
3220}
3221
3222void radeon_driver_postclose(struct drm_device *dev, struct drm_file *file_priv)
3223{
3224 struct drm_radeon_driver_file_fields *radeon_priv =
3225 file_priv->driver_priv;
3226
3227 kfree(radeon_priv);
3228}
3229
3230struct drm_ioctl_desc radeon_ioctls[] = {
3231 DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, radeon_cp_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3232 DRM_IOCTL_DEF_DRV(RADEON_CP_START, radeon_cp_start, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3233 DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, radeon_cp_stop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3234 DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, radeon_cp_reset, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3235 DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, radeon_cp_idle, DRM_AUTH),
3236 DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, radeon_cp_resume, DRM_AUTH),
3237 DRM_IOCTL_DEF_DRV(RADEON_RESET, radeon_engine_reset, DRM_AUTH),
3238 DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, radeon_fullscreen, DRM_AUTH),
3239 DRM_IOCTL_DEF_DRV(RADEON_SWAP, radeon_cp_swap, DRM_AUTH),
3240 DRM_IOCTL_DEF_DRV(RADEON_CLEAR, radeon_cp_clear, DRM_AUTH),
3241 DRM_IOCTL_DEF_DRV(RADEON_VERTEX, radeon_cp_vertex, DRM_AUTH),
3242 DRM_IOCTL_DEF_DRV(RADEON_INDICES, radeon_cp_indices, DRM_AUTH),
3243 DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, radeon_cp_texture, DRM_AUTH),
3244 DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, radeon_cp_stipple, DRM_AUTH),
3245 DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, radeon_cp_indirect, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3246 DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, radeon_cp_vertex2, DRM_AUTH),
3247 DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, radeon_cp_cmdbuf, DRM_AUTH),
3248 DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, radeon_cp_getparam, DRM_AUTH),
3249 DRM_IOCTL_DEF_DRV(RADEON_FLIP, radeon_cp_flip, DRM_AUTH),
3250 DRM_IOCTL_DEF_DRV(RADEON_ALLOC, radeon_mem_alloc, DRM_AUTH),
3251 DRM_IOCTL_DEF_DRV(RADEON_FREE, radeon_mem_free, DRM_AUTH),
3252 DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, radeon_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
3253 DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, radeon_irq_emit, DRM_AUTH),
3254 DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, radeon_irq_wait, DRM_AUTH),
3255 DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, radeon_cp_setparam, DRM_AUTH),
3256 DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, radeon_surface_alloc, DRM_AUTH),
3257 DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, radeon_surface_free, DRM_AUTH),
3258 DRM_IOCTL_DEF_DRV(RADEON_CS, r600_cs_legacy_ioctl, DRM_AUTH)
3259};
3260
3261int radeon_max_ioctl = ARRAY_SIZE(radeon_ioctls);
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-22 13:07:11 -0500