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authorMarek Olšák <marek.olsak@amd.com>2019-06-28 18:31:26 -0400
committerAlex Deucher <alexander.deucher@amd.com>2019-07-09 18:43:09 -0400
commit83145f110eb2ada9d54fcbcf416c02de126381c1 (patch)
tree5cbad266500e8f9b9d05a871aff1966512d7627b
parent5f65ae344f1493c9c6f0a1748da4ce3af71ab541 (diff)
drm/amdgpu: don't invalidate caches in RELEASE_MEM, only do the writeback
This RELEASE_MEM use has the Release semantic, which means we should write back but not invalidate. Invalidations only make sense with the Acquire semantic (ACQUIRE_MEM), or when RELEASE_MEM is used to do the combined Acquire-Release semantic, which is a barrier, not a fence. The undesirable side effect of doing invalidations for the Release semantic is that it invalidates caches while shaders are running, because the Release can execute in the middle of the next IB. UMDs should use ACQUIRE_MEM at the beginning of IBs. Doing cache invalidations for a fence (like in this case) doesn't do anything for correctness. Signed-off-by: Marek Olšák <marek.olsak@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c6
1 files changed, 1 insertions, 5 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 4b2601a5e969..ee41d5592c51 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -4285,11 +4285,7 @@ static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
4285 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 4285 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
4286 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ | 4286 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ |
4287 PACKET3_RELEASE_MEM_GCR_GL2_WB | 4287 PACKET3_RELEASE_MEM_GCR_GL2_WB |
4288 PACKET3_RELEASE_MEM_GCR_GL2_INV | 4288 PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */
4289 PACKET3_RELEASE_MEM_GCR_GL2_US |
4290 PACKET3_RELEASE_MEM_GCR_GL1_INV |
4291 PACKET3_RELEASE_MEM_GCR_GLV_INV |
4292 PACKET3_RELEASE_MEM_GCR_GLM_INV |
4293 PACKET3_RELEASE_MEM_GCR_GLM_WB | 4289 PACKET3_RELEASE_MEM_GCR_GLM_WB |
4294 PACKET3_RELEASE_MEM_CACHE_POLICY(3) | 4290 PACKET3_RELEASE_MEM_CACHE_POLICY(3) |
4295 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 4291 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |