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authorLinus Walleij <linus.walleij@linaro.org>2016-02-22 09:01:01 -0500
committerMarc Zyngier <marc.zyngier@arm.com>2016-03-09 04:38:05 -0500
commit82b0a434b436f5da69ddd24bd6a6fa5dc4484310 (patch)
tree4c20fbfa5ce765f5454874eb3a386619dbe76968
parenta13690297ce49262ae44e41b25a954124609eea8 (diff)
irqchip/gic/realview: Support more RealView DCC variants
In the add-on file for the GIC dealing with the RealView family we currently only handle the PB11MPCore, let's extend this to manage the RealView EB ARM11MPCore as well. The Revision B of the ARM11MPCore core tile is a bit special and needs special handling as it moves a system control register around at random. Cc: Arnd Bergmann <arnd@arndb.de> Cc: devicetree@vger.kernel.org Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
-rw-r--r--Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt1
-rw-r--r--drivers/irqchip/irq-gic-realview.c44
2 files changed, 39 insertions, 6 deletions
diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt b/Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt
index 5a1cb4bc3dfe..793c20ff8fcc 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt
@@ -16,6 +16,7 @@ Main node required properties:
16 "arm,cortex-a15-gic" 16 "arm,cortex-a15-gic"
17 "arm,cortex-a7-gic" 17 "arm,cortex-a7-gic"
18 "arm,cortex-a9-gic" 18 "arm,cortex-a9-gic"
19 "arm,eb11mp-gic"
19 "arm,gic-400" 20 "arm,gic-400"
20 "arm,pl390" 21 "arm,pl390"
21 "arm,tc11mp-gic" 22 "arm,tc11mp-gic"
diff --git a/drivers/irqchip/irq-gic-realview.c b/drivers/irqchip/irq-gic-realview.c
index aa46eb280a7f..54c296401525 100644
--- a/drivers/irqchip/irq-gic-realview.c
+++ b/drivers/irqchip/irq-gic-realview.c
@@ -10,7 +10,8 @@
10#include <linux/irqchip/arm-gic.h> 10#include <linux/irqchip/arm-gic.h>
11 11
12#define REALVIEW_SYS_LOCK_OFFSET 0x20 12#define REALVIEW_SYS_LOCK_OFFSET 0x20
13#define REALVIEW_PB11MP_SYS_PLD_CTRL1 0x74 13#define REALVIEW_SYS_PLD_CTRL1 0x74
14#define REALVIEW_EB_REVB_SYS_PLD_CTRL1 0xD8
14#define VERSATILE_LOCK_VAL 0xA05F 15#define VERSATILE_LOCK_VAL 0xA05F
15#define PLD_INTMODE_MASK BIT(22)|BIT(23)|BIT(24) 16#define PLD_INTMODE_MASK BIT(22)|BIT(23)|BIT(24)
16#define PLD_INTMODE_LEGACY 0x0 17#define PLD_INTMODE_LEGACY 0x0
@@ -18,26 +19,57 @@
18#define PLD_INTMODE_NEW_NO_DCC BIT(23) 19#define PLD_INTMODE_NEW_NO_DCC BIT(23)
19#define PLD_INTMODE_FIQ_ENABLE BIT(24) 20#define PLD_INTMODE_FIQ_ENABLE BIT(24)
20 21
22/* For some reason RealView EB Rev B moved this register */
23static const struct of_device_id syscon_pldset_of_match[] = {
24 {
25 .compatible = "arm,realview-eb11mp-revb-syscon",
26 .data = (void *)REALVIEW_EB_REVB_SYS_PLD_CTRL1,
27 },
28 {
29 .compatible = "arm,realview-eb11mp-revc-syscon",
30 .data = (void *)REALVIEW_SYS_PLD_CTRL1,
31 },
32 {
33 .compatible = "arm,realview-eb-syscon",
34 .data = (void *)REALVIEW_SYS_PLD_CTRL1,
35 },
36 {
37 .compatible = "arm,realview-pb11mp-syscon",
38 .data = (void *)REALVIEW_SYS_PLD_CTRL1,
39 },
40 {},
41};
42
21static int __init 43static int __init
22realview_gic_of_init(struct device_node *node, struct device_node *parent) 44realview_gic_of_init(struct device_node *node, struct device_node *parent)
23{ 45{
24 static struct regmap *map; 46 static struct regmap *map;
47 struct device_node *np;
48 const struct of_device_id *gic_id;
49 u32 pld1_ctrl;
50
51 np = of_find_matching_node_and_match(NULL, syscon_pldset_of_match,
52 &gic_id);
53 if (!np)
54 return -ENODEV;
55 pld1_ctrl = (u32)gic_id->data;
25 56
26 /* The PB11MPCore GIC needs to be configured in the syscon */ 57 /* The PB11MPCore GIC needs to be configured in the syscon */
27 map = syscon_regmap_lookup_by_compatible("arm,realview-pb11mp-syscon"); 58 map = syscon_node_to_regmap(np);
28 if (!IS_ERR(map)) { 59 if (!IS_ERR(map)) {
29 /* new irq mode with no DCC */ 60 /* new irq mode with no DCC */
30 regmap_write(map, REALVIEW_SYS_LOCK_OFFSET, 61 regmap_write(map, REALVIEW_SYS_LOCK_OFFSET,
31 VERSATILE_LOCK_VAL); 62 VERSATILE_LOCK_VAL);
32 regmap_update_bits(map, REALVIEW_PB11MP_SYS_PLD_CTRL1, 63 regmap_update_bits(map, pld1_ctrl,
33 PLD_INTMODE_NEW_NO_DCC, 64 PLD_INTMODE_NEW_NO_DCC,
34 PLD_INTMODE_MASK); 65 PLD_INTMODE_MASK);
35 regmap_write(map, REALVIEW_SYS_LOCK_OFFSET, 0x0000); 66 regmap_write(map, REALVIEW_SYS_LOCK_OFFSET, 0x0000);
36 pr_info("TC11MP GIC: set up interrupt controller to NEW mode, no DCC\n"); 67 pr_info("RealView GIC: set up interrupt controller to NEW mode, no DCC\n");
37 } else { 68 } else {
38 pr_err("TC11MP GIC setup: could not find syscon\n"); 69 pr_err("RealView GIC setup: could not find syscon\n");
39 return -ENXIO; 70 return -ENODEV;
40 } 71 }
41 return gic_of_init(node, parent); 72 return gic_of_init(node, parent);
42} 73}
43IRQCHIP_DECLARE(armtc11mp_gic, "arm,tc11mp-gic", realview_gic_of_init); 74IRQCHIP_DECLARE(armtc11mp_gic, "arm,tc11mp-gic", realview_gic_of_init);
75IRQCHIP_DECLARE(armeb11mp_gic, "arm,eb11mp-gic", realview_gic_of_init);