diff options
author | Maciej S. Szmigiero <mail@maciej.szmigiero.name> | 2015-08-05 11:21:35 -0400 |
---|---|---|
committer | Mark Brown <broonie@kernel.org> | 2015-08-14 15:20:56 -0400 |
commit | 8277df3c66f1a8cecfadc29f7394f623263b4445 (patch) | |
tree | 79b1abe757712df5ee581d446cd4b74c2a3fd474 | |
parent | bc0195aad0daa2ad5b0d76cce22b167bc3435590 (diff) |
ASoC: fsl_ssi: enable IPG clock during AC'97 reg access
IPG clock have to be enabled during AC'97 CODEC register
access in fsl_ssi driver.
Signed-off-by: Maciej Szmigiero <mail@maciej.szmigiero.name>
Signed-off-by: Mark Brown <broonie@kernel.org>
-rw-r--r-- | sound/soc/fsl/fsl_ssi.c | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/sound/soc/fsl/fsl_ssi.c b/sound/soc/fsl/fsl_ssi.c index c7647e066cfd..9c46c7dc0f20 100644 --- a/sound/soc/fsl/fsl_ssi.c +++ b/sound/soc/fsl/fsl_ssi.c | |||
@@ -1127,10 +1127,17 @@ static void fsl_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg, | |||
1127 | struct regmap *regs = fsl_ac97_data->regs; | 1127 | struct regmap *regs = fsl_ac97_data->regs; |
1128 | unsigned int lreg; | 1128 | unsigned int lreg; |
1129 | unsigned int lval; | 1129 | unsigned int lval; |
1130 | int ret; | ||
1130 | 1131 | ||
1131 | if (reg > 0x7f) | 1132 | if (reg > 0x7f) |
1132 | return; | 1133 | return; |
1133 | 1134 | ||
1135 | ret = clk_prepare_enable(fsl_ac97_data->clk); | ||
1136 | if (ret) { | ||
1137 | pr_err("ac97 write clk_prepare_enable failed: %d\n", | ||
1138 | ret); | ||
1139 | return; | ||
1140 | } | ||
1134 | 1141 | ||
1135 | lreg = reg << 12; | 1142 | lreg = reg << 12; |
1136 | regmap_write(regs, CCSR_SSI_SACADD, lreg); | 1143 | regmap_write(regs, CCSR_SSI_SACADD, lreg); |
@@ -1141,6 +1148,8 @@ static void fsl_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg, | |||
1141 | regmap_update_bits(regs, CCSR_SSI_SACNT, CCSR_SSI_SACNT_RDWR_MASK, | 1148 | regmap_update_bits(regs, CCSR_SSI_SACNT, CCSR_SSI_SACNT_RDWR_MASK, |
1142 | CCSR_SSI_SACNT_WR); | 1149 | CCSR_SSI_SACNT_WR); |
1143 | udelay(100); | 1150 | udelay(100); |
1151 | |||
1152 | clk_disable_unprepare(fsl_ac97_data->clk); | ||
1144 | } | 1153 | } |
1145 | 1154 | ||
1146 | static unsigned short fsl_ssi_ac97_read(struct snd_ac97 *ac97, | 1155 | static unsigned short fsl_ssi_ac97_read(struct snd_ac97 *ac97, |
@@ -1151,6 +1160,14 @@ static unsigned short fsl_ssi_ac97_read(struct snd_ac97 *ac97, | |||
1151 | unsigned short val = -1; | 1160 | unsigned short val = -1; |
1152 | u32 reg_val; | 1161 | u32 reg_val; |
1153 | unsigned int lreg; | 1162 | unsigned int lreg; |
1163 | int ret; | ||
1164 | |||
1165 | ret = clk_prepare_enable(fsl_ac97_data->clk); | ||
1166 | if (ret) { | ||
1167 | pr_err("ac97 read clk_prepare_enable failed: %d\n", | ||
1168 | ret); | ||
1169 | return -1; | ||
1170 | } | ||
1154 | 1171 | ||
1155 | lreg = (reg & 0x7f) << 12; | 1172 | lreg = (reg & 0x7f) << 12; |
1156 | regmap_write(regs, CCSR_SSI_SACADD, lreg); | 1173 | regmap_write(regs, CCSR_SSI_SACADD, lreg); |
@@ -1162,6 +1179,8 @@ static unsigned short fsl_ssi_ac97_read(struct snd_ac97 *ac97, | |||
1162 | regmap_read(regs, CCSR_SSI_SACDAT, ®_val); | 1179 | regmap_read(regs, CCSR_SSI_SACDAT, ®_val); |
1163 | val = (reg_val >> 4) & 0xffff; | 1180 | val = (reg_val >> 4) & 0xffff; |
1164 | 1181 | ||
1182 | clk_disable_unprepare(fsl_ac97_data->clk); | ||
1183 | |||
1165 | return val; | 1184 | return val; |
1166 | } | 1185 | } |
1167 | 1186 | ||