diff options
author | Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> | 2018-01-28 22:04:55 -0500 |
---|---|---|
committer | Mark Brown <broonie@kernel.org> | 2018-02-12 04:41:33 -0500 |
commit | 825a52aa768352920b631208cd03250869609936 (patch) | |
tree | 0e69e7aa7ab39bb329c943d2aabc3c36cb0befe8 | |
parent | 7928b2cbe55b2a410a0f5c1f154610059c57b1b2 (diff) |
ASoC: wm8900: replace codec to component
Now we can replace Codec to Component. Let's do it.
Note:
xxx_codec_xxx() -> xxx_component_xxx()
.idle_bias_off = 0 -> .idle_bias_on = 1
.ignore_pmdown_time = 0 -> .use_pmdown_time = 1
- -> .endianness = 1
- -> .non_legacy_dai_naming = 1
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
-rw-r--r-- | sound/soc/codecs/wm8900.c | 251 |
1 files changed, 125 insertions, 126 deletions
diff --git a/sound/soc/codecs/wm8900.c b/sound/soc/codecs/wm8900.c index c77b49a29311..1a14e902949d 100644 --- a/sound/soc/codecs/wm8900.c +++ b/sound/soc/codecs/wm8900.c | |||
@@ -216,23 +216,23 @@ static bool wm8900_volatile_register(struct device *dev, unsigned int reg) | |||
216 | } | 216 | } |
217 | } | 217 | } |
218 | 218 | ||
219 | static void wm8900_reset(struct snd_soc_codec *codec) | 219 | static void wm8900_reset(struct snd_soc_component *component) |
220 | { | 220 | { |
221 | snd_soc_write(codec, WM8900_REG_RESET, 0); | 221 | snd_soc_component_write(component, WM8900_REG_RESET, 0); |
222 | } | 222 | } |
223 | 223 | ||
224 | static int wm8900_hp_event(struct snd_soc_dapm_widget *w, | 224 | static int wm8900_hp_event(struct snd_soc_dapm_widget *w, |
225 | struct snd_kcontrol *kcontrol, int event) | 225 | struct snd_kcontrol *kcontrol, int event) |
226 | { | 226 | { |
227 | struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); | 227 | struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); |
228 | u16 hpctl1 = snd_soc_read(codec, WM8900_REG_HPCTL1); | 228 | u16 hpctl1 = snd_soc_component_read32(component, WM8900_REG_HPCTL1); |
229 | 229 | ||
230 | switch (event) { | 230 | switch (event) { |
231 | case SND_SOC_DAPM_PRE_PMU: | 231 | case SND_SOC_DAPM_PRE_PMU: |
232 | /* Clamp headphone outputs */ | 232 | /* Clamp headphone outputs */ |
233 | hpctl1 = WM8900_REG_HPCTL1_HP_CLAMP_IP | | 233 | hpctl1 = WM8900_REG_HPCTL1_HP_CLAMP_IP | |
234 | WM8900_REG_HPCTL1_HP_CLAMP_OP; | 234 | WM8900_REG_HPCTL1_HP_CLAMP_OP; |
235 | snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1); | 235 | snd_soc_component_write(component, WM8900_REG_HPCTL1, hpctl1); |
236 | break; | 236 | break; |
237 | 237 | ||
238 | case SND_SOC_DAPM_POST_PMU: | 238 | case SND_SOC_DAPM_POST_PMU: |
@@ -241,41 +241,41 @@ static int wm8900_hp_event(struct snd_soc_dapm_widget *w, | |||
241 | hpctl1 |= WM8900_REG_HPCTL1_HP_SHORT | | 241 | hpctl1 |= WM8900_REG_HPCTL1_HP_SHORT | |
242 | WM8900_REG_HPCTL1_HP_SHORT2 | | 242 | WM8900_REG_HPCTL1_HP_SHORT2 | |
243 | WM8900_REG_HPCTL1_HP_IPSTAGE_ENA; | 243 | WM8900_REG_HPCTL1_HP_IPSTAGE_ENA; |
244 | snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1); | 244 | snd_soc_component_write(component, WM8900_REG_HPCTL1, hpctl1); |
245 | 245 | ||
246 | msleep(400); | 246 | msleep(400); |
247 | 247 | ||
248 | /* Enable the output stage */ | 248 | /* Enable the output stage */ |
249 | hpctl1 &= ~WM8900_REG_HPCTL1_HP_CLAMP_OP; | 249 | hpctl1 &= ~WM8900_REG_HPCTL1_HP_CLAMP_OP; |
250 | hpctl1 |= WM8900_REG_HPCTL1_HP_OPSTAGE_ENA; | 250 | hpctl1 |= WM8900_REG_HPCTL1_HP_OPSTAGE_ENA; |
251 | snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1); | 251 | snd_soc_component_write(component, WM8900_REG_HPCTL1, hpctl1); |
252 | 252 | ||
253 | /* Remove the shorts */ | 253 | /* Remove the shorts */ |
254 | hpctl1 &= ~WM8900_REG_HPCTL1_HP_SHORT2; | 254 | hpctl1 &= ~WM8900_REG_HPCTL1_HP_SHORT2; |
255 | snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1); | 255 | snd_soc_component_write(component, WM8900_REG_HPCTL1, hpctl1); |
256 | hpctl1 &= ~WM8900_REG_HPCTL1_HP_SHORT; | 256 | hpctl1 &= ~WM8900_REG_HPCTL1_HP_SHORT; |
257 | snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1); | 257 | snd_soc_component_write(component, WM8900_REG_HPCTL1, hpctl1); |
258 | break; | 258 | break; |
259 | 259 | ||
260 | case SND_SOC_DAPM_PRE_PMD: | 260 | case SND_SOC_DAPM_PRE_PMD: |
261 | /* Short the output */ | 261 | /* Short the output */ |
262 | hpctl1 |= WM8900_REG_HPCTL1_HP_SHORT; | 262 | hpctl1 |= WM8900_REG_HPCTL1_HP_SHORT; |
263 | snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1); | 263 | snd_soc_component_write(component, WM8900_REG_HPCTL1, hpctl1); |
264 | 264 | ||
265 | /* Disable the output stage */ | 265 | /* Disable the output stage */ |
266 | hpctl1 &= ~WM8900_REG_HPCTL1_HP_OPSTAGE_ENA; | 266 | hpctl1 &= ~WM8900_REG_HPCTL1_HP_OPSTAGE_ENA; |
267 | snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1); | 267 | snd_soc_component_write(component, WM8900_REG_HPCTL1, hpctl1); |
268 | 268 | ||
269 | /* Clamp the outputs and power down input */ | 269 | /* Clamp the outputs and power down input */ |
270 | hpctl1 |= WM8900_REG_HPCTL1_HP_CLAMP_IP | | 270 | hpctl1 |= WM8900_REG_HPCTL1_HP_CLAMP_IP | |
271 | WM8900_REG_HPCTL1_HP_CLAMP_OP; | 271 | WM8900_REG_HPCTL1_HP_CLAMP_OP; |
272 | hpctl1 &= ~WM8900_REG_HPCTL1_HP_IPSTAGE_ENA; | 272 | hpctl1 &= ~WM8900_REG_HPCTL1_HP_IPSTAGE_ENA; |
273 | snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1); | 273 | snd_soc_component_write(component, WM8900_REG_HPCTL1, hpctl1); |
274 | break; | 274 | break; |
275 | 275 | ||
276 | case SND_SOC_DAPM_POST_PMD: | 276 | case SND_SOC_DAPM_POST_PMD: |
277 | /* Disable everything */ | 277 | /* Disable everything */ |
278 | snd_soc_write(codec, WM8900_REG_HPCTL1, 0); | 278 | snd_soc_component_write(component, WM8900_REG_HPCTL1, 0); |
279 | break; | 279 | break; |
280 | 280 | ||
281 | default: | 281 | default: |
@@ -635,10 +635,10 @@ static int wm8900_hw_params(struct snd_pcm_substream *substream, | |||
635 | struct snd_pcm_hw_params *params, | 635 | struct snd_pcm_hw_params *params, |
636 | struct snd_soc_dai *dai) | 636 | struct snd_soc_dai *dai) |
637 | { | 637 | { |
638 | struct snd_soc_codec *codec = dai->codec; | 638 | struct snd_soc_component *component = dai->component; |
639 | u16 reg; | 639 | u16 reg; |
640 | 640 | ||
641 | reg = snd_soc_read(codec, WM8900_REG_AUDIO1) & ~0x60; | 641 | reg = snd_soc_component_read32(component, WM8900_REG_AUDIO1) & ~0x60; |
642 | 642 | ||
643 | switch (params_width(params)) { | 643 | switch (params_width(params)) { |
644 | case 16: | 644 | case 16: |
@@ -656,17 +656,17 @@ static int wm8900_hw_params(struct snd_pcm_substream *substream, | |||
656 | return -EINVAL; | 656 | return -EINVAL; |
657 | } | 657 | } |
658 | 658 | ||
659 | snd_soc_write(codec, WM8900_REG_AUDIO1, reg); | 659 | snd_soc_component_write(component, WM8900_REG_AUDIO1, reg); |
660 | 660 | ||
661 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { | 661 | if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { |
662 | reg = snd_soc_read(codec, WM8900_REG_DACCTRL); | 662 | reg = snd_soc_component_read32(component, WM8900_REG_DACCTRL); |
663 | 663 | ||
664 | if (params_rate(params) <= 24000) | 664 | if (params_rate(params) <= 24000) |
665 | reg |= WM8900_REG_DACCTRL_DAC_SB_FILT; | 665 | reg |= WM8900_REG_DACCTRL_DAC_SB_FILT; |
666 | else | 666 | else |
667 | reg &= ~WM8900_REG_DACCTRL_DAC_SB_FILT; | 667 | reg &= ~WM8900_REG_DACCTRL_DAC_SB_FILT; |
668 | 668 | ||
669 | snd_soc_write(codec, WM8900_REG_DACCTRL, reg); | 669 | snd_soc_component_write(component, WM8900_REG_DACCTRL, reg); |
670 | } | 670 | } |
671 | 671 | ||
672 | return 0; | 672 | return 0; |
@@ -751,24 +751,24 @@ static int fll_factors(struct _fll_div *fll_div, unsigned int Fref, | |||
751 | return 0; | 751 | return 0; |
752 | } | 752 | } |
753 | 753 | ||
754 | static int wm8900_set_fll(struct snd_soc_codec *codec, | 754 | static int wm8900_set_fll(struct snd_soc_component *component, |
755 | int fll_id, unsigned int freq_in, unsigned int freq_out) | 755 | int fll_id, unsigned int freq_in, unsigned int freq_out) |
756 | { | 756 | { |
757 | struct wm8900_priv *wm8900 = snd_soc_codec_get_drvdata(codec); | 757 | struct wm8900_priv *wm8900 = snd_soc_component_get_drvdata(component); |
758 | struct _fll_div fll_div; | 758 | struct _fll_div fll_div; |
759 | 759 | ||
760 | if (wm8900->fll_in == freq_in && wm8900->fll_out == freq_out) | 760 | if (wm8900->fll_in == freq_in && wm8900->fll_out == freq_out) |
761 | return 0; | 761 | return 0; |
762 | 762 | ||
763 | /* The digital side should be disabled during any change. */ | 763 | /* The digital side should be disabled during any change. */ |
764 | snd_soc_update_bits(codec, WM8900_REG_POWER1, | 764 | snd_soc_component_update_bits(component, WM8900_REG_POWER1, |
765 | WM8900_REG_POWER1_FLL_ENA, 0); | 765 | WM8900_REG_POWER1_FLL_ENA, 0); |
766 | 766 | ||
767 | /* Disable the FLL? */ | 767 | /* Disable the FLL? */ |
768 | if (!freq_in || !freq_out) { | 768 | if (!freq_in || !freq_out) { |
769 | snd_soc_update_bits(codec, WM8900_REG_CLOCKING1, | 769 | snd_soc_component_update_bits(component, WM8900_REG_CLOCKING1, |
770 | WM8900_REG_CLOCKING1_MCLK_SRC, 0); | 770 | WM8900_REG_CLOCKING1_MCLK_SRC, 0); |
771 | snd_soc_update_bits(codec, WM8900_REG_FLLCTL1, | 771 | snd_soc_component_update_bits(component, WM8900_REG_FLLCTL1, |
772 | WM8900_REG_FLLCTL1_OSC_ENA, 0); | 772 | WM8900_REG_FLLCTL1_OSC_ENA, 0); |
773 | wm8900->fll_in = freq_in; | 773 | wm8900->fll_in = freq_in; |
774 | wm8900->fll_out = freq_out; | 774 | wm8900->fll_out = freq_out; |
@@ -784,32 +784,32 @@ static int wm8900_set_fll(struct snd_soc_codec *codec, | |||
784 | 784 | ||
785 | /* The osclilator *MUST* be enabled before we enable the | 785 | /* The osclilator *MUST* be enabled before we enable the |
786 | * digital circuit. */ | 786 | * digital circuit. */ |
787 | snd_soc_write(codec, WM8900_REG_FLLCTL1, | 787 | snd_soc_component_write(component, WM8900_REG_FLLCTL1, |
788 | fll_div.fll_ratio | WM8900_REG_FLLCTL1_OSC_ENA); | 788 | fll_div.fll_ratio | WM8900_REG_FLLCTL1_OSC_ENA); |
789 | 789 | ||
790 | snd_soc_write(codec, WM8900_REG_FLLCTL4, fll_div.n >> 5); | 790 | snd_soc_component_write(component, WM8900_REG_FLLCTL4, fll_div.n >> 5); |
791 | snd_soc_write(codec, WM8900_REG_FLLCTL5, | 791 | snd_soc_component_write(component, WM8900_REG_FLLCTL5, |
792 | (fll_div.fllclk_div << 6) | (fll_div.n & 0x1f)); | 792 | (fll_div.fllclk_div << 6) | (fll_div.n & 0x1f)); |
793 | 793 | ||
794 | if (fll_div.k) { | 794 | if (fll_div.k) { |
795 | snd_soc_write(codec, WM8900_REG_FLLCTL2, | 795 | snd_soc_component_write(component, WM8900_REG_FLLCTL2, |
796 | (fll_div.k >> 8) | 0x100); | 796 | (fll_div.k >> 8) | 0x100); |
797 | snd_soc_write(codec, WM8900_REG_FLLCTL3, fll_div.k & 0xff); | 797 | snd_soc_component_write(component, WM8900_REG_FLLCTL3, fll_div.k & 0xff); |
798 | } else | 798 | } else |
799 | snd_soc_write(codec, WM8900_REG_FLLCTL2, 0); | 799 | snd_soc_component_write(component, WM8900_REG_FLLCTL2, 0); |
800 | 800 | ||
801 | if (fll_div.fll_slow_lock_ref) | 801 | if (fll_div.fll_slow_lock_ref) |
802 | snd_soc_write(codec, WM8900_REG_FLLCTL6, | 802 | snd_soc_component_write(component, WM8900_REG_FLLCTL6, |
803 | WM8900_REG_FLLCTL6_FLL_SLOW_LOCK_REF); | 803 | WM8900_REG_FLLCTL6_FLL_SLOW_LOCK_REF); |
804 | else | 804 | else |
805 | snd_soc_write(codec, WM8900_REG_FLLCTL6, 0); | 805 | snd_soc_component_write(component, WM8900_REG_FLLCTL6, 0); |
806 | 806 | ||
807 | snd_soc_update_bits(codec, WM8900_REG_POWER1, | 807 | snd_soc_component_update_bits(component, WM8900_REG_POWER1, |
808 | WM8900_REG_POWER1_FLL_ENA, | 808 | WM8900_REG_POWER1_FLL_ENA, |
809 | WM8900_REG_POWER1_FLL_ENA); | 809 | WM8900_REG_POWER1_FLL_ENA); |
810 | 810 | ||
811 | reenable: | 811 | reenable: |
812 | snd_soc_update_bits(codec, WM8900_REG_CLOCKING1, | 812 | snd_soc_component_update_bits(component, WM8900_REG_CLOCKING1, |
813 | WM8900_REG_CLOCKING1_MCLK_SRC, | 813 | WM8900_REG_CLOCKING1_MCLK_SRC, |
814 | WM8900_REG_CLOCKING1_MCLK_SRC); | 814 | WM8900_REG_CLOCKING1_MCLK_SRC); |
815 | return 0; | 815 | return 0; |
@@ -818,41 +818,41 @@ reenable: | |||
818 | static int wm8900_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id, | 818 | static int wm8900_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id, |
819 | int source, unsigned int freq_in, unsigned int freq_out) | 819 | int source, unsigned int freq_in, unsigned int freq_out) |
820 | { | 820 | { |
821 | return wm8900_set_fll(codec_dai->codec, pll_id, freq_in, freq_out); | 821 | return wm8900_set_fll(codec_dai->component, pll_id, freq_in, freq_out); |
822 | } | 822 | } |
823 | 823 | ||
824 | static int wm8900_set_dai_clkdiv(struct snd_soc_dai *codec_dai, | 824 | static int wm8900_set_dai_clkdiv(struct snd_soc_dai *codec_dai, |
825 | int div_id, int div) | 825 | int div_id, int div) |
826 | { | 826 | { |
827 | struct snd_soc_codec *codec = codec_dai->codec; | 827 | struct snd_soc_component *component = codec_dai->component; |
828 | 828 | ||
829 | switch (div_id) { | 829 | switch (div_id) { |
830 | case WM8900_BCLK_DIV: | 830 | case WM8900_BCLK_DIV: |
831 | snd_soc_update_bits(codec, WM8900_REG_CLOCKING1, | 831 | snd_soc_component_update_bits(component, WM8900_REG_CLOCKING1, |
832 | WM8900_REG_CLOCKING1_BCLK_MASK, div); | 832 | WM8900_REG_CLOCKING1_BCLK_MASK, div); |
833 | break; | 833 | break; |
834 | case WM8900_OPCLK_DIV: | 834 | case WM8900_OPCLK_DIV: |
835 | snd_soc_update_bits(codec, WM8900_REG_CLOCKING1, | 835 | snd_soc_component_update_bits(component, WM8900_REG_CLOCKING1, |
836 | WM8900_REG_CLOCKING1_OPCLK_MASK, div); | 836 | WM8900_REG_CLOCKING1_OPCLK_MASK, div); |
837 | break; | 837 | break; |
838 | case WM8900_DAC_LRCLK: | 838 | case WM8900_DAC_LRCLK: |
839 | snd_soc_update_bits(codec, WM8900_REG_AUDIO4, | 839 | snd_soc_component_update_bits(component, WM8900_REG_AUDIO4, |
840 | WM8900_LRC_MASK, div); | 840 | WM8900_LRC_MASK, div); |
841 | break; | 841 | break; |
842 | case WM8900_ADC_LRCLK: | 842 | case WM8900_ADC_LRCLK: |
843 | snd_soc_update_bits(codec, WM8900_REG_AUDIO3, | 843 | snd_soc_component_update_bits(component, WM8900_REG_AUDIO3, |
844 | WM8900_LRC_MASK, div); | 844 | WM8900_LRC_MASK, div); |
845 | break; | 845 | break; |
846 | case WM8900_DAC_CLKDIV: | 846 | case WM8900_DAC_CLKDIV: |
847 | snd_soc_update_bits(codec, WM8900_REG_CLOCKING2, | 847 | snd_soc_component_update_bits(component, WM8900_REG_CLOCKING2, |
848 | WM8900_REG_CLOCKING2_DAC_CLKDIV, div); | 848 | WM8900_REG_CLOCKING2_DAC_CLKDIV, div); |
849 | break; | 849 | break; |
850 | case WM8900_ADC_CLKDIV: | 850 | case WM8900_ADC_CLKDIV: |
851 | snd_soc_update_bits(codec, WM8900_REG_CLOCKING2, | 851 | snd_soc_component_update_bits(component, WM8900_REG_CLOCKING2, |
852 | WM8900_REG_CLOCKING2_ADC_CLKDIV, div); | 852 | WM8900_REG_CLOCKING2_ADC_CLKDIV, div); |
853 | break; | 853 | break; |
854 | case WM8900_LRCLK_MODE: | 854 | case WM8900_LRCLK_MODE: |
855 | snd_soc_update_bits(codec, WM8900_REG_DACCTRL, | 855 | snd_soc_component_update_bits(component, WM8900_REG_DACCTRL, |
856 | WM8900_REG_DACCTRL_AIF_LRCLKRATE, div); | 856 | WM8900_REG_DACCTRL_AIF_LRCLKRATE, div); |
857 | break; | 857 | break; |
858 | default: | 858 | default: |
@@ -866,13 +866,13 @@ static int wm8900_set_dai_clkdiv(struct snd_soc_dai *codec_dai, | |||
866 | static int wm8900_set_dai_fmt(struct snd_soc_dai *codec_dai, | 866 | static int wm8900_set_dai_fmt(struct snd_soc_dai *codec_dai, |
867 | unsigned int fmt) | 867 | unsigned int fmt) |
868 | { | 868 | { |
869 | struct snd_soc_codec *codec = codec_dai->codec; | 869 | struct snd_soc_component *component = codec_dai->component; |
870 | unsigned int clocking1, aif1, aif3, aif4; | 870 | unsigned int clocking1, aif1, aif3, aif4; |
871 | 871 | ||
872 | clocking1 = snd_soc_read(codec, WM8900_REG_CLOCKING1); | 872 | clocking1 = snd_soc_component_read32(component, WM8900_REG_CLOCKING1); |
873 | aif1 = snd_soc_read(codec, WM8900_REG_AUDIO1); | 873 | aif1 = snd_soc_component_read32(component, WM8900_REG_AUDIO1); |
874 | aif3 = snd_soc_read(codec, WM8900_REG_AUDIO3); | 874 | aif3 = snd_soc_component_read32(component, WM8900_REG_AUDIO3); |
875 | aif4 = snd_soc_read(codec, WM8900_REG_AUDIO4); | 875 | aif4 = snd_soc_component_read32(component, WM8900_REG_AUDIO4); |
876 | 876 | ||
877 | /* set master/slave audio interface */ | 877 | /* set master/slave audio interface */ |
878 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { | 878 | switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { |
@@ -968,27 +968,27 @@ static int wm8900_set_dai_fmt(struct snd_soc_dai *codec_dai, | |||
968 | return -EINVAL; | 968 | return -EINVAL; |
969 | } | 969 | } |
970 | 970 | ||
971 | snd_soc_write(codec, WM8900_REG_CLOCKING1, clocking1); | 971 | snd_soc_component_write(component, WM8900_REG_CLOCKING1, clocking1); |
972 | snd_soc_write(codec, WM8900_REG_AUDIO1, aif1); | 972 | snd_soc_component_write(component, WM8900_REG_AUDIO1, aif1); |
973 | snd_soc_write(codec, WM8900_REG_AUDIO3, aif3); | 973 | snd_soc_component_write(component, WM8900_REG_AUDIO3, aif3); |
974 | snd_soc_write(codec, WM8900_REG_AUDIO4, aif4); | 974 | snd_soc_component_write(component, WM8900_REG_AUDIO4, aif4); |
975 | 975 | ||
976 | return 0; | 976 | return 0; |
977 | } | 977 | } |
978 | 978 | ||
979 | static int wm8900_digital_mute(struct snd_soc_dai *codec_dai, int mute) | 979 | static int wm8900_digital_mute(struct snd_soc_dai *codec_dai, int mute) |
980 | { | 980 | { |
981 | struct snd_soc_codec *codec = codec_dai->codec; | 981 | struct snd_soc_component *component = codec_dai->component; |
982 | u16 reg; | 982 | u16 reg; |
983 | 983 | ||
984 | reg = snd_soc_read(codec, WM8900_REG_DACCTRL); | 984 | reg = snd_soc_component_read32(component, WM8900_REG_DACCTRL); |
985 | 985 | ||
986 | if (mute) | 986 | if (mute) |
987 | reg |= WM8900_REG_DACCTRL_MUTE; | 987 | reg |= WM8900_REG_DACCTRL_MUTE; |
988 | else | 988 | else |
989 | reg &= ~WM8900_REG_DACCTRL_MUTE; | 989 | reg &= ~WM8900_REG_DACCTRL_MUTE; |
990 | 990 | ||
991 | snd_soc_write(codec, WM8900_REG_DACCTRL, reg); | 991 | snd_soc_component_write(component, WM8900_REG_DACCTRL, reg); |
992 | 992 | ||
993 | return 0; | 993 | return 0; |
994 | } | 994 | } |
@@ -1028,7 +1028,7 @@ static struct snd_soc_dai_driver wm8900_dai = { | |||
1028 | .ops = &wm8900_dai_ops, | 1028 | .ops = &wm8900_dai_ops, |
1029 | }; | 1029 | }; |
1030 | 1030 | ||
1031 | static int wm8900_set_bias_level(struct snd_soc_codec *codec, | 1031 | static int wm8900_set_bias_level(struct snd_soc_component *component, |
1032 | enum snd_soc_bias_level level) | 1032 | enum snd_soc_bias_level level) |
1033 | { | 1033 | { |
1034 | u16 reg; | 1034 | u16 reg; |
@@ -1036,10 +1036,10 @@ static int wm8900_set_bias_level(struct snd_soc_codec *codec, | |||
1036 | switch (level) { | 1036 | switch (level) { |
1037 | case SND_SOC_BIAS_ON: | 1037 | case SND_SOC_BIAS_ON: |
1038 | /* Enable thermal shutdown */ | 1038 | /* Enable thermal shutdown */ |
1039 | snd_soc_update_bits(codec, WM8900_REG_GPIO, | 1039 | snd_soc_component_update_bits(component, WM8900_REG_GPIO, |
1040 | WM8900_REG_GPIO_TEMP_ENA, | 1040 | WM8900_REG_GPIO_TEMP_ENA, |
1041 | WM8900_REG_GPIO_TEMP_ENA); | 1041 | WM8900_REG_GPIO_TEMP_ENA); |
1042 | snd_soc_update_bits(codec, WM8900_REG_ADDCTL, | 1042 | snd_soc_component_update_bits(component, WM8900_REG_ADDCTL, |
1043 | WM8900_REG_ADDCTL_TEMP_SD, | 1043 | WM8900_REG_ADDCTL_TEMP_SD, |
1044 | WM8900_REG_ADDCTL_TEMP_SD); | 1044 | WM8900_REG_ADDCTL_TEMP_SD); |
1045 | break; | 1045 | break; |
@@ -1049,113 +1049,113 @@ static int wm8900_set_bias_level(struct snd_soc_codec *codec, | |||
1049 | 1049 | ||
1050 | case SND_SOC_BIAS_STANDBY: | 1050 | case SND_SOC_BIAS_STANDBY: |
1051 | /* Charge capacitors if initial power up */ | 1051 | /* Charge capacitors if initial power up */ |
1052 | if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) { | 1052 | if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) { |
1053 | /* STARTUP_BIAS_ENA on */ | 1053 | /* STARTUP_BIAS_ENA on */ |
1054 | snd_soc_write(codec, WM8900_REG_POWER1, | 1054 | snd_soc_component_write(component, WM8900_REG_POWER1, |
1055 | WM8900_REG_POWER1_STARTUP_BIAS_ENA); | 1055 | WM8900_REG_POWER1_STARTUP_BIAS_ENA); |
1056 | 1056 | ||
1057 | /* Startup bias mode */ | 1057 | /* Startup bias mode */ |
1058 | snd_soc_write(codec, WM8900_REG_ADDCTL, | 1058 | snd_soc_component_write(component, WM8900_REG_ADDCTL, |
1059 | WM8900_REG_ADDCTL_BIAS_SRC | | 1059 | WM8900_REG_ADDCTL_BIAS_SRC | |
1060 | WM8900_REG_ADDCTL_VMID_SOFTST); | 1060 | WM8900_REG_ADDCTL_VMID_SOFTST); |
1061 | 1061 | ||
1062 | /* VMID 2x50k */ | 1062 | /* VMID 2x50k */ |
1063 | snd_soc_write(codec, WM8900_REG_POWER1, | 1063 | snd_soc_component_write(component, WM8900_REG_POWER1, |
1064 | WM8900_REG_POWER1_STARTUP_BIAS_ENA | 0x1); | 1064 | WM8900_REG_POWER1_STARTUP_BIAS_ENA | 0x1); |
1065 | 1065 | ||
1066 | /* Allow capacitors to charge */ | 1066 | /* Allow capacitors to charge */ |
1067 | schedule_timeout_interruptible(msecs_to_jiffies(400)); | 1067 | schedule_timeout_interruptible(msecs_to_jiffies(400)); |
1068 | 1068 | ||
1069 | /* Enable bias */ | 1069 | /* Enable bias */ |
1070 | snd_soc_write(codec, WM8900_REG_POWER1, | 1070 | snd_soc_component_write(component, WM8900_REG_POWER1, |
1071 | WM8900_REG_POWER1_STARTUP_BIAS_ENA | | 1071 | WM8900_REG_POWER1_STARTUP_BIAS_ENA | |
1072 | WM8900_REG_POWER1_BIAS_ENA | 0x1); | 1072 | WM8900_REG_POWER1_BIAS_ENA | 0x1); |
1073 | 1073 | ||
1074 | snd_soc_write(codec, WM8900_REG_ADDCTL, 0); | 1074 | snd_soc_component_write(component, WM8900_REG_ADDCTL, 0); |
1075 | 1075 | ||
1076 | snd_soc_write(codec, WM8900_REG_POWER1, | 1076 | snd_soc_component_write(component, WM8900_REG_POWER1, |
1077 | WM8900_REG_POWER1_BIAS_ENA | 0x1); | 1077 | WM8900_REG_POWER1_BIAS_ENA | 0x1); |
1078 | } | 1078 | } |
1079 | 1079 | ||
1080 | reg = snd_soc_read(codec, WM8900_REG_POWER1); | 1080 | reg = snd_soc_component_read32(component, WM8900_REG_POWER1); |
1081 | snd_soc_write(codec, WM8900_REG_POWER1, | 1081 | snd_soc_component_write(component, WM8900_REG_POWER1, |
1082 | (reg & WM8900_REG_POWER1_FLL_ENA) | | 1082 | (reg & WM8900_REG_POWER1_FLL_ENA) | |
1083 | WM8900_REG_POWER1_BIAS_ENA | 0x1); | 1083 | WM8900_REG_POWER1_BIAS_ENA | 0x1); |
1084 | snd_soc_write(codec, WM8900_REG_POWER2, | 1084 | snd_soc_component_write(component, WM8900_REG_POWER2, |
1085 | WM8900_REG_POWER2_SYSCLK_ENA); | 1085 | WM8900_REG_POWER2_SYSCLK_ENA); |
1086 | snd_soc_write(codec, WM8900_REG_POWER3, 0); | 1086 | snd_soc_component_write(component, WM8900_REG_POWER3, 0); |
1087 | break; | 1087 | break; |
1088 | 1088 | ||
1089 | case SND_SOC_BIAS_OFF: | 1089 | case SND_SOC_BIAS_OFF: |
1090 | /* Startup bias enable */ | 1090 | /* Startup bias enable */ |
1091 | reg = snd_soc_read(codec, WM8900_REG_POWER1); | 1091 | reg = snd_soc_component_read32(component, WM8900_REG_POWER1); |
1092 | snd_soc_write(codec, WM8900_REG_POWER1, | 1092 | snd_soc_component_write(component, WM8900_REG_POWER1, |
1093 | reg & WM8900_REG_POWER1_STARTUP_BIAS_ENA); | 1093 | reg & WM8900_REG_POWER1_STARTUP_BIAS_ENA); |
1094 | snd_soc_write(codec, WM8900_REG_ADDCTL, | 1094 | snd_soc_component_write(component, WM8900_REG_ADDCTL, |
1095 | WM8900_REG_ADDCTL_BIAS_SRC | | 1095 | WM8900_REG_ADDCTL_BIAS_SRC | |
1096 | WM8900_REG_ADDCTL_VMID_SOFTST); | 1096 | WM8900_REG_ADDCTL_VMID_SOFTST); |
1097 | 1097 | ||
1098 | /* Discharge caps */ | 1098 | /* Discharge caps */ |
1099 | snd_soc_write(codec, WM8900_REG_POWER1, | 1099 | snd_soc_component_write(component, WM8900_REG_POWER1, |
1100 | WM8900_REG_POWER1_STARTUP_BIAS_ENA); | 1100 | WM8900_REG_POWER1_STARTUP_BIAS_ENA); |
1101 | schedule_timeout_interruptible(msecs_to_jiffies(500)); | 1101 | schedule_timeout_interruptible(msecs_to_jiffies(500)); |
1102 | 1102 | ||
1103 | /* Remove clamp */ | 1103 | /* Remove clamp */ |
1104 | snd_soc_write(codec, WM8900_REG_HPCTL1, 0); | 1104 | snd_soc_component_write(component, WM8900_REG_HPCTL1, 0); |
1105 | 1105 | ||
1106 | /* Power down */ | 1106 | /* Power down */ |
1107 | snd_soc_write(codec, WM8900_REG_ADDCTL, 0); | 1107 | snd_soc_component_write(component, WM8900_REG_ADDCTL, 0); |
1108 | snd_soc_write(codec, WM8900_REG_POWER1, 0); | 1108 | snd_soc_component_write(component, WM8900_REG_POWER1, 0); |
1109 | snd_soc_write(codec, WM8900_REG_POWER2, 0); | 1109 | snd_soc_component_write(component, WM8900_REG_POWER2, 0); |
1110 | snd_soc_write(codec, WM8900_REG_POWER3, 0); | 1110 | snd_soc_component_write(component, WM8900_REG_POWER3, 0); |
1111 | 1111 | ||
1112 | /* Need to let things settle before stopping the clock | 1112 | /* Need to let things settle before stopping the clock |
1113 | * to ensure that restart works, see "Stopping the | 1113 | * to ensure that restart works, see "Stopping the |
1114 | * master clock" in the datasheet. */ | 1114 | * master clock" in the datasheet. */ |
1115 | schedule_timeout_interruptible(msecs_to_jiffies(1)); | 1115 | schedule_timeout_interruptible(msecs_to_jiffies(1)); |
1116 | snd_soc_write(codec, WM8900_REG_POWER2, | 1116 | snd_soc_component_write(component, WM8900_REG_POWER2, |
1117 | WM8900_REG_POWER2_SYSCLK_ENA); | 1117 | WM8900_REG_POWER2_SYSCLK_ENA); |
1118 | break; | 1118 | break; |
1119 | } | 1119 | } |
1120 | return 0; | 1120 | return 0; |
1121 | } | 1121 | } |
1122 | 1122 | ||
1123 | static int wm8900_suspend(struct snd_soc_codec *codec) | 1123 | static int wm8900_suspend(struct snd_soc_component *component) |
1124 | { | 1124 | { |
1125 | struct wm8900_priv *wm8900 = snd_soc_codec_get_drvdata(codec); | 1125 | struct wm8900_priv *wm8900 = snd_soc_component_get_drvdata(component); |
1126 | int fll_out = wm8900->fll_out; | 1126 | int fll_out = wm8900->fll_out; |
1127 | int fll_in = wm8900->fll_in; | 1127 | int fll_in = wm8900->fll_in; |
1128 | int ret; | 1128 | int ret; |
1129 | 1129 | ||
1130 | /* Stop the FLL in an orderly fashion */ | 1130 | /* Stop the FLL in an orderly fashion */ |
1131 | ret = wm8900_set_fll(codec, 0, 0, 0); | 1131 | ret = wm8900_set_fll(component, 0, 0, 0); |
1132 | if (ret != 0) { | 1132 | if (ret != 0) { |
1133 | dev_err(codec->dev, "Failed to stop FLL\n"); | 1133 | dev_err(component->dev, "Failed to stop FLL\n"); |
1134 | return ret; | 1134 | return ret; |
1135 | } | 1135 | } |
1136 | 1136 | ||
1137 | wm8900->fll_out = fll_out; | 1137 | wm8900->fll_out = fll_out; |
1138 | wm8900->fll_in = fll_in; | 1138 | wm8900->fll_in = fll_in; |
1139 | 1139 | ||
1140 | snd_soc_codec_force_bias_level(codec, SND_SOC_BIAS_OFF); | 1140 | snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF); |
1141 | 1141 | ||
1142 | return 0; | 1142 | return 0; |
1143 | } | 1143 | } |
1144 | 1144 | ||
1145 | static int wm8900_resume(struct snd_soc_codec *codec) | 1145 | static int wm8900_resume(struct snd_soc_component *component) |
1146 | { | 1146 | { |
1147 | struct wm8900_priv *wm8900 = snd_soc_codec_get_drvdata(codec); | 1147 | struct wm8900_priv *wm8900 = snd_soc_component_get_drvdata(component); |
1148 | int ret; | 1148 | int ret; |
1149 | 1149 | ||
1150 | wm8900_reset(codec); | 1150 | wm8900_reset(component); |
1151 | 1151 | ||
1152 | ret = regcache_sync(wm8900->regmap); | 1152 | ret = regcache_sync(wm8900->regmap); |
1153 | if (ret != 0) { | 1153 | if (ret != 0) { |
1154 | dev_err(codec->dev, "Failed to restore cache: %d\n", ret); | 1154 | dev_err(component->dev, "Failed to restore cache: %d\n", ret); |
1155 | return ret; | 1155 | return ret; |
1156 | } | 1156 | } |
1157 | 1157 | ||
1158 | snd_soc_codec_force_bias_level(codec, SND_SOC_BIAS_STANDBY); | 1158 | snd_soc_component_force_bias_level(component, SND_SOC_BIAS_STANDBY); |
1159 | 1159 | ||
1160 | /* Restart the FLL? */ | 1160 | /* Restart the FLL? */ |
1161 | if (wm8900->fll_out) { | 1161 | if (wm8900->fll_out) { |
@@ -1165,9 +1165,9 @@ static int wm8900_resume(struct snd_soc_codec *codec) | |||
1165 | wm8900->fll_in = 0; | 1165 | wm8900->fll_in = 0; |
1166 | wm8900->fll_out = 0; | 1166 | wm8900->fll_out = 0; |
1167 | 1167 | ||
1168 | ret = wm8900_set_fll(codec, 0, fll_in, fll_out); | 1168 | ret = wm8900_set_fll(component, 0, fll_in, fll_out); |
1169 | if (ret != 0) { | 1169 | if (ret != 0) { |
1170 | dev_err(codec->dev, "Failed to restart FLL\n"); | 1170 | dev_err(component->dev, "Failed to restart FLL\n"); |
1171 | return ret; | 1171 | return ret; |
1172 | } | 1172 | } |
1173 | } | 1173 | } |
@@ -1175,53 +1175,54 @@ static int wm8900_resume(struct snd_soc_codec *codec) | |||
1175 | return 0; | 1175 | return 0; |
1176 | } | 1176 | } |
1177 | 1177 | ||
1178 | static int wm8900_probe(struct snd_soc_codec *codec) | 1178 | static int wm8900_probe(struct snd_soc_component *component) |
1179 | { | 1179 | { |
1180 | int reg; | 1180 | int reg; |
1181 | 1181 | ||
1182 | reg = snd_soc_read(codec, WM8900_REG_ID); | 1182 | reg = snd_soc_component_read32(component, WM8900_REG_ID); |
1183 | if (reg != 0x8900) { | 1183 | if (reg != 0x8900) { |
1184 | dev_err(codec->dev, "Device is not a WM8900 - ID %x\n", reg); | 1184 | dev_err(component->dev, "Device is not a WM8900 - ID %x\n", reg); |
1185 | return -ENODEV; | 1185 | return -ENODEV; |
1186 | } | 1186 | } |
1187 | 1187 | ||
1188 | wm8900_reset(codec); | 1188 | wm8900_reset(component); |
1189 | 1189 | ||
1190 | /* Turn the chip on */ | 1190 | /* Turn the chip on */ |
1191 | snd_soc_codec_force_bias_level(codec, SND_SOC_BIAS_STANDBY); | 1191 | snd_soc_component_force_bias_level(component, SND_SOC_BIAS_STANDBY); |
1192 | 1192 | ||
1193 | /* Latch the volume update bits */ | 1193 | /* Latch the volume update bits */ |
1194 | snd_soc_update_bits(codec, WM8900_REG_LINVOL, 0x100, 0x100); | 1194 | snd_soc_component_update_bits(component, WM8900_REG_LINVOL, 0x100, 0x100); |
1195 | snd_soc_update_bits(codec, WM8900_REG_RINVOL, 0x100, 0x100); | 1195 | snd_soc_component_update_bits(component, WM8900_REG_RINVOL, 0x100, 0x100); |
1196 | snd_soc_update_bits(codec, WM8900_REG_LOUT1CTL, 0x100, 0x100); | 1196 | snd_soc_component_update_bits(component, WM8900_REG_LOUT1CTL, 0x100, 0x100); |
1197 | snd_soc_update_bits(codec, WM8900_REG_ROUT1CTL, 0x100, 0x100); | 1197 | snd_soc_component_update_bits(component, WM8900_REG_ROUT1CTL, 0x100, 0x100); |
1198 | snd_soc_update_bits(codec, WM8900_REG_LOUT2CTL, 0x100, 0x100); | 1198 | snd_soc_component_update_bits(component, WM8900_REG_LOUT2CTL, 0x100, 0x100); |
1199 | snd_soc_update_bits(codec, WM8900_REG_ROUT2CTL, 0x100, 0x100); | 1199 | snd_soc_component_update_bits(component, WM8900_REG_ROUT2CTL, 0x100, 0x100); |
1200 | snd_soc_update_bits(codec, WM8900_REG_LDAC_DV, 0x100, 0x100); | 1200 | snd_soc_component_update_bits(component, WM8900_REG_LDAC_DV, 0x100, 0x100); |
1201 | snd_soc_update_bits(codec, WM8900_REG_RDAC_DV, 0x100, 0x100); | 1201 | snd_soc_component_update_bits(component, WM8900_REG_RDAC_DV, 0x100, 0x100); |
1202 | snd_soc_update_bits(codec, WM8900_REG_LADC_DV, 0x100, 0x100); | 1202 | snd_soc_component_update_bits(component, WM8900_REG_LADC_DV, 0x100, 0x100); |
1203 | snd_soc_update_bits(codec, WM8900_REG_RADC_DV, 0x100, 0x100); | 1203 | snd_soc_component_update_bits(component, WM8900_REG_RADC_DV, 0x100, 0x100); |
1204 | 1204 | ||
1205 | /* Set the DAC and mixer output bias */ | 1205 | /* Set the DAC and mixer output bias */ |
1206 | snd_soc_write(codec, WM8900_REG_OUTBIASCTL, 0x81); | 1206 | snd_soc_component_write(component, WM8900_REG_OUTBIASCTL, 0x81); |
1207 | 1207 | ||
1208 | return 0; | 1208 | return 0; |
1209 | } | 1209 | } |
1210 | 1210 | ||
1211 | static const struct snd_soc_codec_driver soc_codec_dev_wm8900 = { | 1211 | static const struct snd_soc_component_driver soc_component_dev_wm8900 = { |
1212 | .probe = wm8900_probe, | 1212 | .probe = wm8900_probe, |
1213 | .suspend = wm8900_suspend, | 1213 | .suspend = wm8900_suspend, |
1214 | .resume = wm8900_resume, | 1214 | .resume = wm8900_resume, |
1215 | .set_bias_level = wm8900_set_bias_level, | 1215 | .set_bias_level = wm8900_set_bias_level, |
1216 | 1216 | .controls = wm8900_snd_controls, | |
1217 | .component_driver = { | 1217 | .num_controls = ARRAY_SIZE(wm8900_snd_controls), |
1218 | .controls = wm8900_snd_controls, | 1218 | .dapm_widgets = wm8900_dapm_widgets, |
1219 | .num_controls = ARRAY_SIZE(wm8900_snd_controls), | 1219 | .num_dapm_widgets = ARRAY_SIZE(wm8900_dapm_widgets), |
1220 | .dapm_widgets = wm8900_dapm_widgets, | 1220 | .dapm_routes = wm8900_dapm_routes, |
1221 | .num_dapm_widgets = ARRAY_SIZE(wm8900_dapm_widgets), | 1221 | .num_dapm_routes = ARRAY_SIZE(wm8900_dapm_routes), |
1222 | .dapm_routes = wm8900_dapm_routes, | 1222 | .idle_bias_on = 1, |
1223 | .num_dapm_routes = ARRAY_SIZE(wm8900_dapm_routes), | 1223 | .use_pmdown_time = 1, |
1224 | }, | 1224 | .endianness = 1, |
1225 | .non_legacy_dai_naming = 1, | ||
1225 | }; | 1226 | }; |
1226 | 1227 | ||
1227 | static const struct regmap_config wm8900_regmap = { | 1228 | static const struct regmap_config wm8900_regmap = { |
@@ -1253,15 +1254,14 @@ static int wm8900_spi_probe(struct spi_device *spi) | |||
1253 | 1254 | ||
1254 | spi_set_drvdata(spi, wm8900); | 1255 | spi_set_drvdata(spi, wm8900); |
1255 | 1256 | ||
1256 | ret = snd_soc_register_codec(&spi->dev, | 1257 | ret = devm_snd_soc_register_component(&spi->dev, |
1257 | &soc_codec_dev_wm8900, &wm8900_dai, 1); | 1258 | &soc_component_dev_wm8900, &wm8900_dai, 1); |
1258 | 1259 | ||
1259 | return ret; | 1260 | return ret; |
1260 | } | 1261 | } |
1261 | 1262 | ||
1262 | static int wm8900_spi_remove(struct spi_device *spi) | 1263 | static int wm8900_spi_remove(struct spi_device *spi) |
1263 | { | 1264 | { |
1264 | snd_soc_unregister_codec(&spi->dev); | ||
1265 | return 0; | 1265 | return 0; |
1266 | } | 1266 | } |
1267 | 1267 | ||
@@ -1292,15 +1292,14 @@ static int wm8900_i2c_probe(struct i2c_client *i2c, | |||
1292 | 1292 | ||
1293 | i2c_set_clientdata(i2c, wm8900); | 1293 | i2c_set_clientdata(i2c, wm8900); |
1294 | 1294 | ||
1295 | ret = snd_soc_register_codec(&i2c->dev, | 1295 | ret = devm_snd_soc_register_component(&i2c->dev, |
1296 | &soc_codec_dev_wm8900, &wm8900_dai, 1); | 1296 | &soc_component_dev_wm8900, &wm8900_dai, 1); |
1297 | 1297 | ||
1298 | return ret; | 1298 | return ret; |
1299 | } | 1299 | } |
1300 | 1300 | ||
1301 | static int wm8900_i2c_remove(struct i2c_client *client) | 1301 | static int wm8900_i2c_remove(struct i2c_client *client) |
1302 | { | 1302 | { |
1303 | snd_soc_unregister_codec(&client->dev); | ||
1304 | return 0; | 1303 | return 0; |
1305 | } | 1304 | } |
1306 | 1305 | ||