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authorLinus Torvalds <torvalds@linux-foundation.org>2014-08-13 20:23:32 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2014-08-13 20:23:32 -0400
commit81c02a21b293faecab725f691d709111831e1944 (patch)
tree146d41d8ff3ad03dca611b8fa8ab03c46c5d8978
parentd27c0d90184a13e9e9f28c38e84f889a259f6b5f (diff)
parent3eec595235c17a74094daa1e02d1b0af2e9a7125 (diff)
Merge branch 'x86-apic-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86/apic updates from Thomas Gleixner: "This is a major overhaul to the x86 apic subsystem consisting of the following parts: - Remove obsolete APIC driver abstractions (David Rientjes) - Use the irqdomain facilities to dynamically allocate IRQs for IOAPICs. This is a prerequisite to enable IOAPIC hotplug support, and it also frees up wasted vectors (Jiang Liu) - Misc fixlets. Despite the hickup in Ingos previous pull request - caused by the missing fixup for the suspend/resume issue reported by Borislav - I strongly recommend that this update finds its way into 3.17. Some history for you: This is preparatory work for physical IOAPIC hotplug. The first attempt to support this was done by Yinghai and I shot it down because it just added another layer of obscurity and complexity to the already existing mess without tackling the underlying shortcomings of the current implementation. After quite some on- and offlist discussions, I requested that the design of this functionality must use generic infrastructure, i.e. irq domains, which provide all the mechanisms to dynamically map linux interrupt numbers to physical interrupts. Jiang picked up the idea and did a great job of consolidating the existing interfaces to manage the x86 (IOAPIC) interrupt system by utilizing irq domains. The testing in tip, Linux-next and inside of Intel on various machines did not unearth any oddities until Borislav exposed it to one of his oddball machines. The issue was resolved quickly, but unfortunately the fix fell through the cracks and did not hit the tip tree before Ingo sent the pull request. Not entirely Ingos fault, I also assumed that the fix was already merged when Ingo asked me whether he could send it. Nevertheless this work has a proper design, has undergone several rounds of review and the final fallout after applying it to tip and integrating it into Linux-next has been more than moderate. It's the ground work not only for IOAPIC hotplug, it will also allow us to move the lowlevel vector allocation into the irqdomain hierarchy, which will benefit other architectures as well. Patches are posted already, but they are on hold for two weeks, see below. I really appreciate the competence and responsiveness Jiang has shown in course of this endavour. So I'm sure that any fallout of this will be addressed in a timely manner. FYI, I'm vanishing for 2 weeks into my annual kids summer camp kitchen duty^Wvacation, while you folks are drooling at KS/LinuxCon :) But HPA will have a look at the hopefully zero fallout until I'm back" * 'x86-apic-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (53 commits) x86, irq, PCI: Keep IRQ assignment for PCI devices during suspend/hibernation x86/apic/vsmp: Make is_vsmp_box() static x86, apic: Remove enable_apic_mode callback x86, apic: Remove setup_portio_remap callback x86, apic: Remove multi_timer_check callback x86, apic: Replace noop_check_apicid_used x86, apic: Remove check_apicid_present callback x86, apic: Remove mps_oem_check callback x86, apic: Remove smp_callin_clear_local_apic callback x86, apic: Replace trampoline physical addresses with defaults x86, apic: Remove x86_32_numa_cpu_node callback x86: intel-mid: Use the new io_apic interfaces x86, vsmp: Remove is_vsmp_box() from apic_is_clustered_box() x86, irq: Clean up irqdomain transition code x86, irq, devicetree: Release IOAPIC pin when PCI device is disabled x86, irq, SFI: Release IOAPIC pin when PCI device is disabled x86, irq, mpparse: Release IOAPIC pin when PCI device is disabled x86, irq, ACPI: Release IOAPIC pin when PCI device is disabled x86, irq: Introduce helper functions to release IOAPIC pin x86, irq: Simplify the way to handle ISA IRQ ...
Diffstat
-rw-r--r--arch/x86/Kconfig2
-rw-r--r--arch/x86/include/asm/apic.h46
-rw-r--r--arch/x86/include/asm/hardirq.h3
-rw-r--r--arch/x86/include/asm/i8259.h5
-rw-r--r--arch/x86/include/asm/io_apic.h56
-rw-r--r--arch/x86/include/asm/mpspec.h15
-rw-r--r--arch/x86/include/asm/prom.h2
-rw-r--r--arch/x86/include/asm/smpboot_hooks.h10
-rw-r--r--arch/x86/kernel/acpi/boot.c400
-rw-r--r--arch/x86/kernel/apic/apic.c75
-rw-r--r--arch/x86/kernel/apic/apic_flat_64.c16
-rw-r--r--arch/x86/kernel/apic/apic_noop.c23
-rw-r--r--arch/x86/kernel/apic/apic_numachip.c8
-rw-r--r--arch/x86/kernel/apic/bigsmp_32.c14
-rw-r--r--arch/x86/kernel/apic/io_apic.c759
-rw-r--r--arch/x86/kernel/apic/probe_32.c33
-rw-r--r--arch/x86/kernel/apic/x2apic_cluster.c8
-rw-r--r--arch/x86/kernel/apic/x2apic_phys.c8
-rw-r--r--arch/x86/kernel/apic/x2apic_uv_x.c8
-rw-r--r--arch/x86/kernel/devicetree.c207
-rw-r--r--arch/x86/kernel/irqinit.c12
-rw-r--r--arch/x86/kernel/mpparse.c111
-rw-r--r--arch/x86/kernel/smpboot.c8
-rw-r--r--arch/x86/kernel/vsmp_64.c4
-rw-r--r--arch/x86/pci/acpi.c6
-rw-r--r--arch/x86/pci/intel_mid_pci.c27
-rw-r--r--arch/x86/pci/irq.c16
-rw-r--r--arch/x86/pci/xen.c7
-rw-r--r--arch/x86/platform/ce4100/ce4100.c11
-rw-r--r--arch/x86/platform/intel-mid/device_libs/platform_wdt.c22
-rw-r--r--arch/x86/platform/intel-mid/sfi.c56
-rw-r--r--arch/x86/platform/sfi/sfi.c10
-rw-r--r--drivers/acpi/pci_irq.c7
33 files changed, 918 insertions, 1077 deletions
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 7a7208f16ec3..5d0bf1aa9dcb 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -434,6 +434,7 @@ config X86_INTEL_CE
434 bool "CE4100 TV platform" 434 bool "CE4100 TV platform"
435 depends on PCI 435 depends on PCI
436 depends on PCI_GODIRECT 436 depends on PCI_GODIRECT
437 depends on X86_IO_APIC
437 depends on X86_32 438 depends on X86_32
438 depends on X86_EXTENDED_PLATFORM 439 depends on X86_EXTENDED_PLATFORM
439 select X86_REBOOTFIXUPS 440 select X86_REBOOTFIXUPS
@@ -840,6 +841,7 @@ config X86_IO_APIC
840 def_bool y 841 def_bool y
841 depends on X86_64 || SMP || X86_32_NON_STANDARD || X86_UP_IOAPIC || PCI_MSI 842 depends on X86_64 || SMP || X86_32_NON_STANDARD || X86_UP_IOAPIC || PCI_MSI
842 select GENERIC_IRQ_LEGACY_ALLOC_HWIRQ 843 select GENERIC_IRQ_LEGACY_ALLOC_HWIRQ
844 select IRQ_DOMAIN
843 845
844config X86_REROUTE_FOR_BROKEN_BOOT_IRQS 846config X86_REROUTE_FOR_BROKEN_BOOT_IRQS
845 bool "Reroute for broken boot IRQs" 847 bool "Reroute for broken boot IRQs"
diff --git a/arch/x86/include/asm/apic.h b/arch/x86/include/asm/apic.h
index 79752f2bdec5..465b309af254 100644
--- a/arch/x86/include/asm/apic.h
+++ b/arch/x86/include/asm/apic.h
@@ -85,14 +85,6 @@ static inline bool apic_from_smp_config(void)
85#include <asm/paravirt.h> 85#include <asm/paravirt.h>
86#endif 86#endif
87 87
88#ifdef CONFIG_X86_64
89extern int is_vsmp_box(void);
90#else
91static inline int is_vsmp_box(void)
92{
93 return 0;
94}
95#endif
96extern int setup_profiling_timer(unsigned int); 88extern int setup_profiling_timer(unsigned int);
97 89
98static inline void native_apic_mem_write(u32 reg, u32 v) 90static inline void native_apic_mem_write(u32 reg, u32 v)
@@ -300,7 +292,6 @@ struct apic {
300 292
301 int dest_logical; 293 int dest_logical;
302 unsigned long (*check_apicid_used)(physid_mask_t *map, int apicid); 294 unsigned long (*check_apicid_used)(physid_mask_t *map, int apicid);
303 unsigned long (*check_apicid_present)(int apicid);
304 295
305 void (*vector_allocation_domain)(int cpu, struct cpumask *retmask, 296 void (*vector_allocation_domain)(int cpu, struct cpumask *retmask,
306 const struct cpumask *mask); 297 const struct cpumask *mask);
@@ -309,21 +300,11 @@ struct apic {
309 void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap); 300 void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap);
310 301
311 void (*setup_apic_routing)(void); 302 void (*setup_apic_routing)(void);
312 int (*multi_timer_check)(int apic, int irq);
313 int (*cpu_present_to_apicid)(int mps_cpu); 303 int (*cpu_present_to_apicid)(int mps_cpu);
314 void (*apicid_to_cpu_present)(int phys_apicid, physid_mask_t *retmap); 304 void (*apicid_to_cpu_present)(int phys_apicid, physid_mask_t *retmap);
315 void (*setup_portio_remap)(void);
316 int (*check_phys_apicid_present)(int phys_apicid); 305 int (*check_phys_apicid_present)(int phys_apicid);
317 void (*enable_apic_mode)(void);
318 int (*phys_pkg_id)(int cpuid_apic, int index_msb); 306 int (*phys_pkg_id)(int cpuid_apic, int index_msb);
319 307
320 /*
321 * When one of the next two hooks returns 1 the apic
322 * is switched to this. Essentially they are additional
323 * probe functions:
324 */
325 int (*mps_oem_check)(struct mpc_table *mpc, char *oem, char *productid);
326
327 unsigned int (*get_apic_id)(unsigned long x); 308 unsigned int (*get_apic_id)(unsigned long x);
328 unsigned long (*set_apic_id)(unsigned int id); 309 unsigned long (*set_apic_id)(unsigned int id);
329 unsigned long apic_id_mask; 310 unsigned long apic_id_mask;
@@ -343,11 +324,7 @@ struct apic {
343 /* wakeup_secondary_cpu */ 324 /* wakeup_secondary_cpu */
344 int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip); 325 int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip);
345 326
346 int trampoline_phys_low;
347 int trampoline_phys_high;
348
349 bool wait_for_init_deassert; 327 bool wait_for_init_deassert;
350 void (*smp_callin_clear_local_apic)(void);
351 void (*inquire_remote_apic)(int apicid); 328 void (*inquire_remote_apic)(int apicid);
352 329
353 /* apic ops */ 330 /* apic ops */
@@ -378,14 +355,6 @@ struct apic {
378 * won't be applied properly during early boot in this case. 355 * won't be applied properly during early boot in this case.
379 */ 356 */
380 int (*x86_32_early_logical_apicid)(int cpu); 357 int (*x86_32_early_logical_apicid)(int cpu);
381
382 /*
383 * Optional method called from setup_local_APIC() after logical
384 * apicid is guaranteed to be known to initialize apicid -> node
385 * mapping if NUMA initialization hasn't done so already. Don't
386 * add new users.
387 */
388 int (*x86_32_numa_cpu_node)(int cpu);
389#endif 358#endif
390}; 359};
391 360
@@ -496,14 +465,12 @@ static inline unsigned default_get_apic_id(unsigned long x)
496} 465}
497 466
498/* 467/*
499 * Warm reset vector default position: 468 * Warm reset vector position:
500 */ 469 */
501#define DEFAULT_TRAMPOLINE_PHYS_LOW 0x467 470#define TRAMPOLINE_PHYS_LOW 0x467
502#define DEFAULT_TRAMPOLINE_PHYS_HIGH 0x469 471#define TRAMPOLINE_PHYS_HIGH 0x469
503 472
504#ifdef CONFIG_X86_64 473#ifdef CONFIG_X86_64
505extern int default_acpi_madt_oem_check(char *, char *);
506
507extern void apic_send_IPI_self(int vector); 474extern void apic_send_IPI_self(int vector);
508 475
509DECLARE_PER_CPU(int, x2apic_extra_bits); 476DECLARE_PER_CPU(int, x2apic_extra_bits);
@@ -552,6 +519,8 @@ static inline int default_apic_id_valid(int apicid)
552 return (apicid < 255); 519 return (apicid < 255);
553} 520}
554 521
522extern int default_acpi_madt_oem_check(char *, char *);
523
555extern void default_setup_apic_routing(void); 524extern void default_setup_apic_routing(void);
556 525
557extern struct apic apic_noop; 526extern struct apic apic_noop;
@@ -635,11 +604,6 @@ static inline unsigned long default_check_apicid_used(physid_mask_t *map, int ap
635 return physid_isset(apicid, *map); 604 return physid_isset(apicid, *map);
636} 605}
637 606
638static inline unsigned long default_check_apicid_present(int bit)
639{
640 return physid_isset(bit, phys_cpu_present_map);
641}
642
643static inline void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap) 607static inline void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap)
644{ 608{
645 *retmap = *phys_map; 609 *retmap = *phys_map;
diff --git a/arch/x86/include/asm/hardirq.h b/arch/x86/include/asm/hardirq.h
index 230853da4ec0..0f5fb6b6567e 100644
--- a/arch/x86/include/asm/hardirq.h
+++ b/arch/x86/include/asm/hardirq.h
@@ -40,9 +40,6 @@ typedef struct {
40 40
41DECLARE_PER_CPU_SHARED_ALIGNED(irq_cpustat_t, irq_stat); 41DECLARE_PER_CPU_SHARED_ALIGNED(irq_cpustat_t, irq_stat);
42 42
43/* We can have at most NR_VECTORS irqs routed to a cpu at a time */
44#define MAX_HARDIRQS_PER_CPU NR_VECTORS
45
46#define __ARCH_IRQ_STAT 43#define __ARCH_IRQ_STAT
47 44
48#define inc_irq_stat(member) this_cpu_inc(irq_stat.member) 45#define inc_irq_stat(member) this_cpu_inc(irq_stat.member)
diff --git a/arch/x86/include/asm/i8259.h b/arch/x86/include/asm/i8259.h
index a20365953bf8..ccffa53750a8 100644
--- a/arch/x86/include/asm/i8259.h
+++ b/arch/x86/include/asm/i8259.h
@@ -67,4 +67,9 @@ struct legacy_pic {
67extern struct legacy_pic *legacy_pic; 67extern struct legacy_pic *legacy_pic;
68extern struct legacy_pic null_legacy_pic; 68extern struct legacy_pic null_legacy_pic;
69 69
70static inline int nr_legacy_irqs(void)
71{
72 return legacy_pic->nr_legacy_irqs;
73}
74
70#endif /* _ASM_X86_I8259_H */ 75#endif /* _ASM_X86_I8259_H */
diff --git a/arch/x86/include/asm/io_apic.h b/arch/x86/include/asm/io_apic.h
index 90f97b4b9347..0aeed5ca356e 100644
--- a/arch/x86/include/asm/io_apic.h
+++ b/arch/x86/include/asm/io_apic.h
@@ -98,6 +98,8 @@ struct IR_IO_APIC_route_entry {
98#define IOAPIC_AUTO -1 98#define IOAPIC_AUTO -1
99#define IOAPIC_EDGE 0 99#define IOAPIC_EDGE 0
100#define IOAPIC_LEVEL 1 100#define IOAPIC_LEVEL 1
101#define IOAPIC_MAP_ALLOC 0x1
102#define IOAPIC_MAP_CHECK 0x2
101 103
102#ifdef CONFIG_X86_IO_APIC 104#ifdef CONFIG_X86_IO_APIC
103 105
@@ -118,9 +120,6 @@ extern int mp_irq_entries;
118/* MP IRQ source entries */ 120/* MP IRQ source entries */
119extern struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES]; 121extern struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
120 122
121/* non-0 if default (table-less) MP configuration */
122extern int mpc_default_type;
123
124/* Older SiS APIC requires we rewrite the index register */ 123/* Older SiS APIC requires we rewrite the index register */
125extern int sis_apic_bug; 124extern int sis_apic_bug;
126 125
@@ -133,9 +132,6 @@ extern int noioapicquirk;
133/* -1 if "noapic" boot option passed */ 132/* -1 if "noapic" boot option passed */
134extern int noioapicreroute; 133extern int noioapicreroute;
135 134
136/* 1 if the timer IRQ uses the '8259A Virtual Wire' mode */
137extern int timer_through_8259;
138
139/* 135/*
140 * If we use the IO-APIC for IRQ routing, disable automatic 136 * If we use the IO-APIC for IRQ routing, disable automatic
141 * assignment of PCI IRQ's. 137 * assignment of PCI IRQ's.
@@ -145,24 +141,17 @@ extern int timer_through_8259;
145 141
146struct io_apic_irq_attr; 142struct io_apic_irq_attr;
147struct irq_cfg; 143struct irq_cfg;
148extern int io_apic_set_pci_routing(struct device *dev, int irq,
149 struct io_apic_irq_attr *irq_attr);
150void setup_IO_APIC_irq_extra(u32 gsi);
151extern void ioapic_insert_resources(void); 144extern void ioapic_insert_resources(void);
152 145
153extern int native_setup_ioapic_entry(int, struct IO_APIC_route_entry *, 146extern int native_setup_ioapic_entry(int, struct IO_APIC_route_entry *,
154 unsigned int, int, 147 unsigned int, int,
155 struct io_apic_irq_attr *); 148 struct io_apic_irq_attr *);
156extern int native_setup_ioapic_entry(int, struct IO_APIC_route_entry *,
157 unsigned int, int,
158 struct io_apic_irq_attr *);
159extern void eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg); 149extern void eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg);
160 150
161extern void native_compose_msi_msg(struct pci_dev *pdev, 151extern void native_compose_msi_msg(struct pci_dev *pdev,
162 unsigned int irq, unsigned int dest, 152 unsigned int irq, unsigned int dest,
163 struct msi_msg *msg, u8 hpet_id); 153 struct msi_msg *msg, u8 hpet_id);
164extern void native_eoi_ioapic_pin(int apic, int pin, int vector); 154extern void native_eoi_ioapic_pin(int apic, int pin, int vector);
165int io_apic_setup_irq_pin_once(unsigned int irq, int node, struct io_apic_irq_attr *attr);
166 155
167extern int save_ioapic_entries(void); 156extern int save_ioapic_entries(void);
168extern void mask_ioapic_entries(void); 157extern void mask_ioapic_entries(void);
@@ -171,15 +160,40 @@ extern int restore_ioapic_entries(void);
171extern void setup_ioapic_ids_from_mpc(void); 160extern void setup_ioapic_ids_from_mpc(void);
172extern void setup_ioapic_ids_from_mpc_nocheck(void); 161extern void setup_ioapic_ids_from_mpc_nocheck(void);
173 162
163enum ioapic_domain_type {
164 IOAPIC_DOMAIN_INVALID,
165 IOAPIC_DOMAIN_LEGACY,
166 IOAPIC_DOMAIN_STRICT,
167 IOAPIC_DOMAIN_DYNAMIC,
168};
169
170struct device_node;
171struct irq_domain;
172struct irq_domain_ops;
173
174struct ioapic_domain_cfg {
175 enum ioapic_domain_type type;
176 const struct irq_domain_ops *ops;
177 struct device_node *dev;
178};
179
174struct mp_ioapic_gsi{ 180struct mp_ioapic_gsi{
175 u32 gsi_base; 181 u32 gsi_base;
176 u32 gsi_end; 182 u32 gsi_end;
177}; 183};
178extern struct mp_ioapic_gsi mp_gsi_routing[];
179extern u32 gsi_top; 184extern u32 gsi_top;
180int mp_find_ioapic(u32 gsi); 185
181int mp_find_ioapic_pin(int ioapic, u32 gsi); 186extern int mp_find_ioapic(u32 gsi);
182void __init mp_register_ioapic(int id, u32 address, u32 gsi_base); 187extern int mp_find_ioapic_pin(int ioapic, u32 gsi);
188extern u32 mp_pin_to_gsi(int ioapic, int pin);
189extern int mp_map_gsi_to_irq(u32 gsi, unsigned int flags);
190extern void mp_unmap_irq(int irq);
191extern void __init mp_register_ioapic(int id, u32 address, u32 gsi_base,
192 struct ioapic_domain_cfg *cfg);
193extern int mp_irqdomain_map(struct irq_domain *domain, unsigned int virq,
194 irq_hw_number_t hwirq);
195extern void mp_irqdomain_unmap(struct irq_domain *domain, unsigned int virq);
196extern int mp_set_gsi_attr(u32 gsi, int trigger, int polarity, int node);
183extern void __init pre_init_apic_IRQ0(void); 197extern void __init pre_init_apic_IRQ0(void);
184 198
185extern void mp_save_irq(struct mpc_intsrc *m); 199extern void mp_save_irq(struct mpc_intsrc *m);
@@ -217,14 +231,12 @@ extern void io_apic_eoi(unsigned int apic, unsigned int vector);
217 231
218#define io_apic_assign_pci_irqs 0 232#define io_apic_assign_pci_irqs 0
219#define setup_ioapic_ids_from_mpc x86_init_noop 233#define setup_ioapic_ids_from_mpc x86_init_noop
220static const int timer_through_8259 = 0;
221static inline void ioapic_insert_resources(void) { } 234static inline void ioapic_insert_resources(void) { }
222#define gsi_top (NR_IRQS_LEGACY) 235#define gsi_top (NR_IRQS_LEGACY)
223static inline int mp_find_ioapic(u32 gsi) { return 0; } 236static inline int mp_find_ioapic(u32 gsi) { return 0; }
224 237static inline u32 mp_pin_to_gsi(int ioapic, int pin) { return UINT_MAX; }
225struct io_apic_irq_attr; 238static inline int mp_map_gsi_to_irq(u32 gsi, unsigned int flags) { return gsi; }
226static inline int io_apic_set_pci_routing(struct device *dev, int irq, 239static inline void mp_unmap_irq(int irq) { }
227 struct io_apic_irq_attr *irq_attr) { return 0; }
228 240
229static inline int save_ioapic_entries(void) 241static inline int save_ioapic_entries(void)
230{ 242{
diff --git a/arch/x86/include/asm/mpspec.h b/arch/x86/include/asm/mpspec.h
index f5a617956735..b07233b64578 100644
--- a/arch/x86/include/asm/mpspec.h
+++ b/arch/x86/include/asm/mpspec.h
@@ -40,8 +40,6 @@ extern int mp_bus_id_to_type[MAX_MP_BUSSES];
40extern DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); 40extern DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
41 41
42extern unsigned int boot_cpu_physical_apicid; 42extern unsigned int boot_cpu_physical_apicid;
43extern unsigned int max_physical_apicid;
44extern int mpc_default_type;
45extern unsigned long mp_lapic_addr; 43extern unsigned long mp_lapic_addr;
46 44
47#ifdef CONFIG_X86_LOCAL_APIC 45#ifdef CONFIG_X86_LOCAL_APIC
@@ -88,15 +86,6 @@ static inline void early_reserve_e820_mpc_new(void) { }
88#endif 86#endif
89 87
90int generic_processor_info(int apicid, int version); 88int generic_processor_info(int apicid, int version);
91#ifdef CONFIG_ACPI
92extern void mp_register_ioapic(int id, u32 address, u32 gsi_base);
93extern void mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger,
94 u32 gsi);
95extern void mp_config_acpi_legacy_irqs(void);
96struct device;
97extern int mp_register_gsi(struct device *dev, u32 gsi, int edge_level,
98 int active_high_low);
99#endif /* CONFIG_ACPI */
100 89
101#define PHYSID_ARRAY_SIZE BITS_TO_LONGS(MAX_LOCAL_APIC) 90#define PHYSID_ARRAY_SIZE BITS_TO_LONGS(MAX_LOCAL_APIC)
102 91
@@ -161,8 +150,4 @@ static inline void physid_set_mask_of_physid(int physid, physid_mask_t *map)
161 150
162extern physid_mask_t phys_cpu_present_map; 151extern physid_mask_t phys_cpu_present_map;
163 152
164extern int generic_mps_oem_check(struct mpc_table *, char *, char *);
165
166extern int default_acpi_madt_oem_check(char *, char *);
167
168#endif /* _ASM_X86_MPSPEC_H */ 153#endif /* _ASM_X86_MPSPEC_H */
diff --git a/arch/x86/include/asm/prom.h b/arch/x86/include/asm/prom.h
index fbeb06ed0eaa..1d081ac1cd69 100644
--- a/arch/x86/include/asm/prom.h
+++ b/arch/x86/include/asm/prom.h
@@ -26,12 +26,10 @@
26extern int of_ioapic; 26extern int of_ioapic;
27extern u64 initial_dtb; 27extern u64 initial_dtb;
28extern void add_dtb(u64 data); 28extern void add_dtb(u64 data);
29extern void x86_add_irq_domains(void);
30void x86_of_pci_init(void); 29void x86_of_pci_init(void);
31void x86_dtb_init(void); 30void x86_dtb_init(void);
32#else 31#else
33static inline void add_dtb(u64 data) { } 32static inline void add_dtb(u64 data) { }
34static inline void x86_add_irq_domains(void) { }
35static inline void x86_of_pci_init(void) { } 33static inline void x86_of_pci_init(void) { }
36static inline void x86_dtb_init(void) { } 34static inline void x86_dtb_init(void) { }
37#define of_ioapic 0 35#define of_ioapic 0
diff --git a/arch/x86/include/asm/smpboot_hooks.h b/arch/x86/include/asm/smpboot_hooks.h
index 49adfd7bb4a4..0da7409f0bec 100644
--- a/arch/x86/include/asm/smpboot_hooks.h
+++ b/arch/x86/include/asm/smpboot_hooks.h
@@ -17,11 +17,11 @@ static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip)
17 spin_unlock_irqrestore(&rtc_lock, flags); 17 spin_unlock_irqrestore(&rtc_lock, flags);
18 local_flush_tlb(); 18 local_flush_tlb();
19 pr_debug("1.\n"); 19 pr_debug("1.\n");
20 *((volatile unsigned short *)phys_to_virt(apic->trampoline_phys_high)) = 20 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) =
21 start_eip >> 4; 21 start_eip >> 4;
22 pr_debug("2.\n"); 22 pr_debug("2.\n");
23 *((volatile unsigned short *)phys_to_virt(apic->trampoline_phys_low)) = 23 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) =
24 start_eip & 0xf; 24 start_eip & 0xf;
25 pr_debug("3.\n"); 25 pr_debug("3.\n");
26} 26}
27 27
@@ -42,7 +42,7 @@ static inline void smpboot_restore_warm_reset_vector(void)
42 CMOS_WRITE(0, 0xf); 42 CMOS_WRITE(0, 0xf);
43 spin_unlock_irqrestore(&rtc_lock, flags); 43 spin_unlock_irqrestore(&rtc_lock, flags);
44 44
45 *((volatile u32 *)phys_to_virt(apic->trampoline_phys_low)) = 0; 45 *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0;
46} 46}
47 47
48static inline void __init smpboot_setup_io_apic(void) 48static inline void __init smpboot_setup_io_apic(void)
diff --git a/arch/x86/kernel/acpi/boot.c b/arch/x86/kernel/acpi/boot.c
index a531f6564ed0..b436fc735aa4 100644
--- a/arch/x86/kernel/acpi/boot.c
+++ b/arch/x86/kernel/acpi/boot.c
@@ -31,6 +31,7 @@
31#include <linux/module.h> 31#include <linux/module.h>
32#include <linux/dmi.h> 32#include <linux/dmi.h>
33#include <linux/irq.h> 33#include <linux/irq.h>
34#include <linux/irqdomain.h>
34#include <linux/slab.h> 35#include <linux/slab.h>
35#include <linux/bootmem.h> 36#include <linux/bootmem.h>
36#include <linux/ioport.h> 37#include <linux/ioport.h>
@@ -43,6 +44,7 @@
43#include <asm/io.h> 44#include <asm/io.h>
44#include <asm/mpspec.h> 45#include <asm/mpspec.h>
45#include <asm/smp.h> 46#include <asm/smp.h>
47#include <asm/i8259.h>
46 48
47#include "sleep.h" /* To include x86_acpi_suspend_lowlevel */ 49#include "sleep.h" /* To include x86_acpi_suspend_lowlevel */
48static int __initdata acpi_force = 0; 50static int __initdata acpi_force = 0;
@@ -93,44 +95,7 @@ static u32 isa_irq_to_gsi[NR_IRQS_LEGACY] __read_mostly = {
93 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 95 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
94}; 96};
95 97
96static unsigned int gsi_to_irq(unsigned int gsi) 98#define ACPI_INVALID_GSI INT_MIN
97{
98 unsigned int irq = gsi + NR_IRQS_LEGACY;
99 unsigned int i;
100
101 for (i = 0; i < NR_IRQS_LEGACY; i++) {
102 if (isa_irq_to_gsi[i] == gsi) {
103 return i;
104 }
105 }
106
107 /* Provide an identity mapping of gsi == irq
108 * except on truly weird platforms that have
109 * non isa irqs in the first 16 gsis.
110 */
111 if (gsi >= NR_IRQS_LEGACY)
112 irq = gsi;
113 else
114 irq = gsi_top + gsi;
115
116 return irq;
117}
118
119static u32 irq_to_gsi(int irq)
120{
121 unsigned int gsi;
122
123 if (irq < NR_IRQS_LEGACY)
124 gsi = isa_irq_to_gsi[irq];
125 else if (irq < gsi_top)
126 gsi = irq;
127 else if (irq < (gsi_top + NR_IRQS_LEGACY))
128 gsi = irq - gsi_top;
129 else
130 gsi = 0xffffffff;
131
132 return gsi;
133}
134 99
135/* 100/*
136 * This is just a simple wrapper around early_ioremap(), 101 * This is just a simple wrapper around early_ioremap(),
@@ -341,11 +306,145 @@ acpi_parse_lapic_nmi(struct acpi_subtable_header * header, const unsigned long e
341#endif /*CONFIG_X86_LOCAL_APIC */ 306#endif /*CONFIG_X86_LOCAL_APIC */
342 307
343#ifdef CONFIG_X86_IO_APIC 308#ifdef CONFIG_X86_IO_APIC
309#define MP_ISA_BUS 0
310
311static void __init mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger,
312 u32 gsi)
313{
314 int ioapic;
315 int pin;
316 struct mpc_intsrc mp_irq;
317
318 /*
319 * Convert 'gsi' to 'ioapic.pin'.
320 */
321 ioapic = mp_find_ioapic(gsi);
322 if (ioapic < 0)
323 return;
324 pin = mp_find_ioapic_pin(ioapic, gsi);
325
326 /*
327 * TBD: This check is for faulty timer entries, where the override
328 * erroneously sets the trigger to level, resulting in a HUGE
329 * increase of timer interrupts!
330 */
331 if ((bus_irq == 0) && (trigger == 3))
332 trigger = 1;
333
334 mp_irq.type = MP_INTSRC;
335 mp_irq.irqtype = mp_INT;
336 mp_irq.irqflag = (trigger << 2) | polarity;
337 mp_irq.srcbus = MP_ISA_BUS;
338 mp_irq.srcbusirq = bus_irq; /* IRQ */
339 mp_irq.dstapic = mpc_ioapic_id(ioapic); /* APIC ID */
340 mp_irq.dstirq = pin; /* INTIN# */
341
342 mp_save_irq(&mp_irq);
343
344 /*
345 * Reset default identity mapping if gsi is also an legacy IRQ,
346 * otherwise there will be more than one entry with the same GSI
347 * and acpi_isa_irq_to_gsi() may give wrong result.
348 */
349 if (gsi < nr_legacy_irqs() && isa_irq_to_gsi[gsi] == gsi)
350 isa_irq_to_gsi[gsi] = ACPI_INVALID_GSI;
351 isa_irq_to_gsi[bus_irq] = gsi;
352}
353
354static int mp_config_acpi_gsi(struct device *dev, u32 gsi, int trigger,
355 int polarity)
356{
357#ifdef CONFIG_X86_MPPARSE
358 struct mpc_intsrc mp_irq;
359 struct pci_dev *pdev;
360 unsigned char number;
361 unsigned int devfn;
362 int ioapic;
363 u8 pin;
364
365 if (!acpi_ioapic)
366 return 0;
367 if (!dev || !dev_is_pci(dev))
368 return 0;
369
370 pdev = to_pci_dev(dev);
371 number = pdev->bus->number;
372 devfn = pdev->devfn;
373 pin = pdev->pin;
374 /* print the entry should happen on mptable identically */
375 mp_irq.type = MP_INTSRC;
376 mp_irq.irqtype = mp_INT;
377 mp_irq.irqflag = (trigger == ACPI_EDGE_SENSITIVE ? 4 : 0x0c) |
378 (polarity == ACPI_ACTIVE_HIGH ? 1 : 3);
379 mp_irq.srcbus = number;
380 mp_irq.srcbusirq = (((devfn >> 3) & 0x1f) << 2) | ((pin - 1) & 3);
381 ioapic = mp_find_ioapic(gsi);
382 mp_irq.dstapic = mpc_ioapic_id(ioapic);
383 mp_irq.dstirq = mp_find_ioapic_pin(ioapic, gsi);
384
385 mp_save_irq(&mp_irq);
386#endif
387 return 0;
388}
389
390static int mp_register_gsi(struct device *dev, u32 gsi, int trigger,
391 int polarity)
392{
393 int irq, node;
394
395 if (acpi_irq_model != ACPI_IRQ_MODEL_IOAPIC)
396 return gsi;
397
398 /* Don't set up the ACPI SCI because it's already set up */
399 if (acpi_gbl_FADT.sci_interrupt == gsi)
400 return gsi;
401
402 trigger = trigger == ACPI_EDGE_SENSITIVE ? 0 : 1;
403 polarity = polarity == ACPI_ACTIVE_HIGH ? 0 : 1;
404 node = dev ? dev_to_node(dev) : NUMA_NO_NODE;
405 if (mp_set_gsi_attr(gsi, trigger, polarity, node)) {
406 pr_warn("Failed to set pin attr for GSI%d\n", gsi);
407 return -1;
408 }
409
410 irq = mp_map_gsi_to_irq(gsi, IOAPIC_MAP_ALLOC);
411 if (irq < 0)
412 return irq;
413
414 if (enable_update_mptable)
415 mp_config_acpi_gsi(dev, gsi, trigger, polarity);
416
417 return irq;
418}
419
420static void mp_unregister_gsi(u32 gsi)
421{
422 int irq;
423
424 if (acpi_irq_model != ACPI_IRQ_MODEL_IOAPIC)
425 return;
426
427 if (acpi_gbl_FADT.sci_interrupt == gsi)
428 return;
429
430 irq = mp_map_gsi_to_irq(gsi, 0);
431 if (irq > 0)
432 mp_unmap_irq(irq);
433}
434
435static struct irq_domain_ops acpi_irqdomain_ops = {
436 .map = mp_irqdomain_map,
437 .unmap = mp_irqdomain_unmap,
438};
344 439
345static int __init 440static int __init
346acpi_parse_ioapic(struct acpi_subtable_header * header, const unsigned long end) 441acpi_parse_ioapic(struct acpi_subtable_header * header, const unsigned long end)
347{ 442{
348 struct acpi_madt_io_apic *ioapic = NULL; 443 struct acpi_madt_io_apic *ioapic = NULL;
444 struct ioapic_domain_cfg cfg = {
445 .type = IOAPIC_DOMAIN_DYNAMIC,
446 .ops = &acpi_irqdomain_ops,
447 };
349 448
350 ioapic = (struct acpi_madt_io_apic *)header; 449 ioapic = (struct acpi_madt_io_apic *)header;
351 450
@@ -354,8 +453,12 @@ acpi_parse_ioapic(struct acpi_subtable_header * header, const unsigned long end)
354 453
355 acpi_table_print_madt_entry(header); 454 acpi_table_print_madt_entry(header);
356 455
357 mp_register_ioapic(ioapic->id, 456 /* Statically assign IRQ numbers for IOAPICs hosting legacy IRQs */
358 ioapic->address, ioapic->global_irq_base); 457 if (ioapic->global_irq_base < nr_legacy_irqs())
458 cfg.type = IOAPIC_DOMAIN_LEGACY;
459
460 mp_register_ioapic(ioapic->id, ioapic->address, ioapic->global_irq_base,
461 &cfg);
359 462
360 return 0; 463 return 0;
361} 464}
@@ -378,11 +481,6 @@ static void __init acpi_sci_ioapic_setup(u8 bus_irq, u16 polarity, u16 trigger,
378 if (acpi_sci_flags & ACPI_MADT_POLARITY_MASK) 481 if (acpi_sci_flags & ACPI_MADT_POLARITY_MASK)
379 polarity = acpi_sci_flags & ACPI_MADT_POLARITY_MASK; 482 polarity = acpi_sci_flags & ACPI_MADT_POLARITY_MASK;
380 483
381 /*
382 * mp_config_acpi_legacy_irqs() already setup IRQs < 16
383 * If GSI is < 16, this will update its flags,
384 * else it will create a new mp_irqs[] entry.
385 */
386 mp_override_legacy_irq(bus_irq, polarity, trigger, gsi); 484 mp_override_legacy_irq(bus_irq, polarity, trigger, gsi);
387 485
388 /* 486 /*
@@ -504,25 +602,28 @@ void __init acpi_pic_sci_set_trigger(unsigned int irq, u16 trigger)
504 outb(new >> 8, 0x4d1); 602 outb(new >> 8, 0x4d1);
505} 603}
506 604
507int acpi_gsi_to_irq(u32 gsi, unsigned int *irq) 605int acpi_gsi_to_irq(u32 gsi, unsigned int *irqp)
508{ 606{
509 *irq = gsi_to_irq(gsi); 607 int irq = mp_map_gsi_to_irq(gsi, IOAPIC_MAP_ALLOC | IOAPIC_MAP_CHECK);
510 608
511#ifdef CONFIG_X86_IO_APIC 609 if (irq >= 0) {
512 if (acpi_irq_model == ACPI_IRQ_MODEL_IOAPIC) 610 *irqp = irq;
513 setup_IO_APIC_irq_extra(gsi); 611 return 0;
514#endif 612 }
515 613
516 return 0; 614 return -1;
517} 615}
518EXPORT_SYMBOL_GPL(acpi_gsi_to_irq); 616EXPORT_SYMBOL_GPL(acpi_gsi_to_irq);
519 617
520int acpi_isa_irq_to_gsi(unsigned isa_irq, u32 *gsi) 618int acpi_isa_irq_to_gsi(unsigned isa_irq, u32 *gsi)
521{ 619{
522 if (isa_irq >= 16) 620 if (isa_irq < nr_legacy_irqs() &&
523 return -1; 621 isa_irq_to_gsi[isa_irq] != ACPI_INVALID_GSI) {
524 *gsi = irq_to_gsi(isa_irq); 622 *gsi = isa_irq_to_gsi[isa_irq];
525 return 0; 623 return 0;
624 }
625
626 return -1;
526} 627}
527 628
528static int acpi_register_gsi_pic(struct device *dev, u32 gsi, 629static int acpi_register_gsi_pic(struct device *dev, u32 gsi,
@@ -542,15 +643,25 @@ static int acpi_register_gsi_pic(struct device *dev, u32 gsi,
542static int acpi_register_gsi_ioapic(struct device *dev, u32 gsi, 643static int acpi_register_gsi_ioapic(struct device *dev, u32 gsi,
543 int trigger, int polarity) 644 int trigger, int polarity)
544{ 645{
646 int irq = gsi;
647
545#ifdef CONFIG_X86_IO_APIC 648#ifdef CONFIG_X86_IO_APIC
546 gsi = mp_register_gsi(dev, gsi, trigger, polarity); 649 irq = mp_register_gsi(dev, gsi, trigger, polarity);
547#endif 650#endif
548 651
549 return gsi; 652 return irq;
653}
654
655static void acpi_unregister_gsi_ioapic(u32 gsi)
656{
657#ifdef CONFIG_X86_IO_APIC
658 mp_unregister_gsi(gsi);
659#endif
550} 660}
551 661
552int (*__acpi_register_gsi)(struct device *dev, u32 gsi, 662int (*__acpi_register_gsi)(struct device *dev, u32 gsi,
553 int trigger, int polarity) = acpi_register_gsi_pic; 663 int trigger, int polarity) = acpi_register_gsi_pic;
664void (*__acpi_unregister_gsi)(u32 gsi) = NULL;
554 665
555#ifdef CONFIG_ACPI_SLEEP 666#ifdef CONFIG_ACPI_SLEEP
556int (*acpi_suspend_lowlevel)(void) = x86_acpi_suspend_lowlevel; 667int (*acpi_suspend_lowlevel)(void) = x86_acpi_suspend_lowlevel;
@@ -564,32 +675,22 @@ int (*acpi_suspend_lowlevel)(void);
564 */ 675 */
565int acpi_register_gsi(struct device *dev, u32 gsi, int trigger, int polarity) 676int acpi_register_gsi(struct device *dev, u32 gsi, int trigger, int polarity)
566{ 677{
567 unsigned int irq; 678 return __acpi_register_gsi(dev, gsi, trigger, polarity);
568 unsigned int plat_gsi = gsi;
569
570 plat_gsi = (*__acpi_register_gsi)(dev, gsi, trigger, polarity);
571 irq = gsi_to_irq(plat_gsi);
572
573 return irq;
574} 679}
575EXPORT_SYMBOL_GPL(acpi_register_gsi); 680EXPORT_SYMBOL_GPL(acpi_register_gsi);
576 681
577void acpi_unregister_gsi(u32 gsi) 682void acpi_unregister_gsi(u32 gsi)
578{ 683{
684 if (__acpi_unregister_gsi)
685 __acpi_unregister_gsi(gsi);
579} 686}
580EXPORT_SYMBOL_GPL(acpi_unregister_gsi); 687EXPORT_SYMBOL_GPL(acpi_unregister_gsi);
581 688
582void __init acpi_set_irq_model_pic(void) 689static void __init acpi_set_irq_model_ioapic(void)
583{
584 acpi_irq_model = ACPI_IRQ_MODEL_PIC;
585 __acpi_register_gsi = acpi_register_gsi_pic;
586 acpi_ioapic = 0;
587}
588
589void __init acpi_set_irq_model_ioapic(void)
590{ 690{
591 acpi_irq_model = ACPI_IRQ_MODEL_IOAPIC; 691 acpi_irq_model = ACPI_IRQ_MODEL_IOAPIC;
592 __acpi_register_gsi = acpi_register_gsi_ioapic; 692 __acpi_register_gsi = acpi_register_gsi_ioapic;
693 __acpi_unregister_gsi = acpi_unregister_gsi_ioapic;
593 acpi_ioapic = 1; 694 acpi_ioapic = 1;
594} 695}
595 696
@@ -825,9 +926,8 @@ static int __init early_acpi_parse_madt_lapic_addr_ovr(void)
825 * and (optionally) overriden by a LAPIC_ADDR_OVR entry (64-bit value). 926 * and (optionally) overriden by a LAPIC_ADDR_OVR entry (64-bit value).
826 */ 927 */
827 928
828 count = 929 count = acpi_table_parse_madt(ACPI_MADT_TYPE_LOCAL_APIC_OVERRIDE,
829 acpi_table_parse_madt(ACPI_MADT_TYPE_LOCAL_APIC_OVERRIDE, 930 acpi_parse_lapic_addr_ovr, 0);
830 acpi_parse_lapic_addr_ovr, 0);
831 if (count < 0) { 931 if (count < 0) {
832 printk(KERN_ERR PREFIX 932 printk(KERN_ERR PREFIX
833 "Error parsing LAPIC address override entry\n"); 933 "Error parsing LAPIC address override entry\n");
@@ -852,9 +952,8 @@ static int __init acpi_parse_madt_lapic_entries(void)
852 * and (optionally) overriden by a LAPIC_ADDR_OVR entry (64-bit value). 952 * and (optionally) overriden by a LAPIC_ADDR_OVR entry (64-bit value).
853 */ 953 */
854 954
855 count = 955 count = acpi_table_parse_madt(ACPI_MADT_TYPE_LOCAL_APIC_OVERRIDE,
856 acpi_table_parse_madt(ACPI_MADT_TYPE_LOCAL_APIC_OVERRIDE, 956 acpi_parse_lapic_addr_ovr, 0);
857 acpi_parse_lapic_addr_ovr, 0);
858 if (count < 0) { 957 if (count < 0) {
859 printk(KERN_ERR PREFIX 958 printk(KERN_ERR PREFIX
860 "Error parsing LAPIC address override entry\n"); 959 "Error parsing LAPIC address override entry\n");
@@ -882,11 +981,10 @@ static int __init acpi_parse_madt_lapic_entries(void)
882 return count; 981 return count;
883 } 982 }
884 983
885 x2count = 984 x2count = acpi_table_parse_madt(ACPI_MADT_TYPE_LOCAL_X2APIC_NMI,
886 acpi_table_parse_madt(ACPI_MADT_TYPE_LOCAL_X2APIC_NMI, 985 acpi_parse_x2apic_nmi, 0);
887 acpi_parse_x2apic_nmi, 0); 986 count = acpi_table_parse_madt(ACPI_MADT_TYPE_LOCAL_APIC_NMI,
888 count = 987 acpi_parse_lapic_nmi, 0);
889 acpi_table_parse_madt(ACPI_MADT_TYPE_LOCAL_APIC_NMI, acpi_parse_lapic_nmi, 0);
890 if (count < 0 || x2count < 0) { 988 if (count < 0 || x2count < 0) {
891 printk(KERN_ERR PREFIX "Error parsing LAPIC NMI entry\n"); 989 printk(KERN_ERR PREFIX "Error parsing LAPIC NMI entry\n");
892 /* TBD: Cleanup to allow fallback to MPS */ 990 /* TBD: Cleanup to allow fallback to MPS */
@@ -897,44 +995,7 @@ static int __init acpi_parse_madt_lapic_entries(void)
897#endif /* CONFIG_X86_LOCAL_APIC */ 995#endif /* CONFIG_X86_LOCAL_APIC */
898 996
899#ifdef CONFIG_X86_IO_APIC 997#ifdef CONFIG_X86_IO_APIC
900#define MP_ISA_BUS 0 998static void __init mp_config_acpi_legacy_irqs(void)
901
902void __init mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger, u32 gsi)
903{
904 int ioapic;
905 int pin;
906 struct mpc_intsrc mp_irq;
907
908 /*
909 * Convert 'gsi' to 'ioapic.pin'.
910 */
911 ioapic = mp_find_ioapic(gsi);
912 if (ioapic < 0)
913 return;
914 pin = mp_find_ioapic_pin(ioapic, gsi);
915
916 /*
917 * TBD: This check is for faulty timer entries, where the override
918 * erroneously sets the trigger to level, resulting in a HUGE
919 * increase of timer interrupts!
920 */
921 if ((bus_irq == 0) && (trigger == 3))
922 trigger = 1;
923
924 mp_irq.type = MP_INTSRC;
925 mp_irq.irqtype = mp_INT;
926 mp_irq.irqflag = (trigger << 2) | polarity;
927 mp_irq.srcbus = MP_ISA_BUS;
928 mp_irq.srcbusirq = bus_irq; /* IRQ */
929 mp_irq.dstapic = mpc_ioapic_id(ioapic); /* APIC ID */
930 mp_irq.dstirq = pin; /* INTIN# */
931
932 mp_save_irq(&mp_irq);
933
934 isa_irq_to_gsi[bus_irq] = gsi;
935}
936
937void __init mp_config_acpi_legacy_irqs(void)
938{ 999{
939 int i; 1000 int i;
940 struct mpc_intsrc mp_irq; 1001 struct mpc_intsrc mp_irq;
@@ -952,7 +1013,7 @@ void __init mp_config_acpi_legacy_irqs(void)
952 * Use the default configuration for the IRQs 0-15. Unless 1013 * Use the default configuration for the IRQs 0-15. Unless
953 * overridden by (MADT) interrupt source override entries. 1014 * overridden by (MADT) interrupt source override entries.
954 */ 1015 */
955 for (i = 0; i < 16; i++) { 1016 for (i = 0; i < nr_legacy_irqs(); i++) {
956 int ioapic, pin; 1017 int ioapic, pin;
957 unsigned int dstapic; 1018 unsigned int dstapic;
958 int idx; 1019 int idx;
@@ -1000,84 +1061,6 @@ void __init mp_config_acpi_legacy_irqs(void)
1000 } 1061 }
1001} 1062}
1002 1063
1003static int mp_config_acpi_gsi(struct device *dev, u32 gsi, int trigger,
1004 int polarity)
1005{
1006#ifdef CONFIG_X86_MPPARSE
1007 struct mpc_intsrc mp_irq;
1008 struct pci_dev *pdev;
1009 unsigned char number;
1010 unsigned int devfn;
1011 int ioapic;
1012 u8 pin;
1013
1014 if (!acpi_ioapic)
1015 return 0;
1016 if (!dev || !dev_is_pci(dev))
1017 return 0;
1018
1019 pdev = to_pci_dev(dev);
1020 number = pdev->bus->number;
1021 devfn = pdev->devfn;
1022 pin = pdev->pin;
1023 /* print the entry should happen on mptable identically */
1024 mp_irq.type = MP_INTSRC;
1025 mp_irq.irqtype = mp_INT;
1026 mp_irq.irqflag = (trigger == ACPI_EDGE_SENSITIVE ? 4 : 0x0c) |
1027 (polarity == ACPI_ACTIVE_HIGH ? 1 : 3);
1028 mp_irq.srcbus = number;
1029 mp_irq.srcbusirq = (((devfn >> 3) & 0x1f) << 2) | ((pin - 1) & 3);
1030 ioapic = mp_find_ioapic(gsi);
1031 mp_irq.dstapic = mpc_ioapic_id(ioapic);
1032 mp_irq.dstirq = mp_find_ioapic_pin(ioapic, gsi);
1033
1034 mp_save_irq(&mp_irq);
1035#endif
1036 return 0;
1037}
1038
1039int mp_register_gsi(struct device *dev, u32 gsi, int trigger, int polarity)
1040{
1041 int ioapic;
1042 int ioapic_pin;
1043 struct io_apic_irq_attr irq_attr;
1044 int ret;
1045
1046 if (acpi_irq_model != ACPI_IRQ_MODEL_IOAPIC)
1047 return gsi;
1048
1049 /* Don't set up the ACPI SCI because it's already set up */
1050 if (acpi_gbl_FADT.sci_interrupt == gsi)
1051 return gsi;
1052
1053 ioapic = mp_find_ioapic(gsi);
1054 if (ioapic < 0) {
1055 printk(KERN_WARNING "No IOAPIC for GSI %u\n", gsi);
1056 return gsi;
1057 }
1058
1059 ioapic_pin = mp_find_ioapic_pin(ioapic, gsi);
1060
1061 if (ioapic_pin > MP_MAX_IOAPIC_PIN) {
1062 printk(KERN_ERR "Invalid reference to IOAPIC pin "
1063 "%d-%d\n", mpc_ioapic_id(ioapic),
1064 ioapic_pin);
1065 return gsi;
1066 }
1067
1068 if (enable_update_mptable)
1069 mp_config_acpi_gsi(dev, gsi, trigger, polarity);
1070
1071 set_io_apic_irq_attr(&irq_attr, ioapic, ioapic_pin,
1072 trigger == ACPI_EDGE_SENSITIVE ? 0 : 1,
1073 polarity == ACPI_ACTIVE_HIGH ? 0 : 1);
1074 ret = io_apic_set_pci_routing(dev, gsi_to_irq(gsi), &irq_attr);
1075 if (ret < 0)
1076 gsi = INT_MIN;
1077
1078 return gsi;
1079}
1080
1081/* 1064/*
1082 * Parse IOAPIC related entries in MADT 1065 * Parse IOAPIC related entries in MADT
1083 * returns 0 on success, < 0 on error 1066 * returns 0 on success, < 0 on error
@@ -1107,9 +1090,8 @@ static int __init acpi_parse_madt_ioapic_entries(void)
1107 return -ENODEV; 1090 return -ENODEV;
1108 } 1091 }
1109 1092
1110 count = 1093 count = acpi_table_parse_madt(ACPI_MADT_TYPE_IO_APIC, acpi_parse_ioapic,
1111 acpi_table_parse_madt(ACPI_MADT_TYPE_IO_APIC, acpi_parse_ioapic, 1094 MAX_IO_APICS);
1112 MAX_IO_APICS);
1113 if (!count) { 1095 if (!count) {
1114 printk(KERN_ERR PREFIX "No IOAPIC entries present\n"); 1096 printk(KERN_ERR PREFIX "No IOAPIC entries present\n");
1115 return -ENODEV; 1097 return -ENODEV;
@@ -1118,9 +1100,8 @@ static int __init acpi_parse_madt_ioapic_entries(void)
1118 return count; 1100 return count;
1119 } 1101 }
1120 1102
1121 count = 1103 count = acpi_table_parse_madt(ACPI_MADT_TYPE_INTERRUPT_OVERRIDE,
1122 acpi_table_parse_madt(ACPI_MADT_TYPE_INTERRUPT_OVERRIDE, acpi_parse_int_src_ovr, 1104 acpi_parse_int_src_ovr, nr_irqs);
1123 nr_irqs);
1124 if (count < 0) { 1105 if (count < 0) {
1125 printk(KERN_ERR PREFIX 1106 printk(KERN_ERR PREFIX
1126 "Error parsing interrupt source overrides entry\n"); 1107 "Error parsing interrupt source overrides entry\n");
@@ -1139,9 +1120,8 @@ static int __init acpi_parse_madt_ioapic_entries(void)
1139 /* Fill in identity legacy mappings where no override */ 1120 /* Fill in identity legacy mappings where no override */
1140 mp_config_acpi_legacy_irqs(); 1121 mp_config_acpi_legacy_irqs();
1141 1122
1142 count = 1123 count = acpi_table_parse_madt(ACPI_MADT_TYPE_NMI_SOURCE,
1143 acpi_table_parse_madt(ACPI_MADT_TYPE_NMI_SOURCE, acpi_parse_nmi_src, 1124 acpi_parse_nmi_src, nr_irqs);
1144 nr_irqs);
1145 if (count < 0) { 1125 if (count < 0) {
1146 printk(KERN_ERR PREFIX "Error parsing NMI SRC entry\n"); 1126 printk(KERN_ERR PREFIX "Error parsing NMI SRC entry\n");
1147 /* TBD: Cleanup to allow fallback to MPS */ 1127 /* TBD: Cleanup to allow fallback to MPS */
diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
index ad28db7e6bde..67760275544b 100644
--- a/arch/x86/kernel/apic/apic.c
+++ b/arch/x86/kernel/apic/apic.c
@@ -67,7 +67,7 @@ EXPORT_SYMBOL_GPL(boot_cpu_physical_apicid);
67/* 67/*
68 * The highest APIC ID seen during enumeration. 68 * The highest APIC ID seen during enumeration.
69 */ 69 */
70unsigned int max_physical_apicid; 70static unsigned int max_physical_apicid;
71 71
72/* 72/*
73 * Bitmask of physically existing CPUs: 73 * Bitmask of physically existing CPUs:
@@ -1342,17 +1342,6 @@ void setup_local_APIC(void)
1342 /* always use the value from LDR */ 1342 /* always use the value from LDR */
1343 early_per_cpu(x86_cpu_to_logical_apicid, cpu) = 1343 early_per_cpu(x86_cpu_to_logical_apicid, cpu) =
1344 logical_smp_processor_id(); 1344 logical_smp_processor_id();
1345
1346 /*
1347 * Some NUMA implementations (NUMAQ) don't initialize apicid to
1348 * node mapping during NUMA init. Now that logical apicid is
1349 * guaranteed to be known, give it another chance. This is already
1350 * a bit too late - percpu allocation has already happened without
1351 * proper NUMA affinity.
1352 */
1353 if (apic->x86_32_numa_cpu_node)
1354 set_apicid_to_node(early_per_cpu(x86_cpu_to_apicid, cpu),
1355 apic->x86_32_numa_cpu_node(cpu));
1356#endif 1345#endif
1357 1346
1358 /* 1347 /*
@@ -2053,8 +2042,6 @@ void __init connect_bsp_APIC(void)
2053 imcr_pic_to_apic(); 2042 imcr_pic_to_apic();
2054 } 2043 }
2055#endif 2044#endif
2056 if (apic->enable_apic_mode)
2057 apic->enable_apic_mode();
2058} 2045}
2059 2046
2060/** 2047/**
@@ -2451,51 +2438,6 @@ static void apic_pm_activate(void) { }
2451 2438
2452#ifdef CONFIG_X86_64 2439#ifdef CONFIG_X86_64
2453 2440
2454static int apic_cluster_num(void)
2455{
2456 int i, clusters, zeros;
2457 unsigned id;
2458 u16 *bios_cpu_apicid;
2459 DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS);
2460
2461 bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid);
2462 bitmap_zero(clustermap, NUM_APIC_CLUSTERS);
2463
2464 for (i = 0; i < nr_cpu_ids; i++) {
2465 /* are we being called early in kernel startup? */
2466 if (bios_cpu_apicid) {
2467 id = bios_cpu_apicid[i];
2468 } else if (i < nr_cpu_ids) {
2469 if (cpu_present(i))
2470 id = per_cpu(x86_bios_cpu_apicid, i);
2471 else
2472 continue;
2473 } else
2474 break;
2475
2476 if (id != BAD_APICID)
2477 __set_bit(APIC_CLUSTERID(id), clustermap);
2478 }
2479
2480 /* Problem: Partially populated chassis may not have CPUs in some of
2481 * the APIC clusters they have been allocated. Only present CPUs have
2482 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
2483 * Since clusters are allocated sequentially, count zeros only if
2484 * they are bounded by ones.
2485 */
2486 clusters = 0;
2487 zeros = 0;
2488 for (i = 0; i < NUM_APIC_CLUSTERS; i++) {
2489 if (test_bit(i, clustermap)) {
2490 clusters += 1 + zeros;
2491 zeros = 0;
2492 } else
2493 ++zeros;
2494 }
2495
2496 return clusters;
2497}
2498
2499static int multi_checked; 2441static int multi_checked;
2500static int multi; 2442static int multi;
2501 2443
@@ -2540,20 +2482,7 @@ static void dmi_check_multi(void)
2540int apic_is_clustered_box(void) 2482int apic_is_clustered_box(void)
2541{ 2483{
2542 dmi_check_multi(); 2484 dmi_check_multi();
2543 if (multi) 2485 return multi;
2544 return 1;
2545
2546 if (!is_vsmp_box())
2547 return 0;
2548
2549 /*
2550 * ScaleMP vSMPowered boxes have one cluster per board and TSCs are
2551 * not guaranteed to be synced between boards
2552 */
2553 if (apic_cluster_num() > 1)
2554 return 1;
2555
2556 return 0;
2557} 2486}
2558#endif 2487#endif
2559 2488
diff --git a/arch/x86/kernel/apic/apic_flat_64.c b/arch/x86/kernel/apic/apic_flat_64.c
index 7c1b29479513..de918c410eae 100644
--- a/arch/x86/kernel/apic/apic_flat_64.c
+++ b/arch/x86/kernel/apic/apic_flat_64.c
@@ -168,21 +168,16 @@ static struct apic apic_flat = {
168 .disable_esr = 0, 168 .disable_esr = 0,
169 .dest_logical = APIC_DEST_LOGICAL, 169 .dest_logical = APIC_DEST_LOGICAL,
170 .check_apicid_used = NULL, 170 .check_apicid_used = NULL,
171 .check_apicid_present = NULL,
172 171
173 .vector_allocation_domain = flat_vector_allocation_domain, 172 .vector_allocation_domain = flat_vector_allocation_domain,
174 .init_apic_ldr = flat_init_apic_ldr, 173 .init_apic_ldr = flat_init_apic_ldr,
175 174
176 .ioapic_phys_id_map = NULL, 175 .ioapic_phys_id_map = NULL,
177 .setup_apic_routing = NULL, 176 .setup_apic_routing = NULL,
178 .multi_timer_check = NULL,
179 .cpu_present_to_apicid = default_cpu_present_to_apicid, 177 .cpu_present_to_apicid = default_cpu_present_to_apicid,
180 .apicid_to_cpu_present = NULL, 178 .apicid_to_cpu_present = NULL,
181 .setup_portio_remap = NULL,
182 .check_phys_apicid_present = default_check_phys_apicid_present, 179 .check_phys_apicid_present = default_check_phys_apicid_present,
183 .enable_apic_mode = NULL,
184 .phys_pkg_id = flat_phys_pkg_id, 180 .phys_pkg_id = flat_phys_pkg_id,
185 .mps_oem_check = NULL,
186 181
187 .get_apic_id = flat_get_apic_id, 182 .get_apic_id = flat_get_apic_id,
188 .set_apic_id = set_apic_id, 183 .set_apic_id = set_apic_id,
@@ -196,10 +191,7 @@ static struct apic apic_flat = {
196 .send_IPI_all = flat_send_IPI_all, 191 .send_IPI_all = flat_send_IPI_all,
197 .send_IPI_self = apic_send_IPI_self, 192 .send_IPI_self = apic_send_IPI_self,
198 193
199 .trampoline_phys_low = DEFAULT_TRAMPOLINE_PHYS_LOW,
200 .trampoline_phys_high = DEFAULT_TRAMPOLINE_PHYS_HIGH,
201 .wait_for_init_deassert = false, 194 .wait_for_init_deassert = false,
202 .smp_callin_clear_local_apic = NULL,
203 .inquire_remote_apic = default_inquire_remote_apic, 195 .inquire_remote_apic = default_inquire_remote_apic,
204 196
205 .read = native_apic_mem_read, 197 .read = native_apic_mem_read,
@@ -283,7 +275,6 @@ static struct apic apic_physflat = {
283 .disable_esr = 0, 275 .disable_esr = 0,
284 .dest_logical = 0, 276 .dest_logical = 0,
285 .check_apicid_used = NULL, 277 .check_apicid_used = NULL,
286 .check_apicid_present = NULL,
287 278
288 .vector_allocation_domain = default_vector_allocation_domain, 279 .vector_allocation_domain = default_vector_allocation_domain,
289 /* not needed, but shouldn't hurt: */ 280 /* not needed, but shouldn't hurt: */
@@ -291,14 +282,10 @@ static struct apic apic_physflat = {
291 282
292 .ioapic_phys_id_map = NULL, 283 .ioapic_phys_id_map = NULL,
293 .setup_apic_routing = NULL, 284 .setup_apic_routing = NULL,
294 .multi_timer_check = NULL,
295 .cpu_present_to_apicid = default_cpu_present_to_apicid, 285 .cpu_present_to_apicid = default_cpu_present_to_apicid,
296 .apicid_to_cpu_present = NULL, 286 .apicid_to_cpu_present = NULL,
297 .setup_portio_remap = NULL,
298 .check_phys_apicid_present = default_check_phys_apicid_present, 287 .check_phys_apicid_present = default_check_phys_apicid_present,
299 .enable_apic_mode = NULL,
300 .phys_pkg_id = flat_phys_pkg_id, 288 .phys_pkg_id = flat_phys_pkg_id,
301 .mps_oem_check = NULL,
302 289
303 .get_apic_id = flat_get_apic_id, 290 .get_apic_id = flat_get_apic_id,
304 .set_apic_id = set_apic_id, 291 .set_apic_id = set_apic_id,
@@ -312,10 +299,7 @@ static struct apic apic_physflat = {
312 .send_IPI_all = physflat_send_IPI_all, 299 .send_IPI_all = physflat_send_IPI_all,
313 .send_IPI_self = apic_send_IPI_self, 300 .send_IPI_self = apic_send_IPI_self,
314 301
315 .trampoline_phys_low = DEFAULT_TRAMPOLINE_PHYS_LOW,
316 .trampoline_phys_high = DEFAULT_TRAMPOLINE_PHYS_HIGH,
317 .wait_for_init_deassert = false, 302 .wait_for_init_deassert = false,
318 .smp_callin_clear_local_apic = NULL,
319 .inquire_remote_apic = default_inquire_remote_apic, 303 .inquire_remote_apic = default_inquire_remote_apic,
320 304
321 .read = native_apic_mem_read, 305 .read = native_apic_mem_read,
diff --git a/arch/x86/kernel/apic/apic_noop.c b/arch/x86/kernel/apic/apic_noop.c
index 8c7c98249c20..b205cdbdbe6a 100644
--- a/arch/x86/kernel/apic/apic_noop.c
+++ b/arch/x86/kernel/apic/apic_noop.c
@@ -89,16 +89,6 @@ static const struct cpumask *noop_target_cpus(void)
89 return cpumask_of(0); 89 return cpumask_of(0);
90} 90}
91 91
92static unsigned long noop_check_apicid_used(physid_mask_t *map, int apicid)
93{
94 return physid_isset(apicid, *map);
95}
96
97static unsigned long noop_check_apicid_present(int bit)
98{
99 return physid_isset(bit, phys_cpu_present_map);
100}
101
102static void noop_vector_allocation_domain(int cpu, struct cpumask *retmask, 92static void noop_vector_allocation_domain(int cpu, struct cpumask *retmask,
103 const struct cpumask *mask) 93 const struct cpumask *mask)
104{ 94{
@@ -133,27 +123,21 @@ struct apic apic_noop = {
133 .target_cpus = noop_target_cpus, 123 .target_cpus = noop_target_cpus,
134 .disable_esr = 0, 124 .disable_esr = 0,
135 .dest_logical = APIC_DEST_LOGICAL, 125 .dest_logical = APIC_DEST_LOGICAL,
136 .check_apicid_used = noop_check_apicid_used, 126 .check_apicid_used = default_check_apicid_used,
137 .check_apicid_present = noop_check_apicid_present,
138 127
139 .vector_allocation_domain = noop_vector_allocation_domain, 128 .vector_allocation_domain = noop_vector_allocation_domain,
140 .init_apic_ldr = noop_init_apic_ldr, 129 .init_apic_ldr = noop_init_apic_ldr,
141 130
142 .ioapic_phys_id_map = default_ioapic_phys_id_map, 131 .ioapic_phys_id_map = default_ioapic_phys_id_map,
143 .setup_apic_routing = NULL, 132 .setup_apic_routing = NULL,
144 .multi_timer_check = NULL,
145 133
146 .cpu_present_to_apicid = default_cpu_present_to_apicid, 134 .cpu_present_to_apicid = default_cpu_present_to_apicid,
147 .apicid_to_cpu_present = physid_set_mask_of_physid, 135 .apicid_to_cpu_present = physid_set_mask_of_physid,
148 136
149 .setup_portio_remap = NULL,
150 .check_phys_apicid_present = default_check_phys_apicid_present, 137 .check_phys_apicid_present = default_check_phys_apicid_present,
151 .enable_apic_mode = NULL,
152 138
153 .phys_pkg_id = noop_phys_pkg_id, 139 .phys_pkg_id = noop_phys_pkg_id,
154 140
155 .mps_oem_check = NULL,
156
157 .get_apic_id = noop_get_apic_id, 141 .get_apic_id = noop_get_apic_id,
158 .set_apic_id = NULL, 142 .set_apic_id = NULL,
159 .apic_id_mask = 0x0F << 24, 143 .apic_id_mask = 0x0F << 24,
@@ -168,12 +152,7 @@ struct apic apic_noop = {
168 152
169 .wakeup_secondary_cpu = noop_wakeup_secondary_cpu, 153 .wakeup_secondary_cpu = noop_wakeup_secondary_cpu,
170 154
171 /* should be safe */
172 .trampoline_phys_low = DEFAULT_TRAMPOLINE_PHYS_LOW,
173 .trampoline_phys_high = DEFAULT_TRAMPOLINE_PHYS_HIGH,
174
175 .wait_for_init_deassert = false, 155 .wait_for_init_deassert = false,
176 .smp_callin_clear_local_apic = NULL,
177 .inquire_remote_apic = NULL, 156 .inquire_remote_apic = NULL,
178 157
179 .read = noop_apic_read, 158 .read = noop_apic_read,
diff --git a/arch/x86/kernel/apic/apic_numachip.c b/arch/x86/kernel/apic/apic_numachip.c
index a5b45df8bc88..ae915391ebec 100644
--- a/arch/x86/kernel/apic/apic_numachip.c
+++ b/arch/x86/kernel/apic/apic_numachip.c
@@ -217,21 +217,16 @@ static const struct apic apic_numachip __refconst = {
217 .disable_esr = 0, 217 .disable_esr = 0,
218 .dest_logical = 0, 218 .dest_logical = 0,
219 .check_apicid_used = NULL, 219 .check_apicid_used = NULL,
220 .check_apicid_present = NULL,
221 220
222 .vector_allocation_domain = default_vector_allocation_domain, 221 .vector_allocation_domain = default_vector_allocation_domain,
223 .init_apic_ldr = flat_init_apic_ldr, 222 .init_apic_ldr = flat_init_apic_ldr,
224 223
225 .ioapic_phys_id_map = NULL, 224 .ioapic_phys_id_map = NULL,
226 .setup_apic_routing = NULL, 225 .setup_apic_routing = NULL,
227 .multi_timer_check = NULL,
228 .cpu_present_to_apicid = default_cpu_present_to_apicid, 226 .cpu_present_to_apicid = default_cpu_present_to_apicid,
229 .apicid_to_cpu_present = NULL, 227 .apicid_to_cpu_present = NULL,
230 .setup_portio_remap = NULL,
231 .check_phys_apicid_present = default_check_phys_apicid_present, 228 .check_phys_apicid_present = default_check_phys_apicid_present,
232 .enable_apic_mode = NULL,
233 .phys_pkg_id = numachip_phys_pkg_id, 229 .phys_pkg_id = numachip_phys_pkg_id,
234 .mps_oem_check = NULL,
235 230
236 .get_apic_id = get_apic_id, 231 .get_apic_id = get_apic_id,
237 .set_apic_id = set_apic_id, 232 .set_apic_id = set_apic_id,
@@ -246,10 +241,7 @@ static const struct apic apic_numachip __refconst = {
246 .send_IPI_self = numachip_send_IPI_self, 241 .send_IPI_self = numachip_send_IPI_self,
247 242
248 .wakeup_secondary_cpu = numachip_wakeup_secondary, 243 .wakeup_secondary_cpu = numachip_wakeup_secondary,
249 .trampoline_phys_low = DEFAULT_TRAMPOLINE_PHYS_LOW,
250 .trampoline_phys_high = DEFAULT_TRAMPOLINE_PHYS_HIGH,
251 .wait_for_init_deassert = false, 244 .wait_for_init_deassert = false,
252 .smp_callin_clear_local_apic = NULL,
253 .inquire_remote_apic = NULL, /* REMRD not supported */ 245 .inquire_remote_apic = NULL, /* REMRD not supported */
254 246
255 .read = native_apic_mem_read, 247 .read = native_apic_mem_read,
diff --git a/arch/x86/kernel/apic/bigsmp_32.c b/arch/x86/kernel/apic/bigsmp_32.c
index e4840aa7a255..c4a8d63f8220 100644
--- a/arch/x86/kernel/apic/bigsmp_32.c
+++ b/arch/x86/kernel/apic/bigsmp_32.c
@@ -31,11 +31,6 @@ static unsigned long bigsmp_check_apicid_used(physid_mask_t *map, int apicid)
31 return 0; 31 return 0;
32} 32}
33 33
34static unsigned long bigsmp_check_apicid_present(int bit)
35{
36 return 1;
37}
38
39static int bigsmp_early_logical_apicid(int cpu) 34static int bigsmp_early_logical_apicid(int cpu)
40{ 35{
41 /* on bigsmp, logical apicid is the same as physical */ 36 /* on bigsmp, logical apicid is the same as physical */
@@ -168,21 +163,16 @@ static struct apic apic_bigsmp = {
168 .disable_esr = 1, 163 .disable_esr = 1,
169 .dest_logical = 0, 164 .dest_logical = 0,
170 .check_apicid_used = bigsmp_check_apicid_used, 165 .check_apicid_used = bigsmp_check_apicid_used,
171 .check_apicid_present = bigsmp_check_apicid_present,
172 166
173 .vector_allocation_domain = default_vector_allocation_domain, 167 .vector_allocation_domain = default_vector_allocation_domain,
174 .init_apic_ldr = bigsmp_init_apic_ldr, 168 .init_apic_ldr = bigsmp_init_apic_ldr,
175 169
176 .ioapic_phys_id_map = bigsmp_ioapic_phys_id_map, 170 .ioapic_phys_id_map = bigsmp_ioapic_phys_id_map,
177 .setup_apic_routing = bigsmp_setup_apic_routing, 171 .setup_apic_routing = bigsmp_setup_apic_routing,
178 .multi_timer_check = NULL,
179 .cpu_present_to_apicid = bigsmp_cpu_present_to_apicid, 172 .cpu_present_to_apicid = bigsmp_cpu_present_to_apicid,
180 .apicid_to_cpu_present = physid_set_mask_of_physid, 173 .apicid_to_cpu_present = physid_set_mask_of_physid,
181 .setup_portio_remap = NULL,
182 .check_phys_apicid_present = bigsmp_check_phys_apicid_present, 174 .check_phys_apicid_present = bigsmp_check_phys_apicid_present,
183 .enable_apic_mode = NULL,
184 .phys_pkg_id = bigsmp_phys_pkg_id, 175 .phys_pkg_id = bigsmp_phys_pkg_id,
185 .mps_oem_check = NULL,
186 176
187 .get_apic_id = bigsmp_get_apic_id, 177 .get_apic_id = bigsmp_get_apic_id,
188 .set_apic_id = NULL, 178 .set_apic_id = NULL,
@@ -196,11 +186,7 @@ static struct apic apic_bigsmp = {
196 .send_IPI_all = bigsmp_send_IPI_all, 186 .send_IPI_all = bigsmp_send_IPI_all,
197 .send_IPI_self = default_send_IPI_self, 187 .send_IPI_self = default_send_IPI_self,
198 188
199 .trampoline_phys_low = DEFAULT_TRAMPOLINE_PHYS_LOW,
200 .trampoline_phys_high = DEFAULT_TRAMPOLINE_PHYS_HIGH,
201
202 .wait_for_init_deassert = true, 189 .wait_for_init_deassert = true,
203 .smp_callin_clear_local_apic = NULL,
204 .inquire_remote_apic = default_inquire_remote_apic, 190 .inquire_remote_apic = default_inquire_remote_apic,
205 191
206 .read = native_apic_mem_read, 192 .read = native_apic_mem_read,
diff --git a/arch/x86/kernel/apic/io_apic.c b/arch/x86/kernel/apic/io_apic.c
index 81e08eff05ee..29290f554e79 100644
--- a/arch/x86/kernel/apic/io_apic.c
+++ b/arch/x86/kernel/apic/io_apic.c
@@ -31,6 +31,7 @@
31#include <linux/acpi.h> 31#include <linux/acpi.h>
32#include <linux/module.h> 32#include <linux/module.h>
33#include <linux/syscore_ops.h> 33#include <linux/syscore_ops.h>
34#include <linux/irqdomain.h>
34#include <linux/msi.h> 35#include <linux/msi.h>
35#include <linux/htirq.h> 36#include <linux/htirq.h>
36#include <linux/freezer.h> 37#include <linux/freezer.h>
@@ -62,6 +63,16 @@
62 63
63#define __apicdebuginit(type) static type __init 64#define __apicdebuginit(type) static type __init
64 65
66#define for_each_ioapic(idx) \
67 for ((idx) = 0; (idx) < nr_ioapics; (idx)++)
68#define for_each_ioapic_reverse(idx) \
69 for ((idx) = nr_ioapics - 1; (idx) >= 0; (idx)--)
70#define for_each_pin(idx, pin) \
71 for ((pin) = 0; (pin) < ioapics[(idx)].nr_registers; (pin)++)
72#define for_each_ioapic_pin(idx, pin) \
73 for_each_ioapic((idx)) \
74 for_each_pin((idx), (pin))
75
65#define for_each_irq_pin(entry, head) \ 76#define for_each_irq_pin(entry, head) \
66 for (entry = head; entry; entry = entry->next) 77 for (entry = head; entry; entry = entry->next)
67 78
@@ -73,6 +84,17 @@ int sis_apic_bug = -1;
73 84
74static DEFINE_RAW_SPINLOCK(ioapic_lock); 85static DEFINE_RAW_SPINLOCK(ioapic_lock);
75static DEFINE_RAW_SPINLOCK(vector_lock); 86static DEFINE_RAW_SPINLOCK(vector_lock);
87static DEFINE_MUTEX(ioapic_mutex);
88static unsigned int ioapic_dynirq_base;
89static int ioapic_initialized;
90
91struct mp_pin_info {
92 int trigger;
93 int polarity;
94 int node;
95 int set;
96 u32 count;
97};
76 98
77static struct ioapic { 99static struct ioapic {
78 /* 100 /*
@@ -87,7 +109,9 @@ static struct ioapic {
87 struct mpc_ioapic mp_config; 109 struct mpc_ioapic mp_config;
88 /* IO APIC gsi routing info */ 110 /* IO APIC gsi routing info */
89 struct mp_ioapic_gsi gsi_config; 111 struct mp_ioapic_gsi gsi_config;
90 DECLARE_BITMAP(pin_programmed, MP_MAX_IOAPIC_PIN + 1); 112 struct ioapic_domain_cfg irqdomain_cfg;
113 struct irq_domain *irqdomain;
114 struct mp_pin_info *pin_info;
91} ioapics[MAX_IO_APICS]; 115} ioapics[MAX_IO_APICS];
92 116
93#define mpc_ioapic_ver(ioapic_idx) ioapics[ioapic_idx].mp_config.apicver 117#define mpc_ioapic_ver(ioapic_idx) ioapics[ioapic_idx].mp_config.apicver
@@ -107,6 +131,41 @@ struct mp_ioapic_gsi *mp_ioapic_gsi_routing(int ioapic_idx)
107 return &ioapics[ioapic_idx].gsi_config; 131 return &ioapics[ioapic_idx].gsi_config;
108} 132}
109 133
134static inline int mp_ioapic_pin_count(int ioapic)
135{
136 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(ioapic);
137
138 return gsi_cfg->gsi_end - gsi_cfg->gsi_base + 1;
139}
140
141u32 mp_pin_to_gsi(int ioapic, int pin)
142{
143 return mp_ioapic_gsi_routing(ioapic)->gsi_base + pin;
144}
145
146/*
147 * Initialize all legacy IRQs and all pins on the first IOAPIC
148 * if we have legacy interrupt controller. Kernel boot option "pirq="
149 * may rely on non-legacy pins on the first IOAPIC.
150 */
151static inline int mp_init_irq_at_boot(int ioapic, int irq)
152{
153 if (!nr_legacy_irqs())
154 return 0;
155
156 return ioapic == 0 || (irq >= 0 && irq < nr_legacy_irqs());
157}
158
159static inline struct mp_pin_info *mp_pin_info(int ioapic_idx, int pin)
160{
161 return ioapics[ioapic_idx].pin_info + pin;
162}
163
164static inline struct irq_domain *mp_ioapic_irqdomain(int ioapic)
165{
166 return ioapics[ioapic].irqdomain;
167}
168
110int nr_ioapics; 169int nr_ioapics;
111 170
112/* The one past the highest gsi number used */ 171/* The one past the highest gsi number used */
@@ -118,9 +177,6 @@ struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
118/* # of MP IRQ source entries */ 177/* # of MP IRQ source entries */
119int mp_irq_entries; 178int mp_irq_entries;
120 179
121/* GSI interrupts */
122static int nr_irqs_gsi = NR_IRQS_LEGACY;
123
124#ifdef CONFIG_EISA 180#ifdef CONFIG_EISA
125int mp_bus_id_to_type[MAX_MP_BUSSES]; 181int mp_bus_id_to_type[MAX_MP_BUSSES];
126#endif 182#endif
@@ -149,8 +205,7 @@ static int __init parse_noapic(char *str)
149} 205}
150early_param("noapic", parse_noapic); 206early_param("noapic", parse_noapic);
151 207
152static int io_apic_setup_irq_pin(unsigned int irq, int node, 208static struct irq_cfg *alloc_irq_and_cfg_at(unsigned int at, int node);
153 struct io_apic_irq_attr *attr);
154 209
155/* Will be called in mpparse/acpi/sfi codes for saving IRQ info */ 210/* Will be called in mpparse/acpi/sfi codes for saving IRQ info */
156void mp_save_irq(struct mpc_intsrc *m) 211void mp_save_irq(struct mpc_intsrc *m)
@@ -182,19 +237,15 @@ static struct irq_pin_list *alloc_irq_pin_list(int node)
182 return kzalloc_node(sizeof(struct irq_pin_list), GFP_KERNEL, node); 237 return kzalloc_node(sizeof(struct irq_pin_list), GFP_KERNEL, node);
183} 238}
184 239
185
186/* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
187static struct irq_cfg irq_cfgx[NR_IRQS_LEGACY];
188
189int __init arch_early_irq_init(void) 240int __init arch_early_irq_init(void)
190{ 241{
191 struct irq_cfg *cfg; 242 struct irq_cfg *cfg;
192 int count, node, i; 243 int i, node = cpu_to_node(0);
193 244
194 if (!legacy_pic->nr_legacy_irqs) 245 if (!nr_legacy_irqs())
195 io_apic_irqs = ~0UL; 246 io_apic_irqs = ~0UL;
196 247
197 for (i = 0; i < nr_ioapics; i++) { 248 for_each_ioapic(i) {
198 ioapics[i].saved_registers = 249 ioapics[i].saved_registers =
199 kzalloc(sizeof(struct IO_APIC_route_entry) * 250 kzalloc(sizeof(struct IO_APIC_route_entry) *
200 ioapics[i].nr_registers, GFP_KERNEL); 251 ioapics[i].nr_registers, GFP_KERNEL);
@@ -202,28 +253,20 @@ int __init arch_early_irq_init(void)
202 pr_err("IOAPIC %d: suspend/resume impossible!\n", i); 253 pr_err("IOAPIC %d: suspend/resume impossible!\n", i);
203 } 254 }
204 255
205 cfg = irq_cfgx; 256 /*
206 count = ARRAY_SIZE(irq_cfgx); 257 * For legacy IRQ's, start with assigning irq0 to irq15 to
207 node = cpu_to_node(0); 258 * IRQ0_VECTOR to IRQ15_VECTOR for all cpu's.
208 259 */
209 for (i = 0; i < count; i++) { 260 for (i = 0; i < nr_legacy_irqs(); i++) {
210 irq_set_chip_data(i, &cfg[i]); 261 cfg = alloc_irq_and_cfg_at(i, node);
211 zalloc_cpumask_var_node(&cfg[i].domain, GFP_KERNEL, node); 262 cfg->vector = IRQ0_VECTOR + i;
212 zalloc_cpumask_var_node(&cfg[i].old_domain, GFP_KERNEL, node); 263 cpumask_setall(cfg->domain);
213 /*
214 * For legacy IRQ's, start with assigning irq0 to irq15 to
215 * IRQ0_VECTOR to IRQ15_VECTOR for all cpu's.
216 */
217 if (i < legacy_pic->nr_legacy_irqs) {
218 cfg[i].vector = IRQ0_VECTOR + i;
219 cpumask_setall(cfg[i].domain);
220 }
221 } 264 }
222 265
223 return 0; 266 return 0;
224} 267}
225 268
226static struct irq_cfg *irq_cfg(unsigned int irq) 269static inline struct irq_cfg *irq_cfg(unsigned int irq)
227{ 270{
228 return irq_get_chip_data(irq); 271 return irq_get_chip_data(irq);
229} 272}
@@ -265,7 +308,7 @@ static struct irq_cfg *alloc_irq_and_cfg_at(unsigned int at, int node)
265 if (res < 0) { 308 if (res < 0) {
266 if (res != -EEXIST) 309 if (res != -EEXIST)
267 return NULL; 310 return NULL;
268 cfg = irq_get_chip_data(at); 311 cfg = irq_cfg(at);
269 if (cfg) 312 if (cfg)
270 return cfg; 313 return cfg;
271 } 314 }
@@ -425,6 +468,21 @@ static int __add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pi
425 return 0; 468 return 0;
426} 469}
427 470
471static void __remove_pin_from_irq(struct irq_cfg *cfg, int apic, int pin)
472{
473 struct irq_pin_list **last, *entry;
474
475 last = &cfg->irq_2_pin;
476 for_each_irq_pin(entry, cfg->irq_2_pin)
477 if (entry->apic == apic && entry->pin == pin) {
478 *last = entry->next;
479 kfree(entry);
480 return;
481 } else {
482 last = &entry->next;
483 }
484}
485
428static void add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin) 486static void add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin)
429{ 487{
430 if (__add_pin_to_irq_node(cfg, node, apic, pin)) 488 if (__add_pin_to_irq_node(cfg, node, apic, pin))
@@ -627,9 +685,8 @@ static void clear_IO_APIC (void)
627{ 685{
628 int apic, pin; 686 int apic, pin;
629 687
630 for (apic = 0; apic < nr_ioapics; apic++) 688 for_each_ioapic_pin(apic, pin)
631 for (pin = 0; pin < ioapics[apic].nr_registers; pin++) 689 clear_IO_APIC_pin(apic, pin);
632 clear_IO_APIC_pin(apic, pin);
633} 690}
634 691
635#ifdef CONFIG_X86_32 692#ifdef CONFIG_X86_32
@@ -678,13 +735,13 @@ int save_ioapic_entries(void)
678 int apic, pin; 735 int apic, pin;
679 int err = 0; 736 int err = 0;
680 737
681 for (apic = 0; apic < nr_ioapics; apic++) { 738 for_each_ioapic(apic) {
682 if (!ioapics[apic].saved_registers) { 739 if (!ioapics[apic].saved_registers) {
683 err = -ENOMEM; 740 err = -ENOMEM;
684 continue; 741 continue;
685 } 742 }
686 743
687 for (pin = 0; pin < ioapics[apic].nr_registers; pin++) 744 for_each_pin(apic, pin)
688 ioapics[apic].saved_registers[pin] = 745 ioapics[apic].saved_registers[pin] =
689 ioapic_read_entry(apic, pin); 746 ioapic_read_entry(apic, pin);
690 } 747 }
@@ -699,11 +756,11 @@ void mask_ioapic_entries(void)
699{ 756{
700 int apic, pin; 757 int apic, pin;
701 758
702 for (apic = 0; apic < nr_ioapics; apic++) { 759 for_each_ioapic(apic) {
703 if (!ioapics[apic].saved_registers) 760 if (!ioapics[apic].saved_registers)
704 continue; 761 continue;
705 762
706 for (pin = 0; pin < ioapics[apic].nr_registers; pin++) { 763 for_each_pin(apic, pin) {
707 struct IO_APIC_route_entry entry; 764 struct IO_APIC_route_entry entry;
708 765
709 entry = ioapics[apic].saved_registers[pin]; 766 entry = ioapics[apic].saved_registers[pin];
@@ -722,11 +779,11 @@ int restore_ioapic_entries(void)
722{ 779{
723 int apic, pin; 780 int apic, pin;
724 781
725 for (apic = 0; apic < nr_ioapics; apic++) { 782 for_each_ioapic(apic) {
726 if (!ioapics[apic].saved_registers) 783 if (!ioapics[apic].saved_registers)
727 continue; 784 continue;
728 785
729 for (pin = 0; pin < ioapics[apic].nr_registers; pin++) 786 for_each_pin(apic, pin)
730 ioapic_write_entry(apic, pin, 787 ioapic_write_entry(apic, pin,
731 ioapics[apic].saved_registers[pin]); 788 ioapics[apic].saved_registers[pin]);
732 } 789 }
@@ -785,7 +842,7 @@ static int __init find_isa_irq_apic(int irq, int type)
785 if (i < mp_irq_entries) { 842 if (i < mp_irq_entries) {
786 int ioapic_idx; 843 int ioapic_idx;
787 844
788 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++) 845 for_each_ioapic(ioapic_idx)
789 if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic) 846 if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic)
790 return ioapic_idx; 847 return ioapic_idx;
791 } 848 }
@@ -799,7 +856,7 @@ static int __init find_isa_irq_apic(int irq, int type)
799 */ 856 */
800static int EISA_ELCR(unsigned int irq) 857static int EISA_ELCR(unsigned int irq)
801{ 858{
802 if (irq < legacy_pic->nr_legacy_irqs) { 859 if (irq < nr_legacy_irqs()) {
803 unsigned int port = 0x4d0 + (irq >> 3); 860 unsigned int port = 0x4d0 + (irq >> 3);
804 return (inb(port) >> (irq & 7)) & 1; 861 return (inb(port) >> (irq & 7)) & 1;
805 } 862 }
@@ -939,29 +996,101 @@ static int irq_trigger(int idx)
939 return trigger; 996 return trigger;
940} 997}
941 998
942static int pin_2_irq(int idx, int apic, int pin) 999static int alloc_irq_from_domain(struct irq_domain *domain, u32 gsi, int pin)
1000{
1001 int irq = -1;
1002 int ioapic = (int)(long)domain->host_data;
1003 int type = ioapics[ioapic].irqdomain_cfg.type;
1004
1005 switch (type) {
1006 case IOAPIC_DOMAIN_LEGACY:
1007 /*
1008 * Dynamically allocate IRQ number for non-ISA IRQs in the first 16
1009 * GSIs on some weird platforms.
1010 */
1011 if (gsi < nr_legacy_irqs())
1012 irq = irq_create_mapping(domain, pin);
1013 else if (irq_create_strict_mappings(domain, gsi, pin, 1) == 0)
1014 irq = gsi;
1015 break;
1016 case IOAPIC_DOMAIN_STRICT:
1017 if (irq_create_strict_mappings(domain, gsi, pin, 1) == 0)
1018 irq = gsi;
1019 break;
1020 case IOAPIC_DOMAIN_DYNAMIC:
1021 irq = irq_create_mapping(domain, pin);
1022 break;
1023 default:
1024 WARN(1, "ioapic: unknown irqdomain type %d\n", type);
1025 break;
1026 }
1027
1028 return irq > 0 ? irq : -1;
1029}
1030
1031static int mp_map_pin_to_irq(u32 gsi, int idx, int ioapic, int pin,
1032 unsigned int flags)
943{ 1033{
944 int irq; 1034 int irq;
945 int bus = mp_irqs[idx].srcbus; 1035 struct irq_domain *domain = mp_ioapic_irqdomain(ioapic);
946 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(apic); 1036 struct mp_pin_info *info = mp_pin_info(ioapic, pin);
1037
1038 if (!domain)
1039 return -1;
1040
1041 mutex_lock(&ioapic_mutex);
947 1042
948 /* 1043 /*
949 * Debugging check, we are in big trouble if this message pops up! 1044 * Don't use irqdomain to manage ISA IRQs because there may be
1045 * multiple IOAPIC pins sharing the same ISA IRQ number and
1046 * irqdomain only supports 1:1 mapping between IOAPIC pin and
1047 * IRQ number. A typical IOAPIC has 24 pins, pin 0-15 are used
1048 * for legacy IRQs and pin 16-23 are used for PCI IRQs (PIRQ A-H).
1049 * When ACPI is disabled, only legacy IRQ numbers (IRQ0-15) are
1050 * available, and some BIOSes may use MP Interrupt Source records
1051 * to override IRQ numbers for PIRQs instead of reprogramming
1052 * the interrupt routing logic. Thus there may be multiple pins
1053 * sharing the same legacy IRQ number when ACPI is disabled.
950 */ 1054 */
951 if (mp_irqs[idx].dstirq != pin) 1055 if (idx >= 0 && test_bit(mp_irqs[idx].srcbus, mp_bus_not_pci)) {
952 pr_err("broken BIOS or MPTABLE parser, ayiee!!\n");
953
954 if (test_bit(bus, mp_bus_not_pci)) {
955 irq = mp_irqs[idx].srcbusirq; 1056 irq = mp_irqs[idx].srcbusirq;
1057 if (flags & IOAPIC_MAP_ALLOC) {
1058 if (info->count == 0 &&
1059 mp_irqdomain_map(domain, irq, pin) != 0)
1060 irq = -1;
1061
1062 /* special handling for timer IRQ0 */
1063 if (irq == 0)
1064 info->count++;
1065 }
956 } else { 1066 } else {
957 u32 gsi = gsi_cfg->gsi_base + pin; 1067 irq = irq_find_mapping(domain, pin);
1068 if (irq <= 0 && (flags & IOAPIC_MAP_ALLOC))
1069 irq = alloc_irq_from_domain(domain, gsi, pin);
1070 }
958 1071
959 if (gsi >= NR_IRQS_LEGACY) 1072 if (flags & IOAPIC_MAP_ALLOC) {
960 irq = gsi; 1073 if (irq > 0)
961 else 1074 info->count++;
962 irq = gsi_top + gsi; 1075 else if (info->count == 0)
1076 info->set = 0;
963 } 1077 }
964 1078
1079 mutex_unlock(&ioapic_mutex);
1080
1081 return irq > 0 ? irq : -1;
1082}
1083
1084static int pin_2_irq(int idx, int ioapic, int pin, unsigned int flags)
1085{
1086 u32 gsi = mp_pin_to_gsi(ioapic, pin);
1087
1088 /*
1089 * Debugging check, we are in big trouble if this message pops up!
1090 */
1091 if (mp_irqs[idx].dstirq != pin)
1092 pr_err("broken BIOS or MPTABLE parser, ayiee!!\n");
1093
965#ifdef CONFIG_X86_32 1094#ifdef CONFIG_X86_32
966 /* 1095 /*
967 * PCI IRQ command line redirection. Yes, limits are hardcoded. 1096 * PCI IRQ command line redirection. Yes, limits are hardcoded.
@@ -972,16 +1101,58 @@ static int pin_2_irq(int idx, int apic, int pin)
972 apic_printk(APIC_VERBOSE, KERN_DEBUG 1101 apic_printk(APIC_VERBOSE, KERN_DEBUG
973 "disabling PIRQ%d\n", pin-16); 1102 "disabling PIRQ%d\n", pin-16);
974 } else { 1103 } else {
975 irq = pirq_entries[pin-16]; 1104 int irq = pirq_entries[pin-16];
976 apic_printk(APIC_VERBOSE, KERN_DEBUG 1105 apic_printk(APIC_VERBOSE, KERN_DEBUG
977 "using PIRQ%d -> IRQ %d\n", 1106 "using PIRQ%d -> IRQ %d\n",
978 pin-16, irq); 1107 pin-16, irq);
1108 return irq;
979 } 1109 }
980 } 1110 }
981 } 1111 }
982#endif 1112#endif
983 1113
984 return irq; 1114 return mp_map_pin_to_irq(gsi, idx, ioapic, pin, flags);
1115}
1116
1117int mp_map_gsi_to_irq(u32 gsi, unsigned int flags)
1118{
1119 int ioapic, pin, idx;
1120
1121 ioapic = mp_find_ioapic(gsi);
1122 if (ioapic < 0)
1123 return -1;
1124
1125 pin = mp_find_ioapic_pin(ioapic, gsi);
1126 idx = find_irq_entry(ioapic, pin, mp_INT);
1127 if ((flags & IOAPIC_MAP_CHECK) && idx < 0)
1128 return -1;
1129
1130 return mp_map_pin_to_irq(gsi, idx, ioapic, pin, flags);
1131}
1132
1133void mp_unmap_irq(int irq)
1134{
1135 struct irq_data *data = irq_get_irq_data(irq);
1136 struct mp_pin_info *info;
1137 int ioapic, pin;
1138
1139 if (!data || !data->domain)
1140 return;
1141
1142 ioapic = (int)(long)data->domain->host_data;
1143 pin = (int)data->hwirq;
1144 info = mp_pin_info(ioapic, pin);
1145
1146 mutex_lock(&ioapic_mutex);
1147 if (--info->count == 0) {
1148 info->set = 0;
1149 if (irq < nr_legacy_irqs() &&
1150 ioapics[ioapic].irqdomain_cfg.type == IOAPIC_DOMAIN_LEGACY)
1151 mp_irqdomain_unmap(data->domain, irq);
1152 else
1153 irq_dispose_mapping(irq);
1154 }
1155 mutex_unlock(&ioapic_mutex);
985} 1156}
986 1157
987/* 1158/*
@@ -991,7 +1162,7 @@ static int pin_2_irq(int idx, int apic, int pin)
991int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin, 1162int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin,
992 struct io_apic_irq_attr *irq_attr) 1163 struct io_apic_irq_attr *irq_attr)
993{ 1164{
994 int ioapic_idx, i, best_guess = -1; 1165 int irq, i, best_ioapic = -1, best_idx = -1;
995 1166
996 apic_printk(APIC_DEBUG, 1167 apic_printk(APIC_DEBUG,
997 "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n", 1168 "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
@@ -1001,44 +1172,56 @@ int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin,
1001 "PCI BIOS passed nonexistent PCI bus %d!\n", bus); 1172 "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
1002 return -1; 1173 return -1;
1003 } 1174 }
1175
1004 for (i = 0; i < mp_irq_entries; i++) { 1176 for (i = 0; i < mp_irq_entries; i++) {
1005 int lbus = mp_irqs[i].srcbus; 1177 int lbus = mp_irqs[i].srcbus;
1178 int ioapic_idx, found = 0;
1006 1179
1007 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++) 1180 if (bus != lbus || mp_irqs[i].irqtype != mp_INT ||
1181 slot != ((mp_irqs[i].srcbusirq >> 2) & 0x1f))
1182 continue;
1183
1184 for_each_ioapic(ioapic_idx)
1008 if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic || 1185 if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic ||
1009 mp_irqs[i].dstapic == MP_APIC_ALL) 1186 mp_irqs[i].dstapic == MP_APIC_ALL) {
1187 found = 1;
1010 break; 1188 break;
1189 }
1190 if (!found)
1191 continue;
1011 1192
1012 if (!test_bit(lbus, mp_bus_not_pci) && 1193 /* Skip ISA IRQs */
1013 !mp_irqs[i].irqtype && 1194 irq = pin_2_irq(i, ioapic_idx, mp_irqs[i].dstirq, 0);
1014 (bus == lbus) && 1195 if (irq > 0 && !IO_APIC_IRQ(irq))
1015 (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) { 1196 continue;
1016 int irq = pin_2_irq(i, ioapic_idx, mp_irqs[i].dstirq);
1017 1197
1018 if (!(ioapic_idx || IO_APIC_IRQ(irq))) 1198 if (pin == (mp_irqs[i].srcbusirq & 3)) {
1019 continue; 1199 best_idx = i;
1200 best_ioapic = ioapic_idx;
1201 goto out;
1202 }
1020 1203
1021 if (pin == (mp_irqs[i].srcbusirq & 3)) { 1204 /*
1022 set_io_apic_irq_attr(irq_attr, ioapic_idx, 1205 * Use the first all-but-pin matching entry as a
1023 mp_irqs[i].dstirq, 1206 * best-guess fuzzy result for broken mptables.
1024 irq_trigger(i), 1207 */
1025 irq_polarity(i)); 1208 if (best_idx < 0) {
1026 return irq; 1209 best_idx = i;
1027 } 1210 best_ioapic = ioapic_idx;
1028 /*
1029 * Use the first all-but-pin matching entry as a
1030 * best-guess fuzzy result for broken mptables.
1031 */
1032 if (best_guess < 0) {
1033 set_io_apic_irq_attr(irq_attr, ioapic_idx,
1034 mp_irqs[i].dstirq,
1035 irq_trigger(i),
1036 irq_polarity(i));
1037 best_guess = irq;
1038 }
1039 } 1211 }
1040 } 1212 }
1041 return best_guess; 1213 if (best_idx < 0)
1214 return -1;
1215
1216out:
1217 irq = pin_2_irq(best_idx, best_ioapic, mp_irqs[best_idx].dstirq,
1218 IOAPIC_MAP_ALLOC);
1219 if (irq > 0)
1220 set_io_apic_irq_attr(irq_attr, best_ioapic,
1221 mp_irqs[best_idx].dstirq,
1222 irq_trigger(best_idx),
1223 irq_polarity(best_idx));
1224 return irq;
1042} 1225}
1043EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector); 1226EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1044 1227
@@ -1198,7 +1381,7 @@ void __setup_vector_irq(int cpu)
1198 raw_spin_lock(&vector_lock); 1381 raw_spin_lock(&vector_lock);
1199 /* Mark the inuse vectors */ 1382 /* Mark the inuse vectors */
1200 for_each_active_irq(irq) { 1383 for_each_active_irq(irq) {
1201 cfg = irq_get_chip_data(irq); 1384 cfg = irq_cfg(irq);
1202 if (!cfg) 1385 if (!cfg)
1203 continue; 1386 continue;
1204 1387
@@ -1227,12 +1410,10 @@ static inline int IO_APIC_irq_trigger(int irq)
1227{ 1410{
1228 int apic, idx, pin; 1411 int apic, idx, pin;
1229 1412
1230 for (apic = 0; apic < nr_ioapics; apic++) { 1413 for_each_ioapic_pin(apic, pin) {
1231 for (pin = 0; pin < ioapics[apic].nr_registers; pin++) { 1414 idx = find_irq_entry(apic, pin, mp_INT);
1232 idx = find_irq_entry(apic, pin, mp_INT); 1415 if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin, 0)))
1233 if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin))) 1416 return irq_trigger(idx);
1234 return irq_trigger(idx);
1235 }
1236 } 1417 }
1237 /* 1418 /*
1238 * nonexistent IRQs are edge default 1419 * nonexistent IRQs are edge default
@@ -1330,95 +1511,29 @@ static void setup_ioapic_irq(unsigned int irq, struct irq_cfg *cfg,
1330 } 1511 }
1331 1512
1332 ioapic_register_intr(irq, cfg, attr->trigger); 1513 ioapic_register_intr(irq, cfg, attr->trigger);
1333 if (irq < legacy_pic->nr_legacy_irqs) 1514 if (irq < nr_legacy_irqs())
1334 legacy_pic->mask(irq); 1515 legacy_pic->mask(irq);
1335 1516
1336 ioapic_write_entry(attr->ioapic, attr->ioapic_pin, entry); 1517 ioapic_write_entry(attr->ioapic, attr->ioapic_pin, entry);
1337} 1518}
1338 1519
1339static bool __init io_apic_pin_not_connected(int idx, int ioapic_idx, int pin)
1340{
1341 if (idx != -1)
1342 return false;
1343
1344 apic_printk(APIC_VERBOSE, KERN_DEBUG " apic %d pin %d not connected\n",
1345 mpc_ioapic_id(ioapic_idx), pin);
1346 return true;
1347}
1348
1349static void __init __io_apic_setup_irqs(unsigned int ioapic_idx)
1350{
1351 int idx, node = cpu_to_node(0);
1352 struct io_apic_irq_attr attr;
1353 unsigned int pin, irq;
1354
1355 for (pin = 0; pin < ioapics[ioapic_idx].nr_registers; pin++) {
1356 idx = find_irq_entry(ioapic_idx, pin, mp_INT);
1357 if (io_apic_pin_not_connected(idx, ioapic_idx, pin))
1358 continue;
1359
1360 irq = pin_2_irq(idx, ioapic_idx, pin);
1361
1362 if ((ioapic_idx > 0) && (irq > 16))
1363 continue;
1364
1365 /*
1366 * Skip the timer IRQ if there's a quirk handler
1367 * installed and if it returns 1:
1368 */
1369 if (apic->multi_timer_check &&
1370 apic->multi_timer_check(ioapic_idx, irq))
1371 continue;
1372
1373 set_io_apic_irq_attr(&attr, ioapic_idx, pin, irq_trigger(idx),
1374 irq_polarity(idx));
1375
1376 io_apic_setup_irq_pin(irq, node, &attr);
1377 }
1378}
1379
1380static void __init setup_IO_APIC_irqs(void) 1520static void __init setup_IO_APIC_irqs(void)
1381{ 1521{
1382 unsigned int ioapic_idx; 1522 unsigned int ioapic, pin;
1523 int idx;
1383 1524
1384 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n"); 1525 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1385 1526
1386 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++) 1527 for_each_ioapic_pin(ioapic, pin) {
1387 __io_apic_setup_irqs(ioapic_idx); 1528 idx = find_irq_entry(ioapic, pin, mp_INT);
1388} 1529 if (idx < 0)
1389 1530 apic_printk(APIC_VERBOSE,
1390/* 1531 KERN_DEBUG " apic %d pin %d not connected\n",
1391 * for the gsit that is not in first ioapic 1532 mpc_ioapic_id(ioapic), pin);
1392 * but could not use acpi_register_gsi() 1533 else
1393 * like some special sci in IBM x3330 1534 pin_2_irq(idx, ioapic, pin,
1394 */ 1535 ioapic ? 0 : IOAPIC_MAP_ALLOC);
1395void setup_IO_APIC_irq_extra(u32 gsi) 1536 }
1396{
1397 int ioapic_idx = 0, pin, idx, irq, node = cpu_to_node(0);
1398 struct io_apic_irq_attr attr;
1399
1400 /*
1401 * Convert 'gsi' to 'ioapic.pin'.
1402 */
1403 ioapic_idx = mp_find_ioapic(gsi);
1404 if (ioapic_idx < 0)
1405 return;
1406
1407 pin = mp_find_ioapic_pin(ioapic_idx, gsi);
1408 idx = find_irq_entry(ioapic_idx, pin, mp_INT);
1409 if (idx == -1)
1410 return;
1411
1412 irq = pin_2_irq(idx, ioapic_idx, pin);
1413
1414 /* Only handle the non legacy irqs on secondary ioapics */
1415 if (ioapic_idx == 0 || irq < NR_IRQS_LEGACY)
1416 return;
1417
1418 set_io_apic_irq_attr(&attr, ioapic_idx, pin, irq_trigger(idx),
1419 irq_polarity(idx));
1420
1421 io_apic_setup_irq_pin_once(irq, node, &attr);
1422} 1537}
1423 1538
1424/* 1539/*
@@ -1586,7 +1701,7 @@ __apicdebuginit(void) print_IO_APICs(void)
1586 struct irq_chip *chip; 1701 struct irq_chip *chip;
1587 1702
1588 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries); 1703 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1589 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++) 1704 for_each_ioapic(ioapic_idx)
1590 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n", 1705 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1591 mpc_ioapic_id(ioapic_idx), 1706 mpc_ioapic_id(ioapic_idx),
1592 ioapics[ioapic_idx].nr_registers); 1707 ioapics[ioapic_idx].nr_registers);
@@ -1597,7 +1712,7 @@ __apicdebuginit(void) print_IO_APICs(void)
1597 */ 1712 */
1598 printk(KERN_INFO "testing the IO APIC.......................\n"); 1713 printk(KERN_INFO "testing the IO APIC.......................\n");
1599 1714
1600 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++) 1715 for_each_ioapic(ioapic_idx)
1601 print_IO_APIC(ioapic_idx); 1716 print_IO_APIC(ioapic_idx);
1602 1717
1603 printk(KERN_DEBUG "IRQ to pin mappings:\n"); 1718 printk(KERN_DEBUG "IRQ to pin mappings:\n");
@@ -1608,7 +1723,7 @@ __apicdebuginit(void) print_IO_APICs(void)
1608 if (chip != &ioapic_chip) 1723 if (chip != &ioapic_chip)
1609 continue; 1724 continue;
1610 1725
1611 cfg = irq_get_chip_data(irq); 1726 cfg = irq_cfg(irq);
1612 if (!cfg) 1727 if (!cfg)
1613 continue; 1728 continue;
1614 entry = cfg->irq_2_pin; 1729 entry = cfg->irq_2_pin;
@@ -1758,7 +1873,7 @@ __apicdebuginit(void) print_PIC(void)
1758 unsigned int v; 1873 unsigned int v;
1759 unsigned long flags; 1874 unsigned long flags;
1760 1875
1761 if (!legacy_pic->nr_legacy_irqs) 1876 if (!nr_legacy_irqs())
1762 return; 1877 return;
1763 1878
1764 printk(KERN_DEBUG "\nprinting PIC contents\n"); 1879 printk(KERN_DEBUG "\nprinting PIC contents\n");
@@ -1828,26 +1943,22 @@ static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1828void __init enable_IO_APIC(void) 1943void __init enable_IO_APIC(void)
1829{ 1944{
1830 int i8259_apic, i8259_pin; 1945 int i8259_apic, i8259_pin;
1831 int apic; 1946 int apic, pin;
1832 1947
1833 if (!legacy_pic->nr_legacy_irqs) 1948 if (!nr_legacy_irqs())
1834 return; 1949 return;
1835 1950
1836 for(apic = 0; apic < nr_ioapics; apic++) { 1951 for_each_ioapic_pin(apic, pin) {
1837 int pin;
1838 /* See if any of the pins is in ExtINT mode */ 1952 /* See if any of the pins is in ExtINT mode */
1839 for (pin = 0; pin < ioapics[apic].nr_registers; pin++) { 1953 struct IO_APIC_route_entry entry = ioapic_read_entry(apic, pin);
1840 struct IO_APIC_route_entry entry;
1841 entry = ioapic_read_entry(apic, pin);
1842 1954
1843 /* If the interrupt line is enabled and in ExtInt mode 1955 /* If the interrupt line is enabled and in ExtInt mode
1844 * I have found the pin where the i8259 is connected. 1956 * I have found the pin where the i8259 is connected.
1845 */ 1957 */
1846 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) { 1958 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1847 ioapic_i8259.apic = apic; 1959 ioapic_i8259.apic = apic;
1848 ioapic_i8259.pin = pin; 1960 ioapic_i8259.pin = pin;
1849 goto found_i8259; 1961 goto found_i8259;
1850 }
1851 } 1962 }
1852 } 1963 }
1853 found_i8259: 1964 found_i8259:
@@ -1919,7 +2030,7 @@ void disable_IO_APIC(void)
1919 */ 2030 */
1920 clear_IO_APIC(); 2031 clear_IO_APIC();
1921 2032
1922 if (!legacy_pic->nr_legacy_irqs) 2033 if (!nr_legacy_irqs())
1923 return; 2034 return;
1924 2035
1925 x86_io_apic_ops.disable(); 2036 x86_io_apic_ops.disable();
@@ -1950,7 +2061,7 @@ void __init setup_ioapic_ids_from_mpc_nocheck(void)
1950 /* 2061 /*
1951 * Set the IOAPIC ID to the value stored in the MPC table. 2062 * Set the IOAPIC ID to the value stored in the MPC table.
1952 */ 2063 */
1953 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++) { 2064 for_each_ioapic(ioapic_idx) {
1954 /* Read the register 0 value */ 2065 /* Read the register 0 value */
1955 raw_spin_lock_irqsave(&ioapic_lock, flags); 2066 raw_spin_lock_irqsave(&ioapic_lock, flags);
1956 reg_00.raw = io_apic_read(ioapic_idx, 0); 2067 reg_00.raw = io_apic_read(ioapic_idx, 0);
@@ -2123,7 +2234,7 @@ static unsigned int startup_ioapic_irq(struct irq_data *data)
2123 unsigned long flags; 2234 unsigned long flags;
2124 2235
2125 raw_spin_lock_irqsave(&ioapic_lock, flags); 2236 raw_spin_lock_irqsave(&ioapic_lock, flags);
2126 if (irq < legacy_pic->nr_legacy_irqs) { 2237 if (irq < nr_legacy_irqs()) {
2127 legacy_pic->mask(irq); 2238 legacy_pic->mask(irq);
2128 if (legacy_pic->irq_pending(irq)) 2239 if (legacy_pic->irq_pending(irq))
2129 was_pending = 1; 2240 was_pending = 1;
@@ -2225,7 +2336,7 @@ asmlinkage __visible void smp_irq_move_cleanup_interrupt(void)
2225 apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR); 2336 apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR);
2226 goto unlock; 2337 goto unlock;
2227 } 2338 }
2228 __this_cpu_write(vector_irq[vector], -1); 2339 __this_cpu_write(vector_irq[vector], VECTOR_UNDEFINED);
2229unlock: 2340unlock:
2230 raw_spin_unlock(&desc->lock); 2341 raw_spin_unlock(&desc->lock);
2231 } 2342 }
@@ -2253,7 +2364,7 @@ static void irq_complete_move(struct irq_cfg *cfg)
2253 2364
2254void irq_force_complete_move(int irq) 2365void irq_force_complete_move(int irq)
2255{ 2366{
2256 struct irq_cfg *cfg = irq_get_chip_data(irq); 2367 struct irq_cfg *cfg = irq_cfg(irq);
2257 2368
2258 if (!cfg) 2369 if (!cfg)
2259 return; 2370 return;
@@ -2514,26 +2625,15 @@ static inline void init_IO_APIC_traps(void)
2514 struct irq_cfg *cfg; 2625 struct irq_cfg *cfg;
2515 unsigned int irq; 2626 unsigned int irq;
2516 2627
2517 /*
2518 * NOTE! The local APIC isn't very good at handling
2519 * multiple interrupts at the same interrupt level.
2520 * As the interrupt level is determined by taking the
2521 * vector number and shifting that right by 4, we
2522 * want to spread these out a bit so that they don't
2523 * all fall in the same interrupt level.
2524 *
2525 * Also, we've got to be careful not to trash gate
2526 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2527 */
2528 for_each_active_irq(irq) { 2628 for_each_active_irq(irq) {
2529 cfg = irq_get_chip_data(irq); 2629 cfg = irq_cfg(irq);
2530 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) { 2630 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
2531 /* 2631 /*
2532 * Hmm.. We don't have an entry for this, 2632 * Hmm.. We don't have an entry for this,
2533 * so default to an old-fashioned 8259 2633 * so default to an old-fashioned 8259
2534 * interrupt if we can.. 2634 * interrupt if we can..
2535 */ 2635 */
2536 if (irq < legacy_pic->nr_legacy_irqs) 2636 if (irq < nr_legacy_irqs())
2537 legacy_pic->make_irq(irq); 2637 legacy_pic->make_irq(irq);
2538 else 2638 else
2539 /* Strange. Oh, well.. */ 2639 /* Strange. Oh, well.. */
@@ -2649,8 +2749,6 @@ static int __init disable_timer_pin_setup(char *arg)
2649} 2749}
2650early_param("disable_timer_pin_1", disable_timer_pin_setup); 2750early_param("disable_timer_pin_1", disable_timer_pin_setup);
2651 2751
2652int timer_through_8259 __initdata;
2653
2654/* 2752/*
2655 * This code may look a bit paranoid, but it's supposed to cooperate with 2753 * This code may look a bit paranoid, but it's supposed to cooperate with
2656 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ 2754 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
@@ -2661,7 +2759,7 @@ int timer_through_8259 __initdata;
2661 */ 2759 */
2662static inline void __init check_timer(void) 2760static inline void __init check_timer(void)
2663{ 2761{
2664 struct irq_cfg *cfg = irq_get_chip_data(0); 2762 struct irq_cfg *cfg = irq_cfg(0);
2665 int node = cpu_to_node(0); 2763 int node = cpu_to_node(0);
2666 int apic1, pin1, apic2, pin2; 2764 int apic1, pin1, apic2, pin2;
2667 unsigned long flags; 2765 unsigned long flags;
@@ -2755,7 +2853,6 @@ static inline void __init check_timer(void)
2755 legacy_pic->unmask(0); 2853 legacy_pic->unmask(0);
2756 if (timer_irq_works()) { 2854 if (timer_irq_works()) {
2757 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n"); 2855 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2758 timer_through_8259 = 1;
2759 goto out; 2856 goto out;
2760 } 2857 }
2761 /* 2858 /*
@@ -2827,15 +2924,54 @@ out:
2827 */ 2924 */
2828#define PIC_IRQS (1UL << PIC_CASCADE_IR) 2925#define PIC_IRQS (1UL << PIC_CASCADE_IR)
2829 2926
2927static int mp_irqdomain_create(int ioapic)
2928{
2929 size_t size;
2930 int hwirqs = mp_ioapic_pin_count(ioapic);
2931 struct ioapic *ip = &ioapics[ioapic];
2932 struct ioapic_domain_cfg *cfg = &ip->irqdomain_cfg;
2933 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(ioapic);
2934
2935 size = sizeof(struct mp_pin_info) * mp_ioapic_pin_count(ioapic);
2936 ip->pin_info = kzalloc(size, GFP_KERNEL);
2937 if (!ip->pin_info)
2938 return -ENOMEM;
2939
2940 if (cfg->type == IOAPIC_DOMAIN_INVALID)
2941 return 0;
2942
2943 ip->irqdomain = irq_domain_add_linear(cfg->dev, hwirqs, cfg->ops,
2944 (void *)(long)ioapic);
2945 if(!ip->irqdomain) {
2946 kfree(ip->pin_info);
2947 ip->pin_info = NULL;
2948 return -ENOMEM;
2949 }
2950
2951 if (cfg->type == IOAPIC_DOMAIN_LEGACY ||
2952 cfg->type == IOAPIC_DOMAIN_STRICT)
2953 ioapic_dynirq_base = max(ioapic_dynirq_base,
2954 gsi_cfg->gsi_end + 1);
2955
2956 if (gsi_cfg->gsi_base == 0)
2957 irq_set_default_host(ip->irqdomain);
2958
2959 return 0;
2960}
2961
2830void __init setup_IO_APIC(void) 2962void __init setup_IO_APIC(void)
2831{ 2963{
2964 int ioapic;
2832 2965
2833 /* 2966 /*
2834 * calling enable_IO_APIC() is moved to setup_local_APIC for BP 2967 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
2835 */ 2968 */
2836 io_apic_irqs = legacy_pic->nr_legacy_irqs ? ~PIC_IRQS : ~0UL; 2969 io_apic_irqs = nr_legacy_irqs() ? ~PIC_IRQS : ~0UL;
2837 2970
2838 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n"); 2971 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
2972 for_each_ioapic(ioapic)
2973 BUG_ON(mp_irqdomain_create(ioapic));
2974
2839 /* 2975 /*
2840 * Set up IO-APIC IRQ routing. 2976 * Set up IO-APIC IRQ routing.
2841 */ 2977 */
@@ -2844,8 +2980,10 @@ void __init setup_IO_APIC(void)
2844 sync_Arb_IDs(); 2980 sync_Arb_IDs();
2845 setup_IO_APIC_irqs(); 2981 setup_IO_APIC_irqs();
2846 init_IO_APIC_traps(); 2982 init_IO_APIC_traps();
2847 if (legacy_pic->nr_legacy_irqs) 2983 if (nr_legacy_irqs())
2848 check_timer(); 2984 check_timer();
2985
2986 ioapic_initialized = 1;
2849} 2987}
2850 2988
2851/* 2989/*
@@ -2880,7 +3018,7 @@ static void ioapic_resume(void)
2880{ 3018{
2881 int ioapic_idx; 3019 int ioapic_idx;
2882 3020
2883 for (ioapic_idx = nr_ioapics - 1; ioapic_idx >= 0; ioapic_idx--) 3021 for_each_ioapic_reverse(ioapic_idx)
2884 resume_ioapic_id(ioapic_idx); 3022 resume_ioapic_id(ioapic_idx);
2885 3023
2886 restore_ioapic_entries(); 3024 restore_ioapic_entries();
@@ -2926,7 +3064,7 @@ int arch_setup_hwirq(unsigned int irq, int node)
2926 3064
2927void arch_teardown_hwirq(unsigned int irq) 3065void arch_teardown_hwirq(unsigned int irq)
2928{ 3066{
2929 struct irq_cfg *cfg = irq_get_chip_data(irq); 3067 struct irq_cfg *cfg = irq_cfg(irq);
2930 unsigned long flags; 3068 unsigned long flags;
2931 3069
2932 free_remapped_irq(irq); 3070 free_remapped_irq(irq);
@@ -3053,7 +3191,7 @@ int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc,
3053 if (!irq_offset) 3191 if (!irq_offset)
3054 write_msi_msg(irq, &msg); 3192 write_msi_msg(irq, &msg);
3055 3193
3056 setup_remapped_irq(irq, irq_get_chip_data(irq), chip); 3194 setup_remapped_irq(irq, irq_cfg(irq), chip);
3057 3195
3058 irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge"); 3196 irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge");
3059 3197
@@ -3192,7 +3330,7 @@ int default_setup_hpet_msi(unsigned int irq, unsigned int id)
3192 3330
3193 hpet_msi_write(irq_get_handler_data(irq), &msg); 3331 hpet_msi_write(irq_get_handler_data(irq), &msg);
3194 irq_set_status_flags(irq, IRQ_MOVE_PCNTXT); 3332 irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
3195 setup_remapped_irq(irq, irq_get_chip_data(irq), chip); 3333 setup_remapped_irq(irq, irq_cfg(irq), chip);
3196 3334
3197 irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge"); 3335 irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge");
3198 return 0; 3336 return 0;
@@ -3303,27 +3441,6 @@ io_apic_setup_irq_pin(unsigned int irq, int node, struct io_apic_irq_attr *attr)
3303 return ret; 3441 return ret;
3304} 3442}
3305 3443
3306int io_apic_setup_irq_pin_once(unsigned int irq, int node,
3307 struct io_apic_irq_attr *attr)
3308{
3309 unsigned int ioapic_idx = attr->ioapic, pin = attr->ioapic_pin;
3310 int ret;
3311 struct IO_APIC_route_entry orig_entry;
3312
3313 /* Avoid redundant programming */
3314 if (test_bit(pin, ioapics[ioapic_idx].pin_programmed)) {
3315 pr_debug("Pin %d-%d already programmed\n", mpc_ioapic_id(ioapic_idx), pin);
3316 orig_entry = ioapic_read_entry(attr->ioapic, pin);
3317 if (attr->trigger == orig_entry.trigger && attr->polarity == orig_entry.polarity)
3318 return 0;
3319 return -EBUSY;
3320 }
3321 ret = io_apic_setup_irq_pin(irq, node, attr);
3322 if (!ret)
3323 set_bit(pin, ioapics[ioapic_idx].pin_programmed);
3324 return ret;
3325}
3326
3327static int __init io_apic_get_redir_entries(int ioapic) 3444static int __init io_apic_get_redir_entries(int ioapic)
3328{ 3445{
3329 union IO_APIC_reg_01 reg_01; 3446 union IO_APIC_reg_01 reg_01;
@@ -3340,20 +3457,13 @@ static int __init io_apic_get_redir_entries(int ioapic)
3340 return reg_01.bits.entries + 1; 3457 return reg_01.bits.entries + 1;
3341} 3458}
3342 3459
3343static void __init probe_nr_irqs_gsi(void)
3344{
3345 int nr;
3346
3347 nr = gsi_top + NR_IRQS_LEGACY;
3348 if (nr > nr_irqs_gsi)
3349 nr_irqs_gsi = nr;
3350
3351 printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi);
3352}
3353
3354unsigned int arch_dynirq_lower_bound(unsigned int from) 3460unsigned int arch_dynirq_lower_bound(unsigned int from)
3355{ 3461{
3356 return from < nr_irqs_gsi ? nr_irqs_gsi : from; 3462 /*
3463 * dmar_alloc_hwirq() may be called before setup_IO_APIC(), so use
3464 * gsi_top if ioapic_dynirq_base hasn't been initialized yet.
3465 */
3466 return ioapic_initialized ? ioapic_dynirq_base : gsi_top;
3357} 3467}
3358 3468
3359int __init arch_probe_nr_irqs(void) 3469int __init arch_probe_nr_irqs(void)
@@ -3363,33 +3473,17 @@ int __init arch_probe_nr_irqs(void)
3363 if (nr_irqs > (NR_VECTORS * nr_cpu_ids)) 3473 if (nr_irqs > (NR_VECTORS * nr_cpu_ids))
3364 nr_irqs = NR_VECTORS * nr_cpu_ids; 3474 nr_irqs = NR_VECTORS * nr_cpu_ids;
3365 3475
3366 nr = nr_irqs_gsi + 8 * nr_cpu_ids; 3476 nr = (gsi_top + nr_legacy_irqs()) + 8 * nr_cpu_ids;
3367#if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ) 3477#if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
3368 /* 3478 /*
3369 * for MSI and HT dyn irq 3479 * for MSI and HT dyn irq
3370 */ 3480 */
3371 nr += nr_irqs_gsi * 16; 3481 nr += gsi_top * 16;
3372#endif 3482#endif
3373 if (nr < nr_irqs) 3483 if (nr < nr_irqs)
3374 nr_irqs = nr; 3484 nr_irqs = nr;
3375 3485
3376 return NR_IRQS_LEGACY; 3486 return 0;
3377}
3378
3379int io_apic_set_pci_routing(struct device *dev, int irq,
3380 struct io_apic_irq_attr *irq_attr)
3381{
3382 int node;
3383
3384 if (!IO_APIC_IRQ(irq)) {
3385 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
3386 irq_attr->ioapic);
3387 return -EINVAL;
3388 }
3389
3390 node = dev ? dev_to_node(dev) : cpu_to_node(0);
3391
3392 return io_apic_setup_irq_pin_once(irq, node, irq_attr);
3393} 3487}
3394 3488
3395#ifdef CONFIG_X86_32 3489#ifdef CONFIG_X86_32
@@ -3483,9 +3577,8 @@ static u8 __init io_apic_unique_id(u8 id)
3483 DECLARE_BITMAP(used, 256); 3577 DECLARE_BITMAP(used, 256);
3484 3578
3485 bitmap_zero(used, 256); 3579 bitmap_zero(used, 256);
3486 for (i = 0; i < nr_ioapics; i++) { 3580 for_each_ioapic(i)
3487 __set_bit(mpc_ioapic_id(i), used); 3581 __set_bit(mpc_ioapic_id(i), used);
3488 }
3489 if (!test_bit(id, used)) 3582 if (!test_bit(id, used))
3490 return id; 3583 return id;
3491 return find_first_zero_bit(used, 256); 3584 return find_first_zero_bit(used, 256);
@@ -3543,14 +3636,13 @@ void __init setup_ioapic_dest(void)
3543 if (skip_ioapic_setup == 1) 3636 if (skip_ioapic_setup == 1)
3544 return; 3637 return;
3545 3638
3546 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) 3639 for_each_ioapic_pin(ioapic, pin) {
3547 for (pin = 0; pin < ioapics[ioapic].nr_registers; pin++) {
3548 irq_entry = find_irq_entry(ioapic, pin, mp_INT); 3640 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
3549 if (irq_entry == -1) 3641 if (irq_entry == -1)
3550 continue; 3642 continue;
3551 irq = pin_2_irq(irq_entry, ioapic, pin);
3552 3643
3553 if ((ioapic > 0) && (irq > 16)) 3644 irq = pin_2_irq(irq_entry, ioapic, pin, 0);
3645 if (irq < 0 || !mp_init_irq_at_boot(ioapic, irq))
3554 continue; 3646 continue;
3555 3647
3556 idata = irq_get_irq_data(irq); 3648 idata = irq_get_irq_data(irq);
@@ -3573,29 +3665,33 @@ void __init setup_ioapic_dest(void)
3573 3665
3574static struct resource *ioapic_resources; 3666static struct resource *ioapic_resources;
3575 3667
3576static struct resource * __init ioapic_setup_resources(int nr_ioapics) 3668static struct resource * __init ioapic_setup_resources(void)
3577{ 3669{
3578 unsigned long n; 3670 unsigned long n;
3579 struct resource *res; 3671 struct resource *res;
3580 char *mem; 3672 char *mem;
3581 int i; 3673 int i, num = 0;
3582 3674
3583 if (nr_ioapics <= 0) 3675 for_each_ioapic(i)
3676 num++;
3677 if (num == 0)
3584 return NULL; 3678 return NULL;
3585 3679
3586 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource); 3680 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
3587 n *= nr_ioapics; 3681 n *= num;
3588 3682
3589 mem = alloc_bootmem(n); 3683 mem = alloc_bootmem(n);
3590 res = (void *)mem; 3684 res = (void *)mem;
3591 3685
3592 mem += sizeof(struct resource) * nr_ioapics; 3686 mem += sizeof(struct resource) * num;
3593 3687
3594 for (i = 0; i < nr_ioapics; i++) { 3688 num = 0;
3595 res[i].name = mem; 3689 for_each_ioapic(i) {
3596 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY; 3690 res[num].name = mem;
3691 res[num].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
3597 snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i); 3692 snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i);
3598 mem += IOAPIC_RESOURCE_NAME_SIZE; 3693 mem += IOAPIC_RESOURCE_NAME_SIZE;
3694 num++;
3599 } 3695 }
3600 3696
3601 ioapic_resources = res; 3697 ioapic_resources = res;
@@ -3609,8 +3705,8 @@ void __init native_io_apic_init_mappings(void)
3609 struct resource *ioapic_res; 3705 struct resource *ioapic_res;
3610 int i; 3706 int i;
3611 3707
3612 ioapic_res = ioapic_setup_resources(nr_ioapics); 3708 ioapic_res = ioapic_setup_resources();
3613 for (i = 0; i < nr_ioapics; i++) { 3709 for_each_ioapic(i) {
3614 if (smp_found_config) { 3710 if (smp_found_config) {
3615 ioapic_phys = mpc_ioapic_addr(i); 3711 ioapic_phys = mpc_ioapic_addr(i);
3616#ifdef CONFIG_X86_32 3712#ifdef CONFIG_X86_32
@@ -3641,8 +3737,6 @@ fake_ioapic_page:
3641 ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1; 3737 ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1;
3642 ioapic_res++; 3738 ioapic_res++;
3643 } 3739 }
3644
3645 probe_nr_irqs_gsi();
3646} 3740}
3647 3741
3648void __init ioapic_insert_resources(void) 3742void __init ioapic_insert_resources(void)
@@ -3657,7 +3751,7 @@ void __init ioapic_insert_resources(void)
3657 return; 3751 return;
3658 } 3752 }
3659 3753
3660 for (i = 0; i < nr_ioapics; i++) { 3754 for_each_ioapic(i) {
3661 insert_resource(&iomem_resource, r); 3755 insert_resource(&iomem_resource, r);
3662 r++; 3756 r++;
3663 } 3757 }
@@ -3665,16 +3759,15 @@ void __init ioapic_insert_resources(void)
3665 3759
3666int mp_find_ioapic(u32 gsi) 3760int mp_find_ioapic(u32 gsi)
3667{ 3761{
3668 int i = 0; 3762 int i;
3669 3763
3670 if (nr_ioapics == 0) 3764 if (nr_ioapics == 0)
3671 return -1; 3765 return -1;
3672 3766
3673 /* Find the IOAPIC that manages this GSI. */ 3767 /* Find the IOAPIC that manages this GSI. */
3674 for (i = 0; i < nr_ioapics; i++) { 3768 for_each_ioapic(i) {
3675 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(i); 3769 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(i);
3676 if ((gsi >= gsi_cfg->gsi_base) 3770 if (gsi >= gsi_cfg->gsi_base && gsi <= gsi_cfg->gsi_end)
3677 && (gsi <= gsi_cfg->gsi_end))
3678 return i; 3771 return i;
3679 } 3772 }
3680 3773
@@ -3686,7 +3779,7 @@ int mp_find_ioapic_pin(int ioapic, u32 gsi)
3686{ 3779{
3687 struct mp_ioapic_gsi *gsi_cfg; 3780 struct mp_ioapic_gsi *gsi_cfg;
3688 3781
3689 if (WARN_ON(ioapic == -1)) 3782 if (WARN_ON(ioapic < 0))
3690 return -1; 3783 return -1;
3691 3784
3692 gsi_cfg = mp_ioapic_gsi_routing(ioapic); 3785 gsi_cfg = mp_ioapic_gsi_routing(ioapic);
@@ -3729,7 +3822,8 @@ static __init int bad_ioapic_register(int idx)
3729 return 0; 3822 return 0;
3730} 3823}
3731 3824
3732void __init mp_register_ioapic(int id, u32 address, u32 gsi_base) 3825void __init mp_register_ioapic(int id, u32 address, u32 gsi_base,
3826 struct ioapic_domain_cfg *cfg)
3733{ 3827{
3734 int idx = 0; 3828 int idx = 0;
3735 int entries; 3829 int entries;
@@ -3743,6 +3837,8 @@ void __init mp_register_ioapic(int id, u32 address, u32 gsi_base)
3743 ioapics[idx].mp_config.type = MP_IOAPIC; 3837 ioapics[idx].mp_config.type = MP_IOAPIC;
3744 ioapics[idx].mp_config.flags = MPC_APIC_USABLE; 3838 ioapics[idx].mp_config.flags = MPC_APIC_USABLE;
3745 ioapics[idx].mp_config.apicaddr = address; 3839 ioapics[idx].mp_config.apicaddr = address;
3840 ioapics[idx].irqdomain = NULL;
3841 ioapics[idx].irqdomain_cfg = *cfg;
3746 3842
3747 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address); 3843 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
3748 3844
@@ -3779,6 +3875,77 @@ void __init mp_register_ioapic(int id, u32 address, u32 gsi_base)
3779 nr_ioapics++; 3875 nr_ioapics++;
3780} 3876}
3781 3877
3878int mp_irqdomain_map(struct irq_domain *domain, unsigned int virq,
3879 irq_hw_number_t hwirq)
3880{
3881 int ioapic = (int)(long)domain->host_data;
3882 struct mp_pin_info *info = mp_pin_info(ioapic, hwirq);
3883 struct io_apic_irq_attr attr;
3884
3885 /* Get default attribute if not set by caller yet */
3886 if (!info->set) {
3887 u32 gsi = mp_pin_to_gsi(ioapic, hwirq);
3888
3889 if (acpi_get_override_irq(gsi, &info->trigger,
3890 &info->polarity) < 0) {
3891 /*
3892 * PCI interrupts are always polarity one level
3893 * triggered.
3894 */
3895 info->trigger = 1;
3896 info->polarity = 1;
3897 }
3898 info->node = NUMA_NO_NODE;
3899 info->set = 1;
3900 }
3901 set_io_apic_irq_attr(&attr, ioapic, hwirq, info->trigger,
3902 info->polarity);
3903
3904 return io_apic_setup_irq_pin(virq, info->node, &attr);
3905}
3906
3907void mp_irqdomain_unmap(struct irq_domain *domain, unsigned int virq)
3908{
3909 struct irq_data *data = irq_get_irq_data(virq);
3910 struct irq_cfg *cfg = irq_cfg(virq);
3911 int ioapic = (int)(long)domain->host_data;
3912 int pin = (int)data->hwirq;
3913
3914 ioapic_mask_entry(ioapic, pin);
3915 __remove_pin_from_irq(cfg, ioapic, pin);
3916 WARN_ON(cfg->irq_2_pin != NULL);
3917 arch_teardown_hwirq(virq);
3918}
3919
3920int mp_set_gsi_attr(u32 gsi, int trigger, int polarity, int node)
3921{
3922 int ret = 0;
3923 int ioapic, pin;
3924 struct mp_pin_info *info;
3925
3926 ioapic = mp_find_ioapic(gsi);
3927 if (ioapic < 0)
3928 return -ENODEV;
3929
3930 pin = mp_find_ioapic_pin(ioapic, gsi);
3931 info = mp_pin_info(ioapic, pin);
3932 trigger = trigger ? 1 : 0;
3933 polarity = polarity ? 1 : 0;
3934
3935 mutex_lock(&ioapic_mutex);
3936 if (!info->set) {
3937 info->trigger = trigger;
3938 info->polarity = polarity;
3939 info->node = node;
3940 info->set = 1;
3941 } else if (info->trigger != trigger || info->polarity != polarity) {
3942 ret = -EBUSY;
3943 }
3944 mutex_unlock(&ioapic_mutex);
3945
3946 return ret;
3947}
3948
3782/* Enable IOAPIC early just for system timer */ 3949/* Enable IOAPIC early just for system timer */
3783void __init pre_init_apic_IRQ0(void) 3950void __init pre_init_apic_IRQ0(void)
3784{ 3951{
diff --git a/arch/x86/kernel/apic/probe_32.c b/arch/x86/kernel/apic/probe_32.c
index cceb352c968c..bda488680dbc 100644
--- a/arch/x86/kernel/apic/probe_32.c
+++ b/arch/x86/kernel/apic/probe_32.c
@@ -88,21 +88,16 @@ static struct apic apic_default = {
88 .disable_esr = 0, 88 .disable_esr = 0,
89 .dest_logical = APIC_DEST_LOGICAL, 89 .dest_logical = APIC_DEST_LOGICAL,
90 .check_apicid_used = default_check_apicid_used, 90 .check_apicid_used = default_check_apicid_used,
91 .check_apicid_present = default_check_apicid_present,
92 91
93 .vector_allocation_domain = flat_vector_allocation_domain, 92 .vector_allocation_domain = flat_vector_allocation_domain,
94 .init_apic_ldr = default_init_apic_ldr, 93 .init_apic_ldr = default_init_apic_ldr,
95 94
96 .ioapic_phys_id_map = default_ioapic_phys_id_map, 95 .ioapic_phys_id_map = default_ioapic_phys_id_map,
97 .setup_apic_routing = setup_apic_flat_routing, 96 .setup_apic_routing = setup_apic_flat_routing,
98 .multi_timer_check = NULL,
99 .cpu_present_to_apicid = default_cpu_present_to_apicid, 97 .cpu_present_to_apicid = default_cpu_present_to_apicid,
100 .apicid_to_cpu_present = physid_set_mask_of_physid, 98 .apicid_to_cpu_present = physid_set_mask_of_physid,
101 .setup_portio_remap = NULL,
102 .check_phys_apicid_present = default_check_phys_apicid_present, 99 .check_phys_apicid_present = default_check_phys_apicid_present,
103 .enable_apic_mode = NULL,
104 .phys_pkg_id = default_phys_pkg_id, 100 .phys_pkg_id = default_phys_pkg_id,
105 .mps_oem_check = NULL,
106 101
107 .get_apic_id = default_get_apic_id, 102 .get_apic_id = default_get_apic_id,
108 .set_apic_id = NULL, 103 .set_apic_id = NULL,
@@ -116,11 +111,7 @@ static struct apic apic_default = {
116 .send_IPI_all = default_send_IPI_all, 111 .send_IPI_all = default_send_IPI_all,
117 .send_IPI_self = default_send_IPI_self, 112 .send_IPI_self = default_send_IPI_self,
118 113
119 .trampoline_phys_low = DEFAULT_TRAMPOLINE_PHYS_LOW,
120 .trampoline_phys_high = DEFAULT_TRAMPOLINE_PHYS_HIGH,
121
122 .wait_for_init_deassert = true, 114 .wait_for_init_deassert = true,
123 .smp_callin_clear_local_apic = NULL,
124 .inquire_remote_apic = default_inquire_remote_apic, 115 .inquire_remote_apic = default_inquire_remote_apic,
125 116
126 .read = native_apic_mem_read, 117 .read = native_apic_mem_read,
@@ -214,29 +205,7 @@ void __init generic_apic_probe(void)
214 printk(KERN_INFO "Using APIC driver %s\n", apic->name); 205 printk(KERN_INFO "Using APIC driver %s\n", apic->name);
215} 206}
216 207
217/* These functions can switch the APIC even after the initial ->probe() */ 208/* This function can switch the APIC even after the initial ->probe() */
218
219int __init
220generic_mps_oem_check(struct mpc_table *mpc, char *oem, char *productid)
221{
222 struct apic **drv;
223
224 for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) {
225 if (!((*drv)->mps_oem_check))
226 continue;
227 if (!(*drv)->mps_oem_check(mpc, oem, productid))
228 continue;
229
230 if (!cmdline_apic) {
231 apic = *drv;
232 printk(KERN_INFO "Switched to APIC driver `%s'.\n",
233 apic->name);
234 }
235 return 1;
236 }
237 return 0;
238}
239
240int __init default_acpi_madt_oem_check(char *oem_id, char *oem_table_id) 209int __init default_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
241{ 210{
242 struct apic **drv; 211 struct apic **drv;
diff --git a/arch/x86/kernel/apic/x2apic_cluster.c b/arch/x86/kernel/apic/x2apic_cluster.c
index e66766bf1641..6ce600f9bc78 100644
--- a/arch/x86/kernel/apic/x2apic_cluster.c
+++ b/arch/x86/kernel/apic/x2apic_cluster.c
@@ -249,21 +249,16 @@ static struct apic apic_x2apic_cluster = {
249 .disable_esr = 0, 249 .disable_esr = 0,
250 .dest_logical = APIC_DEST_LOGICAL, 250 .dest_logical = APIC_DEST_LOGICAL,
251 .check_apicid_used = NULL, 251 .check_apicid_used = NULL,
252 .check_apicid_present = NULL,
253 252
254 .vector_allocation_domain = cluster_vector_allocation_domain, 253 .vector_allocation_domain = cluster_vector_allocation_domain,
255 .init_apic_ldr = init_x2apic_ldr, 254 .init_apic_ldr = init_x2apic_ldr,
256 255
257 .ioapic_phys_id_map = NULL, 256 .ioapic_phys_id_map = NULL,
258 .setup_apic_routing = NULL, 257 .setup_apic_routing = NULL,
259 .multi_timer_check = NULL,
260 .cpu_present_to_apicid = default_cpu_present_to_apicid, 258 .cpu_present_to_apicid = default_cpu_present_to_apicid,
261 .apicid_to_cpu_present = NULL, 259 .apicid_to_cpu_present = NULL,
262 .setup_portio_remap = NULL,
263 .check_phys_apicid_present = default_check_phys_apicid_present, 260 .check_phys_apicid_present = default_check_phys_apicid_present,
264 .enable_apic_mode = NULL,
265 .phys_pkg_id = x2apic_phys_pkg_id, 261 .phys_pkg_id = x2apic_phys_pkg_id,
266 .mps_oem_check = NULL,
267 262
268 .get_apic_id = x2apic_get_apic_id, 263 .get_apic_id = x2apic_get_apic_id,
269 .set_apic_id = x2apic_set_apic_id, 264 .set_apic_id = x2apic_set_apic_id,
@@ -277,10 +272,7 @@ static struct apic apic_x2apic_cluster = {
277 .send_IPI_all = x2apic_send_IPI_all, 272 .send_IPI_all = x2apic_send_IPI_all,
278 .send_IPI_self = x2apic_send_IPI_self, 273 .send_IPI_self = x2apic_send_IPI_self,
279 274
280 .trampoline_phys_low = DEFAULT_TRAMPOLINE_PHYS_LOW,
281 .trampoline_phys_high = DEFAULT_TRAMPOLINE_PHYS_HIGH,
282 .wait_for_init_deassert = false, 275 .wait_for_init_deassert = false,
283 .smp_callin_clear_local_apic = NULL,
284 .inquire_remote_apic = NULL, 276 .inquire_remote_apic = NULL,
285 277
286 .read = native_apic_msr_read, 278 .read = native_apic_msr_read,
diff --git a/arch/x86/kernel/apic/x2apic_phys.c b/arch/x86/kernel/apic/x2apic_phys.c
index 6d600ebf6c12..6fae733e9194 100644
--- a/arch/x86/kernel/apic/x2apic_phys.c
+++ b/arch/x86/kernel/apic/x2apic_phys.c
@@ -103,21 +103,16 @@ static struct apic apic_x2apic_phys = {
103 .disable_esr = 0, 103 .disable_esr = 0,
104 .dest_logical = 0, 104 .dest_logical = 0,
105 .check_apicid_used = NULL, 105 .check_apicid_used = NULL,
106 .check_apicid_present = NULL,
107 106
108 .vector_allocation_domain = default_vector_allocation_domain, 107 .vector_allocation_domain = default_vector_allocation_domain,
109 .init_apic_ldr = init_x2apic_ldr, 108 .init_apic_ldr = init_x2apic_ldr,
110 109
111 .ioapic_phys_id_map = NULL, 110 .ioapic_phys_id_map = NULL,
112 .setup_apic_routing = NULL, 111 .setup_apic_routing = NULL,
113 .multi_timer_check = NULL,
114 .cpu_present_to_apicid = default_cpu_present_to_apicid, 112 .cpu_present_to_apicid = default_cpu_present_to_apicid,
115 .apicid_to_cpu_present = NULL, 113 .apicid_to_cpu_present = NULL,
116 .setup_portio_remap = NULL,
117 .check_phys_apicid_present = default_check_phys_apicid_present, 114 .check_phys_apicid_present = default_check_phys_apicid_present,
118 .enable_apic_mode = NULL,
119 .phys_pkg_id = x2apic_phys_pkg_id, 115 .phys_pkg_id = x2apic_phys_pkg_id,
120 .mps_oem_check = NULL,
121 116
122 .get_apic_id = x2apic_get_apic_id, 117 .get_apic_id = x2apic_get_apic_id,
123 .set_apic_id = x2apic_set_apic_id, 118 .set_apic_id = x2apic_set_apic_id,
@@ -131,10 +126,7 @@ static struct apic apic_x2apic_phys = {
131 .send_IPI_all = x2apic_send_IPI_all, 126 .send_IPI_all = x2apic_send_IPI_all,
132 .send_IPI_self = x2apic_send_IPI_self, 127 .send_IPI_self = x2apic_send_IPI_self,
133 128
134 .trampoline_phys_low = DEFAULT_TRAMPOLINE_PHYS_LOW,
135 .trampoline_phys_high = DEFAULT_TRAMPOLINE_PHYS_HIGH,
136 .wait_for_init_deassert = false, 129 .wait_for_init_deassert = false,
137 .smp_callin_clear_local_apic = NULL,
138 .inquire_remote_apic = NULL, 130 .inquire_remote_apic = NULL,
139 131
140 .read = native_apic_msr_read, 132 .read = native_apic_msr_read,
diff --git a/arch/x86/kernel/apic/x2apic_uv_x.c b/arch/x86/kernel/apic/x2apic_uv_x.c
index 293b41df54ef..004f017aa7b9 100644
--- a/arch/x86/kernel/apic/x2apic_uv_x.c
+++ b/arch/x86/kernel/apic/x2apic_uv_x.c
@@ -365,21 +365,16 @@ static struct apic __refdata apic_x2apic_uv_x = {
365 .disable_esr = 0, 365 .disable_esr = 0,
366 .dest_logical = APIC_DEST_LOGICAL, 366 .dest_logical = APIC_DEST_LOGICAL,
367 .check_apicid_used = NULL, 367 .check_apicid_used = NULL,
368 .check_apicid_present = NULL,
369 368
370 .vector_allocation_domain = default_vector_allocation_domain, 369 .vector_allocation_domain = default_vector_allocation_domain,
371 .init_apic_ldr = uv_init_apic_ldr, 370 .init_apic_ldr = uv_init_apic_ldr,
372 371
373 .ioapic_phys_id_map = NULL, 372 .ioapic_phys_id_map = NULL,
374 .setup_apic_routing = NULL, 373 .setup_apic_routing = NULL,
375 .multi_timer_check = NULL,
376 .cpu_present_to_apicid = default_cpu_present_to_apicid, 374 .cpu_present_to_apicid = default_cpu_present_to_apicid,
377 .apicid_to_cpu_present = NULL, 375 .apicid_to_cpu_present = NULL,
378 .setup_portio_remap = NULL,
379 .check_phys_apicid_present = default_check_phys_apicid_present, 376 .check_phys_apicid_present = default_check_phys_apicid_present,
380 .enable_apic_mode = NULL,
381 .phys_pkg_id = uv_phys_pkg_id, 377 .phys_pkg_id = uv_phys_pkg_id,
382 .mps_oem_check = NULL,
383 378
384 .get_apic_id = x2apic_get_apic_id, 379 .get_apic_id = x2apic_get_apic_id,
385 .set_apic_id = set_apic_id, 380 .set_apic_id = set_apic_id,
@@ -394,10 +389,7 @@ static struct apic __refdata apic_x2apic_uv_x = {
394 .send_IPI_self = uv_send_IPI_self, 389 .send_IPI_self = uv_send_IPI_self,
395 390
396 .wakeup_secondary_cpu = uv_wakeup_secondary, 391 .wakeup_secondary_cpu = uv_wakeup_secondary,
397 .trampoline_phys_low = DEFAULT_TRAMPOLINE_PHYS_LOW,
398 .trampoline_phys_high = DEFAULT_TRAMPOLINE_PHYS_HIGH,
399 .wait_for_init_deassert = false, 392 .wait_for_init_deassert = false,
400 .smp_callin_clear_local_apic = NULL,
401 .inquire_remote_apic = NULL, 393 .inquire_remote_apic = NULL,
402 394
403 .read = native_apic_msr_read, 395 .read = native_apic_msr_read,
diff --git a/arch/x86/kernel/devicetree.c b/arch/x86/kernel/devicetree.c
index 7db54b5d5f86..3d3503351242 100644
--- a/arch/x86/kernel/devicetree.c
+++ b/arch/x86/kernel/devicetree.c
@@ -21,6 +21,7 @@
21#include <asm/apic.h> 21#include <asm/apic.h>
22#include <asm/pci_x86.h> 22#include <asm/pci_x86.h>
23#include <asm/setup.h> 23#include <asm/setup.h>
24#include <asm/i8259.h>
24 25
25__initdata u64 initial_dtb; 26__initdata u64 initial_dtb;
26char __initdata cmd_line[COMMAND_LINE_SIZE]; 27char __initdata cmd_line[COMMAND_LINE_SIZE];
@@ -165,82 +166,6 @@ static void __init dtb_lapic_setup(void)
165#ifdef CONFIG_X86_IO_APIC 166#ifdef CONFIG_X86_IO_APIC
166static unsigned int ioapic_id; 167static unsigned int ioapic_id;
167 168
168static void __init dtb_add_ioapic(struct device_node *dn)
169{
170 struct resource r;
171 int ret;
172
173 ret = of_address_to_resource(dn, 0, &r);
174 if (ret) {
175 printk(KERN_ERR "Can't obtain address from node %s.\n",
176 dn->full_name);
177 return;
178 }
179 mp_register_ioapic(++ioapic_id, r.start, gsi_top);
180}
181
182static void __init dtb_ioapic_setup(void)
183{
184 struct device_node *dn;
185
186 for_each_compatible_node(dn, NULL, "intel,ce4100-ioapic")
187 dtb_add_ioapic(dn);
188
189 if (nr_ioapics) {
190 of_ioapic = 1;
191 return;
192 }
193 printk(KERN_ERR "Error: No information about IO-APIC in OF.\n");
194}
195#else
196static void __init dtb_ioapic_setup(void) {}
197#endif
198
199static void __init dtb_apic_setup(void)
200{
201 dtb_lapic_setup();
202 dtb_ioapic_setup();
203}
204
205#ifdef CONFIG_OF_FLATTREE
206static void __init x86_flattree_get_config(void)
207{
208 u32 size, map_len;
209 void *dt;
210
211 if (!initial_dtb)
212 return;
213
214 map_len = max(PAGE_SIZE - (initial_dtb & ~PAGE_MASK), (u64)128);
215
216 initial_boot_params = dt = early_memremap(initial_dtb, map_len);
217 size = of_get_flat_dt_size();
218 if (map_len < size) {
219 early_iounmap(dt, map_len);
220 initial_boot_params = dt = early_memremap(initial_dtb, size);
221 map_len = size;
222 }
223
224 unflatten_and_copy_device_tree();
225 early_iounmap(dt, map_len);
226}
227#else
228static inline void x86_flattree_get_config(void) { }
229#endif
230
231void __init x86_dtb_init(void)
232{
233 x86_flattree_get_config();
234
235 if (!of_have_populated_dt())
236 return;
237
238 dtb_setup_hpet();
239 dtb_apic_setup();
240}
241
242#ifdef CONFIG_X86_IO_APIC
243
244struct of_ioapic_type { 169struct of_ioapic_type {
245 u32 out_type; 170 u32 out_type;
246 u32 trigger; 171 u32 trigger;
@@ -276,10 +201,8 @@ static int ioapic_xlate(struct irq_domain *domain,
276 const u32 *intspec, u32 intsize, 201 const u32 *intspec, u32 intsize,
277 irq_hw_number_t *out_hwirq, u32 *out_type) 202 irq_hw_number_t *out_hwirq, u32 *out_type)
278{ 203{
279 struct io_apic_irq_attr attr;
280 struct of_ioapic_type *it; 204 struct of_ioapic_type *it;
281 u32 line, idx; 205 u32 line, idx, gsi;
282 int rc;
283 206
284 if (WARN_ON(intsize < 2)) 207 if (WARN_ON(intsize < 2))
285 return -EINVAL; 208 return -EINVAL;
@@ -291,13 +214,10 @@ static int ioapic_xlate(struct irq_domain *domain,
291 214
292 it = &of_ioapic_type[intspec[1]]; 215 it = &of_ioapic_type[intspec[1]];
293 216
294 idx = (u32) domain->host_data; 217 idx = (u32)(long)domain->host_data;
295 set_io_apic_irq_attr(&attr, idx, line, it->trigger, it->polarity); 218 gsi = mp_pin_to_gsi(idx, line);
296 219 if (mp_set_gsi_attr(gsi, it->trigger, it->polarity, cpu_to_node(0)))
297 rc = io_apic_setup_irq_pin_once(irq_find_mapping(domain, line), 220 return -EBUSY;
298 cpu_to_node(0), &attr);
299 if (rc)
300 return rc;
301 221
302 *out_hwirq = line; 222 *out_hwirq = line;
303 *out_type = it->out_type; 223 *out_type = it->out_type;
@@ -305,81 +225,86 @@ static int ioapic_xlate(struct irq_domain *domain,
305} 225}
306 226
307const struct irq_domain_ops ioapic_irq_domain_ops = { 227const struct irq_domain_ops ioapic_irq_domain_ops = {
228 .map = mp_irqdomain_map,
229 .unmap = mp_irqdomain_unmap,
308 .xlate = ioapic_xlate, 230 .xlate = ioapic_xlate,
309}; 231};
310 232
311static void dt_add_ioapic_domain(unsigned int ioapic_num, 233static void __init dtb_add_ioapic(struct device_node *dn)
312 struct device_node *np)
313{ 234{
314 struct irq_domain *id; 235 struct resource r;
315 struct mp_ioapic_gsi *gsi_cfg;
316 int ret; 236 int ret;
317 int num; 237 struct ioapic_domain_cfg cfg = {
318 238 .type = IOAPIC_DOMAIN_DYNAMIC,
319 gsi_cfg = mp_ioapic_gsi_routing(ioapic_num); 239 .ops = &ioapic_irq_domain_ops,
320 num = gsi_cfg->gsi_end - gsi_cfg->gsi_base + 1; 240 .dev = dn,
321 241 };
322 id = irq_domain_add_linear(np, num, &ioapic_irq_domain_ops, 242
323 (void *)ioapic_num); 243 ret = of_address_to_resource(dn, 0, &r);
324 BUG_ON(!id); 244 if (ret) {
325 if (gsi_cfg->gsi_base == 0) { 245 printk(KERN_ERR "Can't obtain address from node %s.\n",
326 /* 246 dn->full_name);
327 * The first NR_IRQS_LEGACY irq descs are allocated in 247 return;
328 * early_irq_init() and need just a mapping. The
329 * remaining irqs need both. All of them are preallocated
330 * and assigned so we can keep the 1:1 mapping which the ioapic
331 * is having.
332 */
333 irq_domain_associate_many(id, 0, 0, NR_IRQS_LEGACY);
334
335 if (num > NR_IRQS_LEGACY) {
336 ret = irq_create_strict_mappings(id, NR_IRQS_LEGACY,
337 NR_IRQS_LEGACY, num - NR_IRQS_LEGACY);
338 if (ret)
339 pr_err("Error creating mapping for the "
340 "remaining IRQs: %d\n", ret);
341 }
342 irq_set_default_host(id);
343 } else {
344 ret = irq_create_strict_mappings(id, gsi_cfg->gsi_base, 0, num);
345 if (ret)
346 pr_err("Error creating IRQ mapping: %d\n", ret);
347 } 248 }
249 mp_register_ioapic(++ioapic_id, r.start, gsi_top, &cfg);
348} 250}
349 251
350static void __init ioapic_add_ofnode(struct device_node *np) 252static void __init dtb_ioapic_setup(void)
351{ 253{
352 struct resource r; 254 struct device_node *dn;
353 int i, ret;
354 255
355 ret = of_address_to_resource(np, 0, &r); 256 for_each_compatible_node(dn, NULL, "intel,ce4100-ioapic")
356 if (ret) { 257 dtb_add_ioapic(dn);
357 printk(KERN_ERR "Failed to obtain address for %s\n", 258
358 np->full_name); 259 if (nr_ioapics) {
260 of_ioapic = 1;
359 return; 261 return;
360 } 262 }
263 printk(KERN_ERR "Error: No information about IO-APIC in OF.\n");
264}
265#else
266static void __init dtb_ioapic_setup(void) {}
267#endif
361 268
362 for (i = 0; i < nr_ioapics; i++) { 269static void __init dtb_apic_setup(void)
363 if (r.start == mpc_ioapic_addr(i)) { 270{
364 dt_add_ioapic_domain(i, np); 271 dtb_lapic_setup();
365 return; 272 dtb_ioapic_setup();
366 }
367 }
368 printk(KERN_ERR "IOxAPIC at %s is not registered.\n", np->full_name);
369} 273}
370 274
371void __init x86_add_irq_domains(void) 275#ifdef CONFIG_OF_FLATTREE
276static void __init x86_flattree_get_config(void)
372{ 277{
373 struct device_node *dp; 278 u32 size, map_len;
279 void *dt;
374 280
375 if (!of_have_populated_dt()) 281 if (!initial_dtb)
376 return; 282 return;
377 283
378 for_each_node_with_property(dp, "interrupt-controller") { 284 map_len = max(PAGE_SIZE - (initial_dtb & ~PAGE_MASK), (u64)128);
379 if (of_device_is_compatible(dp, "intel,ce4100-ioapic")) 285
380 ioapic_add_ofnode(dp); 286 initial_boot_params = dt = early_memremap(initial_dtb, map_len);
287 size = of_get_flat_dt_size();
288 if (map_len < size) {
289 early_iounmap(dt, map_len);
290 initial_boot_params = dt = early_memremap(initial_dtb, size);
291 map_len = size;
381 } 292 }
293
294 unflatten_and_copy_device_tree();
295 early_iounmap(dt, map_len);
382} 296}
383#else 297#else
384void __init x86_add_irq_domains(void) { } 298static inline void x86_flattree_get_config(void) { }
385#endif 299#endif
300
301void __init x86_dtb_init(void)
302{
303 x86_flattree_get_config();
304
305 if (!of_have_populated_dt())
306 return;
307
308 dtb_setup_hpet();
309 dtb_apic_setup();
310}
diff --git a/arch/x86/kernel/irqinit.c b/arch/x86/kernel/irqinit.c
index 7f50156542fb..1e6cff5814fa 100644
--- a/arch/x86/kernel/irqinit.c
+++ b/arch/x86/kernel/irqinit.c
@@ -78,7 +78,7 @@ void __init init_ISA_irqs(void)
78#endif 78#endif
79 legacy_pic->init(0); 79 legacy_pic->init(0);
80 80
81 for (i = 0; i < legacy_pic->nr_legacy_irqs; i++) 81 for (i = 0; i < nr_legacy_irqs(); i++)
82 irq_set_chip_and_handler_name(i, chip, handle_level_irq, name); 82 irq_set_chip_and_handler_name(i, chip, handle_level_irq, name);
83} 83}
84 84
@@ -87,12 +87,6 @@ void __init init_IRQ(void)
87 int i; 87 int i;
88 88
89 /* 89 /*
90 * We probably need a better place for this, but it works for
91 * now ...
92 */
93 x86_add_irq_domains();
94
95 /*
96 * On cpu 0, Assign IRQ0_VECTOR..IRQ15_VECTOR's to IRQ 0..15. 90 * On cpu 0, Assign IRQ0_VECTOR..IRQ15_VECTOR's to IRQ 0..15.
97 * If these IRQ's are handled by legacy interrupt-controllers like PIC, 91 * If these IRQ's are handled by legacy interrupt-controllers like PIC,
98 * then this configuration will likely be static after the boot. If 92 * then this configuration will likely be static after the boot. If
@@ -100,7 +94,7 @@ void __init init_IRQ(void)
100 * then this vector space can be freed and re-used dynamically as the 94 * then this vector space can be freed and re-used dynamically as the
101 * irq's migrate etc. 95 * irq's migrate etc.
102 */ 96 */
103 for (i = 0; i < legacy_pic->nr_legacy_irqs; i++) 97 for (i = 0; i < nr_legacy_irqs(); i++)
104 per_cpu(vector_irq, 0)[IRQ0_VECTOR + i] = i; 98 per_cpu(vector_irq, 0)[IRQ0_VECTOR + i] = i;
105 99
106 x86_init.irqs.intr_init(); 100 x86_init.irqs.intr_init();
@@ -121,7 +115,7 @@ void setup_vector_irq(int cpu)
121 * legacy PIC, for the new cpu that is coming online, setup the static 115 * legacy PIC, for the new cpu that is coming online, setup the static
122 * legacy vector to irq mapping: 116 * legacy vector to irq mapping:
123 */ 117 */
124 for (irq = 0; irq < legacy_pic->nr_legacy_irqs; irq++) 118 for (irq = 0; irq < nr_legacy_irqs(); irq++)
125 per_cpu(vector_irq, cpu)[IRQ0_VECTOR + irq] = irq; 119 per_cpu(vector_irq, cpu)[IRQ0_VECTOR + irq] = irq;
126#endif 120#endif
127 121
diff --git a/arch/x86/kernel/mpparse.c b/arch/x86/kernel/mpparse.c
index d2b56489d70f..2d2a237f2c73 100644
--- a/arch/x86/kernel/mpparse.c
+++ b/arch/x86/kernel/mpparse.c
@@ -19,6 +19,7 @@
19#include <linux/module.h> 19#include <linux/module.h>
20#include <linux/smp.h> 20#include <linux/smp.h>
21#include <linux/pci.h> 21#include <linux/pci.h>
22#include <linux/irqdomain.h>
22 23
23#include <asm/mtrr.h> 24#include <asm/mtrr.h>
24#include <asm/mpspec.h> 25#include <asm/mpspec.h>
@@ -67,7 +68,7 @@ static void __init MP_processor_info(struct mpc_cpu *m)
67 boot_cpu_physical_apicid = m->apicid; 68 boot_cpu_physical_apicid = m->apicid;
68 } 69 }
69 70
70 printk(KERN_INFO "Processor #%d%s\n", m->apicid, bootup_cpu); 71 pr_info("Processor #%d%s\n", m->apicid, bootup_cpu);
71 generic_processor_info(apicid, m->apicver); 72 generic_processor_info(apicid, m->apicver);
72} 73}
73 74
@@ -87,9 +88,8 @@ static void __init MP_bus_info(struct mpc_bus *m)
87 88
88#if MAX_MP_BUSSES < 256 89#if MAX_MP_BUSSES < 256
89 if (m->busid >= MAX_MP_BUSSES) { 90 if (m->busid >= MAX_MP_BUSSES) {
90 printk(KERN_WARNING "MP table busid value (%d) for bustype %s " 91 pr_warn("MP table busid value (%d) for bustype %s is too large, max. supported is %d\n",
91 " is too large, max. supported is %d\n", 92 m->busid, str, MAX_MP_BUSSES - 1);
92 m->busid, str, MAX_MP_BUSSES - 1);
93 return; 93 return;
94 } 94 }
95#endif 95#endif
@@ -110,19 +110,29 @@ static void __init MP_bus_info(struct mpc_bus *m)
110 mp_bus_id_to_type[m->busid] = MP_BUS_EISA; 110 mp_bus_id_to_type[m->busid] = MP_BUS_EISA;
111#endif 111#endif
112 } else 112 } else
113 printk(KERN_WARNING "Unknown bustype %s - ignoring\n", str); 113 pr_warn("Unknown bustype %s - ignoring\n", str);
114} 114}
115 115
116static struct irq_domain_ops mp_ioapic_irqdomain_ops = {
117 .map = mp_irqdomain_map,
118 .unmap = mp_irqdomain_unmap,
119};
120
116static void __init MP_ioapic_info(struct mpc_ioapic *m) 121static void __init MP_ioapic_info(struct mpc_ioapic *m)
117{ 122{
123 struct ioapic_domain_cfg cfg = {
124 .type = IOAPIC_DOMAIN_LEGACY,
125 .ops = &mp_ioapic_irqdomain_ops,
126 };
127
118 if (m->flags & MPC_APIC_USABLE) 128 if (m->flags & MPC_APIC_USABLE)
119 mp_register_ioapic(m->apicid, m->apicaddr, gsi_top); 129 mp_register_ioapic(m->apicid, m->apicaddr, gsi_top, &cfg);
120} 130}
121 131
122static void __init print_mp_irq_info(struct mpc_intsrc *mp_irq) 132static void __init print_mp_irq_info(struct mpc_intsrc *mp_irq)
123{ 133{
124 apic_printk(APIC_VERBOSE, "Int: type %d, pol %d, trig %d, bus %02x," 134 apic_printk(APIC_VERBOSE,
125 " IRQ %02x, APIC ID %x, APIC INT %02x\n", 135 "Int: type %d, pol %d, trig %d, bus %02x, IRQ %02x, APIC ID %x, APIC INT %02x\n",
126 mp_irq->irqtype, mp_irq->irqflag & 3, 136 mp_irq->irqtype, mp_irq->irqflag & 3,
127 (mp_irq->irqflag >> 2) & 3, mp_irq->srcbus, 137 (mp_irq->irqflag >> 2) & 3, mp_irq->srcbus,
128 mp_irq->srcbusirq, mp_irq->dstapic, mp_irq->dstirq); 138 mp_irq->srcbusirq, mp_irq->dstapic, mp_irq->dstirq);
@@ -135,8 +145,8 @@ static inline void __init MP_ioapic_info(struct mpc_ioapic *m) {}
135 145
136static void __init MP_lintsrc_info(struct mpc_lintsrc *m) 146static void __init MP_lintsrc_info(struct mpc_lintsrc *m)
137{ 147{
138 apic_printk(APIC_VERBOSE, "Lint: type %d, pol %d, trig %d, bus %02x," 148 apic_printk(APIC_VERBOSE,
139 " IRQ %02x, APIC ID %x, APIC LINT %02x\n", 149 "Lint: type %d, pol %d, trig %d, bus %02x, IRQ %02x, APIC ID %x, APIC LINT %02x\n",
140 m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbusid, 150 m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbusid,
141 m->srcbusirq, m->destapic, m->destapiclint); 151 m->srcbusirq, m->destapic, m->destapiclint);
142} 152}
@@ -148,34 +158,33 @@ static int __init smp_check_mpc(struct mpc_table *mpc, char *oem, char *str)
148{ 158{
149 159
150 if (memcmp(mpc->signature, MPC_SIGNATURE, 4)) { 160 if (memcmp(mpc->signature, MPC_SIGNATURE, 4)) {
151 printk(KERN_ERR "MPTABLE: bad signature [%c%c%c%c]!\n", 161 pr_err("MPTABLE: bad signature [%c%c%c%c]!\n",
152 mpc->signature[0], mpc->signature[1], 162 mpc->signature[0], mpc->signature[1],
153 mpc->signature[2], mpc->signature[3]); 163 mpc->signature[2], mpc->signature[3]);
154 return 0; 164 return 0;
155 } 165 }
156 if (mpf_checksum((unsigned char *)mpc, mpc->length)) { 166 if (mpf_checksum((unsigned char *)mpc, mpc->length)) {
157 printk(KERN_ERR "MPTABLE: checksum error!\n"); 167 pr_err("MPTABLE: checksum error!\n");
158 return 0; 168 return 0;
159 } 169 }
160 if (mpc->spec != 0x01 && mpc->spec != 0x04) { 170 if (mpc->spec != 0x01 && mpc->spec != 0x04) {
161 printk(KERN_ERR "MPTABLE: bad table version (%d)!!\n", 171 pr_err("MPTABLE: bad table version (%d)!!\n", mpc->spec);
162 mpc->spec);
163 return 0; 172 return 0;
164 } 173 }
165 if (!mpc->lapic) { 174 if (!mpc->lapic) {
166 printk(KERN_ERR "MPTABLE: null local APIC address!\n"); 175 pr_err("MPTABLE: null local APIC address!\n");
167 return 0; 176 return 0;
168 } 177 }
169 memcpy(oem, mpc->oem, 8); 178 memcpy(oem, mpc->oem, 8);
170 oem[8] = 0; 179 oem[8] = 0;
171 printk(KERN_INFO "MPTABLE: OEM ID: %s\n", oem); 180 pr_info("MPTABLE: OEM ID: %s\n", oem);
172 181
173 memcpy(str, mpc->productid, 12); 182 memcpy(str, mpc->productid, 12);
174 str[12] = 0; 183 str[12] = 0;
175 184
176 printk(KERN_INFO "MPTABLE: Product ID: %s\n", str); 185 pr_info("MPTABLE: Product ID: %s\n", str);
177 186
178 printk(KERN_INFO "MPTABLE: APIC at: 0x%X\n", mpc->lapic); 187 pr_info("MPTABLE: APIC at: 0x%X\n", mpc->lapic);
179 188
180 return 1; 189 return 1;
181} 190}
@@ -188,8 +197,8 @@ static void skip_entry(unsigned char **ptr, int *count, int size)
188 197
189static void __init smp_dump_mptable(struct mpc_table *mpc, unsigned char *mpt) 198static void __init smp_dump_mptable(struct mpc_table *mpc, unsigned char *mpt)
190{ 199{
191 printk(KERN_ERR "Your mptable is wrong, contact your HW vendor!\n" 200 pr_err("Your mptable is wrong, contact your HW vendor!\n");
192 "type %x\n", *mpt); 201 pr_cont("type %x\n", *mpt);
193 print_hex_dump(KERN_ERR, " ", DUMP_PREFIX_ADDRESS, 16, 202 print_hex_dump(KERN_ERR, " ", DUMP_PREFIX_ADDRESS, 16,
194 1, mpc, mpc->length, 1); 203 1, mpc, mpc->length, 1);
195} 204}
@@ -207,9 +216,6 @@ static int __init smp_read_mpc(struct mpc_table *mpc, unsigned early)
207 if (!smp_check_mpc(mpc, oem, str)) 216 if (!smp_check_mpc(mpc, oem, str))
208 return 0; 217 return 0;
209 218
210#ifdef CONFIG_X86_32
211 generic_mps_oem_check(mpc, oem, str);
212#endif
213 /* Initialize the lapic mapping */ 219 /* Initialize the lapic mapping */
214 if (!acpi_lapic) 220 if (!acpi_lapic)
215 register_lapic_address(mpc->lapic); 221 register_lapic_address(mpc->lapic);
@@ -259,7 +265,7 @@ static int __init smp_read_mpc(struct mpc_table *mpc, unsigned early)
259 } 265 }
260 266
261 if (!num_processors) 267 if (!num_processors)
262 printk(KERN_ERR "MPTABLE: no processors registered!\n"); 268 pr_err("MPTABLE: no processors registered!\n");
263 return num_processors; 269 return num_processors;
264} 270}
265 271
@@ -295,16 +301,13 @@ static void __init construct_default_ioirq_mptable(int mpc_default_type)
295 * If it does, we assume it's valid. 301 * If it does, we assume it's valid.
296 */ 302 */
297 if (mpc_default_type == 5) { 303 if (mpc_default_type == 5) {
298 printk(KERN_INFO "ISA/PCI bus type with no IRQ information... " 304 pr_info("ISA/PCI bus type with no IRQ information... falling back to ELCR\n");
299 "falling back to ELCR\n");
300 305
301 if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2) || 306 if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2) ||
302 ELCR_trigger(13)) 307 ELCR_trigger(13))
303 printk(KERN_ERR "ELCR contains invalid data... " 308 pr_err("ELCR contains invalid data... not using ELCR\n");
304 "not using ELCR\n");
305 else { 309 else {
306 printk(KERN_INFO 310 pr_info("Using ELCR to identify PCI interrupts\n");
307 "Using ELCR to identify PCI interrupts\n");
308 ELCR_fallback = 1; 311 ELCR_fallback = 1;
309 } 312 }
310 } 313 }
@@ -353,7 +356,7 @@ static void __init construct_ioapic_table(int mpc_default_type)
353 bus.busid = 0; 356 bus.busid = 0;
354 switch (mpc_default_type) { 357 switch (mpc_default_type) {
355 default: 358 default:
356 printk(KERN_ERR "???\nUnknown standard configuration %d\n", 359 pr_err("???\nUnknown standard configuration %d\n",
357 mpc_default_type); 360 mpc_default_type);
358 /* fall through */ 361 /* fall through */
359 case 1: 362 case 1:
@@ -462,8 +465,8 @@ static int __init check_physptr(struct mpf_intel *mpf, unsigned int early)
462#ifdef CONFIG_X86_LOCAL_APIC 465#ifdef CONFIG_X86_LOCAL_APIC
463 smp_found_config = 0; 466 smp_found_config = 0;
464#endif 467#endif
465 printk(KERN_ERR "BIOS bug, MP table errors detected!...\n" 468 pr_err("BIOS bug, MP table errors detected!...\n");
466 "... disabling SMP support. (tell your hw vendor)\n"); 469 pr_cont("... disabling SMP support. (tell your hw vendor)\n");
467 early_iounmap(mpc, size); 470 early_iounmap(mpc, size);
468 return -1; 471 return -1;
469 } 472 }
@@ -481,8 +484,7 @@ static int __init check_physptr(struct mpf_intel *mpf, unsigned int early)
481 if (!mp_irq_entries) { 484 if (!mp_irq_entries) {
482 struct mpc_bus bus; 485 struct mpc_bus bus;
483 486
484 printk(KERN_ERR "BIOS bug, no explicit IRQ entries, " 487 pr_err("BIOS bug, no explicit IRQ entries, using default mptable. (tell your hw vendor)\n");
485 "using default mptable. (tell your hw vendor)\n");
486 488
487 bus.type = MP_BUS; 489 bus.type = MP_BUS;
488 bus.busid = 0; 490 bus.busid = 0;
@@ -516,14 +518,14 @@ void __init default_get_smp_config(unsigned int early)
516 if (acpi_lapic && acpi_ioapic) 518 if (acpi_lapic && acpi_ioapic)
517 return; 519 return;
518 520
519 printk(KERN_INFO "Intel MultiProcessor Specification v1.%d\n", 521 pr_info("Intel MultiProcessor Specification v1.%d\n",
520 mpf->specification); 522 mpf->specification);
521#if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32) 523#if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32)
522 if (mpf->feature2 & (1 << 7)) { 524 if (mpf->feature2 & (1 << 7)) {
523 printk(KERN_INFO " IMCR and PIC compatibility mode.\n"); 525 pr_info(" IMCR and PIC compatibility mode.\n");
524 pic_mode = 1; 526 pic_mode = 1;
525 } else { 527 } else {
526 printk(KERN_INFO " Virtual Wire compatibility mode.\n"); 528 pr_info(" Virtual Wire compatibility mode.\n");
527 pic_mode = 0; 529 pic_mode = 0;
528 } 530 }
529#endif 531#endif
@@ -539,8 +541,7 @@ void __init default_get_smp_config(unsigned int early)
539 return; 541 return;
540 } 542 }
541 543
542 printk(KERN_INFO "Default MP configuration #%d\n", 544 pr_info("Default MP configuration #%d\n", mpf->feature1);
543 mpf->feature1);
544 construct_default_ISA_mptable(mpf->feature1); 545 construct_default_ISA_mptable(mpf->feature1);
545 546
546 } else if (mpf->physptr) { 547 } else if (mpf->physptr) {
@@ -550,7 +551,7 @@ void __init default_get_smp_config(unsigned int early)
550 BUG(); 551 BUG();
551 552
552 if (!early) 553 if (!early)
553 printk(KERN_INFO "Processors: %d\n", num_processors); 554 pr_info("Processors: %d\n", num_processors);
554 /* 555 /*
555 * Only use the first configuration found. 556 * Only use the first configuration found.
556 */ 557 */
@@ -583,10 +584,10 @@ static int __init smp_scan_config(unsigned long base, unsigned long length)
583#endif 584#endif
584 mpf_found = mpf; 585 mpf_found = mpf;
585 586
586 printk(KERN_INFO "found SMP MP-table at [mem %#010llx-%#010llx] mapped at [%p]\n", 587 pr_info("found SMP MP-table at [mem %#010llx-%#010llx] mapped at [%p]\n",
587 (unsigned long long) virt_to_phys(mpf), 588 (unsigned long long) virt_to_phys(mpf),
588 (unsigned long long) virt_to_phys(mpf) + 589 (unsigned long long) virt_to_phys(mpf) +
589 sizeof(*mpf) - 1, mpf); 590 sizeof(*mpf) - 1, mpf);
590 591
591 mem = virt_to_phys(mpf); 592 mem = virt_to_phys(mpf);
592 memblock_reserve(mem, sizeof(*mpf)); 593 memblock_reserve(mem, sizeof(*mpf));
@@ -735,7 +736,7 @@ static int __init replace_intsrc_all(struct mpc_table *mpc,
735 int nr_m_spare = 0; 736 int nr_m_spare = 0;
736 unsigned char *mpt = ((unsigned char *)mpc) + count; 737 unsigned char *mpt = ((unsigned char *)mpc) + count;
737 738
738 printk(KERN_INFO "mpc_length %x\n", mpc->length); 739 pr_info("mpc_length %x\n", mpc->length);
739 while (count < mpc->length) { 740 while (count < mpc->length) {
740 switch (*mpt) { 741 switch (*mpt) {
741 case MP_PROCESSOR: 742 case MP_PROCESSOR:
@@ -862,13 +863,13 @@ static int __init update_mp_table(void)
862 if (!smp_check_mpc(mpc, oem, str)) 863 if (!smp_check_mpc(mpc, oem, str))
863 return 0; 864 return 0;
864 865
865 printk(KERN_INFO "mpf: %llx\n", (u64)virt_to_phys(mpf)); 866 pr_info("mpf: %llx\n", (u64)virt_to_phys(mpf));
866 printk(KERN_INFO "physptr: %x\n", mpf->physptr); 867 pr_info("physptr: %x\n", mpf->physptr);
867 868
868 if (mpc_new_phys && mpc->length > mpc_new_length) { 869 if (mpc_new_phys && mpc->length > mpc_new_length) {
869 mpc_new_phys = 0; 870 mpc_new_phys = 0;
870 printk(KERN_INFO "mpc_new_length is %ld, please use alloc_mptable=8k\n", 871 pr_info("mpc_new_length is %ld, please use alloc_mptable=8k\n",
871 mpc_new_length); 872 mpc_new_length);
872 } 873 }
873 874
874 if (!mpc_new_phys) { 875 if (!mpc_new_phys) {
@@ -879,10 +880,10 @@ static int __init update_mp_table(void)
879 mpc->checksum = 0xff; 880 mpc->checksum = 0xff;
880 new = mpf_checksum((unsigned char *)mpc, mpc->length); 881 new = mpf_checksum((unsigned char *)mpc, mpc->length);
881 if (old == new) { 882 if (old == new) {
882 printk(KERN_INFO "mpc is readonly, please try alloc_mptable instead\n"); 883 pr_info("mpc is readonly, please try alloc_mptable instead\n");
883 return 0; 884 return 0;
884 } 885 }
885 printk(KERN_INFO "use in-position replacing\n"); 886 pr_info("use in-position replacing\n");
886 } else { 887 } else {
887 mpf->physptr = mpc_new_phys; 888 mpf->physptr = mpc_new_phys;
888 mpc_new = phys_to_virt(mpc_new_phys); 889 mpc_new = phys_to_virt(mpc_new_phys);
@@ -892,7 +893,7 @@ static int __init update_mp_table(void)
892 if (mpc_new_phys - mpf->physptr) { 893 if (mpc_new_phys - mpf->physptr) {
893 struct mpf_intel *mpf_new; 894 struct mpf_intel *mpf_new;
894 /* steal 16 bytes from [0, 1k) */ 895 /* steal 16 bytes from [0, 1k) */
895 printk(KERN_INFO "mpf new: %x\n", 0x400 - 16); 896 pr_info("mpf new: %x\n", 0x400 - 16);
896 mpf_new = phys_to_virt(0x400 - 16); 897 mpf_new = phys_to_virt(0x400 - 16);
897 memcpy(mpf_new, mpf, 16); 898 memcpy(mpf_new, mpf, 16);
898 mpf = mpf_new; 899 mpf = mpf_new;
@@ -900,7 +901,7 @@ static int __init update_mp_table(void)
900 } 901 }
901 mpf->checksum = 0; 902 mpf->checksum = 0;
902 mpf->checksum -= mpf_checksum((unsigned char *)mpf, 16); 903 mpf->checksum -= mpf_checksum((unsigned char *)mpf, 16);
903 printk(KERN_INFO "physptr new: %x\n", mpf->physptr); 904 pr_info("physptr new: %x\n", mpf->physptr);
904 } 905 }
905 906
906 /* 907 /*
diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c
index 5492798930ef..2d872e08fab9 100644
--- a/arch/x86/kernel/smpboot.c
+++ b/arch/x86/kernel/smpboot.c
@@ -168,10 +168,6 @@ static void smp_callin(void)
168 * CPU, first the APIC. (this is probably redundant on most 168 * CPU, first the APIC. (this is probably redundant on most
169 * boards) 169 * boards)
170 */ 170 */
171
172 pr_debug("CALLIN, before setup_local_APIC()\n");
173 if (apic->smp_callin_clear_local_apic)
174 apic->smp_callin_clear_local_apic();
175 setup_local_APIC(); 171 setup_local_APIC();
176 end_local_APIC_setup(); 172 end_local_APIC_setup();
177 173
@@ -1143,10 +1139,6 @@ void __init native_smp_prepare_cpus(unsigned int max_cpus)
1143 enable_IO_APIC(); 1139 enable_IO_APIC();
1144 1140
1145 bsp_end_local_APIC_setup(); 1141 bsp_end_local_APIC_setup();
1146
1147 if (apic->setup_portio_remap)
1148 apic->setup_portio_remap();
1149
1150 smpboot_setup_io_apic(); 1142 smpboot_setup_io_apic();
1151 /* 1143 /*
1152 * Set up local APIC timer on boot CPU. 1144 * Set up local APIC timer on boot CPU.
diff --git a/arch/x86/kernel/vsmp_64.c b/arch/x86/kernel/vsmp_64.c
index b99b9ad8540c..ee22c1d93ae5 100644
--- a/arch/x86/kernel/vsmp_64.c
+++ b/arch/x86/kernel/vsmp_64.c
@@ -152,7 +152,7 @@ static void __init detect_vsmp_box(void)
152 is_vsmp = 1; 152 is_vsmp = 1;
153} 153}
154 154
155int is_vsmp_box(void) 155static int is_vsmp_box(void)
156{ 156{
157 if (is_vsmp != -1) 157 if (is_vsmp != -1)
158 return is_vsmp; 158 return is_vsmp;
@@ -166,7 +166,7 @@ int is_vsmp_box(void)
166static void __init detect_vsmp_box(void) 166static void __init detect_vsmp_box(void)
167{ 167{
168} 168}
169int is_vsmp_box(void) 169static int is_vsmp_box(void)
170{ 170{
171 return 0; 171 return 0;
172} 172}
diff --git a/arch/x86/pci/acpi.c b/arch/x86/pci/acpi.c
index 5075371ab593..cfd1b132b8e3 100644
--- a/arch/x86/pci/acpi.c
+++ b/arch/x86/pci/acpi.c
@@ -448,7 +448,7 @@ static void probe_pci_root_info(struct pci_root_info *info,
448 return; 448 return;
449 449
450 size = sizeof(*info->res) * info->res_num; 450 size = sizeof(*info->res) * info->res_num;
451 info->res = kzalloc(size, GFP_KERNEL); 451 info->res = kzalloc_node(size, GFP_KERNEL, info->sd.node);
452 if (!info->res) { 452 if (!info->res) {
453 info->res_num = 0; 453 info->res_num = 0;
454 return; 454 return;
@@ -456,7 +456,7 @@ static void probe_pci_root_info(struct pci_root_info *info,
456 456
457 size = sizeof(*info->res_offset) * info->res_num; 457 size = sizeof(*info->res_offset) * info->res_num;
458 info->res_num = 0; 458 info->res_num = 0;
459 info->res_offset = kzalloc(size, GFP_KERNEL); 459 info->res_offset = kzalloc_node(size, GFP_KERNEL, info->sd.node);
460 if (!info->res_offset) { 460 if (!info->res_offset) {
461 kfree(info->res); 461 kfree(info->res);
462 info->res = NULL; 462 info->res = NULL;
@@ -499,7 +499,7 @@ struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root)
499 if (node != NUMA_NO_NODE && !node_online(node)) 499 if (node != NUMA_NO_NODE && !node_online(node))
500 node = NUMA_NO_NODE; 500 node = NUMA_NO_NODE;
501 501
502 info = kzalloc(sizeof(*info), GFP_KERNEL); 502 info = kzalloc_node(sizeof(*info), GFP_KERNEL, node);
503 if (!info) { 503 if (!info) {
504 printk(KERN_WARNING "pci_bus %04x:%02x: " 504 printk(KERN_WARNING "pci_bus %04x:%02x: "
505 "ignored (out of memory)\n", domain, busnum); 505 "ignored (out of memory)\n", domain, busnum);
diff --git a/arch/x86/pci/intel_mid_pci.c b/arch/x86/pci/intel_mid_pci.c
index 84b9d672843d..3865116c51fb 100644
--- a/arch/x86/pci/intel_mid_pci.c
+++ b/arch/x86/pci/intel_mid_pci.c
@@ -208,27 +208,31 @@ static int pci_write(struct pci_bus *bus, unsigned int devfn, int where,
208 208
209static int intel_mid_pci_irq_enable(struct pci_dev *dev) 209static int intel_mid_pci_irq_enable(struct pci_dev *dev)
210{ 210{
211 u8 pin; 211 int polarity;
212 struct io_apic_irq_attr irq_attr;
213 212
214 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); 213 if (intel_mid_identify_cpu() == INTEL_MID_CPU_CHIP_TANGIER)
214 polarity = 0; /* active high */
215 else
216 polarity = 1; /* active low */
215 217
216 /* 218 /*
217 * MRST only have IOAPIC, the PCI irq lines are 1:1 mapped to 219 * MRST only have IOAPIC, the PCI irq lines are 1:1 mapped to
218 * IOAPIC RTE entries, so we just enable RTE for the device. 220 * IOAPIC RTE entries, so we just enable RTE for the device.
219 */ 221 */
220 irq_attr.ioapic = mp_find_ioapic(dev->irq); 222 if (mp_set_gsi_attr(dev->irq, 1, polarity, dev_to_node(&dev->dev)))
221 irq_attr.ioapic_pin = dev->irq; 223 return -EBUSY;
222 irq_attr.trigger = 1; /* level */ 224 if (mp_map_gsi_to_irq(dev->irq, IOAPIC_MAP_ALLOC) < 0)
223 if (intel_mid_identify_cpu() == INTEL_MID_CPU_CHIP_TANGIER) 225 return -EBUSY;
224 irq_attr.polarity = 0; /* active high */
225 else
226 irq_attr.polarity = 1; /* active low */
227 io_apic_set_pci_routing(&dev->dev, dev->irq, &irq_attr);
228 226
229 return 0; 227 return 0;
230} 228}
231 229
230static void intel_mid_pci_irq_disable(struct pci_dev *dev)
231{
232 if (!dev->dev.power.is_prepared && dev->irq > 0)
233 mp_unmap_irq(dev->irq);
234}
235
232struct pci_ops intel_mid_pci_ops = { 236struct pci_ops intel_mid_pci_ops = {
233 .read = pci_read, 237 .read = pci_read,
234 .write = pci_write, 238 .write = pci_write,
@@ -245,6 +249,7 @@ int __init intel_mid_pci_init(void)
245 pr_info("Intel MID platform detected, using MID PCI ops\n"); 249 pr_info("Intel MID platform detected, using MID PCI ops\n");
246 pci_mmcfg_late_init(); 250 pci_mmcfg_late_init();
247 pcibios_enable_irq = intel_mid_pci_irq_enable; 251 pcibios_enable_irq = intel_mid_pci_irq_enable;
252 pcibios_disable_irq = intel_mid_pci_irq_disable;
248 pci_root_ops = intel_mid_pci_ops; 253 pci_root_ops = intel_mid_pci_ops;
249 pci_soc_mode = 1; 254 pci_soc_mode = 1;
250 /* Continue with standard init */ 255 /* Continue with standard init */
diff --git a/arch/x86/pci/irq.c b/arch/x86/pci/irq.c
index 84112f55dd7a..bc1a2c341891 100644
--- a/arch/x86/pci/irq.c
+++ b/arch/x86/pci/irq.c
@@ -26,6 +26,7 @@ static int acer_tm360_irqrouting;
26static struct irq_routing_table *pirq_table; 26static struct irq_routing_table *pirq_table;
27 27
28static int pirq_enable_irq(struct pci_dev *dev); 28static int pirq_enable_irq(struct pci_dev *dev);
29static void pirq_disable_irq(struct pci_dev *dev);
29 30
30/* 31/*
31 * Never use: 0, 1, 2 (timer, keyboard, and cascade) 32 * Never use: 0, 1, 2 (timer, keyboard, and cascade)
@@ -53,7 +54,7 @@ struct irq_router_handler {
53}; 54};
54 55
55int (*pcibios_enable_irq)(struct pci_dev *dev) = pirq_enable_irq; 56int (*pcibios_enable_irq)(struct pci_dev *dev) = pirq_enable_irq;
56void (*pcibios_disable_irq)(struct pci_dev *dev) = NULL; 57void (*pcibios_disable_irq)(struct pci_dev *dev) = pirq_disable_irq;
57 58
58/* 59/*
59 * Check passed address for the PCI IRQ Routing Table signature 60 * Check passed address for the PCI IRQ Routing Table signature
@@ -1186,7 +1187,7 @@ void pcibios_penalize_isa_irq(int irq, int active)
1186 1187
1187static int pirq_enable_irq(struct pci_dev *dev) 1188static int pirq_enable_irq(struct pci_dev *dev)
1188{ 1189{
1189 u8 pin; 1190 u8 pin = 0;
1190 1191
1191 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); 1192 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
1192 if (pin && !pcibios_lookup_irq(dev, 1)) { 1193 if (pin && !pcibios_lookup_irq(dev, 1)) {
@@ -1227,8 +1228,6 @@ static int pirq_enable_irq(struct pci_dev *dev)
1227 } 1228 }
1228 dev = temp_dev; 1229 dev = temp_dev;
1229 if (irq >= 0) { 1230 if (irq >= 0) {
1230 io_apic_set_pci_routing(&dev->dev, irq,
1231 &irq_attr);
1232 dev->irq = irq; 1231 dev->irq = irq;
1233 dev_info(&dev->dev, "PCI->APIC IRQ transform: " 1232 dev_info(&dev->dev, "PCI->APIC IRQ transform: "
1234 "INT %c -> IRQ %d\n", 'A' + pin - 1, irq); 1233 "INT %c -> IRQ %d\n", 'A' + pin - 1, irq);
@@ -1254,3 +1253,12 @@ static int pirq_enable_irq(struct pci_dev *dev)
1254 } 1253 }
1255 return 0; 1254 return 0;
1256} 1255}
1256
1257static void pirq_disable_irq(struct pci_dev *dev)
1258{
1259 if (io_apic_assign_pci_irqs && !dev->dev.power.is_prepared &&
1260 dev->irq) {
1261 mp_unmap_irq(dev->irq);
1262 dev->irq = 0;
1263 }
1264}
diff --git a/arch/x86/pci/xen.c b/arch/x86/pci/xen.c
index 905956f16465..093f5f4272d3 100644
--- a/arch/x86/pci/xen.c
+++ b/arch/x86/pci/xen.c
@@ -23,6 +23,7 @@
23#include <xen/features.h> 23#include <xen/features.h>
24#include <xen/events.h> 24#include <xen/events.h>
25#include <asm/xen/pci.h> 25#include <asm/xen/pci.h>
26#include <asm/i8259.h>
26 27
27static int xen_pcifront_enable_irq(struct pci_dev *dev) 28static int xen_pcifront_enable_irq(struct pci_dev *dev)
28{ 29{
@@ -40,7 +41,7 @@ static int xen_pcifront_enable_irq(struct pci_dev *dev)
40 /* In PV DomU the Xen PCI backend puts the PIRQ in the interrupt line.*/ 41 /* In PV DomU the Xen PCI backend puts the PIRQ in the interrupt line.*/
41 pirq = gsi; 42 pirq = gsi;
42 43
43 if (gsi < NR_IRQS_LEGACY) 44 if (gsi < nr_legacy_irqs())
44 share = 0; 45 share = 0;
45 46
46 rc = xen_bind_pirq_gsi_to_irq(gsi, pirq, share, "pcifront"); 47 rc = xen_bind_pirq_gsi_to_irq(gsi, pirq, share, "pcifront");
@@ -511,7 +512,7 @@ int __init pci_xen_initial_domain(void)
511 xen_setup_acpi_sci(); 512 xen_setup_acpi_sci();
512 __acpi_register_gsi = acpi_register_gsi_xen; 513 __acpi_register_gsi = acpi_register_gsi_xen;
513 /* Pre-allocate legacy irqs */ 514 /* Pre-allocate legacy irqs */
514 for (irq = 0; irq < NR_IRQS_LEGACY; irq++) { 515 for (irq = 0; irq < nr_legacy_irqs(); irq++) {
515 int trigger, polarity; 516 int trigger, polarity;
516 517
517 if (acpi_get_override_irq(irq, &trigger, &polarity) == -1) 518 if (acpi_get_override_irq(irq, &trigger, &polarity) == -1)
@@ -522,7 +523,7 @@ int __init pci_xen_initial_domain(void)
522 true /* Map GSI to PIRQ */); 523 true /* Map GSI to PIRQ */);
523 } 524 }
524 if (0 == nr_ioapics) { 525 if (0 == nr_ioapics) {
525 for (irq = 0; irq < NR_IRQS_LEGACY; irq++) 526 for (irq = 0; irq < nr_legacy_irqs(); irq++)
526 xen_bind_pirq_gsi_to_irq(irq, irq, 0, "xt-pic"); 527 xen_bind_pirq_gsi_to_irq(irq, irq, 0, "xt-pic");
527 } 528 }
528 return 0; 529 return 0;
diff --git a/arch/x86/platform/ce4100/ce4100.c b/arch/x86/platform/ce4100/ce4100.c
index 8244f5ec2f4c..701fd5843c87 100644
--- a/arch/x86/platform/ce4100/ce4100.c
+++ b/arch/x86/platform/ce4100/ce4100.c
@@ -135,14 +135,10 @@ static void __init sdv_arch_setup(void)
135 sdv_serial_fixup(); 135 sdv_serial_fixup();
136} 136}
137 137
138#ifdef CONFIG_X86_IO_APIC
139static void sdv_pci_init(void) 138static void sdv_pci_init(void)
140{ 139{
141 x86_of_pci_init(); 140 x86_of_pci_init();
142 /* We can't set this earlier, because we need to calibrate the timer */
143 legacy_pic = &null_legacy_pic;
144} 141}
145#endif
146 142
147/* 143/*
148 * CE4100 specific x86_init function overrides and early setup 144 * CE4100 specific x86_init function overrides and early setup
@@ -155,7 +151,9 @@ void __init x86_ce4100_early_setup(void)
155 x86_init.resources.probe_roms = x86_init_noop; 151 x86_init.resources.probe_roms = x86_init_noop;
156 x86_init.mpparse.get_smp_config = x86_init_uint_noop; 152 x86_init.mpparse.get_smp_config = x86_init_uint_noop;
157 x86_init.mpparse.find_smp_config = x86_init_noop; 153 x86_init.mpparse.find_smp_config = x86_init_noop;
154 x86_init.mpparse.setup_ioapic_ids = setup_ioapic_ids_from_mpc_nocheck;
158 x86_init.pci.init = ce4100_pci_init; 155 x86_init.pci.init = ce4100_pci_init;
156 x86_init.pci.init_irq = sdv_pci_init;
159 157
160 /* 158 /*
161 * By default, the reboot method is ACPI which is supported by the 159 * By default, the reboot method is ACPI which is supported by the
@@ -166,10 +164,5 @@ void __init x86_ce4100_early_setup(void)
166 */ 164 */
167 reboot_type = BOOT_KBD; 165 reboot_type = BOOT_KBD;
168 166
169#ifdef CONFIG_X86_IO_APIC
170 x86_init.pci.init_irq = sdv_pci_init;
171 x86_init.mpparse.setup_ioapic_ids = setup_ioapic_ids_from_mpc_nocheck;
172#endif
173
174 pm_power_off = ce4100_power_off; 167 pm_power_off = ce4100_power_off;
175} 168}
diff --git a/arch/x86/platform/intel-mid/device_libs/platform_wdt.c b/arch/x86/platform/intel-mid/device_libs/platform_wdt.c
index 973cf3bfa9fd..0b283d4d0ad7 100644
--- a/arch/x86/platform/intel-mid/device_libs/platform_wdt.c
+++ b/arch/x86/platform/intel-mid/device_libs/platform_wdt.c
@@ -26,28 +26,18 @@ static struct platform_device wdt_dev = {
26 26
27static int tangier_probe(struct platform_device *pdev) 27static int tangier_probe(struct platform_device *pdev)
28{ 28{
29 int ioapic; 29 int gsi;
30 int irq;
31 struct intel_mid_wdt_pdata *pdata = pdev->dev.platform_data; 30 struct intel_mid_wdt_pdata *pdata = pdev->dev.platform_data;
32 struct io_apic_irq_attr irq_attr = { 0 };
33 31
34 if (!pdata) 32 if (!pdata)
35 return -EINVAL; 33 return -EINVAL;
36 34
37 irq = pdata->irq; 35 /* IOAPIC builds identity mapping between GSI and IRQ on MID */
38 ioapic = mp_find_ioapic(irq); 36 gsi = pdata->irq;
39 if (ioapic >= 0) { 37 if (mp_set_gsi_attr(gsi, 1, 0, cpu_to_node(0)) ||
40 int ret; 38 mp_map_gsi_to_irq(gsi, IOAPIC_MAP_ALLOC) <= 0) {
41 irq_attr.ioapic = ioapic;
42 irq_attr.ioapic_pin = irq;
43 irq_attr.trigger = 1;
44 /* irq_attr.polarity = 0; -> Active high */
45 ret = io_apic_set_pci_routing(NULL, irq, &irq_attr);
46 if (ret)
47 return ret;
48 } else {
49 dev_warn(&pdev->dev, "cannot find interrupt %d in ioapic\n", 39 dev_warn(&pdev->dev, "cannot find interrupt %d in ioapic\n",
50 irq); 40 gsi);
51 return -EINVAL; 41 return -EINVAL;
52 } 42 }
53 43
diff --git a/arch/x86/platform/intel-mid/sfi.c b/arch/x86/platform/intel-mid/sfi.c
index 994c40bd7cb7..3c53a90fdb18 100644
--- a/arch/x86/platform/intel-mid/sfi.c
+++ b/arch/x86/platform/intel-mid/sfi.c
@@ -432,9 +432,8 @@ static int __init sfi_parse_devs(struct sfi_table_header *table)
432 struct sfi_table_simple *sb; 432 struct sfi_table_simple *sb;
433 struct sfi_device_table_entry *pentry; 433 struct sfi_device_table_entry *pentry;
434 struct devs_id *dev = NULL; 434 struct devs_id *dev = NULL;
435 int num, i; 435 int num, i, ret;
436 int ioapic; 436 int polarity;
437 struct io_apic_irq_attr irq_attr;
438 437
439 sb = (struct sfi_table_simple *)table; 438 sb = (struct sfi_table_simple *)table;
440 num = SFI_GET_NUM_ENTRIES(sb, struct sfi_device_table_entry); 439 num = SFI_GET_NUM_ENTRIES(sb, struct sfi_device_table_entry);
@@ -448,35 +447,30 @@ static int __init sfi_parse_devs(struct sfi_table_header *table)
448 * devices, but they have separate RTE entry in IOAPIC 447 * devices, but they have separate RTE entry in IOAPIC
449 * so we have to enable them one by one here 448 * so we have to enable them one by one here
450 */ 449 */
451 ioapic = mp_find_ioapic(irq); 450 if (intel_mid_identify_cpu() ==
452 if (ioapic >= 0) { 451 INTEL_MID_CPU_CHIP_TANGIER) {
453 irq_attr.ioapic = ioapic; 452 if (!strncmp(pentry->name, "r69001-ts-i2c", 13))
454 irq_attr.ioapic_pin = irq; 453 /* active low */
455 irq_attr.trigger = 1; 454 polarity = 1;
456 if (intel_mid_identify_cpu() == 455 else if (!strncmp(pentry->name,
457 INTEL_MID_CPU_CHIP_TANGIER) { 456 "synaptics_3202", 14))
458 if (!strncmp(pentry->name, 457 /* active low */
459 "r69001-ts-i2c", 13)) 458 polarity = 1;
460 /* active low */ 459 else if (irq == 41)
461 irq_attr.polarity = 1; 460 /* fast_int_1 */
462 else if (!strncmp(pentry->name, 461 polarity = 1;
463 "synaptics_3202", 14)) 462 else
464 /* active low */ 463 /* active high */
465 irq_attr.polarity = 1; 464 polarity = 0;
466 else if (irq == 41) 465 } else {
467 /* fast_int_1 */ 466 /* PNW and CLV go with active low */
468 irq_attr.polarity = 1; 467 polarity = 1;
469 else
470 /* active high */
471 irq_attr.polarity = 0;
472 } else {
473 /* PNW and CLV go with active low */
474 irq_attr.polarity = 1;
475 }
476 io_apic_set_pci_routing(NULL, irq, &irq_attr);
477 } 468 }
478 } else { 469
479 irq = 0; /* No irq */ 470 ret = mp_set_gsi_attr(irq, 1, polarity, NUMA_NO_NODE);
471 if (ret == 0)
472 ret = mp_map_gsi_to_irq(irq, IOAPIC_MAP_ALLOC);
473 WARN_ON(ret < 0);
480 } 474 }
481 475
482 dev = get_device_id(pentry->type, pentry->name); 476 dev = get_device_id(pentry->type, pentry->name);
diff --git a/arch/x86/platform/sfi/sfi.c b/arch/x86/platform/sfi/sfi.c
index bcd1a703e3e6..2a8a74f3bd76 100644
--- a/arch/x86/platform/sfi/sfi.c
+++ b/arch/x86/platform/sfi/sfi.c
@@ -25,6 +25,7 @@
25#include <linux/init.h> 25#include <linux/init.h>
26#include <linux/sfi.h> 26#include <linux/sfi.h>
27#include <linux/io.h> 27#include <linux/io.h>
28#include <linux/irqdomain.h>
28 29
29#include <asm/io_apic.h> 30#include <asm/io_apic.h>
30#include <asm/mpspec.h> 31#include <asm/mpspec.h>
@@ -70,19 +71,26 @@ static int __init sfi_parse_cpus(struct sfi_table_header *table)
70#endif /* CONFIG_X86_LOCAL_APIC */ 71#endif /* CONFIG_X86_LOCAL_APIC */
71 72
72#ifdef CONFIG_X86_IO_APIC 73#ifdef CONFIG_X86_IO_APIC
74static struct irq_domain_ops sfi_ioapic_irqdomain_ops = {
75 .map = mp_irqdomain_map,
76};
73 77
74static int __init sfi_parse_ioapic(struct sfi_table_header *table) 78static int __init sfi_parse_ioapic(struct sfi_table_header *table)
75{ 79{
76 struct sfi_table_simple *sb; 80 struct sfi_table_simple *sb;
77 struct sfi_apic_table_entry *pentry; 81 struct sfi_apic_table_entry *pentry;
78 int i, num; 82 int i, num;
83 struct ioapic_domain_cfg cfg = {
84 .type = IOAPIC_DOMAIN_STRICT,
85 .ops = &sfi_ioapic_irqdomain_ops,
86 };
79 87
80 sb = (struct sfi_table_simple *)table; 88 sb = (struct sfi_table_simple *)table;
81 num = SFI_GET_NUM_ENTRIES(sb, struct sfi_apic_table_entry); 89 num = SFI_GET_NUM_ENTRIES(sb, struct sfi_apic_table_entry);
82 pentry = (struct sfi_apic_table_entry *)sb->pentry; 90 pentry = (struct sfi_apic_table_entry *)sb->pentry;
83 91
84 for (i = 0; i < num; i++) { 92 for (i = 0; i < num; i++) {
85 mp_register_ioapic(i, pentry->phys_addr, gsi_top); 93 mp_register_ioapic(i, pentry->phys_addr, gsi_top, &cfg);
86 pentry++; 94 pentry++;
87 } 95 }
88 96
diff --git a/drivers/acpi/pci_irq.c b/drivers/acpi/pci_irq.c
index 9c62340c2360..c96887d5289e 100644
--- a/drivers/acpi/pci_irq.c
+++ b/drivers/acpi/pci_irq.c
@@ -481,6 +481,10 @@ void acpi_pci_irq_disable(struct pci_dev *dev)
481 if (!pin) 481 if (!pin)
482 return; 482 return;
483 483
484 /* Keep IOAPIC pin configuration when suspending */
485 if (dev->dev.power.is_prepared)
486 return;
487
484 entry = acpi_pci_irq_lookup(dev, pin); 488 entry = acpi_pci_irq_lookup(dev, pin);
485 if (!entry) 489 if (!entry)
486 return; 490 return;
@@ -498,5 +502,6 @@ void acpi_pci_irq_disable(struct pci_dev *dev)
498 */ 502 */
499 503
500 dev_dbg(&dev->dev, "PCI INT %c disabled\n", pin_name(pin)); 504 dev_dbg(&dev->dev, "PCI INT %c disabled\n", pin_name(pin));
501 acpi_unregister_gsi(gsi); 505 if (gsi >= 0 && dev->irq > 0)
506 acpi_unregister_gsi(gsi);
502} 507}
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-05 08:00:13 -0500