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authorCK Hu <ck.hu@mediatek.com>2016-06-03 10:59:29 -0400
committerMatthias Brugger <matthias.bgg@gmail.com>2016-06-03 11:39:23 -0400
commit81ad4dbaf7afff590e81c7fe0c519c5a67d1a444 (patch)
treee5f7dc66528e2c4f305c86277bc6885f616932d5
parent1a695a905c18548062509178b98bc91e67510864 (diff)
arm64: dts: mt8173: Add display subsystem related nodes
This patch adds the device nodes for the DISP function blocks comprising the display subsystem. Signed-off-by: CK Hu <ck.hu@mediatek.com> Signed-off-by: Cawa Cheng <cawa.cheng@mediatek.com> Signed-off-by: Jie Qiu <jie.qiu@mediatek.com> Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Diffstat
-rw-r--r--arch/arm64/boot/dts/mediatek/mt8173.dtsi223
1 files changed, 223 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 05f89c4a5413..78529e4e8379 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -26,6 +26,23 @@
26 #address-cells = <2>; 26 #address-cells = <2>;
27 #size-cells = <2>; 27 #size-cells = <2>;
28 28
29 aliases {
30 ovl0 = &ovl0;
31 ovl1 = &ovl1;
32 rdma0 = &rdma0;
33 rdma1 = &rdma1;
34 rdma2 = &rdma2;
35 wdma0 = &wdma0;
36 wdma1 = &wdma1;
37 color0 = &color0;
38 color1 = &color1;
39 split0 = &split0;
40 split1 = &split1;
41 dpi0 = &dpi0;
42 dsi0 = &dsi0;
43 dsi1 = &dsi1;
44 };
45
29 cpus { 46 cpus {
30 #address-cells = <1>; 47 #address-cells = <1>;
31 #size-cells = <0>; 48 #size-cells = <0>;
@@ -343,6 +360,26 @@
343 #clock-cells = <1>; 360 #clock-cells = <1>;
344 }; 361 };
345 362
363 mipi_tx0: mipi-dphy@10215000 {
364 compatible = "mediatek,mt8173-mipi-tx";
365 reg = <0 0x10215000 0 0x1000>;
366 clocks = <&clk26m>;
367 clock-output-names = "mipi_tx0_pll";
368 #clock-cells = <0>;
369 #phy-cells = <0>;
370 status = "disabled";
371 };
372
373 mipi_tx1: mipi-dphy@10216000 {
374 compatible = "mediatek,mt8173-mipi-tx";
375 reg = <0 0x10216000 0 0x1000>;
376 clocks = <&clk26m>;
377 clock-output-names = "mipi_tx1_pll";
378 #clock-cells = <0>;
379 #phy-cells = <0>;
380 status = "disabled";
381 };
382
346 gic: interrupt-controller@10220000 { 383 gic: interrupt-controller@10220000 {
347 compatible = "arm,gic-400"; 384 compatible = "arm,gic-400";
348 #interrupt-cells = <3>; 385 #interrupt-cells = <3>;
@@ -652,9 +689,181 @@
652 mmsys: clock-controller@14000000 { 689 mmsys: clock-controller@14000000 {
653 compatible = "mediatek,mt8173-mmsys", "syscon"; 690 compatible = "mediatek,mt8173-mmsys", "syscon";
654 reg = <0 0x14000000 0 0x1000>; 691 reg = <0 0x14000000 0 0x1000>;
692 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
655 #clock-cells = <1>; 693 #clock-cells = <1>;
656 }; 694 };
657 695
696 ovl0: ovl@1400c000 {
697 compatible = "mediatek,mt8173-disp-ovl";
698 reg = <0 0x1400c000 0 0x1000>;
699 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
700 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
701 clocks = <&mmsys CLK_MM_DISP_OVL0>;
702 iommus = <&iommu M4U_PORT_DISP_OVL0>;
703 mediatek,larb = <&larb0>;
704 };
705
706 ovl1: ovl@1400d000 {
707 compatible = "mediatek,mt8173-disp-ovl";
708 reg = <0 0x1400d000 0 0x1000>;
709 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_LOW>;
710 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
711 clocks = <&mmsys CLK_MM_DISP_OVL1>;
712 iommus = <&iommu M4U_PORT_DISP_OVL1>;
713 mediatek,larb = <&larb4>;
714 };
715
716 rdma0: rdma@1400e000 {
717 compatible = "mediatek,mt8173-disp-rdma";
718 reg = <0 0x1400e000 0 0x1000>;
719 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>;
720 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
721 clocks = <&mmsys CLK_MM_DISP_RDMA0>;
722 iommus = <&iommu M4U_PORT_DISP_RDMA0>;
723 mediatek,larb = <&larb0>;
724 };
725
726 rdma1: rdma@1400f000 {
727 compatible = "mediatek,mt8173-disp-rdma";
728 reg = <0 0x1400f000 0 0x1000>;
729 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_LOW>;
730 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
731 clocks = <&mmsys CLK_MM_DISP_RDMA1>;
732 iommus = <&iommu M4U_PORT_DISP_RDMA1>;
733 mediatek,larb = <&larb4>;
734 };
735
736 rdma2: rdma@14010000 {
737 compatible = "mediatek,mt8173-disp-rdma";
738 reg = <0 0x14010000 0 0x1000>;
739 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_LOW>;
740 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
741 clocks = <&mmsys CLK_MM_DISP_RDMA2>;
742 iommus = <&iommu M4U_PORT_DISP_RDMA2>;
743 mediatek,larb = <&larb4>;
744 };
745
746 wdma0: wdma@14011000 {
747 compatible = "mediatek,mt8173-disp-wdma";
748 reg = <0 0x14011000 0 0x1000>;
749 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>;
750 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
751 clocks = <&mmsys CLK_MM_DISP_WDMA0>;
752 iommus = <&iommu M4U_PORT_DISP_WDMA0>;
753 mediatek,larb = <&larb0>;
754 };
755
756 wdma1: wdma@14012000 {
757 compatible = "mediatek,mt8173-disp-wdma";
758 reg = <0 0x14012000 0 0x1000>;
759 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_LOW>;
760 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
761 clocks = <&mmsys CLK_MM_DISP_WDMA1>;
762 iommus = <&iommu M4U_PORT_DISP_WDMA1>;
763 mediatek,larb = <&larb4>;
764 };
765
766 color0: color@14013000 {
767 compatible = "mediatek,mt8173-disp-color";
768 reg = <0 0x14013000 0 0x1000>;
769 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>;
770 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
771 clocks = <&mmsys CLK_MM_DISP_COLOR0>;
772 };
773
774 color1: color@14014000 {
775 compatible = "mediatek,mt8173-disp-color";
776 reg = <0 0x14014000 0 0x1000>;
777 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>;
778 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
779 clocks = <&mmsys CLK_MM_DISP_COLOR1>;
780 };
781
782 aal@14015000 {
783 compatible = "mediatek,mt8173-disp-aal";
784 reg = <0 0x14015000 0 0x1000>;
785 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
786 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
787 clocks = <&mmsys CLK_MM_DISP_AAL>;
788 };
789
790 gamma@14016000 {
791 compatible = "mediatek,mt8173-disp-gamma";
792 reg = <0 0x14016000 0 0x1000>;
793 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>;
794 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
795 clocks = <&mmsys CLK_MM_DISP_GAMMA>;
796 };
797
798 merge@14017000 {
799 compatible = "mediatek,mt8173-disp-merge";
800 reg = <0 0x14017000 0 0x1000>;
801 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
802 clocks = <&mmsys CLK_MM_DISP_MERGE>;
803 };
804
805 split0: split@14018000 {
806 compatible = "mediatek,mt8173-disp-split";
807 reg = <0 0x14018000 0 0x1000>;
808 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
809 clocks = <&mmsys CLK_MM_DISP_SPLIT0>;
810 };
811
812 split1: split@14019000 {
813 compatible = "mediatek,mt8173-disp-split";
814 reg = <0 0x14019000 0 0x1000>;
815 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
816 clocks = <&mmsys CLK_MM_DISP_SPLIT1>;
817 };
818
819 ufoe@1401a000 {
820 compatible = "mediatek,mt8173-disp-ufoe";
821 reg = <0 0x1401a000 0 0x1000>;
822 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>;
823 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
824 clocks = <&mmsys CLK_MM_DISP_UFOE>;
825 };
826
827 dsi0: dsi@1401b000 {
828 compatible = "mediatek,mt8173-dsi";
829 reg = <0 0x1401b000 0 0x1000>;
830 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>;
831 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
832 clocks = <&mmsys CLK_MM_DSI0_ENGINE>,
833 <&mmsys CLK_MM_DSI0_DIGITAL>,
834 <&mipi_tx0>;
835 clock-names = "engine", "digital", "hs";
836 phys = <&mipi_tx0>;
837 phy-names = "dphy";
838 status = "disabled";
839 };
840
841 dsi1: dsi@1401c000 {
842 compatible = "mediatek,mt8173-dsi";
843 reg = <0 0x1401c000 0 0x1000>;
844 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
845 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
846 clocks = <&mmsys CLK_MM_DSI1_ENGINE>,
847 <&mmsys CLK_MM_DSI1_DIGITAL>,
848 <&mipi_tx1>;
849 clock-names = "engine", "digital", "hs";
850 phy = <&mipi_tx1>;
851 phy-names = "dphy";
852 status = "disabled";
853 };
854
855 dpi0: dpi@1401d000 {
856 compatible = "mediatek,mt8173-dpi";
857 reg = <0 0x1401d000 0 0x1000>;
858 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
859 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
860 clocks = <&mmsys CLK_MM_DPI_PIXEL>,
861 <&mmsys CLK_MM_DPI_ENGINE>,
862 <&apmixedsys CLK_APMIXED_TVDPLL>;
863 clock-names = "pixel", "engine", "pll";
864 status = "disabled";
865 };
866
658 pwm0: pwm@1401e000 { 867 pwm0: pwm@1401e000 {
659 compatible = "mediatek,mt8173-disp-pwm", 868 compatible = "mediatek,mt8173-disp-pwm",
660 "mediatek,mt6595-disp-pwm"; 869 "mediatek,mt6595-disp-pwm";
@@ -677,6 +886,14 @@
677 status = "disabled"; 886 status = "disabled";
678 }; 887 };
679 888
889 mutex: mutex@14020000 {
890 compatible = "mediatek,mt8173-disp-mutex";
891 reg = <0 0x14020000 0 0x1000>;
892 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
893 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
894 clocks = <&mmsys CLK_MM_MUTEX_32K>;
895 };
896
680 larb0: larb@14021000 { 897 larb0: larb@14021000 {
681 compatible = "mediatek,mt8173-smi-larb"; 898 compatible = "mediatek,mt8173-smi-larb";
682 reg = <0 0x14021000 0 0x1000>; 899 reg = <0 0x14021000 0 0x1000>;
@@ -696,6 +913,12 @@
696 clock-names = "apb", "smi"; 913 clock-names = "apb", "smi";
697 }; 914 };
698 915
916 od@14023000 {
917 compatible = "mediatek,mt8173-disp-od";
918 reg = <0 0x14023000 0 0x1000>;
919 clocks = <&mmsys CLK_MM_DISP_OD>;
920 };
921
699 larb4: larb@14027000 { 922 larb4: larb@14027000 {
700 compatible = "mediatek,mt8173-smi-larb"; 923 compatible = "mediatek,mt8173-smi-larb";
701 reg = <0 0x14027000 0 0x1000>; 924 reg = <0 0x14027000 0 0x1000>;
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-11 07:04:23 -0400