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authorMingkai Hu <Mingkai.Hu@nxp.com>2016-09-13 04:09:59 -0400
committerShawn Guo <shawnguo@kernel.org>2016-10-21 09:33:50 -0400
commit8126d88162a5cef24b7d8106b45185bcb3fd3fe8 (patch)
treea7d2fc98b573ddc7485882bb3b34db0f3e4e70a1
parent4afb47445570e0fd5763169c48033c6486aa7709 (diff)
arm64: dts: add QorIQ LS1046A SoC support
LS1046A is an SoC with 4 ARMv8 A72 cores and most other IP blocks are similar to LS1043A which also complies to Freescale Chassis 2.1 spec. Created LS1046A SoC DTSI file to be included by board level DTS files. Signed-off-by: Horia Geant? <horia.geanta@nxp.com> Signed-off-by: Mihai Bantea <mihai.bantea@nxp.com> Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@nxp.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi515
1 files changed, 515 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
new file mode 100644
index 000000000000..38806ca53829
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -0,0 +1,515 @@
1/*
2 * Device Tree Include file for Freescale Layerscape-1046A family SoC.
3 *
4 * Copyright 2016, Freescale Semiconductor, Inc.
5 *
6 * Mingkai Hu <mingkai.hu@nxp.com>
7 *
8 * This file is dual-licensed: you can use it either under the terms
9 * of the GPLv2 or the X11 license, at your option. Note that this dual
10 * licensing only applies to this file, and not this project as a
11 * whole.
12 *
13 * a) This library is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of the
16 * License, or (at your option) any later version.
17 *
18 * This library is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * Or, alternatively,
24 *
25 * b) Permission is hereby granted, free of charge, to any person
26 * obtaining a copy of this software and associated documentation
27 * files (the "Software"), to deal in the Software without
28 * restriction, including without limitation the rights to use,
29 * copy, modify, merge, publish, distribute, sublicense, and/or
30 * sell copies of the Software, and to permit persons to whom the
31 * Software is furnished to do so, subject to the following
32 * conditions:
33 *
34 * The above copyright notice and this permission notice shall be
35 * included in all copies or substantial portions of the Software.
36 *
37 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
38 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
39 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
40 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
41 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
42 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
43 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
44 * OTHER DEALINGS IN THE SOFTWARE.
45 */
46
47#include <dt-bindings/interrupt-controller/arm-gic.h>
48
49/ {
50 compatible = "fsl,ls1046a";
51 interrupt-parent = <&gic>;
52 #address-cells = <2>;
53 #size-cells = <2>;
54
55 aliases {
56 crypto = &crypto;
57 };
58
59 cpus {
60 #address-cells = <1>;
61 #size-cells = <0>;
62
63 cpu0: cpu@0 {
64 device_type = "cpu";
65 compatible = "arm,cortex-a72";
66 reg = <0x0>;
67 clocks = <&clockgen 1 0>;
68 next-level-cache = <&l2>;
69 cpu-idle-states = <&CPU_PH20>;
70 };
71
72 cpu1: cpu@1 {
73 device_type = "cpu";
74 compatible = "arm,cortex-a72";
75 reg = <0x1>;
76 clocks = <&clockgen 1 0>;
77 next-level-cache = <&l2>;
78 cpu-idle-states = <&CPU_PH20>;
79 };
80
81 cpu2: cpu@2 {
82 device_type = "cpu";
83 compatible = "arm,cortex-a72";
84 reg = <0x2>;
85 clocks = <&clockgen 1 0>;
86 next-level-cache = <&l2>;
87 cpu-idle-states = <&CPU_PH20>;
88 };
89
90 cpu3: cpu@3 {
91 device_type = "cpu";
92 compatible = "arm,cortex-a72";
93 reg = <0x3>;
94 clocks = <&clockgen 1 0>;
95 next-level-cache = <&l2>;
96 cpu-idle-states = <&CPU_PH20>;
97 };
98
99 l2: l2-cache {
100 compatible = "cache";
101 };
102 };
103
104 idle-states {
105 /*
106 * PSCI node is not added default, U-boot will add missing
107 * parts if it determines to use PSCI.
108 */
109 entry-method = "arm,psci";
110
111 CPU_PH20: cpu-ph20 {
112 compatible = "arm,idle-state";
113 idle-state-name = "PH20";
114 arm,psci-suspend-param = <0x00010000>;
115 entry-latency-us = <1000>;
116 exit-latency-us = <1000>;
117 min-residency-us = <3000>;
118 };
119 };
120
121 memory@80000000 {
122 device_type = "memory";
123 };
124
125 sysclk: sysclk {
126 compatible = "fixed-clock";
127 #clock-cells = <0>;
128 clock-frequency = <100000000>;
129 clock-output-names = "sysclk";
130 };
131
132 reboot {
133 compatible ="syscon-reboot";
134 regmap = <&dcfg>;
135 offset = <0xb0>;
136 mask = <0x02>;
137 };
138
139 timer {
140 compatible = "arm,armv8-timer";
141 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xf) |
142 IRQ_TYPE_LEVEL_LOW)>,
143 <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xf) |
144 IRQ_TYPE_LEVEL_LOW)>,
145 <GIC_PPI 11 (GIC_CPU_MASK_RAW(0xf) |
146 IRQ_TYPE_LEVEL_LOW)>,
147 <GIC_PPI 10 (GIC_CPU_MASK_RAW(0xf) |
148 IRQ_TYPE_LEVEL_LOW)>;
149 };
150
151 pmu {
152 compatible = "arm,cortex-a72-pmu";
153 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
154 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
155 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
156 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
157 interrupt-affinity = <&cpu0>,
158 <&cpu1>,
159 <&cpu2>,
160 <&cpu3>;
161 };
162
163 gic: interrupt-controller@1400000 {
164 compatible = "arm,gic-400";
165 #interrupt-cells = <3>;
166 interrupt-controller;
167 reg = <0x0 0x1410000 0 0x10000>, /* GICD */
168 <0x0 0x1420000 0 0x20000>, /* GICC */
169 <0x0 0x1440000 0 0x20000>, /* GICH */
170 <0x0 0x1460000 0 0x20000>; /* GICV */
171 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
172 IRQ_TYPE_LEVEL_LOW)>;
173 };
174
175 soc {
176 compatible = "simple-bus";
177 #address-cells = <2>;
178 #size-cells = <2>;
179 ranges;
180
181 ddr: memory-controller@1080000 {
182 compatible = "fsl,qoriq-memory-controller";
183 reg = <0x0 0x1080000 0x0 0x1000>;
184 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
185 big-endian;
186 };
187
188 ifc: ifc@1530000 {
189 compatible = "fsl,ifc", "simple-bus";
190 reg = <0x0 0x1530000 0x0 0x10000>;
191 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
192 };
193
194 qspi: quadspi@1550000 {
195 compatible = "fsl,ls1021a-qspi";
196 #address-cells = <1>;
197 #size-cells = <0>;
198 reg = <0x0 0x1550000 0x0 0x10000>,
199 <0x0 0x40000000 0x0 0x10000000>;
200 reg-names = "QuadSPI", "QuadSPI-memory";
201 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
202 clock-names = "qspi_en", "qspi";
203 clocks = <&clockgen 4 1>, <&clockgen 4 1>;
204 big-endian;
205 fsl,qspi-has-second-chip;
206 status = "disabled";
207 };
208
209 esdhc: esdhc@1560000 {
210 compatible = "fsl,esdhc";
211 reg = <0x0 0x1560000 0x0 0x10000>;
212 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
213 clock-frequency = <0>;
214 voltage-ranges = <1800 1800 3300 3300>;
215 sdhci,auto-cmd12;
216 big-endian;
217 bus-width = <4>;
218 };
219
220 scfg: scfg@1570000 {
221 compatible = "fsl,ls1046a-scfg", "syscon";
222 reg = <0x0 0x1570000 0x0 0x10000>;
223 big-endian;
224 };
225
226 crypto: crypto@1700000 {
227 compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
228 "fsl,sec-v4.0";
229 fsl,sec-era = <8>;
230 #address-cells = <1>;
231 #size-cells = <1>;
232 ranges = <0x0 0x00 0x1700000 0x100000>;
233 reg = <0x00 0x1700000 0x0 0x100000>;
234 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
235
236 sec_jr0: jr@10000 {
237 compatible = "fsl,sec-v5.4-job-ring",
238 "fsl,sec-v5.0-job-ring",
239 "fsl,sec-v4.0-job-ring";
240 reg = <0x10000 0x10000>;
241 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
242 };
243
244 sec_jr1: jr@20000 {
245 compatible = "fsl,sec-v5.4-job-ring",
246 "fsl,sec-v5.0-job-ring",
247 "fsl,sec-v4.0-job-ring";
248 reg = <0x20000 0x10000>;
249 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
250 };
251
252 sec_jr2: jr@30000 {
253 compatible = "fsl,sec-v5.4-job-ring",
254 "fsl,sec-v5.0-job-ring",
255 "fsl,sec-v4.0-job-ring";
256 reg = <0x30000 0x10000>;
257 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
258 };
259
260 sec_jr3: jr@40000 {
261 compatible = "fsl,sec-v5.4-job-ring",
262 "fsl,sec-v5.0-job-ring",
263 "fsl,sec-v4.0-job-ring";
264 reg = <0x40000 0x10000>;
265 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
266 };
267 };
268
269 dcfg: dcfg@1ee0000 {
270 compatible = "fsl,ls1046a-dcfg", "syscon";
271 reg = <0x0 0x1ee0000 0x0 0x10000>;
272 big-endian;
273 };
274
275 clockgen: clocking@1ee1000 {
276 compatible = "fsl,ls1046a-clockgen";
277 reg = <0x0 0x1ee1000 0x0 0x1000>;
278 #clock-cells = <2>;
279 clocks = <&sysclk>;
280 };
281
282 dspi: dspi@2100000 {
283 compatible = "fsl,ls1021a-v1.0-dspi";
284 #address-cells = <1>;
285 #size-cells = <0>;
286 reg = <0x0 0x2100000 0x0 0x10000>;
287 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
288 clock-names = "dspi";
289 clocks = <&clockgen 4 1>;
290 spi-num-chipselects = <5>;
291 big-endian;
292 status = "disabled";
293 };
294
295 i2c0: i2c@2180000 {
296 compatible = "fsl,vf610-i2c";
297 #address-cells = <1>;
298 #size-cells = <0>;
299 reg = <0x0 0x2180000 0x0 0x10000>;
300 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
301 clocks = <&clockgen 4 1>;
302 dmas = <&edma0 1 39>,
303 <&edma0 1 38>;
304 dma-names = "tx", "rx";
305 status = "disabled";
306 };
307
308 i2c1: i2c@2190000 {
309 compatible = "fsl,vf610-i2c";
310 #address-cells = <1>;
311 #size-cells = <0>;
312 reg = <0x0 0x2190000 0x0 0x10000>;
313 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
314 clocks = <&clockgen 4 1>;
315 status = "disabled";
316 };
317
318 i2c2: i2c@21a0000 {
319 compatible = "fsl,vf610-i2c";
320 #address-cells = <1>;
321 #size-cells = <0>;
322 reg = <0x0 0x21a0000 0x0 0x10000>;
323 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
324 clocks = <&clockgen 4 1>;
325 status = "disabled";
326 };
327
328 i2c3: i2c@21b0000 {
329 compatible = "fsl,vf610-i2c";
330 #address-cells = <1>;
331 #size-cells = <0>;
332 reg = <0x0 0x21b0000 0x0 0x10000>;
333 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
334 clocks = <&clockgen 4 1>;
335 status = "disabled";
336 };
337
338 duart0: serial@21c0500 {
339 compatible = "fsl,ns16550", "ns16550a";
340 reg = <0x00 0x21c0500 0x0 0x100>;
341 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
342 clocks = <&clockgen 4 1>;
343 };
344
345 duart1: serial@21c0600 {
346 compatible = "fsl,ns16550", "ns16550a";
347 reg = <0x00 0x21c0600 0x0 0x100>;
348 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
349 clocks = <&clockgen 4 1>;
350 };
351
352 duart2: serial@21d0500 {
353 compatible = "fsl,ns16550", "ns16550a";
354 reg = <0x0 0x21d0500 0x0 0x100>;
355 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
356 clocks = <&clockgen 4 1>;
357 };
358
359 duart3: serial@21d0600 {
360 compatible = "fsl,ns16550", "ns16550a";
361 reg = <0x0 0x21d0600 0x0 0x100>;
362 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
363 clocks = <&clockgen 4 1>;
364 };
365
366 gpio0: gpio@2300000 {
367 compatible = "fsl,qoriq-gpio";
368 reg = <0x0 0x2300000 0x0 0x10000>;
369 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
370 gpio-controller;
371 #gpio-cells = <2>;
372 interrupt-controller;
373 #interrupt-cells = <2>;
374 };
375
376 gpio1: gpio@2310000 {
377 compatible = "fsl,qoriq-gpio";
378 reg = <0x0 0x2310000 0x0 0x10000>;
379 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
380 gpio-controller;
381 #gpio-cells = <2>;
382 interrupt-controller;
383 #interrupt-cells = <2>;
384 };
385
386 gpio2: gpio@2320000 {
387 compatible = "fsl,qoriq-gpio";
388 reg = <0x0 0x2320000 0x0 0x10000>;
389 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
390 gpio-controller;
391 #gpio-cells = <2>;
392 interrupt-controller;
393 #interrupt-cells = <2>;
394 };
395
396 gpio3: gpio@2330000 {
397 compatible = "fsl,qoriq-gpio";
398 reg = <0x0 0x2330000 0x0 0x10000>;
399 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
400 gpio-controller;
401 #gpio-cells = <2>;
402 interrupt-controller;
403 #interrupt-cells = <2>;
404 };
405
406 lpuart0: serial@2950000 {
407 compatible = "fsl,ls1021a-lpuart";
408 reg = <0x0 0x2950000 0x0 0x1000>;
409 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
410 clocks = <&clockgen 4 0>;
411 clock-names = "ipg";
412 status = "disabled";
413 };
414
415 lpuart1: serial@2960000 {
416 compatible = "fsl,ls1021a-lpuart";
417 reg = <0x0 0x2960000 0x0 0x1000>;
418 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
419 clocks = <&clockgen 4 1>;
420 clock-names = "ipg";
421 status = "disabled";
422 };
423
424 lpuart2: serial@2970000 {
425 compatible = "fsl,ls1021a-lpuart";
426 reg = <0x0 0x2970000 0x0 0x1000>;
427 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
428 clocks = <&clockgen 4 1>;
429 clock-names = "ipg";
430 status = "disabled";
431 };
432
433 lpuart3: serial@2980000 {
434 compatible = "fsl,ls1021a-lpuart";
435 reg = <0x0 0x2980000 0x0 0x1000>;
436 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
437 clocks = <&clockgen 4 1>;
438 clock-names = "ipg";
439 status = "disabled";
440 };
441
442 lpuart4: serial@2990000 {
443 compatible = "fsl,ls1021a-lpuart";
444 reg = <0x0 0x2990000 0x0 0x1000>;
445 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
446 clocks = <&clockgen 4 1>;
447 clock-names = "ipg";
448 status = "disabled";
449 };
450
451 lpuart5: serial@29a0000 {
452 compatible = "fsl,ls1021a-lpuart";
453 reg = <0x0 0x29a0000 0x0 0x1000>;
454 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
455 clocks = <&clockgen 4 1>;
456 clock-names = "ipg";
457 status = "disabled";
458 };
459
460 wdog0: watchdog@2ad0000 {
461 compatible = "fsl,imx21-wdt";
462 reg = <0x0 0x2ad0000 0x0 0x10000>;
463 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
464 clocks = <&clockgen 4 1>;
465 big-endian;
466 };
467
468 edma0: edma@2c00000 {
469 #dma-cells = <2>;
470 compatible = "fsl,vf610-edma";
471 reg = <0x0 0x2c00000 0x0 0x10000>,
472 <0x0 0x2c10000 0x0 0x10000>,
473 <0x0 0x2c20000 0x0 0x10000>;
474 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
475 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
476 interrupt-names = "edma-tx", "edma-err";
477 dma-channels = <32>;
478 big-endian;
479 clock-names = "dmamux0", "dmamux1";
480 clocks = <&clockgen 4 1>,
481 <&clockgen 4 1>;
482 };
483
484 usb0: usb@2f00000 {
485 compatible = "snps,dwc3";
486 reg = <0x0 0x2f00000 0x0 0x10000>;
487 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
488 dr_mode = "host";
489 snps,quirk-frame-length-adjustment = <0x20>;
490 };
491
492 usb1: usb@3000000 {
493 compatible = "snps,dwc3";
494 reg = <0x0 0x3000000 0x0 0x10000>;
495 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
496 dr_mode = "host";
497 snps,quirk-frame-length-adjustment = <0x20>;
498 };
499
500 usb2: usb@3100000 {
501 compatible = "snps,dwc3";
502 reg = <0x0 0x3100000 0x0 0x10000>;
503 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
504 dr_mode = "host";
505 snps,quirk-frame-length-adjustment = <0x20>;
506 };
507
508 sata: sata@3200000 {
509 compatible = "fsl,ls1046a-ahci";
510 reg = <0x0 0x3200000 0x0 0x10000>;
511 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
512 clocks = <&clockgen 4 1>;
513 };
514 };
515};
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-23 09:41:28 -0400