Merge tag 'v4.1-next-arm64' of https://github.com/mbgg/linux-mediatek into next/dt

Merge "ARM: mediatek: arm64 updates for v4.2" from Matthias Brugger:

- dts: mt8173: fix style convention for pinctrl node
- dts: mt8173: fix indentation for some nodes

* tag 'v4.1-next-arm64' of https://github.com/mbgg/linux-mediatek:
  arm64: dts: mt8173: fix some indentation
  arm64: dts: mt8173: Fixup pinctrl nodes

1 files changed, 22 insertions, 19 deletions

diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 924fdb6673ff..27237a1c1a87 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -91,13 +91,13 @@
                 compatible = "arm,armv8-timer";
                 interrupt-parent = <&gic>;
                 interrupts = <GIC_PPI 13
-                        (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                              (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
                              <GIC_PPI 14
-                        (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                              (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
                              <GIC_PPI 11
-                        (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                              (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
                              <GIC_PPI 10
-                        (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+                              (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
         };
 
         soc {
@@ -106,14 +106,13 @@
                 compatible = "simple-bus";
                 ranges;
 
-                syscfg_pctl_a: syscfg_pctl_a@10005000 {
-                        compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon";
-                        reg = <0 0x10005000 0 0x1000>;
-                };
-
-                pio: pinctrl@0x10005000 {
+                /*
+                 * Pinctrl access register at 0x10005000 through regmap.
+                 * Register 0x1000b000 is used by EINT.
+                 */
+                pio: pinctrl@10005000 {
                         compatible = "mediatek,mt8173-pinctrl";
-                        reg = <0 0x1000B000 0 0x1000>;
+                        reg = <0 0x1000b000 0 0x1000>;
                         mediatek,pctl-regmap = <&syscfg_pctl_a>;
                         pins-are-numbered;
                         gpio-controller;
@@ -121,13 +120,18 @@
                         interrupt-controller;
                         #interrupt-cells = <2>;
                         interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
-                                                <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
-                                                <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
+                                     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
+                };
+
+                syscfg_pctl_a: syscfg_pctl_a@10005000 {
+                        compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon";
+                        reg = <0 0x10005000 0 0x1000>;
                 };
 
                 sysirq: intpol-controller@10200620 {
                         compatible = "mediatek,mt8173-sysirq",
-                                        "mediatek,mt6577-sysirq";
+                                     "mediatek,mt6577-sysirq";
                         interrupt-controller;
                         #interrupt-cells = <3>;
                         interrupt-parent = <&gic>;
@@ -149,7 +153,7 @@
 
                 uart0: serial@11002000 {
                         compatible = "mediatek,mt8173-uart",
-                                        "mediatek,mt6577-uart";
+                                     "mediatek,mt6577-uart";
                         reg = <0 0x11002000 0 0x400>;
                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>;
                         clocks = <&uart_clk>;
@@ -158,7 +162,7 @@
 
                 uart1: serial@11003000 {
                         compatible = "mediatek,mt8173-uart",
-                                        "mediatek,mt6577-uart";
+                                     "mediatek,mt6577-uart";
                         reg = <0 0x11003000 0 0x400>;
                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
                         clocks = <&uart_clk>;
@@ -167,7 +171,7 @@
 
                 uart2: serial@11004000 {
                         compatible = "mediatek,mt8173-uart",
-                                        "mediatek,mt6577-uart";
+                                     "mediatek,mt6577-uart";
                         reg = <0 0x11004000 0 0x400>;
                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
                         clocks = <&uart_clk>;
@@ -176,13 +180,12 @@
 
                 uart3: serial@11005000 {
                         compatible = "mediatek,mt8173-uart",
-                                        "mediatek,mt6577-uart";
+                                     "mediatek,mt6577-uart";
                         reg = <0 0x11005000 0 0x400>;
                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
                         clocks = <&uart_clk>;
                         status = "disabled";
                 };
         };
-
 };