diff options
author | Christian König <christian.koenig@amd.com> | 2018-08-22 06:04:11 -0400 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2018-08-27 16:10:36 -0400 |
commit | 80dbea4720bb43b473219fad0cf3b426f2cd04cc (patch) | |
tree | 974bc95ee8d1528ae30240383e800e3307f19ffc | |
parent | f5d850331ea9bdf18e68ae298cff35c7b7233993 (diff) |
drm/amdgpu: implement soft_recovery for GFX9
Try to kill waves on the SQ.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index 44707f94b2c5..ab5cacea967b 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | |||
@@ -4421,6 +4421,18 @@ static void gfx_v9_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, | |||
4421 | ref, mask); | 4421 | ref, mask); |
4422 | } | 4422 | } |
4423 | 4423 | ||
4424 | static void gfx_v9_0_ring_soft_recovery(struct amdgpu_ring *ring, unsigned vmid) | ||
4425 | { | ||
4426 | struct amdgpu_device *adev = ring->adev; | ||
4427 | uint32_t value = 0; | ||
4428 | |||
4429 | value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); | ||
4430 | value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); | ||
4431 | value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); | ||
4432 | value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); | ||
4433 | WREG32(mmSQ_CMD, value); | ||
4434 | } | ||
4435 | |||
4424 | static void gfx_v9_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, | 4436 | static void gfx_v9_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, |
4425 | enum amdgpu_interrupt_state state) | 4437 | enum amdgpu_interrupt_state state) |
4426 | { | 4438 | { |
@@ -4743,6 +4755,7 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = { | |||
4743 | .emit_wreg = gfx_v9_0_ring_emit_wreg, | 4755 | .emit_wreg = gfx_v9_0_ring_emit_wreg, |
4744 | .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait, | 4756 | .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait, |
4745 | .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait, | 4757 | .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait, |
4758 | .soft_recovery = gfx_v9_0_ring_soft_recovery, | ||
4746 | }; | 4759 | }; |
4747 | 4760 | ||
4748 | static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = { | 4761 | static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = { |