arm64: dts: qcom: 8x16: UART1 add CTS_N, RTS_N pin configurations

Add devicetree bindings for UART1 CTS_N and RTS_N pins.

Signed-off-by: Ivan T. Ivanov <ivan.ivanov@linaro.org>
Signed-off-by: Andy Gross <agross@codeaurora.org>

1 files changed, 9 insertions, 4 deletions

diff --git a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi
index 49ec55a37614..d656e892fd52 100644
--- a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi
@@ -16,10 +16,13 @@
         blsp1_uart1_default: blsp1_uart1_default {
                 pinmux {
                         function = "blsp_uart1";
-                        pins = "gpio0", "gpio1";
+                        //      TX, RX, CTS_N, RTS_N
+                        pins = "gpio0", "gpio1",
+                               "gpio2", "gpio3";
                 };
                 pinconf {
-                        pins = "gpio0", "gpio1";
+                        pins = "gpio0", "gpio1",
+                               "gpio2", "gpio3";
                         drive-strength = <16>;
                         bias-disable;
                 };
@@ -28,10 +31,12 @@
         blsp1_uart1_sleep: blsp1_uart1_sleep {
                 pinmux {
                         function = "gpio";
-                        pins = "gpio0", "gpio1";
+                        pins = "gpio0", "gpio1",
+                               "gpio2", "gpio3";
                 };
                 pinconf {
-                        pins = "gpio0", "gpio1";
+                        pins = "gpio0", "gpio1",
+                               "gpio2", "gpio3";
                         drive-strength = <2>;
                         bias-pull-down;
                 };