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authorIdo Schimmel <idosch@mellanox.com>2015-10-15 11:43:28 -0400
committerDavid S. Miller <davem@davemloft.net>2015-10-16 02:27:56 -0400
commit801bd3defb2eac756e6570168d0f8187781ad8ad (patch)
tree14ba70e7aa706221a721d5d69e600866286a2931
parentf24af330159aa1afbc6670e5786856a2a99d112c (diff)
mlxsw: Add trap group for control packets
Previously, we trapped flooded and control packets using the same trap group. This can cause flooded packets to overflow the PCI bus and prevent control packets (e.g. STP, LACP) from getting to the CPU. Solve this by splitting the RX trap group to RX and control, which allows us to configure a policer on the first, thereby preventing it from overflowing the PCI bus. Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
-rw-r--r--drivers/net/ethernet/mellanox/mlxsw/reg.h26
-rw-r--r--drivers/net/ethernet/mellanox/mlxsw/switchx2.c5
2 files changed, 24 insertions, 7 deletions
diff --git a/drivers/net/ethernet/mellanox/mlxsw/reg.h b/drivers/net/ethernet/mellanox/mlxsw/reg.h
index fc6f520db575..7b245af10e42 100644
--- a/drivers/net/ethernet/mellanox/mlxsw/reg.h
+++ b/drivers/net/ethernet/mellanox/mlxsw/reg.h
@@ -1029,8 +1029,11 @@ MLXSW_ITEM32(reg, htgt, swid, 0x00, 24, 8);
1029 */ 1029 */
1030MLXSW_ITEM32(reg, htgt, type, 0x00, 8, 4); 1030MLXSW_ITEM32(reg, htgt, type, 0x00, 8, 4);
1031 1031
1032#define MLXSW_REG_HTGT_TRAP_GROUP_EMAD 0x0 1032enum mlxsw_reg_htgt_trap_group {
1033#define MLXSW_REG_HTGT_TRAP_GROUP_RX 0x1 1033 MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
1034 MLXSW_REG_HTGT_TRAP_GROUP_RX,
1035 MLXSW_REG_HTGT_TRAP_GROUP_CTRL,
1036};
1034 1037
1035/* reg_htgt_trap_group 1038/* reg_htgt_trap_group
1036 * Trap group number. User defined number specifying which trap groups 1039 * Trap group number. User defined number specifying which trap groups
@@ -1097,6 +1100,7 @@ MLXSW_ITEM32(reg, htgt, local_path_cpu_tclass, 0x10, 16, 6);
1097 1100
1098#define MLXSW_REG_HTGT_LOCAL_PATH_RDQ_EMAD 0x15 1101#define MLXSW_REG_HTGT_LOCAL_PATH_RDQ_EMAD 0x15
1099#define MLXSW_REG_HTGT_LOCAL_PATH_RDQ_RX 0x14 1102#define MLXSW_REG_HTGT_LOCAL_PATH_RDQ_RX 0x14
1103#define MLXSW_REG_HTGT_LOCAL_PATH_RDQ_CTRL 0x13
1100 1104
1101/* reg_htgt_local_path_rdq 1105/* reg_htgt_local_path_rdq
1102 * Receive descriptor queue (RDQ) to use for the trap group. 1106 * Receive descriptor queue (RDQ) to use for the trap group.
@@ -1104,21 +1108,29 @@ MLXSW_ITEM32(reg, htgt, local_path_cpu_tclass, 0x10, 16, 6);
1104 */ 1108 */
1105MLXSW_ITEM32(reg, htgt, local_path_rdq, 0x10, 0, 6); 1109MLXSW_ITEM32(reg, htgt, local_path_rdq, 0x10, 0, 6);
1106 1110
1107static inline void mlxsw_reg_htgt_pack(char *payload, u8 trap_group) 1111static inline void mlxsw_reg_htgt_pack(char *payload,
1112 enum mlxsw_reg_htgt_trap_group group)
1108{ 1113{
1109 u8 swid, rdq; 1114 u8 swid, rdq;
1110 1115
1111 MLXSW_REG_ZERO(htgt, payload); 1116 MLXSW_REG_ZERO(htgt, payload);
1112 if (MLXSW_REG_HTGT_TRAP_GROUP_EMAD == trap_group) { 1117 switch (group) {
1118 case MLXSW_REG_HTGT_TRAP_GROUP_EMAD:
1113 swid = MLXSW_PORT_SWID_ALL_SWIDS; 1119 swid = MLXSW_PORT_SWID_ALL_SWIDS;
1114 rdq = MLXSW_REG_HTGT_LOCAL_PATH_RDQ_EMAD; 1120 rdq = MLXSW_REG_HTGT_LOCAL_PATH_RDQ_EMAD;
1115 } else { 1121 break;
1122 case MLXSW_REG_HTGT_TRAP_GROUP_RX:
1116 swid = 0; 1123 swid = 0;
1117 rdq = MLXSW_REG_HTGT_LOCAL_PATH_RDQ_RX; 1124 rdq = MLXSW_REG_HTGT_LOCAL_PATH_RDQ_RX;
1125 break;
1126 case MLXSW_REG_HTGT_TRAP_GROUP_CTRL:
1127 swid = 0;
1128 rdq = MLXSW_REG_HTGT_LOCAL_PATH_RDQ_CTRL;
1129 break;
1118 } 1130 }
1119 mlxsw_reg_htgt_swid_set(payload, swid); 1131 mlxsw_reg_htgt_swid_set(payload, swid);
1120 mlxsw_reg_htgt_type_set(payload, MLXSW_REG_HTGT_PATH_TYPE_LOCAL); 1132 mlxsw_reg_htgt_type_set(payload, MLXSW_REG_HTGT_PATH_TYPE_LOCAL);
1121 mlxsw_reg_htgt_trap_group_set(payload, trap_group); 1133 mlxsw_reg_htgt_trap_group_set(payload, group);
1122 mlxsw_reg_htgt_pide_set(payload, MLXSW_REG_HTGT_POLICER_DISABLE); 1134 mlxsw_reg_htgt_pide_set(payload, MLXSW_REG_HTGT_POLICER_DISABLE);
1123 mlxsw_reg_htgt_pid_set(payload, 0); 1135 mlxsw_reg_htgt_pid_set(payload, 0);
1124 mlxsw_reg_htgt_mirror_action_set(payload, MLXSW_REG_HTGT_TRAP_TO_CPU); 1136 mlxsw_reg_htgt_mirror_action_set(payload, MLXSW_REG_HTGT_TRAP_TO_CPU);
@@ -1211,7 +1223,7 @@ MLXSW_ITEM32(reg, hpkt, ctrl, 0x04, 16, 2);
1211 1223
1212static inline void mlxsw_reg_hpkt_pack(char *payload, u8 action, u16 trap_id) 1224static inline void mlxsw_reg_hpkt_pack(char *payload, u8 action, u16 trap_id)
1213{ 1225{
1214 u8 trap_group; 1226 enum mlxsw_reg_htgt_trap_group trap_group;
1215 1227
1216 MLXSW_REG_ZERO(hpkt, payload); 1228 MLXSW_REG_ZERO(hpkt, payload);
1217 mlxsw_reg_hpkt_ack_set(payload, MLXSW_REG_HPKT_ACK_NOT_REQUIRED); 1229 mlxsw_reg_hpkt_ack_set(payload, MLXSW_REG_HPKT_ACK_NOT_REQUIRED);
diff --git a/drivers/net/ethernet/mellanox/mlxsw/switchx2.c b/drivers/net/ethernet/mellanox/mlxsw/switchx2.c
index 85dcda44d0b0..4f72e0a423d9 100644
--- a/drivers/net/ethernet/mellanox/mlxsw/switchx2.c
+++ b/drivers/net/ethernet/mellanox/mlxsw/switchx2.c
@@ -1313,6 +1313,11 @@ static int mlxsw_sx_traps_init(struct mlxsw_sx *mlxsw_sx)
1313 if (err) 1313 if (err)
1314 return err; 1314 return err;
1315 1315
1316 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_CTRL);
1317 err = mlxsw_reg_write(mlxsw_sx->core, MLXSW_REG(htgt), htgt_pl);
1318 if (err)
1319 return err;
1320
1316 for (i = 0; i < ARRAY_SIZE(mlxsw_sx_rx_listener); i++) { 1321 for (i = 0; i < ARRAY_SIZE(mlxsw_sx_rx_listener); i++) {
1317 err = mlxsw_core_rx_listener_register(mlxsw_sx->core, 1322 err = mlxsw_core_rx_listener_register(mlxsw_sx->core,
1318 &mlxsw_sx_rx_listener[i], 1323 &mlxsw_sx_rx_listener[i],