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authorDan Carpenter <dan.carpenter@oracle.com>2015-12-04 17:21:08 -0500
committerBjorn Helgaas <bhelgaas@google.com>2015-12-04 17:21:08 -0500
commit7f52f31443ae9b2e6a71ec54cfc5a2c89006ea27 (patch)
treee00588408eae2d9749a0d1cf374170f60f949ef8
parent3845d2953aacf00ad069806ba8d1495675069f23 (diff)
PCI: altera: Fix loop in tlp_read_packet()
TLP_LOOP is 500 and the "loop" variable was a u8 so "loop < TLP_LOOP" is always true. We only need this condition to work if there is a problem so it would have been easy to miss this in testing. Make it a normal for loop with "int i" instead of over thinking things and making it complicated. Fixes: 6bb4dd154ae8 ("PCI: altera: Add Altera PCIe host controller driver") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Ley Foon Tan <lftan@altera.com>
-rw-r--r--drivers/pci/host/pcie-altera.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/pci/host/pcie-altera.c b/drivers/pci/host/pcie-altera.c
index e5dda38bdde5..f0820d3fadf6 100644
--- a/drivers/pci/host/pcie-altera.c
+++ b/drivers/pci/host/pcie-altera.c
@@ -166,7 +166,7 @@ static bool altera_pcie_valid_config(struct altera_pcie *pcie,
166 166
167static int tlp_read_packet(struct altera_pcie *pcie, u32 *value) 167static int tlp_read_packet(struct altera_pcie *pcie, u32 *value)
168{ 168{
169 u8 loop; 169 int i;
170 bool sop = 0; 170 bool sop = 0;
171 u32 ctrl; 171 u32 ctrl;
172 u32 reg0, reg1; 172 u32 reg0, reg1;
@@ -175,7 +175,7 @@ static int tlp_read_packet(struct altera_pcie *pcie, u32 *value)
175 * Minimum 2 loops to read TLP headers and 1 loop to read data 175 * Minimum 2 loops to read TLP headers and 1 loop to read data
176 * payload. 176 * payload.
177 */ 177 */
178 for (loop = 0; loop < TLP_LOOP; loop++) { 178 for (i = 0; i < TLP_LOOP; i++) {
179 ctrl = cra_readl(pcie, RP_RXCPL_STATUS); 179 ctrl = cra_readl(pcie, RP_RXCPL_STATUS);
180 if ((ctrl & RP_RXCPL_SOP) || (ctrl & RP_RXCPL_EOP) || sop) { 180 if ((ctrl & RP_RXCPL_SOP) || (ctrl & RP_RXCPL_EOP) || sop) {
181 reg0 = cra_readl(pcie, RP_RXCPL_REG0); 181 reg0 = cra_readl(pcie, RP_RXCPL_REG0);