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authorArnd Bergmann <arnd@arndb.de>2015-05-29 08:54:13 -0400
committerArnd Bergmann <arnd@arndb.de>2015-05-29 08:54:13 -0400
commit7f05a7612e299c0aef8156e70a546ba7e5d5f947 (patch)
treefcc06a9c6f22877929e706f41b0b1ee2aa6e5d04
parent0fcbffc4bdc262bd9d5802dc61fb0dcf54102f4e (diff)
parent2a910d139e405f1038c0f2ea7f9ac45acc84cce9 (diff)
Merge tag 'v4.1-next-soc' of https://github.com/mbgg/linux-mediatek into next/drivers
Merge "ARM: mediatek: soc updates for v4.2" from Matthias Brugger: - pmic wrapper: fix clock handling - pmic wrapper: fix state machine - pmic wrapper: fix compile dependency * tag 'v4.1-next-soc' of https://github.com/mbgg/linux-mediatek: soc: mediatek: Add compile dependency to pmic-wrapper soc: mediatek: PMIC wrap: Fix register state machine handling soc: mediatek: PMIC wrap: Fix clock rate handling
-rw-r--r--drivers/soc/mediatek/Kconfig1
-rw-r--r--drivers/soc/mediatek/mtk-pmic-wrap.c54
2 files changed, 10 insertions, 45 deletions
diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig
index bcdb22d5e215..3c1850332a90 100644
--- a/drivers/soc/mediatek/Kconfig
+++ b/drivers/soc/mediatek/Kconfig
@@ -4,6 +4,7 @@
4config MTK_PMIC_WRAP 4config MTK_PMIC_WRAP
5 tristate "MediaTek PMIC Wrapper Support" 5 tristate "MediaTek PMIC Wrapper Support"
6 depends on ARCH_MEDIATEK 6 depends on ARCH_MEDIATEK
7 depends on RESET_CONTROLLER
7 select REGMAP 8 select REGMAP
8 help 9 help
9 Say yes here to add support for MediaTek PMIC Wrapper found 10 Say yes here to add support for MediaTek PMIC Wrapper found
diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c
index db5be1eec54c..f432291feee9 100644
--- a/drivers/soc/mediatek/mtk-pmic-wrap.c
+++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
@@ -443,11 +443,6 @@ static int pwrap_wait_for_state(struct pmic_wrapper *wrp,
443static int pwrap_write(struct pmic_wrapper *wrp, u32 adr, u32 wdata) 443static int pwrap_write(struct pmic_wrapper *wrp, u32 adr, u32 wdata)
444{ 444{
445 int ret; 445 int ret;
446 u32 val;
447
448 val = pwrap_readl(wrp, PWRAP_WACS2_RDATA);
449 if (PWRAP_GET_WACS_FSM(val) == PWRAP_WACS_FSM_WFVLDCLR)
450 pwrap_writel(wrp, 1, PWRAP_WACS2_VLDCLR);
451 446
452 ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle); 447 ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle);
453 if (ret) 448 if (ret)
@@ -462,11 +457,6 @@ static int pwrap_write(struct pmic_wrapper *wrp, u32 adr, u32 wdata)
462static int pwrap_read(struct pmic_wrapper *wrp, u32 adr, u32 *rdata) 457static int pwrap_read(struct pmic_wrapper *wrp, u32 adr, u32 *rdata)
463{ 458{
464 int ret; 459 int ret;
465 u32 val;
466
467 val = pwrap_readl(wrp, PWRAP_WACS2_RDATA);
468 if (PWRAP_GET_WACS_FSM(val) == PWRAP_WACS_FSM_WFVLDCLR)
469 pwrap_writel(wrp, 1, PWRAP_WACS2_VLDCLR);
470 460
471 ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle); 461 ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle);
472 if (ret) 462 if (ret)
@@ -480,6 +470,8 @@ static int pwrap_read(struct pmic_wrapper *wrp, u32 adr, u32 *rdata)
480 470
481 *rdata = PWRAP_GET_WACS_RDATA(pwrap_readl(wrp, PWRAP_WACS2_RDATA)); 471 *rdata = PWRAP_GET_WACS_RDATA(pwrap_readl(wrp, PWRAP_WACS2_RDATA));
482 472
473 pwrap_writel(wrp, 1, PWRAP_WACS2_VLDCLR);
474
483 return 0; 475 return 0;
484} 476}
485 477
@@ -563,45 +555,17 @@ static int pwrap_init_sidly(struct pmic_wrapper *wrp)
563 555
564static int pwrap_init_reg_clock(struct pmic_wrapper *wrp) 556static int pwrap_init_reg_clock(struct pmic_wrapper *wrp)
565{ 557{
566 unsigned long rate_spi; 558 if (pwrap_is_mt8135(wrp)) {
567 int ck_mhz; 559 pwrap_writel(wrp, 0x4, PWRAP_CSHEXT);
568
569 rate_spi = clk_get_rate(wrp->clk_spi);
570
571 if (rate_spi > 26000000)
572 ck_mhz = 26;
573 else if (rate_spi > 18000000)
574 ck_mhz = 18;
575 else
576 ck_mhz = 0;
577
578 switch (ck_mhz) {
579 case 18:
580 if (pwrap_is_mt8135(wrp))
581 pwrap_writel(wrp, 0xc, PWRAP_CSHEXT);
582 pwrap_writel(wrp, 0x4, PWRAP_CSHEXT_WRITE);
583 pwrap_writel(wrp, 0xc, PWRAP_CSHEXT_READ);
584 pwrap_writel(wrp, 0x0, PWRAP_CSLEXT_START);
585 pwrap_writel(wrp, 0x0, PWRAP_CSLEXT_END);
586 break;
587 case 26:
588 if (pwrap_is_mt8135(wrp))
589 pwrap_writel(wrp, 0x4, PWRAP_CSHEXT);
590 pwrap_writel(wrp, 0x0, PWRAP_CSHEXT_WRITE); 560 pwrap_writel(wrp, 0x0, PWRAP_CSHEXT_WRITE);
591 pwrap_writel(wrp, 0x4, PWRAP_CSHEXT_READ); 561 pwrap_writel(wrp, 0x4, PWRAP_CSHEXT_READ);
592 pwrap_writel(wrp, 0x0, PWRAP_CSLEXT_START); 562 pwrap_writel(wrp, 0x0, PWRAP_CSLEXT_START);
593 pwrap_writel(wrp, 0x0, PWRAP_CSLEXT_END); 563 pwrap_writel(wrp, 0x0, PWRAP_CSLEXT_END);
594 break; 564 } else {
595 case 0: 565 pwrap_writel(wrp, 0x0, PWRAP_CSHEXT_WRITE);
596 if (pwrap_is_mt8135(wrp)) 566 pwrap_writel(wrp, 0x4, PWRAP_CSHEXT_READ);
597 pwrap_writel(wrp, 0xf, PWRAP_CSHEXT); 567 pwrap_writel(wrp, 0x2, PWRAP_CSLEXT_START);
598 pwrap_writel(wrp, 0xf, PWRAP_CSHEXT_WRITE); 568 pwrap_writel(wrp, 0x2, PWRAP_CSLEXT_END);
599 pwrap_writel(wrp, 0xf, PWRAP_CSHEXT_READ);
600 pwrap_writel(wrp, 0xf, PWRAP_CSLEXT_START);
601 pwrap_writel(wrp, 0xf, PWRAP_CSLEXT_END);
602 break;
603 default:
604 return -EINVAL;
605 } 569 }
606 570
607 return 0; 571 return 0;