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authorAllen Pais <allen.pais@oracle.com>2017-07-24 02:14:18 -0400
committerDavid S. Miller <davem@davemloft.net>2017-08-04 14:08:53 -0400
commit7d484acb2f90643de7e242fd47e48c3ebb22df3a (patch)
tree81bdd10b755d48275984c845d3ad9588c0c2b288
parent9e48cd4a77d5170433a2e611eeda7accdf96604d (diff)
sparc64: recognize and support sparc M8 cpu type
Recognize SPARC-M8 cpu type, hardware caps and cpu distribution map. Signed-off-by: Allen Pais <allen.pais@oracle.com> Signed-off-by: David Aldridge <david.j.aldridge@oracle.com> Signed-off-by: David S. Miller <davem@davemloft.net>
-rw-r--r--arch/sparc/include/asm/spitfire.h2
-rw-r--r--arch/sparc/kernel/cpu.c6
-rw-r--r--arch/sparc/kernel/cpumap.c1
-rw-r--r--arch/sparc/kernel/head_64.S6
-rw-r--r--arch/sparc/kernel/setup_64.c15
-rw-r--r--arch/sparc/mm/init_64.c2
6 files changed, 30 insertions, 2 deletions
diff --git a/arch/sparc/include/asm/spitfire.h b/arch/sparc/include/asm/spitfire.h
index 9cc2afe10ef0..1b1286d05069 100644
--- a/arch/sparc/include/asm/spitfire.h
+++ b/arch/sparc/include/asm/spitfire.h
@@ -47,6 +47,7 @@
47#define SUN4V_CHIP_NIAGARA5 0x05 47#define SUN4V_CHIP_NIAGARA5 0x05
48#define SUN4V_CHIP_SPARC_M6 0x06 48#define SUN4V_CHIP_SPARC_M6 0x06
49#define SUN4V_CHIP_SPARC_M7 0x07 49#define SUN4V_CHIP_SPARC_M7 0x07
50#define SUN4V_CHIP_SPARC_M8 0x08
50#define SUN4V_CHIP_SPARC64X 0x8a 51#define SUN4V_CHIP_SPARC64X 0x8a
51#define SUN4V_CHIP_SPARC_SN 0x8b 52#define SUN4V_CHIP_SPARC_SN 0x8b
52#define SUN4V_CHIP_UNKNOWN 0xff 53#define SUN4V_CHIP_UNKNOWN 0xff
@@ -63,6 +64,7 @@
63#define CPU_ID_NIAGARA5 ('5') 64#define CPU_ID_NIAGARA5 ('5')
64#define CPU_ID_M6 ('6') 65#define CPU_ID_M6 ('6')
65#define CPU_ID_M7 ('7') 66#define CPU_ID_M7 ('7')
67#define CPU_ID_M8 ('8')
66#define CPU_ID_SONOMA1 ('N') 68#define CPU_ID_SONOMA1 ('N')
67 69
68#ifndef __ASSEMBLY__ 70#ifndef __ASSEMBLY__
diff --git a/arch/sparc/kernel/cpu.c b/arch/sparc/kernel/cpu.c
index 493e023a468a..ef4f18f7a674 100644
--- a/arch/sparc/kernel/cpu.c
+++ b/arch/sparc/kernel/cpu.c
@@ -506,6 +506,12 @@ static void __init sun4v_cpu_probe(void)
506 sparc_pmu_type = "sparc-m7"; 506 sparc_pmu_type = "sparc-m7";
507 break; 507 break;
508 508
509 case SUN4V_CHIP_SPARC_M8:
510 sparc_cpu_type = "SPARC-M8";
511 sparc_fpu_type = "SPARC-M8 integrated FPU";
512 sparc_pmu_type = "sparc-m8";
513 break;
514
509 case SUN4V_CHIP_SPARC_SN: 515 case SUN4V_CHIP_SPARC_SN:
510 sparc_cpu_type = "SPARC-SN"; 516 sparc_cpu_type = "SPARC-SN";
511 sparc_fpu_type = "SPARC-SN integrated FPU"; 517 sparc_fpu_type = "SPARC-SN integrated FPU";
diff --git a/arch/sparc/kernel/cpumap.c b/arch/sparc/kernel/cpumap.c
index 45c820e1cba5..90d550bbfeef 100644
--- a/arch/sparc/kernel/cpumap.c
+++ b/arch/sparc/kernel/cpumap.c
@@ -328,6 +328,7 @@ static int iterate_cpu(struct cpuinfo_tree *t, unsigned int root_index)
328 case SUN4V_CHIP_NIAGARA5: 328 case SUN4V_CHIP_NIAGARA5:
329 case SUN4V_CHIP_SPARC_M6: 329 case SUN4V_CHIP_SPARC_M6:
330 case SUN4V_CHIP_SPARC_M7: 330 case SUN4V_CHIP_SPARC_M7:
331 case SUN4V_CHIP_SPARC_M8:
331 case SUN4V_CHIP_SPARC_SN: 332 case SUN4V_CHIP_SPARC_SN:
332 case SUN4V_CHIP_SPARC64X: 333 case SUN4V_CHIP_SPARC64X:
333 rover_inc_table = niagara_iterate_method; 334 rover_inc_table = niagara_iterate_method;
diff --git a/arch/sparc/kernel/head_64.S b/arch/sparc/kernel/head_64.S
index ddb5e24adf49..78e0211753d2 100644
--- a/arch/sparc/kernel/head_64.S
+++ b/arch/sparc/kernel/head_64.S
@@ -439,6 +439,9 @@ EXPORT_SYMBOL(sun4v_chip_type)
439 cmp %g2, CPU_ID_M7 439 cmp %g2, CPU_ID_M7
440 be,pt %xcc, 5f 440 be,pt %xcc, 5f
441 mov SUN4V_CHIP_SPARC_M7, %g4 441 mov SUN4V_CHIP_SPARC_M7, %g4
442 cmp %g2, CPU_ID_M8
443 be,pt %xcc, 5f
444 mov SUN4V_CHIP_SPARC_M8, %g4
442 cmp %g2, CPU_ID_SONOMA1 445 cmp %g2, CPU_ID_SONOMA1
443 be,pt %xcc, 5f 446 be,pt %xcc, 5f
444 mov SUN4V_CHIP_SPARC_SN, %g4 447 mov SUN4V_CHIP_SPARC_SN, %g4
@@ -602,6 +605,9 @@ niagara_tlb_fixup:
602 cmp %g1, SUN4V_CHIP_SPARC_M7 605 cmp %g1, SUN4V_CHIP_SPARC_M7
603 be,pt %xcc, niagara4_patch 606 be,pt %xcc, niagara4_patch
604 nop 607 nop
608 cmp %g1, SUN4V_CHIP_SPARC_M8
609 be,pt %xcc, niagara4_patch
610 nop
605 cmp %g1, SUN4V_CHIP_SPARC_SN 611 cmp %g1, SUN4V_CHIP_SPARC_SN
606 be,pt %xcc, niagara4_patch 612 be,pt %xcc, niagara4_patch
607 nop 613 nop
diff --git a/arch/sparc/kernel/setup_64.c b/arch/sparc/kernel/setup_64.c
index 4d9c3e13c150..150ee7d4b059 100644
--- a/arch/sparc/kernel/setup_64.c
+++ b/arch/sparc/kernel/setup_64.c
@@ -288,10 +288,17 @@ static void __init sun4v_patch(void)
288 288
289 sun4v_patch_2insn_range(&__sun4v_2insn_patch, 289 sun4v_patch_2insn_range(&__sun4v_2insn_patch,
290 &__sun4v_2insn_patch_end); 290 &__sun4v_2insn_patch_end);
291 if (sun4v_chip_type == SUN4V_CHIP_SPARC_M7 || 291
292 sun4v_chip_type == SUN4V_CHIP_SPARC_SN) 292 switch (sun4v_chip_type) {
293 case SUN4V_CHIP_SPARC_M7:
294 case SUN4V_CHIP_SPARC_M8:
295 case SUN4V_CHIP_SPARC_SN:
293 sun_m7_patch_2insn_range(&__sun_m7_2insn_patch, 296 sun_m7_patch_2insn_range(&__sun_m7_2insn_patch,
294 &__sun_m7_2insn_patch_end); 297 &__sun_m7_2insn_patch_end);
298 break;
299 default:
300 break;
301 }
295 302
296 sun4v_hvapi_init(); 303 sun4v_hvapi_init();
297} 304}
@@ -529,6 +536,7 @@ static void __init init_sparc64_elf_hwcap(void)
529 sun4v_chip_type == SUN4V_CHIP_NIAGARA5 || 536 sun4v_chip_type == SUN4V_CHIP_NIAGARA5 ||
530 sun4v_chip_type == SUN4V_CHIP_SPARC_M6 || 537 sun4v_chip_type == SUN4V_CHIP_SPARC_M6 ||
531 sun4v_chip_type == SUN4V_CHIP_SPARC_M7 || 538 sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||
539 sun4v_chip_type == SUN4V_CHIP_SPARC_M8 ||
532 sun4v_chip_type == SUN4V_CHIP_SPARC_SN || 540 sun4v_chip_type == SUN4V_CHIP_SPARC_SN ||
533 sun4v_chip_type == SUN4V_CHIP_SPARC64X) 541 sun4v_chip_type == SUN4V_CHIP_SPARC64X)
534 cap |= HWCAP_SPARC_BLKINIT; 542 cap |= HWCAP_SPARC_BLKINIT;
@@ -538,6 +546,7 @@ static void __init init_sparc64_elf_hwcap(void)
538 sun4v_chip_type == SUN4V_CHIP_NIAGARA5 || 546 sun4v_chip_type == SUN4V_CHIP_NIAGARA5 ||
539 sun4v_chip_type == SUN4V_CHIP_SPARC_M6 || 547 sun4v_chip_type == SUN4V_CHIP_SPARC_M6 ||
540 sun4v_chip_type == SUN4V_CHIP_SPARC_M7 || 548 sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||
549 sun4v_chip_type == SUN4V_CHIP_SPARC_M8 ||
541 sun4v_chip_type == SUN4V_CHIP_SPARC_SN || 550 sun4v_chip_type == SUN4V_CHIP_SPARC_SN ||
542 sun4v_chip_type == SUN4V_CHIP_SPARC64X) 551 sun4v_chip_type == SUN4V_CHIP_SPARC64X)
543 cap |= HWCAP_SPARC_N2; 552 cap |= HWCAP_SPARC_N2;
@@ -568,6 +577,7 @@ static void __init init_sparc64_elf_hwcap(void)
568 sun4v_chip_type == SUN4V_CHIP_NIAGARA5 || 577 sun4v_chip_type == SUN4V_CHIP_NIAGARA5 ||
569 sun4v_chip_type == SUN4V_CHIP_SPARC_M6 || 578 sun4v_chip_type == SUN4V_CHIP_SPARC_M6 ||
570 sun4v_chip_type == SUN4V_CHIP_SPARC_M7 || 579 sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||
580 sun4v_chip_type == SUN4V_CHIP_SPARC_M8 ||
571 sun4v_chip_type == SUN4V_CHIP_SPARC_SN || 581 sun4v_chip_type == SUN4V_CHIP_SPARC_SN ||
572 sun4v_chip_type == SUN4V_CHIP_SPARC64X) 582 sun4v_chip_type == SUN4V_CHIP_SPARC64X)
573 cap |= (AV_SPARC_VIS | AV_SPARC_VIS2 | 583 cap |= (AV_SPARC_VIS | AV_SPARC_VIS2 |
@@ -578,6 +588,7 @@ static void __init init_sparc64_elf_hwcap(void)
578 sun4v_chip_type == SUN4V_CHIP_NIAGARA5 || 588 sun4v_chip_type == SUN4V_CHIP_NIAGARA5 ||
579 sun4v_chip_type == SUN4V_CHIP_SPARC_M6 || 589 sun4v_chip_type == SUN4V_CHIP_SPARC_M6 ||
580 sun4v_chip_type == SUN4V_CHIP_SPARC_M7 || 590 sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||
591 sun4v_chip_type == SUN4V_CHIP_SPARC_M8 ||
581 sun4v_chip_type == SUN4V_CHIP_SPARC_SN || 592 sun4v_chip_type == SUN4V_CHIP_SPARC_SN ||
582 sun4v_chip_type == SUN4V_CHIP_SPARC64X) 593 sun4v_chip_type == SUN4V_CHIP_SPARC64X)
583 cap |= (AV_SPARC_VIS3 | AV_SPARC_HPC | 594 cap |= (AV_SPARC_VIS3 | AV_SPARC_HPC |
diff --git a/arch/sparc/mm/init_64.c b/arch/sparc/mm/init_64.c
index fed73f14aa49..c24f4bfc3b84 100644
--- a/arch/sparc/mm/init_64.c
+++ b/arch/sparc/mm/init_64.c
@@ -2161,6 +2161,7 @@ static void __init sun4v_linear_pte_xor_finalize(void)
2161 */ 2161 */
2162 switch (sun4v_chip_type) { 2162 switch (sun4v_chip_type) {
2163 case SUN4V_CHIP_SPARC_M7: 2163 case SUN4V_CHIP_SPARC_M7:
2164 case SUN4V_CHIP_SPARC_M8:
2164 case SUN4V_CHIP_SPARC_SN: 2165 case SUN4V_CHIP_SPARC_SN:
2165 pagecv_flag = 0x00; 2166 pagecv_flag = 0x00;
2166 break; 2167 break;
@@ -2313,6 +2314,7 @@ void __init paging_init(void)
2313 */ 2314 */
2314 switch (sun4v_chip_type) { 2315 switch (sun4v_chip_type) {
2315 case SUN4V_CHIP_SPARC_M7: 2316 case SUN4V_CHIP_SPARC_M7:
2317 case SUN4V_CHIP_SPARC_M8:
2316 case SUN4V_CHIP_SPARC_SN: 2318 case SUN4V_CHIP_SPARC_SN:
2317 page_cache4v_flag = _PAGE_CP_4V; 2319 page_cache4v_flag = _PAGE_CP_4V;
2318 break; 2320 break;