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authorDavid S. Miller <davem@davemloft.net>2019-04-27 17:11:49 -0400
committerDavid S. Miller <davem@davemloft.net>2019-04-27 17:11:49 -0400
commit7cb523d4fec7f8aed894e4080ff4bfb4383d9132 (patch)
tree100379af99b8022d686f4be0d37d4830968b2a30
parent84ee91640fc4b1f4cc1039d5a6b55dff032786e9 (diff)
parentc24eef283a23b85cbd755265539dc4dbe3fee949 (diff)
Merge branch 'net-ethernet-ti-clean-up-and-optimizations'
Grygorii Strashko says: ==================== net: ethernet: ti: clean up and optimizations This is a preparation series for introducing new switchbase TI CPSW driver which was originally introduced [1][2] by Ilias Apalodimas <ilias.apalodimas@linaro.org> and also discussed in private mails and at Netdev x13 confernce. Following discussions and suggestions (mostly by Andrew and Ivan) we going to introduce the new driver which is operating in dual-emac mode by default, thus working as 2 individual network interfaces. When both interfaces joined the bridge - CPSW driver will enter a switch mode and discard dual_mac configuration. The CPSW will be switched back to dual_mac mode if any port leaves the bridge. All configuration is going to be implemented via switchdev API. Hence overall change is already very big I'm sending prerequisite patches which are mostly minor fixes/clean ups and code refactoring to separate common parts to be reused by both drivers. Probably the most serious change from functional point of view is Patch 11. These patches were NFS boot tetested on TI AM335x/AM437x/AM5xx boards. These patches can be found at: git@git.ti.com:~gragst/ti-linux-kernel/gragsts-ti-linux-kernel.git branch: lkml-5.1-cpsw-clean-up-v2 changes in v2: - added new patch 16 to get rid of force type conversation - other chages metioned in patches ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat
-rw-r--r--drivers/net/ethernet/ti/Kconfig19
-rw-r--r--drivers/net/ethernet/ti/Makefile9
-rw-r--r--drivers/net/ethernet/ti/cpmac.c14
-rw-r--r--drivers/net/ethernet/ti/cpsw-common.c12
-rw-r--r--drivers/net/ethernet/ti/cpsw-phy-sel.c9
-rw-r--r--drivers/net/ethernet/ti/cpsw.c1526
-rw-r--r--drivers/net/ethernet/ti/cpsw.h9
-rw-r--r--drivers/net/ethernet/ti/cpsw_ale.c55
-rw-r--r--drivers/net/ethernet/ti/cpsw_ale.h12
-rw-r--r--drivers/net/ethernet/ti/cpsw_ethtool.c719
-rw-r--r--drivers/net/ethernet/ti/cpsw_priv.c132
-rw-r--r--drivers/net/ethernet/ti/cpsw_priv.h429
-rw-r--r--drivers/net/ethernet/ti/cpsw_sl.c328
-rw-r--r--drivers/net/ethernet/ti/cpsw_sl.h73
-rw-r--r--drivers/net/ethernet/ti/cpts.c14
-rw-r--r--drivers/net/ethernet/ti/cpts.h14
-rw-r--r--drivers/net/ethernet/ti/davinci_cpdma.c37
-rw-r--r--drivers/net/ethernet/ti/davinci_cpdma.h13
-rw-r--r--drivers/net/ethernet/ti/davinci_emac.c16
-rw-r--r--drivers/net/ethernet/ti/davinci_mdio.c19
-rw-r--r--drivers/net/ethernet/ti/netcp.h10
-rw-r--r--drivers/net/ethernet/ti/netcp_core.c10
-rw-r--r--drivers/net/ethernet/ti/netcp_ethss.c10
-rw-r--r--drivers/net/ethernet/ti/netcp_sgmii.c9
-rw-r--r--drivers/net/ethernet/ti/netcp_xgbepcsr.c9
25 files changed, 1868 insertions, 1639 deletions
diff --git a/drivers/net/ethernet/ti/Kconfig b/drivers/net/ethernet/ti/Kconfig
index 8b21b40a9fe5..afbdc9744230 100644
--- a/drivers/net/ethernet/ti/Kconfig
+++ b/drivers/net/ethernet/ti/Kconfig
@@ -20,7 +20,6 @@ config TI_DAVINCI_EMAC
20 tristate "TI DaVinci EMAC Support" 20 tristate "TI DaVinci EMAC Support"
21 depends on ARM && ( ARCH_DAVINCI || ARCH_OMAP3 ) || COMPILE_TEST 21 depends on ARM && ( ARCH_DAVINCI || ARCH_OMAP3 ) || COMPILE_TEST
22 select TI_DAVINCI_MDIO 22 select TI_DAVINCI_MDIO
23 select TI_DAVINCI_CPDMA
24 select PHYLIB 23 select PHYLIB
25 ---help--- 24 ---help---
26 This driver supports TI's DaVinci Ethernet . 25 This driver supports TI's DaVinci Ethernet .
@@ -38,16 +37,6 @@ config TI_DAVINCI_MDIO
38 To compile this driver as a module, choose M here: the module 37 To compile this driver as a module, choose M here: the module
39 will be called davinci_mdio. This is recommended. 38 will be called davinci_mdio. This is recommended.
40 39
41config TI_DAVINCI_CPDMA
42 tristate "TI DaVinci CPDMA Support"
43 depends on ARCH_DAVINCI || ARCH_OMAP2PLUS || COMPILE_TEST
44 select GENERIC_ALLOCATOR
45 ---help---
46 This driver supports TI's DaVinci CPDMA dma engine.
47
48 To compile this driver as a module, choose M here: the module
49 will be called davinci_cpdma. This is recommended.
50
51config TI_CPSW_PHY_SEL 40config TI_CPSW_PHY_SEL
52 bool "TI CPSW Phy mode Selection (DEPRECATED)" 41 bool "TI CPSW Phy mode Selection (DEPRECATED)"
53 default n 42 default n
@@ -55,17 +44,10 @@ config TI_CPSW_PHY_SEL
55 This driver supports configuring of the phy mode connected to 44 This driver supports configuring of the phy mode connected to
56 the CPSW. DEPRECATED: use PHY_TI_GMII_SEL. 45 the CPSW. DEPRECATED: use PHY_TI_GMII_SEL.
57 46
58config TI_CPSW_ALE
59 tristate "TI CPSW ALE Support"
60 ---help---
61 This driver supports TI's CPSW ALE module.
62
63config TI_CPSW 47config TI_CPSW
64 tristate "TI CPSW Switch Support" 48 tristate "TI CPSW Switch Support"
65 depends on ARCH_DAVINCI || ARCH_OMAP2PLUS || COMPILE_TEST 49 depends on ARCH_DAVINCI || ARCH_OMAP2PLUS || COMPILE_TEST
66 select TI_DAVINCI_CPDMA
67 select TI_DAVINCI_MDIO 50 select TI_DAVINCI_MDIO
68 select TI_CPSW_ALE
69 select MFD_SYSCON 51 select MFD_SYSCON
70 select REGMAP 52 select REGMAP
71 ---help--- 53 ---help---
@@ -94,7 +76,6 @@ config TI_CPTS_MOD
94 76
95config TI_KEYSTONE_NETCP 77config TI_KEYSTONE_NETCP
96 tristate "TI Keystone NETCP Core Support" 78 tristate "TI Keystone NETCP Core Support"
97 select TI_CPSW_ALE
98 select TI_DAVINCI_MDIO 79 select TI_DAVINCI_MDIO
99 depends on OF 80 depends on OF
100 depends on KEYSTONE_NAVIGATOR_DMA && KEYSTONE_NAVIGATOR_QMSS 81 depends on KEYSTONE_NAVIGATOR_DMA && KEYSTONE_NAVIGATOR_QMSS
diff --git a/drivers/net/ethernet/ti/Makefile b/drivers/net/ethernet/ti/Makefile
index 0be551de821c..c3f53a40b48f 100644
--- a/drivers/net/ethernet/ti/Makefile
+++ b/drivers/net/ethernet/ti/Makefile
@@ -8,16 +8,15 @@ obj-$(CONFIG_TI_DAVINCI_EMAC) += cpsw-common.o
8 8
9obj-$(CONFIG_TLAN) += tlan.o 9obj-$(CONFIG_TLAN) += tlan.o
10obj-$(CONFIG_CPMAC) += cpmac.o 10obj-$(CONFIG_CPMAC) += cpmac.o
11obj-$(CONFIG_TI_DAVINCI_EMAC) += davinci_emac.o 11obj-$(CONFIG_TI_DAVINCI_EMAC) += ti_davinci_emac.o
12ti_davinci_emac-y := davinci_emac.o davinci_cpdma.o
12obj-$(CONFIG_TI_DAVINCI_MDIO) += davinci_mdio.o 13obj-$(CONFIG_TI_DAVINCI_MDIO) += davinci_mdio.o
13obj-$(CONFIG_TI_DAVINCI_CPDMA) += davinci_cpdma.o
14obj-$(CONFIG_TI_CPSW_PHY_SEL) += cpsw-phy-sel.o 14obj-$(CONFIG_TI_CPSW_PHY_SEL) += cpsw-phy-sel.o
15obj-$(CONFIG_TI_CPSW_ALE) += cpsw_ale.o
16obj-$(CONFIG_TI_CPTS_MOD) += cpts.o 15obj-$(CONFIG_TI_CPTS_MOD) += cpts.o
17obj-$(CONFIG_TI_CPSW) += ti_cpsw.o 16obj-$(CONFIG_TI_CPSW) += ti_cpsw.o
18ti_cpsw-y := cpsw.o 17ti_cpsw-y := cpsw.o davinci_cpdma.o cpsw_ale.o cpsw_priv.o cpsw_sl.o cpsw_ethtool.o
19 18
20obj-$(CONFIG_TI_KEYSTONE_NETCP) += keystone_netcp.o 19obj-$(CONFIG_TI_KEYSTONE_NETCP) += keystone_netcp.o
21keystone_netcp-y := netcp_core.o 20keystone_netcp-y := netcp_core.o cpsw_ale.o
22obj-$(CONFIG_TI_KEYSTONE_NETCP_ETHSS) += keystone_netcp_ethss.o 21obj-$(CONFIG_TI_KEYSTONE_NETCP_ETHSS) += keystone_netcp_ethss.o
23keystone_netcp_ethss-y := netcp_ethss.o netcp_sgmii.o netcp_xgbepcsr.o 22keystone_netcp_ethss-y := netcp_ethss.o netcp_sgmii.o netcp_xgbepcsr.o
diff --git a/drivers/net/ethernet/ti/cpmac.c b/drivers/net/ethernet/ti/cpmac.c
index e2d47b24a869..3a655a4dc10e 100644
--- a/drivers/net/ethernet/ti/cpmac.c
+++ b/drivers/net/ethernet/ti/cpmac.c
@@ -1,19 +1,7 @@
1// SPDX-License-Identifier: GPL-2.0+
1/* 2/*
2 * Copyright (C) 2006, 2007 Eugene Konev 3 * Copyright (C) 2006, 2007 Eugene Konev
3 * 4 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
17 */ 5 */
18 6
19#include <linux/module.h> 7#include <linux/module.h>
diff --git a/drivers/net/ethernet/ti/cpsw-common.c b/drivers/net/ethernet/ti/cpsw-common.c
index 38d1cc557c11..bfa81bbfce3f 100644
--- a/drivers/net/ethernet/ti/cpsw-common.c
+++ b/drivers/net/ethernet/ti/cpsw-common.c
@@ -1,14 +1,4 @@
1/* 1// SPDX-License-Identifier: GPL-2.0+
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; either version 2 of the License, or
5 * (at your option) any later version.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12 2
13#include <linux/kernel.h> 3#include <linux/kernel.h>
14#include <linux/module.h> 4#include <linux/module.h>
diff --git a/drivers/net/ethernet/ti/cpsw-phy-sel.c b/drivers/net/ethernet/ti/cpsw-phy-sel.c
index fec275e2208d..48e0924259f5 100644
--- a/drivers/net/ethernet/ti/cpsw-phy-sel.c
+++ b/drivers/net/ethernet/ti/cpsw-phy-sel.c
@@ -1,17 +1,10 @@
1// SPDX-License-Identifier: GPL-2.0
1/* Texas Instruments Ethernet Switch Driver 2/* Texas Instruments Ethernet Switch Driver
2 * 3 *
3 * Copyright (C) 2013 Texas Instruments 4 * Copyright (C) 2013 Texas Instruments
4 * 5 *
5 * Module Author: Mugunthan V N <mugunthanvnm@ti.com> 6 * Module Author: Mugunthan V N <mugunthanvnm@ti.com>
6 * 7 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * version 2 as published by the Free Software Foundation.
10 *
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */ 8 */
16 9
17#include <linux/platform_device.h> 10#include <linux/platform_device.h>
diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c
index a591583d120e..660c716e7eb6 100644
--- a/drivers/net/ethernet/ti/cpsw.c
+++ b/drivers/net/ethernet/ti/cpsw.c
@@ -1,16 +1,9 @@
1// SPDX-License-Identifier: GPL-2.0
1/* 2/*
2 * Texas Instruments Ethernet Switch Driver 3 * Texas Instruments Ethernet Switch Driver
3 * 4 *
4 * Copyright (C) 2012 Texas Instruments 5 * Copyright (C) 2012 Texas Instruments
5 * 6 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */ 7 */
15 8
16#include <linux/kernel.h> 9#include <linux/kernel.h>
@@ -44,138 +37,13 @@
44 37
45#include "cpsw.h" 38#include "cpsw.h"
46#include "cpsw_ale.h" 39#include "cpsw_ale.h"
40#include "cpsw_priv.h"
41#include "cpsw_sl.h"
47#include "cpts.h" 42#include "cpts.h"
48#include "davinci_cpdma.h" 43#include "davinci_cpdma.h"
49 44
50#include <net/pkt_sched.h> 45#include <net/pkt_sched.h>
51 46
52#define CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_WOL | \
53 NETIF_MSG_DRV | NETIF_MSG_LINK | \
54 NETIF_MSG_IFUP | NETIF_MSG_INTR | \
55 NETIF_MSG_PROBE | NETIF_MSG_TIMER | \
56 NETIF_MSG_IFDOWN | NETIF_MSG_RX_ERR | \
57 NETIF_MSG_TX_ERR | NETIF_MSG_TX_DONE | \
58 NETIF_MSG_PKTDATA | NETIF_MSG_TX_QUEUED | \
59 NETIF_MSG_RX_STATUS)
60
61#define cpsw_info(priv, type, format, ...) \
62do { \
63 if (netif_msg_##type(priv) && net_ratelimit()) \
64 dev_info(priv->dev, format, ## __VA_ARGS__); \
65} while (0)
66
67#define cpsw_err(priv, type, format, ...) \
68do { \
69 if (netif_msg_##type(priv) && net_ratelimit()) \
70 dev_err(priv->dev, format, ## __VA_ARGS__); \
71} while (0)
72
73#define cpsw_dbg(priv, type, format, ...) \
74do { \
75 if (netif_msg_##type(priv) && net_ratelimit()) \
76 dev_dbg(priv->dev, format, ## __VA_ARGS__); \
77} while (0)
78
79#define cpsw_notice(priv, type, format, ...) \
80do { \
81 if (netif_msg_##type(priv) && net_ratelimit()) \
82 dev_notice(priv->dev, format, ## __VA_ARGS__); \
83} while (0)
84
85#define ALE_ALL_PORTS 0x7
86
87#define CPSW_MAJOR_VERSION(reg) (reg >> 8 & 0x7)
88#define CPSW_MINOR_VERSION(reg) (reg & 0xff)
89#define CPSW_RTL_VERSION(reg) ((reg >> 11) & 0x1f)
90
91#define CPSW_VERSION_1 0x19010a
92#define CPSW_VERSION_2 0x19010c
93#define CPSW_VERSION_3 0x19010f
94#define CPSW_VERSION_4 0x190112
95
96#define HOST_PORT_NUM 0
97#define CPSW_ALE_PORTS_NUM 3
98#define SLIVER_SIZE 0x40
99
100#define CPSW1_HOST_PORT_OFFSET 0x028
101#define CPSW1_SLAVE_OFFSET 0x050
102#define CPSW1_SLAVE_SIZE 0x040
103#define CPSW1_CPDMA_OFFSET 0x100
104#define CPSW1_STATERAM_OFFSET 0x200
105#define CPSW1_HW_STATS 0x400
106#define CPSW1_CPTS_OFFSET 0x500
107#define CPSW1_ALE_OFFSET 0x600
108#define CPSW1_SLIVER_OFFSET 0x700
109
110#define CPSW2_HOST_PORT_OFFSET 0x108
111#define CPSW2_SLAVE_OFFSET 0x200
112#define CPSW2_SLAVE_SIZE 0x100
113#define CPSW2_CPDMA_OFFSET 0x800
114#define CPSW2_HW_STATS 0x900
115#define CPSW2_STATERAM_OFFSET 0xa00
116#define CPSW2_CPTS_OFFSET 0xc00
117#define CPSW2_ALE_OFFSET 0xd00
118#define CPSW2_SLIVER_OFFSET 0xd80
119#define CPSW2_BD_OFFSET 0x2000
120
121#define CPDMA_RXTHRESH 0x0c0
122#define CPDMA_RXFREE 0x0e0
123#define CPDMA_TXHDP 0x00
124#define CPDMA_RXHDP 0x20
125#define CPDMA_TXCP 0x40
126#define CPDMA_RXCP 0x60
127
128#define CPSW_POLL_WEIGHT 64
129#define CPSW_RX_VLAN_ENCAP_HDR_SIZE 4
130#define CPSW_MIN_PACKET_SIZE (VLAN_ETH_ZLEN)
131#define CPSW_MAX_PACKET_SIZE (VLAN_ETH_FRAME_LEN +\
132 ETH_FCS_LEN +\
133 CPSW_RX_VLAN_ENCAP_HDR_SIZE)
134
135#define RX_PRIORITY_MAPPING 0x76543210
136#define TX_PRIORITY_MAPPING 0x33221100
137#define CPDMA_TX_PRIORITY_MAP 0x76543210
138
139#define CPSW_VLAN_AWARE BIT(1)
140#define CPSW_RX_VLAN_ENCAP BIT(2)
141#define CPSW_ALE_VLAN_AWARE 1
142
143#define CPSW_FIFO_NORMAL_MODE (0 << 16)
144#define CPSW_FIFO_DUAL_MAC_MODE (1 << 16)
145#define CPSW_FIFO_RATE_LIMIT_MODE (2 << 16)
146
147#define CPSW_INTPACEEN (0x3f << 16)
148#define CPSW_INTPRESCALE_MASK (0x7FF << 0)
149#define CPSW_CMINTMAX_CNT 63
150#define CPSW_CMINTMIN_CNT 2
151#define CPSW_CMINTMAX_INTVL (1000 / CPSW_CMINTMIN_CNT)
152#define CPSW_CMINTMIN_INTVL ((1000 / CPSW_CMINTMAX_CNT) + 1)
153
154#define cpsw_slave_index(cpsw, priv) \
155 ((cpsw->data.dual_emac) ? priv->emac_port : \
156 cpsw->data.active_slave)
157#define IRQ_NUM 2
158#define CPSW_MAX_QUEUES 8
159#define CPSW_CPDMA_DESCS_POOL_SIZE_DEFAULT 256
160#define CPSW_FIFO_QUEUE_TYPE_SHIFT 16
161#define CPSW_FIFO_SHAPE_EN_SHIFT 16
162#define CPSW_FIFO_RATE_EN_SHIFT 20
163#define CPSW_TC_NUM 4
164#define CPSW_FIFO_SHAPERS_NUM (CPSW_TC_NUM - 1)
165#define CPSW_PCT_MASK 0x7f
166
167#define CPSW_RX_VLAN_ENCAP_HDR_PRIO_SHIFT 29
168#define CPSW_RX_VLAN_ENCAP_HDR_PRIO_MSK GENMASK(2, 0)
169#define CPSW_RX_VLAN_ENCAP_HDR_VID_SHIFT 16
170#define CPSW_RX_VLAN_ENCAP_HDR_PKT_TYPE_SHIFT 8
171#define CPSW_RX_VLAN_ENCAP_HDR_PKT_TYPE_MSK GENMASK(1, 0)
172enum {
173 CPSW_RX_VLAN_ENCAP_HDR_PKT_VLAN_TAG = 0,
174 CPSW_RX_VLAN_ENCAP_HDR_PKT_RESERV,
175 CPSW_RX_VLAN_ENCAP_HDR_PKT_PRIO_TAG,
176 CPSW_RX_VLAN_ENCAP_HDR_PKT_UNTAG,
177};
178
179static int debug_level; 47static int debug_level;
180module_param(debug_level, int, 0); 48module_param(debug_level, int, 0);
181MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)"); 49MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)");
@@ -192,369 +60,6 @@ static int descs_pool_size = CPSW_CPDMA_DESCS_POOL_SIZE_DEFAULT;
192module_param(descs_pool_size, int, 0444); 60module_param(descs_pool_size, int, 0444);
193MODULE_PARM_DESC(descs_pool_size, "Number of CPDMA CPPI descriptors in pool"); 61MODULE_PARM_DESC(descs_pool_size, "Number of CPDMA CPPI descriptors in pool");
194 62
195struct cpsw_wr_regs {
196 u32 id_ver;
197 u32 soft_reset;
198 u32 control;
199 u32 int_control;
200 u32 rx_thresh_en;
201 u32 rx_en;
202 u32 tx_en;
203 u32 misc_en;
204 u32 mem_allign1[8];
205 u32 rx_thresh_stat;
206 u32 rx_stat;
207 u32 tx_stat;
208 u32 misc_stat;
209 u32 mem_allign2[8];
210 u32 rx_imax;
211 u32 tx_imax;
212
213};
214
215struct cpsw_ss_regs {
216 u32 id_ver;
217 u32 control;
218 u32 soft_reset;
219 u32 stat_port_en;
220 u32 ptype;
221 u32 soft_idle;
222 u32 thru_rate;
223 u32 gap_thresh;
224 u32 tx_start_wds;
225 u32 flow_control;
226 u32 vlan_ltype;
227 u32 ts_ltype;
228 u32 dlr_ltype;
229};
230
231/* CPSW_PORT_V1 */
232#define CPSW1_MAX_BLKS 0x00 /* Maximum FIFO Blocks */
233#define CPSW1_BLK_CNT 0x04 /* FIFO Block Usage Count (Read Only) */
234#define CPSW1_TX_IN_CTL 0x08 /* Transmit FIFO Control */
235#define CPSW1_PORT_VLAN 0x0c /* VLAN Register */
236#define CPSW1_TX_PRI_MAP 0x10 /* Tx Header Priority to Switch Pri Mapping */
237#define CPSW1_TS_CTL 0x14 /* Time Sync Control */
238#define CPSW1_TS_SEQ_LTYPE 0x18 /* Time Sync Sequence ID Offset and Msg Type */
239#define CPSW1_TS_VLAN 0x1c /* Time Sync VLAN1 and VLAN2 */
240
241/* CPSW_PORT_V2 */
242#define CPSW2_CONTROL 0x00 /* Control Register */
243#define CPSW2_MAX_BLKS 0x08 /* Maximum FIFO Blocks */
244#define CPSW2_BLK_CNT 0x0c /* FIFO Block Usage Count (Read Only) */
245#define CPSW2_TX_IN_CTL 0x10 /* Transmit FIFO Control */
246#define CPSW2_PORT_VLAN 0x14 /* VLAN Register */
247#define CPSW2_TX_PRI_MAP 0x18 /* Tx Header Priority to Switch Pri Mapping */
248#define CPSW2_TS_SEQ_MTYPE 0x1c /* Time Sync Sequence ID Offset and Msg Type */
249
250/* CPSW_PORT_V1 and V2 */
251#define SA_LO 0x20 /* CPGMAC_SL Source Address Low */
252#define SA_HI 0x24 /* CPGMAC_SL Source Address High */
253#define SEND_PERCENT 0x28 /* Transmit Queue Send Percentages */
254
255/* CPSW_PORT_V2 only */
256#define RX_DSCP_PRI_MAP0 0x30 /* Rx DSCP Priority to Rx Packet Mapping */
257#define RX_DSCP_PRI_MAP1 0x34 /* Rx DSCP Priority to Rx Packet Mapping */
258#define RX_DSCP_PRI_MAP2 0x38 /* Rx DSCP Priority to Rx Packet Mapping */
259#define RX_DSCP_PRI_MAP3 0x3c /* Rx DSCP Priority to Rx Packet Mapping */
260#define RX_DSCP_PRI_MAP4 0x40 /* Rx DSCP Priority to Rx Packet Mapping */
261#define RX_DSCP_PRI_MAP5 0x44 /* Rx DSCP Priority to Rx Packet Mapping */
262#define RX_DSCP_PRI_MAP6 0x48 /* Rx DSCP Priority to Rx Packet Mapping */
263#define RX_DSCP_PRI_MAP7 0x4c /* Rx DSCP Priority to Rx Packet Mapping */
264
265/* Bit definitions for the CPSW2_CONTROL register */
266#define PASS_PRI_TAGGED BIT(24) /* Pass Priority Tagged */
267#define VLAN_LTYPE2_EN BIT(21) /* VLAN LTYPE 2 enable */
268#define VLAN_LTYPE1_EN BIT(20) /* VLAN LTYPE 1 enable */
269#define DSCP_PRI_EN BIT(16) /* DSCP Priority Enable */
270#define TS_107 BIT(15) /* Tyme Sync Dest IP Address 107 */
271#define TS_320 BIT(14) /* Time Sync Dest Port 320 enable */
272#define TS_319 BIT(13) /* Time Sync Dest Port 319 enable */
273#define TS_132 BIT(12) /* Time Sync Dest IP Addr 132 enable */
274#define TS_131 BIT(11) /* Time Sync Dest IP Addr 131 enable */
275#define TS_130 BIT(10) /* Time Sync Dest IP Addr 130 enable */
276#define TS_129 BIT(9) /* Time Sync Dest IP Addr 129 enable */
277#define TS_TTL_NONZERO BIT(8) /* Time Sync Time To Live Non-zero enable */
278#define TS_ANNEX_F_EN BIT(6) /* Time Sync Annex F enable */
279#define TS_ANNEX_D_EN BIT(4) /* Time Sync Annex D enable */
280#define TS_LTYPE2_EN BIT(3) /* Time Sync LTYPE 2 enable */
281#define TS_LTYPE1_EN BIT(2) /* Time Sync LTYPE 1 enable */
282#define TS_TX_EN BIT(1) /* Time Sync Transmit Enable */
283#define TS_RX_EN BIT(0) /* Time Sync Receive Enable */
284
285#define CTRL_V2_TS_BITS \
286 (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
287 TS_TTL_NONZERO | TS_ANNEX_D_EN | TS_LTYPE1_EN | VLAN_LTYPE1_EN)
288
289#define CTRL_V2_ALL_TS_MASK (CTRL_V2_TS_BITS | TS_TX_EN | TS_RX_EN)
290#define CTRL_V2_TX_TS_BITS (CTRL_V2_TS_BITS | TS_TX_EN)
291#define CTRL_V2_RX_TS_BITS (CTRL_V2_TS_BITS | TS_RX_EN)
292
293
294#define CTRL_V3_TS_BITS \
295 (TS_107 | TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
296 TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\
297 TS_LTYPE1_EN | VLAN_LTYPE1_EN)
298
299#define CTRL_V3_ALL_TS_MASK (CTRL_V3_TS_BITS | TS_TX_EN | TS_RX_EN)
300#define CTRL_V3_TX_TS_BITS (CTRL_V3_TS_BITS | TS_TX_EN)
301#define CTRL_V3_RX_TS_BITS (CTRL_V3_TS_BITS | TS_RX_EN)
302
303/* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */
304#define TS_SEQ_ID_OFFSET_SHIFT (16) /* Time Sync Sequence ID Offset */
305#define TS_SEQ_ID_OFFSET_MASK (0x3f)
306#define TS_MSG_TYPE_EN_SHIFT (0) /* Time Sync Message Type Enable */
307#define TS_MSG_TYPE_EN_MASK (0xffff)
308
309/* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
310#define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3))
311
312/* Bit definitions for the CPSW1_TS_CTL register */
313#define CPSW_V1_TS_RX_EN BIT(0)
314#define CPSW_V1_TS_TX_EN BIT(4)
315#define CPSW_V1_MSG_TYPE_OFS 16
316
317/* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */
318#define CPSW_V1_SEQ_ID_OFS_SHIFT 16
319
320#define CPSW_MAX_BLKS_TX 15
321#define CPSW_MAX_BLKS_TX_SHIFT 4
322#define CPSW_MAX_BLKS_RX 5
323
324struct cpsw_host_regs {
325 u32 max_blks;
326 u32 blk_cnt;
327 u32 tx_in_ctl;
328 u32 port_vlan;
329 u32 tx_pri_map;
330 u32 cpdma_tx_pri_map;
331 u32 cpdma_rx_chan_map;
332};
333
334struct cpsw_sliver_regs {
335 u32 id_ver;
336 u32 mac_control;
337 u32 mac_status;
338 u32 soft_reset;
339 u32 rx_maxlen;
340 u32 __reserved_0;
341 u32 rx_pause;
342 u32 tx_pause;
343 u32 __reserved_1;
344 u32 rx_pri_map;
345};
346
347struct cpsw_hw_stats {
348 u32 rxgoodframes;
349 u32 rxbroadcastframes;
350 u32 rxmulticastframes;
351 u32 rxpauseframes;
352 u32 rxcrcerrors;
353 u32 rxaligncodeerrors;
354 u32 rxoversizedframes;
355 u32 rxjabberframes;
356 u32 rxundersizedframes;
357 u32 rxfragments;
358 u32 __pad_0[2];
359 u32 rxoctets;
360 u32 txgoodframes;
361 u32 txbroadcastframes;
362 u32 txmulticastframes;
363 u32 txpauseframes;
364 u32 txdeferredframes;
365 u32 txcollisionframes;
366 u32 txsinglecollframes;
367 u32 txmultcollframes;
368 u32 txexcessivecollisions;
369 u32 txlatecollisions;
370 u32 txunderrun;
371 u32 txcarriersenseerrors;
372 u32 txoctets;
373 u32 octetframes64;
374 u32 octetframes65t127;
375 u32 octetframes128t255;
376 u32 octetframes256t511;
377 u32 octetframes512t1023;
378 u32 octetframes1024tup;
379 u32 netoctets;
380 u32 rxsofoverruns;
381 u32 rxmofoverruns;
382 u32 rxdmaoverruns;
383};
384
385struct cpsw_slave_data {
386 struct device_node *phy_node;
387 char phy_id[MII_BUS_ID_SIZE];
388 int phy_if;
389 u8 mac_addr[ETH_ALEN];
390 u16 dual_emac_res_vlan; /* Reserved VLAN for DualEMAC */
391 struct phy *ifphy;
392};
393
394struct cpsw_platform_data {
395 struct cpsw_slave_data *slave_data;
396 u32 ss_reg_ofs; /* Subsystem control register offset */
397 u32 channels; /* number of cpdma channels (symmetric) */
398 u32 slaves; /* number of slave cpgmac ports */
399 u32 active_slave; /* time stamping, ethtool and SIOCGMIIPHY slave */
400 u32 ale_entries; /* ale table size */
401 u32 bd_ram_size; /*buffer descriptor ram size */
402 u32 mac_control; /* Mac control register */
403 u16 default_vlan; /* Def VLAN for ALE lookup in VLAN aware mode*/
404 bool dual_emac; /* Enable Dual EMAC mode */
405};
406
407struct cpsw_slave {
408 void __iomem *regs;
409 struct cpsw_sliver_regs __iomem *sliver;
410 int slave_num;
411 u32 mac_control;
412 struct cpsw_slave_data *data;
413 struct phy_device *phy;
414 struct net_device *ndev;
415 u32 port_vlan;
416};
417
418static inline u32 slave_read(struct cpsw_slave *slave, u32 offset)
419{
420 return readl_relaxed(slave->regs + offset);
421}
422
423static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset)
424{
425 writel_relaxed(val, slave->regs + offset);
426}
427
428struct cpsw_vector {
429 struct cpdma_chan *ch;
430 int budget;
431};
432
433struct cpsw_common {
434 struct device *dev;
435 struct cpsw_platform_data data;
436 struct napi_struct napi_rx;
437 struct napi_struct napi_tx;
438 struct cpsw_ss_regs __iomem *regs;
439 struct cpsw_wr_regs __iomem *wr_regs;
440 u8 __iomem *hw_stats;
441 struct cpsw_host_regs __iomem *host_port_regs;
442 u32 version;
443 u32 coal_intvl;
444 u32 bus_freq_mhz;
445 int rx_packet_max;
446 struct cpsw_slave *slaves;
447 struct cpdma_ctlr *dma;
448 struct cpsw_vector txv[CPSW_MAX_QUEUES];
449 struct cpsw_vector rxv[CPSW_MAX_QUEUES];
450 struct cpsw_ale *ale;
451 bool quirk_irq;
452 bool rx_irq_disabled;
453 bool tx_irq_disabled;
454 u32 irqs_table[IRQ_NUM];
455 struct cpts *cpts;
456 int rx_ch_num, tx_ch_num;
457 int speed;
458 int usage_count;
459};
460
461struct cpsw_priv {
462 struct net_device *ndev;
463 struct device *dev;
464 u32 msg_enable;
465 u8 mac_addr[ETH_ALEN];
466 bool rx_pause;
467 bool tx_pause;
468 bool mqprio_hw;
469 int fifo_bw[CPSW_TC_NUM];
470 int shp_cfg_speed;
471 int tx_ts_enabled;
472 int rx_ts_enabled;
473 u32 emac_port;
474 struct cpsw_common *cpsw;
475};
476
477struct cpsw_stats {
478 char stat_string[ETH_GSTRING_LEN];
479 int type;
480 int sizeof_stat;
481 int stat_offset;
482};
483
484enum {
485 CPSW_STATS,
486 CPDMA_RX_STATS,
487 CPDMA_TX_STATS,
488};
489
490#define CPSW_STAT(m) CPSW_STATS, \
491 FIELD_SIZEOF(struct cpsw_hw_stats, m), \
492 offsetof(struct cpsw_hw_stats, m)
493#define CPDMA_RX_STAT(m) CPDMA_RX_STATS, \
494 FIELD_SIZEOF(struct cpdma_chan_stats, m), \
495 offsetof(struct cpdma_chan_stats, m)
496#define CPDMA_TX_STAT(m) CPDMA_TX_STATS, \
497 FIELD_SIZEOF(struct cpdma_chan_stats, m), \
498 offsetof(struct cpdma_chan_stats, m)
499
500static const struct cpsw_stats cpsw_gstrings_stats[] = {
501 { "Good Rx Frames", CPSW_STAT(rxgoodframes) },
502 { "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes) },
503 { "Multicast Rx Frames", CPSW_STAT(rxmulticastframes) },
504 { "Pause Rx Frames", CPSW_STAT(rxpauseframes) },
505 { "Rx CRC Errors", CPSW_STAT(rxcrcerrors) },
506 { "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors) },
507 { "Oversize Rx Frames", CPSW_STAT(rxoversizedframes) },
508 { "Rx Jabbers", CPSW_STAT(rxjabberframes) },
509 { "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes) },
510 { "Rx Fragments", CPSW_STAT(rxfragments) },
511 { "Rx Octets", CPSW_STAT(rxoctets) },
512 { "Good Tx Frames", CPSW_STAT(txgoodframes) },
513 { "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes) },
514 { "Multicast Tx Frames", CPSW_STAT(txmulticastframes) },
515 { "Pause Tx Frames", CPSW_STAT(txpauseframes) },
516 { "Deferred Tx Frames", CPSW_STAT(txdeferredframes) },
517 { "Collisions", CPSW_STAT(txcollisionframes) },
518 { "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes) },
519 { "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes) },
520 { "Excessive Collisions", CPSW_STAT(txexcessivecollisions) },
521 { "Late Collisions", CPSW_STAT(txlatecollisions) },
522 { "Tx Underrun", CPSW_STAT(txunderrun) },
523 { "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors) },
524 { "Tx Octets", CPSW_STAT(txoctets) },
525 { "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64) },
526 { "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127) },
527 { "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255) },
528 { "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511) },
529 { "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023) },
530 { "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup) },
531 { "Net Octets", CPSW_STAT(netoctets) },
532 { "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns) },
533 { "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns) },
534 { "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns) },
535};
536
537static const struct cpsw_stats cpsw_gstrings_ch_stats[] = {
538 { "head_enqueue", CPDMA_RX_STAT(head_enqueue) },
539 { "tail_enqueue", CPDMA_RX_STAT(tail_enqueue) },
540 { "pad_enqueue", CPDMA_RX_STAT(pad_enqueue) },
541 { "misqueued", CPDMA_RX_STAT(misqueued) },
542 { "desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail) },
543 { "pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail) },
544 { "runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff) },
545 { "runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff) },
546 { "empty_dequeue", CPDMA_RX_STAT(empty_dequeue) },
547 { "busy_dequeue", CPDMA_RX_STAT(busy_dequeue) },
548 { "good_dequeue", CPDMA_RX_STAT(good_dequeue) },
549 { "requeue", CPDMA_RX_STAT(requeue) },
550 { "teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) },
551};
552
553#define CPSW_STATS_COMMON_LEN ARRAY_SIZE(cpsw_gstrings_stats)
554#define CPSW_STATS_CH_LEN ARRAY_SIZE(cpsw_gstrings_ch_stats)
555
556#define ndev_to_cpsw(ndev) (((struct cpsw_priv *)netdev_priv(ndev))->cpsw)
557#define napi_to_cpsw(napi) container_of(napi, struct cpsw_common, napi)
558#define for_each_slave(priv, func, arg...) \ 63#define for_each_slave(priv, func, arg...) \
559 do { \ 64 do { \
560 struct cpsw_slave *slave; \ 65 struct cpsw_slave *slave; \
@@ -572,11 +77,6 @@ static const struct cpsw_stats cpsw_gstrings_ch_stats[] = {
572static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev, 77static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev,
573 __be16 proto, u16 vid); 78 __be16 proto, u16 vid);
574 79
575static inline int cpsw_get_slave_port(u32 slave_num)
576{
577 return slave_num + 1;
578}
579
580static void cpsw_set_promiscious(struct net_device *ndev, bool enable) 80static void cpsw_set_promiscious(struct net_device *ndev, bool enable)
581{ 81{
582 struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 82 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
@@ -653,13 +153,6 @@ static void cpsw_set_promiscious(struct net_device *ndev, bool enable)
653 } 153 }
654} 154}
655 155
656struct addr_sync_ctx {
657 struct net_device *ndev;
658 const u8 *addr; /* address to be synched */
659 int consumed; /* number of address instances */
660 int flush; /* flush flag */
661};
662
663/** 156/**
664 * cpsw_set_mc - adds multicast entry to the table if it's not added or deletes 157 * cpsw_set_mc - adds multicast entry to the table if it's not added or deletes
665 * if it's not deleted 158 * if it's not deleted
@@ -800,12 +293,17 @@ static int cpsw_purge_all_mc(struct net_device *ndev, const u8 *addr, int num)
800 293
801static void cpsw_ndo_set_rx_mode(struct net_device *ndev) 294static void cpsw_ndo_set_rx_mode(struct net_device *ndev)
802{ 295{
803 struct cpsw_common *cpsw = ndev_to_cpsw(ndev); 296 struct cpsw_priv *priv = netdev_priv(ndev);
297 struct cpsw_common *cpsw = priv->cpsw;
298 int slave_port = -1;
299
300 if (cpsw->data.dual_emac)
301 slave_port = priv->emac_port + 1;
804 302
805 if (ndev->flags & IFF_PROMISC) { 303 if (ndev->flags & IFF_PROMISC) {
806 /* Enable promiscuous mode */ 304 /* Enable promiscuous mode */
807 cpsw_set_promiscious(ndev, true); 305 cpsw_set_promiscious(ndev, true);
808 cpsw_ale_set_allmulti(cpsw->ale, IFF_ALLMULTI); 306 cpsw_ale_set_allmulti(cpsw->ale, IFF_ALLMULTI, slave_port);
809 return; 307 return;
810 } else { 308 } else {
811 /* Disable promiscuous mode */ 309 /* Disable promiscuous mode */
@@ -813,14 +311,15 @@ static void cpsw_ndo_set_rx_mode(struct net_device *ndev)
813 } 311 }
814 312
815 /* Restore allmulti on vlans if necessary */ 313 /* Restore allmulti on vlans if necessary */
816 cpsw_ale_set_allmulti(cpsw->ale, ndev->flags & IFF_ALLMULTI); 314 cpsw_ale_set_allmulti(cpsw->ale,
315 ndev->flags & IFF_ALLMULTI, slave_port);
817 316
818 /* add/remove mcast address either for real netdev or for vlan */ 317 /* add/remove mcast address either for real netdev or for vlan */
819 __hw_addr_ref_sync_dev(&ndev->mc, ndev, cpsw_add_mc_addr, 318 __hw_addr_ref_sync_dev(&ndev->mc, ndev, cpsw_add_mc_addr,
820 cpsw_del_mc_addr); 319 cpsw_del_mc_addr);
821} 320}
822 321
823static void cpsw_intr_enable(struct cpsw_common *cpsw) 322void cpsw_intr_enable(struct cpsw_common *cpsw)
824{ 323{
825 writel_relaxed(0xFF, &cpsw->wr_regs->tx_en); 324 writel_relaxed(0xFF, &cpsw->wr_regs->tx_en);
826 writel_relaxed(0xFF, &cpsw->wr_regs->rx_en); 325 writel_relaxed(0xFF, &cpsw->wr_regs->rx_en);
@@ -829,7 +328,7 @@ static void cpsw_intr_enable(struct cpsw_common *cpsw)
829 return; 328 return;
830} 329}
831 330
832static void cpsw_intr_disable(struct cpsw_common *cpsw) 331void cpsw_intr_disable(struct cpsw_common *cpsw)
833{ 332{
834 writel_relaxed(0, &cpsw->wr_regs->tx_en); 333 writel_relaxed(0, &cpsw->wr_regs->tx_en);
835 writel_relaxed(0, &cpsw->wr_regs->rx_en); 334 writel_relaxed(0, &cpsw->wr_regs->rx_en);
@@ -838,7 +337,7 @@ static void cpsw_intr_disable(struct cpsw_common *cpsw)
838 return; 337 return;
839} 338}
840 339
841static void cpsw_tx_handler(void *token, int len, int status) 340void cpsw_tx_handler(void *token, int len, int status)
842{ 341{
843 struct netdev_queue *txq; 342 struct netdev_queue *txq;
844 struct sk_buff *skb = token; 343 struct sk_buff *skb = token;
@@ -970,11 +469,9 @@ requeue:
970 dev_kfree_skb_any(new_skb); 469 dev_kfree_skb_any(new_skb);
971} 470}
972 471
973static void cpsw_split_res(struct net_device *ndev) 472void cpsw_split_res(struct cpsw_common *cpsw)
974{ 473{
975 struct cpsw_priv *priv = netdev_priv(ndev);
976 u32 consumed_rate = 0, bigest_rate = 0; 474 u32 consumed_rate = 0, bigest_rate = 0;
977 struct cpsw_common *cpsw = priv->cpsw;
978 struct cpsw_vector *txv = cpsw->txv; 475 struct cpsw_vector *txv = cpsw->txv;
979 int i, ch_weight, rlim_ch_num = 0; 476 int i, ch_weight, rlim_ch_num = 0;
980 int budget, bigest_rate_ch = 0; 477 int budget, bigest_rate_ch = 0;
@@ -1254,29 +751,32 @@ static void _cpsw_adjust_link(struct cpsw_slave *slave,
1254 slave_port = cpsw_get_slave_port(slave->slave_num); 751 slave_port = cpsw_get_slave_port(slave->slave_num);
1255 752
1256 if (phy->link) { 753 if (phy->link) {
1257 mac_control = cpsw->data.mac_control; 754 mac_control = CPSW_SL_CTL_GMII_EN;
1258
1259 /* enable forwarding */
1260 cpsw_ale_control_set(cpsw->ale, slave_port,
1261 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
1262 755
1263 if (phy->speed == 1000) 756 if (phy->speed == 1000)
1264 mac_control |= BIT(7); /* GIGABITEN */ 757 mac_control |= CPSW_SL_CTL_GIG;
1265 if (phy->duplex) 758 if (phy->duplex)
1266 mac_control |= BIT(0); /* FULLDUPLEXEN */ 759 mac_control |= CPSW_SL_CTL_FULLDUPLEX;
1267 760
1268 /* set speed_in input in case RMII mode is used in 100Mbps */ 761 /* set speed_in input in case RMII mode is used in 100Mbps */
1269 if (phy->speed == 100) 762 if (phy->speed == 100)
1270 mac_control |= BIT(15); 763 mac_control |= CPSW_SL_CTL_IFCTL_A;
1271 /* in band mode only works in 10Mbps RGMII mode */ 764 /* in band mode only works in 10Mbps RGMII mode */
1272 else if ((phy->speed == 10) && phy_interface_is_rgmii(phy)) 765 else if ((phy->speed == 10) && phy_interface_is_rgmii(phy))
1273 mac_control |= BIT(18); /* In Band mode */ 766 mac_control |= CPSW_SL_CTL_EXT_EN; /* In Band mode */
1274 767
1275 if (priv->rx_pause) 768 if (priv->rx_pause)
1276 mac_control |= BIT(3); 769 mac_control |= CPSW_SL_CTL_RX_FLOW_EN;
1277 770
1278 if (priv->tx_pause) 771 if (priv->tx_pause)
1279 mac_control |= BIT(4); 772 mac_control |= CPSW_SL_CTL_TX_FLOW_EN;
773
774 if (mac_control != slave->mac_control)
775 cpsw_sl_ctl_set(slave->mac_sl, mac_control);
776
777 /* enable forwarding */
778 cpsw_ale_control_set(cpsw->ale, slave_port,
779 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
1280 780
1281 *link = true; 781 *link = true;
1282 782
@@ -1290,12 +790,14 @@ static void _cpsw_adjust_link(struct cpsw_slave *slave,
1290 /* disable forwarding */ 790 /* disable forwarding */
1291 cpsw_ale_control_set(cpsw->ale, slave_port, 791 cpsw_ale_control_set(cpsw->ale, slave_port,
1292 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 792 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
793
794 cpsw_sl_wait_for_idle(slave->mac_sl, 100);
795
796 cpsw_sl_ctl_reset(slave->mac_sl);
1293 } 797 }
1294 798
1295 if (mac_control != slave->mac_control) { 799 if (mac_control != slave->mac_control)
1296 phy_print_status(phy); 800 phy_print_status(phy);
1297 writel_relaxed(mac_control, &slave->sliver->mac_control);
1298 }
1299 801
1300 slave->mac_control = mac_control; 802 slave->mac_control = mac_control;
1301} 803}
@@ -1348,7 +850,7 @@ static void cpsw_adjust_link(struct net_device *ndev)
1348 850
1349 if (link) { 851 if (link) {
1350 if (cpsw_need_resplit(cpsw)) 852 if (cpsw_need_resplit(cpsw))
1351 cpsw_split_res(ndev); 853 cpsw_split_res(cpsw);
1352 854
1353 netif_carrier_on(ndev); 855 netif_carrier_on(ndev);
1354 if (netif_running(ndev)) 856 if (netif_running(ndev))
@@ -1359,167 +861,6 @@ static void cpsw_adjust_link(struct net_device *ndev)
1359 } 861 }
1360} 862}
1361 863
1362static int cpsw_get_coalesce(struct net_device *ndev,
1363 struct ethtool_coalesce *coal)
1364{
1365 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1366
1367 coal->rx_coalesce_usecs = cpsw->coal_intvl;
1368 return 0;
1369}
1370
1371static int cpsw_set_coalesce(struct net_device *ndev,
1372 struct ethtool_coalesce *coal)
1373{
1374 struct cpsw_priv *priv = netdev_priv(ndev);
1375 u32 int_ctrl;
1376 u32 num_interrupts = 0;
1377 u32 prescale = 0;
1378 u32 addnl_dvdr = 1;
1379 u32 coal_intvl = 0;
1380 struct cpsw_common *cpsw = priv->cpsw;
1381
1382 coal_intvl = coal->rx_coalesce_usecs;
1383
1384 int_ctrl = readl(&cpsw->wr_regs->int_control);
1385 prescale = cpsw->bus_freq_mhz * 4;
1386
1387 if (!coal->rx_coalesce_usecs) {
1388 int_ctrl &= ~(CPSW_INTPRESCALE_MASK | CPSW_INTPACEEN);
1389 goto update_return;
1390 }
1391
1392 if (coal_intvl < CPSW_CMINTMIN_INTVL)
1393 coal_intvl = CPSW_CMINTMIN_INTVL;
1394
1395 if (coal_intvl > CPSW_CMINTMAX_INTVL) {
1396 /* Interrupt pacer works with 4us Pulse, we can
1397 * throttle further by dilating the 4us pulse.
1398 */
1399 addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale;
1400
1401 if (addnl_dvdr > 1) {
1402 prescale *= addnl_dvdr;
1403 if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr))
1404 coal_intvl = (CPSW_CMINTMAX_INTVL
1405 * addnl_dvdr);
1406 } else {
1407 addnl_dvdr = 1;
1408 coal_intvl = CPSW_CMINTMAX_INTVL;
1409 }
1410 }
1411
1412 num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
1413 writel(num_interrupts, &cpsw->wr_regs->rx_imax);
1414 writel(num_interrupts, &cpsw->wr_regs->tx_imax);
1415
1416 int_ctrl |= CPSW_INTPACEEN;
1417 int_ctrl &= (~CPSW_INTPRESCALE_MASK);
1418 int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK);
1419
1420update_return:
1421 writel(int_ctrl, &cpsw->wr_regs->int_control);
1422
1423 cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl);
1424 cpsw->coal_intvl = coal_intvl;
1425
1426 return 0;
1427}
1428
1429static int cpsw_get_sset_count(struct net_device *ndev, int sset)
1430{
1431 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1432
1433 switch (sset) {
1434 case ETH_SS_STATS:
1435 return (CPSW_STATS_COMMON_LEN +
1436 (cpsw->rx_ch_num + cpsw->tx_ch_num) *
1437 CPSW_STATS_CH_LEN);
1438 default:
1439 return -EOPNOTSUPP;
1440 }
1441}
1442
1443static void cpsw_add_ch_strings(u8 **p, int ch_num, int rx_dir)
1444{
1445 int ch_stats_len;
1446 int line;
1447 int i;
1448
1449 ch_stats_len = CPSW_STATS_CH_LEN * ch_num;
1450 for (i = 0; i < ch_stats_len; i++) {
1451 line = i % CPSW_STATS_CH_LEN;
1452 snprintf(*p, ETH_GSTRING_LEN,
1453 "%s DMA chan %ld: %s", rx_dir ? "Rx" : "Tx",
1454 (long)(i / CPSW_STATS_CH_LEN),
1455 cpsw_gstrings_ch_stats[line].stat_string);
1456 *p += ETH_GSTRING_LEN;
1457 }
1458}
1459
1460static void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1461{
1462 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1463 u8 *p = data;
1464 int i;
1465
1466 switch (stringset) {
1467 case ETH_SS_STATS:
1468 for (i = 0; i < CPSW_STATS_COMMON_LEN; i++) {
1469 memcpy(p, cpsw_gstrings_stats[i].stat_string,
1470 ETH_GSTRING_LEN);
1471 p += ETH_GSTRING_LEN;
1472 }
1473
1474 cpsw_add_ch_strings(&p, cpsw->rx_ch_num, 1);
1475 cpsw_add_ch_strings(&p, cpsw->tx_ch_num, 0);
1476 break;
1477 }
1478}
1479
1480static void cpsw_get_ethtool_stats(struct net_device *ndev,
1481 struct ethtool_stats *stats, u64 *data)
1482{
1483 u8 *p;
1484 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1485 struct cpdma_chan_stats ch_stats;
1486 int i, l, ch;
1487
1488 /* Collect Davinci CPDMA stats for Rx and Tx Channel */
1489 for (l = 0; l < CPSW_STATS_COMMON_LEN; l++)
1490 data[l] = readl(cpsw->hw_stats +
1491 cpsw_gstrings_stats[l].stat_offset);
1492
1493 for (ch = 0; ch < cpsw->rx_ch_num; ch++) {
1494 cpdma_chan_get_stats(cpsw->rxv[ch].ch, &ch_stats);
1495 for (i = 0; i < CPSW_STATS_CH_LEN; i++, l++) {
1496 p = (u8 *)&ch_stats +
1497 cpsw_gstrings_ch_stats[i].stat_offset;
1498 data[l] = *(u32 *)p;
1499 }
1500 }
1501
1502 for (ch = 0; ch < cpsw->tx_ch_num; ch++) {
1503 cpdma_chan_get_stats(cpsw->txv[ch].ch, &ch_stats);
1504 for (i = 0; i < CPSW_STATS_CH_LEN; i++, l++) {
1505 p = (u8 *)&ch_stats +
1506 cpsw_gstrings_ch_stats[i].stat_offset;
1507 data[l] = *(u32 *)p;
1508 }
1509 }
1510}
1511
1512static inline int cpsw_tx_packet_submit(struct cpsw_priv *priv,
1513 struct sk_buff *skb,
1514 struct cpdma_chan *txch)
1515{
1516 struct cpsw_common *cpsw = priv->cpsw;
1517
1518 skb_tx_timestamp(skb);
1519 return cpdma_chan_submit(txch, skb, skb->data, skb->len,
1520 priv->emac_port + cpsw->data.dual_emac);
1521}
1522
1523static inline void cpsw_add_dual_emac_def_ale_entries( 864static inline void cpsw_add_dual_emac_def_ale_entries(
1524 struct cpsw_priv *priv, struct cpsw_slave *slave, 865 struct cpsw_priv *priv, struct cpsw_slave *slave,
1525 u32 slave_port) 866 u32 slave_port)
@@ -1542,24 +883,18 @@ static inline void cpsw_add_dual_emac_def_ale_entries(
1542 ALE_PORT_DROP_UNKNOWN_VLAN, 1); 883 ALE_PORT_DROP_UNKNOWN_VLAN, 1);
1543} 884}
1544 885
1545static void soft_reset_slave(struct cpsw_slave *slave)
1546{
1547 char name[32];
1548
1549 snprintf(name, sizeof(name), "slave-%d", slave->slave_num);
1550 soft_reset(name, &slave->sliver->soft_reset);
1551}
1552
1553static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv) 886static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv)
1554{ 887{
1555 u32 slave_port; 888 u32 slave_port;
1556 struct phy_device *phy; 889 struct phy_device *phy;
1557 struct cpsw_common *cpsw = priv->cpsw; 890 struct cpsw_common *cpsw = priv->cpsw;
1558 891
1559 soft_reset_slave(slave); 892 cpsw_sl_reset(slave->mac_sl, 100);
893 cpsw_sl_ctl_reset(slave->mac_sl);
1560 894
1561 /* setup priority mapping */ 895 /* setup priority mapping */
1562 writel_relaxed(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map); 896 cpsw_sl_reg_write(slave->mac_sl, CPSW_SL_RX_PRI_MAP,
897 RX_PRIORITY_MAPPING);
1563 898
1564 switch (cpsw->version) { 899 switch (cpsw->version) {
1565 case CPSW_VERSION_1: 900 case CPSW_VERSION_1:
@@ -1585,7 +920,8 @@ static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv)
1585 } 920 }
1586 921
1587 /* setup max packet size, and mac address */ 922 /* setup max packet size, and mac address */
1588 writel_relaxed(cpsw->rx_packet_max, &slave->sliver->rx_maxlen); 923 cpsw_sl_reg_write(slave->mac_sl, CPSW_SL_RX_MAXLEN,
924 cpsw->rx_packet_max);
1589 cpsw_set_slave_mac(slave, priv); 925 cpsw_set_slave_mac(slave, priv);
1590 926
1591 slave->mac_control = 0; /* no link yet */ 927 slave->mac_control = 0; /* no link yet */
@@ -1696,7 +1032,7 @@ static void cpsw_init_host_port(struct cpsw_priv *priv)
1696 } 1032 }
1697} 1033}
1698 1034
1699static int cpsw_fill_rx_channels(struct cpsw_priv *priv) 1035int cpsw_fill_rx_channels(struct cpsw_priv *priv)
1700{ 1036{
1701 struct cpsw_common *cpsw = priv->cpsw; 1037 struct cpsw_common *cpsw = priv->cpsw;
1702 struct sk_buff *skb; 1038 struct sk_buff *skb;
@@ -1748,7 +1084,8 @@ static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_common *cpsw)
1748 slave->phy = NULL; 1084 slave->phy = NULL;
1749 cpsw_ale_control_set(cpsw->ale, slave_port, 1085 cpsw_ale_control_set(cpsw->ale, slave_port,
1750 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 1086 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
1751 soft_reset_slave(slave); 1087 cpsw_sl_reset(slave->mac_sl, 100);
1088 cpsw_sl_ctl_reset(slave->mac_sl);
1752} 1089}
1753 1090
1754static int cpsw_tc_to_fifo(int tc, int num_tc) 1091static int cpsw_tc_to_fifo(int tc, int num_tc)
@@ -2114,7 +1451,7 @@ static int cpsw_ndo_stop(struct net_device *ndev)
2114 for_each_slave(priv, cpsw_slave_stop, cpsw); 1451 for_each_slave(priv, cpsw_slave_stop, cpsw);
2115 1452
2116 if (cpsw_need_resplit(cpsw)) 1453 if (cpsw_need_resplit(cpsw))
2117 cpsw_split_res(ndev); 1454 cpsw_split_res(cpsw);
2118 1455
2119 cpsw->usage_count--; 1456 cpsw->usage_count--;
2120 pm_runtime_put_sync(cpsw->dev); 1457 pm_runtime_put_sync(cpsw->dev);
@@ -2147,7 +1484,9 @@ static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb,
2147 1484
2148 txch = cpsw->txv[q_idx].ch; 1485 txch = cpsw->txv[q_idx].ch;
2149 txq = netdev_get_tx_queue(ndev, q_idx); 1486 txq = netdev_get_tx_queue(ndev, q_idx);
2150 ret = cpsw_tx_packet_submit(priv, skb, txch); 1487 skb_tx_timestamp(skb);
1488 ret = cpdma_chan_submit(txch, skb, skb->data, skb->len,
1489 priv->emac_port + cpsw->data.dual_emac);
2151 if (unlikely(ret != 0)) { 1490 if (unlikely(ret != 0)) {
2152 cpsw_err(priv, tx_err, "desc submit failed\n"); 1491 cpsw_err(priv, tx_err, "desc submit failed\n");
2153 goto fail; 1492 goto fail;
@@ -2418,18 +1757,6 @@ static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p)
2418 return 0; 1757 return 0;
2419} 1758}
2420 1759
2421#ifdef CONFIG_NET_POLL_CONTROLLER
2422static void cpsw_ndo_poll_controller(struct net_device *ndev)
2423{
2424 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2425
2426 cpsw_intr_disable(cpsw);
2427 cpsw_rx_interrupt(cpsw->irqs_table[0], cpsw);
2428 cpsw_tx_interrupt(cpsw->irqs_table[1], cpsw);
2429 cpsw_intr_enable(cpsw);
2430}
2431#endif
2432
2433static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv, 1760static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv,
2434 unsigned short vid) 1761 unsigned short vid)
2435{ 1762{
@@ -2601,7 +1928,7 @@ static int cpsw_ndo_set_tx_maxrate(struct net_device *ndev, int queue, u32 rate)
2601 netdev_get_tx_queue(slave->ndev, queue)->tx_maxrate = rate; 1928 netdev_get_tx_queue(slave->ndev, queue)->tx_maxrate = rate;
2602 } 1929 }
2603 1930
2604 cpsw_split_res(ndev); 1931 cpsw_split_res(cpsw);
2605 return ret; 1932 return ret;
2606} 1933}
2607 1934
@@ -2695,25 +2022,6 @@ static const struct net_device_ops cpsw_netdev_ops = {
2695 .ndo_setup_tc = cpsw_ndo_setup_tc, 2022 .ndo_setup_tc = cpsw_ndo_setup_tc,
2696}; 2023};
2697 2024
2698static int cpsw_get_regs_len(struct net_device *ndev)
2699{
2700 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2701
2702 return cpsw->data.ale_entries * ALE_ENTRY_WORDS * sizeof(u32);
2703}
2704
2705static void cpsw_get_regs(struct net_device *ndev,
2706 struct ethtool_regs *regs, void *p)
2707{
2708 u32 *reg = p;
2709 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2710
2711 /* update CPSW IP version */
2712 regs->version = cpsw->version;
2713
2714 cpsw_ale_dump(cpsw->ale, reg);
2715}
2716
2717static void cpsw_get_drvinfo(struct net_device *ndev, 2025static void cpsw_get_drvinfo(struct net_device *ndev,
2718 struct ethtool_drvinfo *info) 2026 struct ethtool_drvinfo *info)
2719{ 2027{
@@ -2725,119 +2033,6 @@ static void cpsw_get_drvinfo(struct net_device *ndev,
2725 strlcpy(info->bus_info, pdev->name, sizeof(info->bus_info)); 2033 strlcpy(info->bus_info, pdev->name, sizeof(info->bus_info));
2726} 2034}
2727 2035
2728static u32 cpsw_get_msglevel(struct net_device *ndev)
2729{
2730 struct cpsw_priv *priv = netdev_priv(ndev);
2731 return priv->msg_enable;
2732}
2733
2734static void cpsw_set_msglevel(struct net_device *ndev, u32 value)
2735{
2736 struct cpsw_priv *priv = netdev_priv(ndev);
2737 priv->msg_enable = value;
2738}
2739
2740#if IS_ENABLED(CONFIG_TI_CPTS)
2741static int cpsw_get_ts_info(struct net_device *ndev,
2742 struct ethtool_ts_info *info)
2743{
2744 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2745
2746 info->so_timestamping =
2747 SOF_TIMESTAMPING_TX_HARDWARE |
2748 SOF_TIMESTAMPING_TX_SOFTWARE |
2749 SOF_TIMESTAMPING_RX_HARDWARE |
2750 SOF_TIMESTAMPING_RX_SOFTWARE |
2751 SOF_TIMESTAMPING_SOFTWARE |
2752 SOF_TIMESTAMPING_RAW_HARDWARE;
2753 info->phc_index = cpsw->cpts->phc_index;
2754 info->tx_types =
2755 (1 << HWTSTAMP_TX_OFF) |
2756 (1 << HWTSTAMP_TX_ON);
2757 info->rx_filters =
2758 (1 << HWTSTAMP_FILTER_NONE) |
2759 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
2760 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
2761 return 0;
2762}
2763#else
2764static int cpsw_get_ts_info(struct net_device *ndev,
2765 struct ethtool_ts_info *info)
2766{
2767 info->so_timestamping =
2768 SOF_TIMESTAMPING_TX_SOFTWARE |
2769 SOF_TIMESTAMPING_RX_SOFTWARE |
2770 SOF_TIMESTAMPING_SOFTWARE;
2771 info->phc_index = -1;
2772 info->tx_types = 0;
2773 info->rx_filters = 0;
2774 return 0;
2775}
2776#endif
2777
2778static int cpsw_get_link_ksettings(struct net_device *ndev,
2779 struct ethtool_link_ksettings *ecmd)
2780{
2781 struct cpsw_priv *priv = netdev_priv(ndev);
2782 struct cpsw_common *cpsw = priv->cpsw;
2783 int slave_no = cpsw_slave_index(cpsw, priv);
2784
2785 if (!cpsw->slaves[slave_no].phy)
2786 return -EOPNOTSUPP;
2787
2788 phy_ethtool_ksettings_get(cpsw->slaves[slave_no].phy, ecmd);
2789 return 0;
2790}
2791
2792static int cpsw_set_link_ksettings(struct net_device *ndev,
2793 const struct ethtool_link_ksettings *ecmd)
2794{
2795 struct cpsw_priv *priv = netdev_priv(ndev);
2796 struct cpsw_common *cpsw = priv->cpsw;
2797 int slave_no = cpsw_slave_index(cpsw, priv);
2798
2799 if (cpsw->slaves[slave_no].phy)
2800 return phy_ethtool_ksettings_set(cpsw->slaves[slave_no].phy,
2801 ecmd);
2802 else
2803 return -EOPNOTSUPP;
2804}
2805
2806static void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2807{
2808 struct cpsw_priv *priv = netdev_priv(ndev);
2809 struct cpsw_common *cpsw = priv->cpsw;
2810 int slave_no = cpsw_slave_index(cpsw, priv);
2811
2812 wol->supported = 0;
2813 wol->wolopts = 0;
2814
2815 if (cpsw->slaves[slave_no].phy)
2816 phy_ethtool_get_wol(cpsw->slaves[slave_no].phy, wol);
2817}
2818
2819static int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2820{
2821 struct cpsw_priv *priv = netdev_priv(ndev);
2822 struct cpsw_common *cpsw = priv->cpsw;
2823 int slave_no = cpsw_slave_index(cpsw, priv);
2824
2825 if (cpsw->slaves[slave_no].phy)
2826 return phy_ethtool_set_wol(cpsw->slaves[slave_no].phy, wol);
2827 else
2828 return -EOPNOTSUPP;
2829}
2830
2831static void cpsw_get_pauseparam(struct net_device *ndev,
2832 struct ethtool_pauseparam *pause)
2833{
2834 struct cpsw_priv *priv = netdev_priv(ndev);
2835
2836 pause->autoneg = AUTONEG_DISABLE;
2837 pause->rx_pause = priv->rx_pause ? true : false;
2838 pause->tx_pause = priv->tx_pause ? true : false;
2839}
2840
2841static int cpsw_set_pauseparam(struct net_device *ndev, 2036static int cpsw_set_pauseparam(struct net_device *ndev,
2842 struct ethtool_pauseparam *pause) 2037 struct ethtool_pauseparam *pause)
2843{ 2038{
@@ -2851,316 +2046,10 @@ static int cpsw_set_pauseparam(struct net_device *ndev,
2851 return 0; 2046 return 0;
2852} 2047}
2853 2048
2854static int cpsw_ethtool_op_begin(struct net_device *ndev)
2855{
2856 struct cpsw_priv *priv = netdev_priv(ndev);
2857 struct cpsw_common *cpsw = priv->cpsw;
2858 int ret;
2859
2860 ret = pm_runtime_get_sync(cpsw->dev);
2861 if (ret < 0) {
2862 cpsw_err(priv, drv, "ethtool begin failed %d\n", ret);
2863 pm_runtime_put_noidle(cpsw->dev);
2864 }
2865
2866 return ret;
2867}
2868
2869static void cpsw_ethtool_op_complete(struct net_device *ndev)
2870{
2871 struct cpsw_priv *priv = netdev_priv(ndev);
2872 int ret;
2873
2874 ret = pm_runtime_put(priv->cpsw->dev);
2875 if (ret < 0)
2876 cpsw_err(priv, drv, "ethtool complete failed %d\n", ret);
2877}
2878
2879static void cpsw_get_channels(struct net_device *ndev,
2880 struct ethtool_channels *ch)
2881{
2882 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2883
2884 ch->max_rx = cpsw->quirk_irq ? 1 : CPSW_MAX_QUEUES;
2885 ch->max_tx = cpsw->quirk_irq ? 1 : CPSW_MAX_QUEUES;
2886 ch->max_combined = 0;
2887 ch->max_other = 0;
2888 ch->other_count = 0;
2889 ch->rx_count = cpsw->rx_ch_num;
2890 ch->tx_count = cpsw->tx_ch_num;
2891 ch->combined_count = 0;
2892}
2893
2894static int cpsw_check_ch_settings(struct cpsw_common *cpsw,
2895 struct ethtool_channels *ch)
2896{
2897 if (cpsw->quirk_irq) {
2898 dev_err(cpsw->dev, "Maximum one tx/rx queue is allowed");
2899 return -EOPNOTSUPP;
2900 }
2901
2902 if (ch->combined_count)
2903 return -EINVAL;
2904
2905 /* verify we have at least one channel in each direction */
2906 if (!ch->rx_count || !ch->tx_count)
2907 return -EINVAL;
2908
2909 if (ch->rx_count > cpsw->data.channels ||
2910 ch->tx_count > cpsw->data.channels)
2911 return -EINVAL;
2912
2913 return 0;
2914}
2915
2916static int cpsw_update_channels_res(struct cpsw_priv *priv, int ch_num, int rx)
2917{
2918 struct cpsw_common *cpsw = priv->cpsw;
2919 void (*handler)(void *, int, int);
2920 struct netdev_queue *queue;
2921 struct cpsw_vector *vec;
2922 int ret, *ch, vch;
2923
2924 if (rx) {
2925 ch = &cpsw->rx_ch_num;
2926 vec = cpsw->rxv;
2927 handler = cpsw_rx_handler;
2928 } else {
2929 ch = &cpsw->tx_ch_num;
2930 vec = cpsw->txv;
2931 handler = cpsw_tx_handler;
2932 }
2933
2934 while (*ch < ch_num) {
2935 vch = rx ? *ch : 7 - *ch;
2936 vec[*ch].ch = cpdma_chan_create(cpsw->dma, vch, handler, rx);
2937 queue = netdev_get_tx_queue(priv->ndev, *ch);
2938 queue->tx_maxrate = 0;
2939
2940 if (IS_ERR(vec[*ch].ch))
2941 return PTR_ERR(vec[*ch].ch);
2942
2943 if (!vec[*ch].ch)
2944 return -EINVAL;
2945
2946 cpsw_info(priv, ifup, "created new %d %s channel\n", *ch,
2947 (rx ? "rx" : "tx"));
2948 (*ch)++;
2949 }
2950
2951 while (*ch > ch_num) {
2952 (*ch)--;
2953
2954 ret = cpdma_chan_destroy(vec[*ch].ch);
2955 if (ret)
2956 return ret;
2957
2958 cpsw_info(priv, ifup, "destroyed %d %s channel\n", *ch,
2959 (rx ? "rx" : "tx"));
2960 }
2961
2962 return 0;
2963}
2964
2965static int cpsw_update_channels(struct cpsw_priv *priv,
2966 struct ethtool_channels *ch)
2967{
2968 int ret;
2969
2970 ret = cpsw_update_channels_res(priv, ch->rx_count, 1);
2971 if (ret)
2972 return ret;
2973
2974 ret = cpsw_update_channels_res(priv, ch->tx_count, 0);
2975 if (ret)
2976 return ret;
2977
2978 return 0;
2979}
2980
2981static void cpsw_suspend_data_pass(struct net_device *ndev)
2982{
2983 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2984 struct cpsw_slave *slave;
2985 int i;
2986
2987 /* Disable NAPI scheduling */
2988 cpsw_intr_disable(cpsw);
2989
2990 /* Stop all transmit queues for every network device.
2991 * Disable re-using rx descriptors with dormant_on.
2992 */
2993 for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++) {
2994 if (!(slave->ndev && netif_running(slave->ndev)))
2995 continue;
2996
2997 netif_tx_stop_all_queues(slave->ndev);
2998 netif_dormant_on(slave->ndev);
2999 }
3000
3001 /* Handle rest of tx packets and stop cpdma channels */
3002 cpdma_ctlr_stop(cpsw->dma);
3003}
3004
3005static int cpsw_resume_data_pass(struct net_device *ndev)
3006{
3007 struct cpsw_priv *priv = netdev_priv(ndev);
3008 struct cpsw_common *cpsw = priv->cpsw;
3009 struct cpsw_slave *slave;
3010 int i, ret;
3011
3012 /* Allow rx packets handling */
3013 for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++)
3014 if (slave->ndev && netif_running(slave->ndev))
3015 netif_dormant_off(slave->ndev);
3016
3017 /* After this receive is started */
3018 if (cpsw->usage_count) {
3019 ret = cpsw_fill_rx_channels(priv);
3020 if (ret)
3021 return ret;
3022
3023 cpdma_ctlr_start(cpsw->dma);
3024 cpsw_intr_enable(cpsw);
3025 }
3026
3027 /* Resume transmit for every affected interface */
3028 for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++)
3029 if (slave->ndev && netif_running(slave->ndev))
3030 netif_tx_start_all_queues(slave->ndev);
3031
3032 return 0;
3033}
3034
3035static int cpsw_set_channels(struct net_device *ndev, 2049static int cpsw_set_channels(struct net_device *ndev,
3036 struct ethtool_channels *chs) 2050 struct ethtool_channels *chs)
3037{ 2051{
3038 struct cpsw_priv *priv = netdev_priv(ndev); 2052 return cpsw_set_channels_common(ndev, chs, cpsw_rx_handler);
3039 struct cpsw_common *cpsw = priv->cpsw;
3040 struct cpsw_slave *slave;
3041 int i, ret;
3042
3043 ret = cpsw_check_ch_settings(cpsw, chs);
3044 if (ret < 0)
3045 return ret;
3046
3047 cpsw_suspend_data_pass(ndev);
3048 ret = cpsw_update_channels(priv, chs);
3049 if (ret)
3050 goto err;
3051
3052 for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++) {
3053 if (!(slave->ndev && netif_running(slave->ndev)))
3054 continue;
3055
3056 /* Inform stack about new count of queues */
3057 ret = netif_set_real_num_tx_queues(slave->ndev,
3058 cpsw->tx_ch_num);
3059 if (ret) {
3060 dev_err(priv->dev, "cannot set real number of tx queues\n");
3061 goto err;
3062 }
3063
3064 ret = netif_set_real_num_rx_queues(slave->ndev,
3065 cpsw->rx_ch_num);
3066 if (ret) {
3067 dev_err(priv->dev, "cannot set real number of rx queues\n");
3068 goto err;
3069 }
3070 }
3071
3072 if (cpsw->usage_count)
3073 cpsw_split_res(ndev);
3074
3075 ret = cpsw_resume_data_pass(ndev);
3076 if (!ret)
3077 return 0;
3078err:
3079 dev_err(priv->dev, "cannot update channels number, closing device\n");
3080 dev_close(ndev);
3081 return ret;
3082}
3083
3084static int cpsw_get_eee(struct net_device *ndev, struct ethtool_eee *edata)
3085{
3086 struct cpsw_priv *priv = netdev_priv(ndev);
3087 struct cpsw_common *cpsw = priv->cpsw;
3088 int slave_no = cpsw_slave_index(cpsw, priv);
3089
3090 if (cpsw->slaves[slave_no].phy)
3091 return phy_ethtool_get_eee(cpsw->slaves[slave_no].phy, edata);
3092 else
3093 return -EOPNOTSUPP;
3094}
3095
3096static int cpsw_set_eee(struct net_device *ndev, struct ethtool_eee *edata)
3097{
3098 struct cpsw_priv *priv = netdev_priv(ndev);
3099 struct cpsw_common *cpsw = priv->cpsw;
3100 int slave_no = cpsw_slave_index(cpsw, priv);
3101
3102 if (cpsw->slaves[slave_no].phy)
3103 return phy_ethtool_set_eee(cpsw->slaves[slave_no].phy, edata);
3104 else
3105 return -EOPNOTSUPP;
3106}
3107
3108static int cpsw_nway_reset(struct net_device *ndev)
3109{
3110 struct cpsw_priv *priv = netdev_priv(ndev);
3111 struct cpsw_common *cpsw = priv->cpsw;
3112 int slave_no = cpsw_slave_index(cpsw, priv);
3113
3114 if (cpsw->slaves[slave_no].phy)
3115 return genphy_restart_aneg(cpsw->slaves[slave_no].phy);
3116 else
3117 return -EOPNOTSUPP;
3118}
3119
3120static void cpsw_get_ringparam(struct net_device *ndev,
3121 struct ethtool_ringparam *ering)
3122{
3123 struct cpsw_priv *priv = netdev_priv(ndev);
3124 struct cpsw_common *cpsw = priv->cpsw;
3125
3126 /* not supported */
3127 ering->tx_max_pending = 0;
3128 ering->tx_pending = cpdma_get_num_tx_descs(cpsw->dma);
3129 ering->rx_max_pending = descs_pool_size - CPSW_MAX_QUEUES;
3130 ering->rx_pending = cpdma_get_num_rx_descs(cpsw->dma);
3131}
3132
3133static int cpsw_set_ringparam(struct net_device *ndev,
3134 struct ethtool_ringparam *ering)
3135{
3136 struct cpsw_priv *priv = netdev_priv(ndev);
3137 struct cpsw_common *cpsw = priv->cpsw;
3138 int ret;
3139
3140 /* ignore ering->tx_pending - only rx_pending adjustment is supported */
3141
3142 if (ering->rx_mini_pending || ering->rx_jumbo_pending ||
3143 ering->rx_pending < CPSW_MAX_QUEUES ||
3144 ering->rx_pending > (descs_pool_size - CPSW_MAX_QUEUES))
3145 return -EINVAL;
3146
3147 if (ering->rx_pending == cpdma_get_num_rx_descs(cpsw->dma))
3148 return 0;
3149
3150 cpsw_suspend_data_pass(ndev);
3151
3152 cpdma_set_num_rx_descs(cpsw->dma, ering->rx_pending);
3153
3154 if (cpsw->usage_count)
3155 cpdma_chan_split_pool(cpsw->dma);
3156
3157 ret = cpsw_resume_data_pass(ndev);
3158 if (!ret)
3159 return 0;
3160
3161 dev_err(&ndev->dev, "cannot set ring params, closing device\n");
3162 dev_close(ndev);
3163 return ret;
3164} 2053}
3165 2054
3166static const struct ethtool_ops cpsw_ethtool_ops = { 2055static const struct ethtool_ops cpsw_ethtool_ops = {
@@ -3193,19 +2082,6 @@ static const struct ethtool_ops cpsw_ethtool_ops = {
3193 .set_ringparam = cpsw_set_ringparam, 2082 .set_ringparam = cpsw_set_ringparam,
3194}; 2083};
3195 2084
3196static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_common *cpsw,
3197 u32 slave_reg_ofs, u32 sliver_reg_ofs)
3198{
3199 void __iomem *regs = cpsw->regs;
3200 int slave_num = slave->slave_num;
3201 struct cpsw_slave_data *data = cpsw->data.slave_data + slave_num;
3202
3203 slave->data = data;
3204 slave->regs = regs + slave_reg_ofs;
3205 slave->sliver = regs + sliver_reg_ofs;
3206 slave->port_vlan = data->dual_emac_res_vlan;
3207}
3208
3209static int cpsw_probe_dt(struct cpsw_platform_data *data, 2085static int cpsw_probe_dt(struct cpsw_platform_data *data,
3210 struct platform_device *pdev) 2086 struct platform_device *pdev)
3211{ 2087{
@@ -3408,7 +2284,8 @@ static int cpsw_probe_dual_emac(struct cpsw_priv *priv)
3408 struct cpsw_priv *priv_sl2; 2284 struct cpsw_priv *priv_sl2;
3409 int ret = 0; 2285 int ret = 0;
3410 2286
3411 ndev = alloc_etherdev_mq(sizeof(struct cpsw_priv), CPSW_MAX_QUEUES); 2287 ndev = devm_alloc_etherdev_mqs(cpsw->dev, sizeof(struct cpsw_priv),
2288 CPSW_MAX_QUEUES, CPSW_MAX_QUEUES);
3412 if (!ndev) { 2289 if (!ndev) {
3413 dev_err(cpsw->dev, "cpsw: error allocating net_device\n"); 2290 dev_err(cpsw->dev, "cpsw: error allocating net_device\n");
3414 return -ENOMEM; 2291 return -ENOMEM;
@@ -3442,11 +2319,8 @@ static int cpsw_probe_dual_emac(struct cpsw_priv *priv)
3442 /* register the network device */ 2319 /* register the network device */
3443 SET_NETDEV_DEV(ndev, cpsw->dev); 2320 SET_NETDEV_DEV(ndev, cpsw->dev);
3444 ret = register_netdev(ndev); 2321 ret = register_netdev(ndev);
3445 if (ret) { 2322 if (ret)
3446 dev_err(cpsw->dev, "cpsw: error registering net device\n"); 2323 dev_err(cpsw->dev, "cpsw: error registering net device\n");
3447 free_netdev(ndev);
3448 ret = -ENODEV;
3449 }
3450 2324
3451 return ret; 2325 return ret;
3452} 2326}
@@ -3467,63 +2341,74 @@ static const struct soc_device_attribute cpsw_soc_devices[] = {
3467 2341
3468static int cpsw_probe(struct platform_device *pdev) 2342static int cpsw_probe(struct platform_device *pdev)
3469{ 2343{
2344 struct device *dev = &pdev->dev;
3470 struct clk *clk; 2345 struct clk *clk;
3471 struct cpsw_platform_data *data; 2346 struct cpsw_platform_data *data;
3472 struct net_device *ndev; 2347 struct net_device *ndev;
3473 struct cpsw_priv *priv; 2348 struct cpsw_priv *priv;
3474 struct cpdma_params dma_params;
3475 struct cpsw_ale_params ale_params;
3476 void __iomem *ss_regs; 2349 void __iomem *ss_regs;
3477 void __iomem *cpts_regs;
3478 struct resource *res, *ss_res; 2350 struct resource *res, *ss_res;
3479 struct gpio_descs *mode; 2351 struct gpio_descs *mode;
3480 u32 slave_offset, sliver_offset, slave_size;
3481 const struct soc_device_attribute *soc; 2352 const struct soc_device_attribute *soc;
3482 struct cpsw_common *cpsw; 2353 struct cpsw_common *cpsw;
3483 int ret = 0, i, ch; 2354 int ret = 0, ch;
3484 int irq; 2355 int irq;
3485 2356
3486 cpsw = devm_kzalloc(&pdev->dev, sizeof(struct cpsw_common), GFP_KERNEL); 2357 cpsw = devm_kzalloc(dev, sizeof(struct cpsw_common), GFP_KERNEL);
3487 if (!cpsw) 2358 if (!cpsw)
3488 return -ENOMEM; 2359 return -ENOMEM;
3489 2360
3490 cpsw->dev = &pdev->dev; 2361 cpsw->dev = dev;
3491 2362
3492 ndev = alloc_etherdev_mq(sizeof(struct cpsw_priv), CPSW_MAX_QUEUES); 2363 mode = devm_gpiod_get_array_optional(dev, "mode", GPIOD_OUT_LOW);
3493 if (!ndev) { 2364 if (IS_ERR(mode)) {
3494 dev_err(&pdev->dev, "error allocating net_device\n"); 2365 ret = PTR_ERR(mode);
3495 return -ENOMEM; 2366 dev_err(dev, "gpio request failed, ret %d\n", ret);
2367 return ret;
3496 } 2368 }
3497 2369
3498 platform_set_drvdata(pdev, ndev); 2370 clk = devm_clk_get(dev, "fck");
3499 priv = netdev_priv(ndev); 2371 if (IS_ERR(clk)) {
3500 priv->cpsw = cpsw;
3501 priv->ndev = ndev;
3502 priv->dev = &ndev->dev;
3503 priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
3504 cpsw->rx_packet_max = max(rx_packet_max, 128);
3505
3506 mode = devm_gpiod_get_array_optional(&pdev->dev, "mode", GPIOD_OUT_LOW);
3507 if (IS_ERR(mode)) {
3508 ret = PTR_ERR(mode); 2372 ret = PTR_ERR(mode);
3509 dev_err(&pdev->dev, "gpio request failed, ret %d\n", ret); 2373 dev_err(dev, "fck is not found %d\n", ret);
3510 goto clean_ndev_ret; 2374 return ret;
3511 } 2375 }
2376 cpsw->bus_freq_mhz = clk_get_rate(clk) / 1000000;
2377
2378 ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2379 ss_regs = devm_ioremap_resource(dev, ss_res);
2380 if (IS_ERR(ss_regs))
2381 return PTR_ERR(ss_regs);
2382 cpsw->regs = ss_regs;
2383
2384 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2385 cpsw->wr_regs = devm_ioremap_resource(dev, res);
2386 if (IS_ERR(cpsw->wr_regs))
2387 return PTR_ERR(cpsw->wr_regs);
2388
2389 /* RX IRQ */
2390 irq = platform_get_irq(pdev, 1);
2391 if (irq < 0)
2392 return irq;
2393 cpsw->irqs_table[0] = irq;
2394
2395 /* TX IRQ */
2396 irq = platform_get_irq(pdev, 2);
2397 if (irq < 0)
2398 return irq;
2399 cpsw->irqs_table[1] = irq;
3512 2400
3513 /* 2401 /*
3514 * This may be required here for child devices. 2402 * This may be required here for child devices.
3515 */ 2403 */
3516 pm_runtime_enable(&pdev->dev); 2404 pm_runtime_enable(dev);
3517
3518 /* Select default pin state */
3519 pinctrl_pm_select_default_state(&pdev->dev);
3520 2405
3521 /* Need to enable clocks with runtime PM api to access module 2406 /* Need to enable clocks with runtime PM api to access module
3522 * registers 2407 * registers
3523 */ 2408 */
3524 ret = pm_runtime_get_sync(&pdev->dev); 2409 ret = pm_runtime_get_sync(dev);
3525 if (ret < 0) { 2410 if (ret < 0) {
3526 pm_runtime_put_noidle(&pdev->dev); 2411 pm_runtime_put_noidle(dev);
3527 goto clean_runtime_disable_ret; 2412 goto clean_runtime_disable_ret;
3528 } 2413 }
3529 2414
@@ -3531,170 +2416,72 @@ static int cpsw_probe(struct platform_device *pdev)
3531 if (ret) 2416 if (ret)
3532 goto clean_dt_ret; 2417 goto clean_dt_ret;
3533 2418
3534 data = &cpsw->data; 2419 soc = soc_device_match(cpsw_soc_devices);
3535 cpsw->rx_ch_num = 1; 2420 if (soc)
3536 cpsw->tx_ch_num = 1; 2421 cpsw->quirk_irq = 1;
3537
3538 if (is_valid_ether_addr(data->slave_data[0].mac_addr)) {
3539 memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN);
3540 dev_info(&pdev->dev, "Detected MACID = %pM\n", priv->mac_addr);
3541 } else {
3542 eth_random_addr(priv->mac_addr);
3543 dev_info(&pdev->dev, "Random MACID = %pM\n", priv->mac_addr);
3544 }
3545
3546 memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
3547 2422
3548 cpsw->slaves = devm_kcalloc(&pdev->dev, 2423 data = &cpsw->data;
2424 cpsw->slaves = devm_kcalloc(dev,
3549 data->slaves, sizeof(struct cpsw_slave), 2425 data->slaves, sizeof(struct cpsw_slave),
3550 GFP_KERNEL); 2426 GFP_KERNEL);
3551 if (!cpsw->slaves) { 2427 if (!cpsw->slaves) {
3552 ret = -ENOMEM; 2428 ret = -ENOMEM;
3553 goto clean_dt_ret; 2429 goto clean_dt_ret;
3554 } 2430 }
3555 for (i = 0; i < data->slaves; i++)
3556 cpsw->slaves[i].slave_num = i;
3557
3558 cpsw->slaves[0].ndev = ndev;
3559 priv->emac_port = 0;
3560
3561 clk = devm_clk_get(&pdev->dev, "fck");
3562 if (IS_ERR(clk)) {
3563 dev_err(priv->dev, "fck is not found\n");
3564 ret = -ENODEV;
3565 goto clean_dt_ret;
3566 }
3567 cpsw->bus_freq_mhz = clk_get_rate(clk) / 1000000;
3568 2431
3569 ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2432 cpsw->rx_packet_max = max(rx_packet_max, CPSW_MAX_PACKET_SIZE);
3570 ss_regs = devm_ioremap_resource(&pdev->dev, ss_res); 2433 cpsw->descs_pool_size = descs_pool_size;
3571 if (IS_ERR(ss_regs)) {
3572 ret = PTR_ERR(ss_regs);
3573 goto clean_dt_ret;
3574 }
3575 cpsw->regs = ss_regs;
3576 2434
3577 cpsw->version = readl(&cpsw->regs->id_ver); 2435 ret = cpsw_init_common(cpsw, ss_regs, ale_ageout,
3578 2436 ss_res->start + CPSW2_BD_OFFSET,
3579 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 2437 descs_pool_size);
3580 cpsw->wr_regs = devm_ioremap_resource(&pdev->dev, res); 2438 if (ret)
3581 if (IS_ERR(cpsw->wr_regs)) {
3582 ret = PTR_ERR(cpsw->wr_regs);
3583 goto clean_dt_ret;
3584 }
3585
3586 memset(&dma_params, 0, sizeof(dma_params));
3587 memset(&ale_params, 0, sizeof(ale_params));
3588
3589 switch (cpsw->version) {
3590 case CPSW_VERSION_1:
3591 cpsw->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET;
3592 cpts_regs = ss_regs + CPSW1_CPTS_OFFSET;
3593 cpsw->hw_stats = ss_regs + CPSW1_HW_STATS;
3594 dma_params.dmaregs = ss_regs + CPSW1_CPDMA_OFFSET;
3595 dma_params.txhdp = ss_regs + CPSW1_STATERAM_OFFSET;
3596 ale_params.ale_regs = ss_regs + CPSW1_ALE_OFFSET;
3597 slave_offset = CPSW1_SLAVE_OFFSET;
3598 slave_size = CPSW1_SLAVE_SIZE;
3599 sliver_offset = CPSW1_SLIVER_OFFSET;
3600 dma_params.desc_mem_phys = 0;
3601 break;
3602 case CPSW_VERSION_2:
3603 case CPSW_VERSION_3:
3604 case CPSW_VERSION_4:
3605 cpsw->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET;
3606 cpts_regs = ss_regs + CPSW2_CPTS_OFFSET;
3607 cpsw->hw_stats = ss_regs + CPSW2_HW_STATS;
3608 dma_params.dmaregs = ss_regs + CPSW2_CPDMA_OFFSET;
3609 dma_params.txhdp = ss_regs + CPSW2_STATERAM_OFFSET;
3610 ale_params.ale_regs = ss_regs + CPSW2_ALE_OFFSET;
3611 slave_offset = CPSW2_SLAVE_OFFSET;
3612 slave_size = CPSW2_SLAVE_SIZE;
3613 sliver_offset = CPSW2_SLIVER_OFFSET;
3614 dma_params.desc_mem_phys =
3615 (u32 __force) ss_res->start + CPSW2_BD_OFFSET;
3616 break;
3617 default:
3618 dev_err(priv->dev, "unknown version 0x%08x\n", cpsw->version);
3619 ret = -ENODEV;
3620 goto clean_dt_ret;
3621 }
3622 for (i = 0; i < cpsw->data.slaves; i++) {
3623 struct cpsw_slave *slave = &cpsw->slaves[i];
3624
3625 cpsw_slave_init(slave, cpsw, slave_offset, sliver_offset);
3626 slave_offset += slave_size;
3627 sliver_offset += SLIVER_SIZE;
3628 }
3629
3630 dma_params.dev = &pdev->dev;
3631 dma_params.rxthresh = dma_params.dmaregs + CPDMA_RXTHRESH;
3632 dma_params.rxfree = dma_params.dmaregs + CPDMA_RXFREE;
3633 dma_params.rxhdp = dma_params.txhdp + CPDMA_RXHDP;
3634 dma_params.txcp = dma_params.txhdp + CPDMA_TXCP;
3635 dma_params.rxcp = dma_params.txhdp + CPDMA_RXCP;
3636
3637 dma_params.num_chan = data->channels;
3638 dma_params.has_soft_reset = true;
3639 dma_params.min_packet_size = CPSW_MIN_PACKET_SIZE;
3640 dma_params.desc_mem_size = data->bd_ram_size;
3641 dma_params.desc_align = 16;
3642 dma_params.has_ext_regs = true;
3643 dma_params.desc_hw_addr = dma_params.desc_mem_phys;
3644 dma_params.bus_freq_mhz = cpsw->bus_freq_mhz;
3645 dma_params.descs_pool_size = descs_pool_size;
3646
3647 cpsw->dma = cpdma_ctlr_create(&dma_params);
3648 if (!cpsw->dma) {
3649 dev_err(priv->dev, "error initializing dma\n");
3650 ret = -ENOMEM;
3651 goto clean_dt_ret; 2439 goto clean_dt_ret;
3652 }
3653
3654 soc = soc_device_match(cpsw_soc_devices);
3655 if (soc)
3656 cpsw->quirk_irq = 1;
3657 2440
3658 ch = cpsw->quirk_irq ? 0 : 7; 2441 ch = cpsw->quirk_irq ? 0 : 7;
3659 cpsw->txv[0].ch = cpdma_chan_create(cpsw->dma, ch, cpsw_tx_handler, 0); 2442 cpsw->txv[0].ch = cpdma_chan_create(cpsw->dma, ch, cpsw_tx_handler, 0);
3660 if (IS_ERR(cpsw->txv[0].ch)) { 2443 if (IS_ERR(cpsw->txv[0].ch)) {
3661 dev_err(priv->dev, "error initializing tx dma channel\n"); 2444 dev_err(dev, "error initializing tx dma channel\n");
3662 ret = PTR_ERR(cpsw->txv[0].ch); 2445 ret = PTR_ERR(cpsw->txv[0].ch);
3663 goto clean_dma_ret; 2446 goto clean_cpts;
3664 } 2447 }
3665 2448
3666 cpsw->rxv[0].ch = cpdma_chan_create(cpsw->dma, 0, cpsw_rx_handler, 1); 2449 cpsw->rxv[0].ch = cpdma_chan_create(cpsw->dma, 0, cpsw_rx_handler, 1);
3667 if (IS_ERR(cpsw->rxv[0].ch)) { 2450 if (IS_ERR(cpsw->rxv[0].ch)) {
3668 dev_err(priv->dev, "error initializing rx dma channel\n"); 2451 dev_err(dev, "error initializing rx dma channel\n");
3669 ret = PTR_ERR(cpsw->rxv[0].ch); 2452 ret = PTR_ERR(cpsw->rxv[0].ch);
3670 goto clean_dma_ret; 2453 goto clean_cpts;
3671 } 2454 }
2455 cpsw_split_res(cpsw);
3672 2456
3673 ale_params.dev = &pdev->dev; 2457 /* setup netdev */
3674 ale_params.ale_ageout = ale_ageout; 2458 ndev = devm_alloc_etherdev_mqs(dev, sizeof(struct cpsw_priv),
3675 ale_params.ale_entries = data->ale_entries; 2459 CPSW_MAX_QUEUES, CPSW_MAX_QUEUES);
3676 ale_params.ale_ports = CPSW_ALE_PORTS_NUM; 2460 if (!ndev) {
3677 2461 dev_err(dev, "error allocating net_device\n");
3678 cpsw->ale = cpsw_ale_create(&ale_params); 2462 goto clean_cpts;
3679 if (!cpsw->ale) {
3680 dev_err(priv->dev, "error initializing ale engine\n");
3681 ret = -ENODEV;
3682 goto clean_dma_ret;
3683 } 2463 }
3684 2464
3685 cpsw->cpts = cpts_create(cpsw->dev, cpts_regs, cpsw->dev->of_node); 2465 platform_set_drvdata(pdev, ndev);
3686 if (IS_ERR(cpsw->cpts)) { 2466 priv = netdev_priv(ndev);
3687 ret = PTR_ERR(cpsw->cpts); 2467 priv->cpsw = cpsw;
3688 goto clean_dma_ret; 2468 priv->ndev = ndev;
3689 } 2469 priv->dev = dev;
2470 priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2471 priv->emac_port = 0;
3690 2472
3691 ndev->irq = platform_get_irq(pdev, 1); 2473 if (is_valid_ether_addr(data->slave_data[0].mac_addr)) {
3692 if (ndev->irq < 0) { 2474 memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN);
3693 dev_err(priv->dev, "error getting irq resource\n"); 2475 dev_info(dev, "Detected MACID = %pM\n", priv->mac_addr);
3694 ret = ndev->irq; 2476 } else {
3695 goto clean_dma_ret; 2477 eth_random_addr(priv->mac_addr);
2478 dev_info(dev, "Random MACID = %pM\n", priv->mac_addr);
3696 } 2479 }
3697 2480
2481 memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
2482
2483 cpsw->slaves[0].ndev = ndev;
2484
3698 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_VLAN_CTAG_RX; 2485 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_VLAN_CTAG_RX;
3699 2486
3700 ndev->netdev_ops = &cpsw_netdev_ops; 2487 ndev->netdev_ops = &cpsw_netdev_ops;
@@ -3705,15 +2492,14 @@ static int cpsw_probe(struct platform_device *pdev)
3705 netif_tx_napi_add(ndev, &cpsw->napi_tx, 2492 netif_tx_napi_add(ndev, &cpsw->napi_tx,
3706 cpsw->quirk_irq ? cpsw_tx_poll : cpsw_tx_mq_poll, 2493 cpsw->quirk_irq ? cpsw_tx_poll : cpsw_tx_mq_poll,
3707 CPSW_POLL_WEIGHT); 2494 CPSW_POLL_WEIGHT);
3708 cpsw_split_res(ndev);
3709 2495
3710 /* register the network device */ 2496 /* register the network device */
3711 SET_NETDEV_DEV(ndev, &pdev->dev); 2497 SET_NETDEV_DEV(ndev, dev);
3712 ret = register_netdev(ndev); 2498 ret = register_netdev(ndev);
3713 if (ret) { 2499 if (ret) {
3714 dev_err(priv->dev, "error registering net device\n"); 2500 dev_err(dev, "error registering net device\n");
3715 ret = -ENODEV; 2501 ret = -ENODEV;
3716 goto clean_dma_ret; 2502 goto clean_cpts;
3717 } 2503 }
3718 2504
3719 if (cpsw->data.dual_emac) { 2505 if (cpsw->data.dual_emac) {
@@ -3731,40 +2517,24 @@ static int cpsw_probe(struct platform_device *pdev)
3731 * If anyone wants to implement support for those, make sure to 2517 * If anyone wants to implement support for those, make sure to
3732 * first request and append them to irqs_table array. 2518 * first request and append them to irqs_table array.
3733 */ 2519 */
3734 2520 ret = devm_request_irq(dev, cpsw->irqs_table[0], cpsw_rx_interrupt,
3735 /* RX IRQ */ 2521 0, dev_name(dev), cpsw);
3736 irq = platform_get_irq(pdev, 1);
3737 if (irq < 0) {
3738 ret = irq;
3739 goto clean_dma_ret;
3740 }
3741
3742 cpsw->irqs_table[0] = irq;
3743 ret = devm_request_irq(&pdev->dev, irq, cpsw_rx_interrupt,
3744 0, dev_name(&pdev->dev), cpsw);
3745 if (ret < 0) { 2522 if (ret < 0) {
3746 dev_err(priv->dev, "error attaching irq (%d)\n", ret); 2523 dev_err(dev, "error attaching irq (%d)\n", ret);
3747 goto clean_dma_ret; 2524 goto clean_unregister_netdev_ret;
3748 } 2525 }
3749 2526
3750 /* TX IRQ */
3751 irq = platform_get_irq(pdev, 2);
3752 if (irq < 0) {
3753 ret = irq;
3754 goto clean_dma_ret;
3755 }
3756 2527
3757 cpsw->irqs_table[1] = irq; 2528 ret = devm_request_irq(dev, cpsw->irqs_table[1], cpsw_tx_interrupt,
3758 ret = devm_request_irq(&pdev->dev, irq, cpsw_tx_interrupt,
3759 0, dev_name(&pdev->dev), cpsw); 2529 0, dev_name(&pdev->dev), cpsw);
3760 if (ret < 0) { 2530 if (ret < 0) {
3761 dev_err(priv->dev, "error attaching irq (%d)\n", ret); 2531 dev_err(dev, "error attaching irq (%d)\n", ret);
3762 goto clean_dma_ret; 2532 goto clean_unregister_netdev_ret;
3763 } 2533 }
3764 2534
3765 cpsw_notice(priv, probe, 2535 cpsw_notice(priv, probe,
3766 "initialized device (regs %pa, irq %d, pool size %d)\n", 2536 "initialized device (regs %pa, irq %d, pool size %d)\n",
3767 &ss_res->start, ndev->irq, dma_params.descs_pool_size); 2537 &ss_res->start, cpsw->irqs_table[0], descs_pool_size);
3768 2538
3769 pm_runtime_put(&pdev->dev); 2539 pm_runtime_put(&pdev->dev);
3770 2540
@@ -3772,15 +2542,14 @@ static int cpsw_probe(struct platform_device *pdev)
3772 2542
3773clean_unregister_netdev_ret: 2543clean_unregister_netdev_ret:
3774 unregister_netdev(ndev); 2544 unregister_netdev(ndev);
3775clean_dma_ret: 2545clean_cpts:
2546 cpts_release(cpsw->cpts);
3776 cpdma_ctlr_destroy(cpsw->dma); 2547 cpdma_ctlr_destroy(cpsw->dma);
3777clean_dt_ret: 2548clean_dt_ret:
3778 cpsw_remove_dt(pdev); 2549 cpsw_remove_dt(pdev);
3779 pm_runtime_put_sync(&pdev->dev); 2550 pm_runtime_put_sync(&pdev->dev);
3780clean_runtime_disable_ret: 2551clean_runtime_disable_ret:
3781 pm_runtime_disable(&pdev->dev); 2552 pm_runtime_disable(&pdev->dev);
3782clean_ndev_ret:
3783 free_netdev(priv->ndev);
3784 return ret; 2553 return ret;
3785} 2554}
3786 2555
@@ -3805,9 +2574,6 @@ static int cpsw_remove(struct platform_device *pdev)
3805 cpsw_remove_dt(pdev); 2574 cpsw_remove_dt(pdev);
3806 pm_runtime_put_sync(&pdev->dev); 2575 pm_runtime_put_sync(&pdev->dev);
3807 pm_runtime_disable(&pdev->dev); 2576 pm_runtime_disable(&pdev->dev);
3808 if (cpsw->data.dual_emac)
3809 free_netdev(cpsw->slaves[1].ndev);
3810 free_netdev(ndev);
3811 return 0; 2577 return 0;
3812} 2578}
3813 2579
diff --git a/drivers/net/ethernet/ti/cpsw.h b/drivers/net/ethernet/ti/cpsw.h
index 907e05fc22e4..35d602f03281 100644
--- a/drivers/net/ethernet/ti/cpsw.h
+++ b/drivers/net/ethernet/ti/cpsw.h
@@ -1,15 +1,8 @@
1/* SPDX-License-Identifier: GPL-2.0 */
1/* Texas Instruments Ethernet Switch Driver 2/* Texas Instruments Ethernet Switch Driver
2 * 3 *
3 * Copyright (C) 2013 Texas Instruments 4 * Copyright (C) 2013 Texas Instruments
4 * 5 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * version 2 as published by the Free Software Foundation.
8 *
9 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
10 * kind, whether express or implied; without even the implied warranty
11 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */ 6 */
14#ifndef __CPSW_H__ 7#ifndef __CPSW_H__
15#define __CPSW_H__ 8#define __CPSW_H__
diff --git a/drivers/net/ethernet/ti/cpsw_ale.c b/drivers/net/ethernet/ti/cpsw_ale.c
index 798c989d5d93..84025dcc78d5 100644
--- a/drivers/net/ethernet/ti/cpsw_ale.c
+++ b/drivers/net/ethernet/ti/cpsw_ale.c
@@ -1,16 +1,9 @@
1// SPDX-License-Identifier: GPL-2.0
1/* 2/*
2 * Texas Instruments N-Port Ethernet Switch Address Lookup Engine 3 * Texas Instruments N-Port Ethernet Switch Address Lookup Engine
3 * 4 *
4 * Copyright (C) 2012 Texas Instruments 5 * Copyright (C) 2012 Texas Instruments
5 * 6 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */ 7 */
15#include <linux/kernel.h> 8#include <linux/kernel.h>
16#include <linux/module.h> 9#include <linux/module.h>
@@ -287,6 +280,9 @@ int cpsw_ale_flush_multicast(struct cpsw_ale *ale, int port_mask, int vid)
287 if (cpsw_ale_get_mcast(ale_entry)) { 280 if (cpsw_ale_get_mcast(ale_entry)) {
288 u8 addr[6]; 281 u8 addr[6];
289 282
283 if (cpsw_ale_get_super(ale_entry))
284 continue;
285
290 cpsw_ale_get_addr(ale_entry, addr); 286 cpsw_ale_get_addr(ale_entry, addr);
291 if (!is_broadcast_ether_addr(addr)) 287 if (!is_broadcast_ether_addr(addr))
292 cpsw_ale_flush_mcast(ale, ale_entry, port_mask); 288 cpsw_ale_flush_mcast(ale, ale_entry, port_mask);
@@ -296,7 +292,6 @@ int cpsw_ale_flush_multicast(struct cpsw_ale *ale, int port_mask, int vid)
296 } 292 }
297 return 0; 293 return 0;
298} 294}
299EXPORT_SYMBOL_GPL(cpsw_ale_flush_multicast);
300 295
301static inline void cpsw_ale_set_vlan_entry_type(u32 *ale_entry, 296static inline void cpsw_ale_set_vlan_entry_type(u32 *ale_entry,
302 int flags, u16 vid) 297 int flags, u16 vid)
@@ -334,7 +329,6 @@ int cpsw_ale_add_ucast(struct cpsw_ale *ale, const u8 *addr, int port,
334 cpsw_ale_write(ale, idx, ale_entry); 329 cpsw_ale_write(ale, idx, ale_entry);
335 return 0; 330 return 0;
336} 331}
337EXPORT_SYMBOL_GPL(cpsw_ale_add_ucast);
338 332
339int cpsw_ale_del_ucast(struct cpsw_ale *ale, const u8 *addr, int port, 333int cpsw_ale_del_ucast(struct cpsw_ale *ale, const u8 *addr, int port,
340 int flags, u16 vid) 334 int flags, u16 vid)
@@ -350,7 +344,6 @@ int cpsw_ale_del_ucast(struct cpsw_ale *ale, const u8 *addr, int port,
350 cpsw_ale_write(ale, idx, ale_entry); 344 cpsw_ale_write(ale, idx, ale_entry);
351 return 0; 345 return 0;
352} 346}
353EXPORT_SYMBOL_GPL(cpsw_ale_del_ucast);
354 347
355int cpsw_ale_add_mcast(struct cpsw_ale *ale, const u8 *addr, int port_mask, 348int cpsw_ale_add_mcast(struct cpsw_ale *ale, const u8 *addr, int port_mask,
356 int flags, u16 vid, int mcast_state) 349 int flags, u16 vid, int mcast_state)
@@ -365,7 +358,7 @@ int cpsw_ale_add_mcast(struct cpsw_ale *ale, const u8 *addr, int port_mask,
365 cpsw_ale_set_vlan_entry_type(ale_entry, flags, vid); 358 cpsw_ale_set_vlan_entry_type(ale_entry, flags, vid);
366 359
367 cpsw_ale_set_addr(ale_entry, addr); 360 cpsw_ale_set_addr(ale_entry, addr);
368 cpsw_ale_set_super(ale_entry, (flags & ALE_BLOCKED) ? 1 : 0); 361 cpsw_ale_set_super(ale_entry, (flags & ALE_SUPER) ? 1 : 0);
369 cpsw_ale_set_mcast_state(ale_entry, mcast_state); 362 cpsw_ale_set_mcast_state(ale_entry, mcast_state);
370 363
371 mask = cpsw_ale_get_port_mask(ale_entry, 364 mask = cpsw_ale_get_port_mask(ale_entry,
@@ -384,7 +377,6 @@ int cpsw_ale_add_mcast(struct cpsw_ale *ale, const u8 *addr, int port_mask,
384 cpsw_ale_write(ale, idx, ale_entry); 377 cpsw_ale_write(ale, idx, ale_entry);
385 return 0; 378 return 0;
386} 379}
387EXPORT_SYMBOL_GPL(cpsw_ale_add_mcast);
388 380
389int cpsw_ale_del_mcast(struct cpsw_ale *ale, const u8 *addr, int port_mask, 381int cpsw_ale_del_mcast(struct cpsw_ale *ale, const u8 *addr, int port_mask,
390 int flags, u16 vid) 382 int flags, u16 vid)
@@ -407,7 +399,6 @@ int cpsw_ale_del_mcast(struct cpsw_ale *ale, const u8 *addr, int port_mask,
407 cpsw_ale_write(ale, idx, ale_entry); 399 cpsw_ale_write(ale, idx, ale_entry);
408 return 0; 400 return 0;
409} 401}
410EXPORT_SYMBOL_GPL(cpsw_ale_del_mcast);
411 402
412/* ALE NetCP NU switch specific vlan functions */ 403/* ALE NetCP NU switch specific vlan functions */
413static void cpsw_ale_set_vlan_mcast(struct cpsw_ale *ale, u32 *ale_entry, 404static void cpsw_ale_set_vlan_mcast(struct cpsw_ale *ale, u32 *ale_entry,
@@ -458,7 +449,6 @@ int cpsw_ale_add_vlan(struct cpsw_ale *ale, u16 vid, int port, int untag,
458 cpsw_ale_write(ale, idx, ale_entry); 449 cpsw_ale_write(ale, idx, ale_entry);
459 return 0; 450 return 0;
460} 451}
461EXPORT_SYMBOL_GPL(cpsw_ale_add_vlan);
462 452
463int cpsw_ale_del_vlan(struct cpsw_ale *ale, u16 vid, int port_mask) 453int cpsw_ale_del_vlan(struct cpsw_ale *ale, u16 vid, int port_mask)
464{ 454{
@@ -480,40 +470,39 @@ int cpsw_ale_del_vlan(struct cpsw_ale *ale, u16 vid, int port_mask)
480 cpsw_ale_write(ale, idx, ale_entry); 470 cpsw_ale_write(ale, idx, ale_entry);
481 return 0; 471 return 0;
482} 472}
483EXPORT_SYMBOL_GPL(cpsw_ale_del_vlan);
484 473
485void cpsw_ale_set_allmulti(struct cpsw_ale *ale, int allmulti) 474void cpsw_ale_set_allmulti(struct cpsw_ale *ale, int allmulti, int port)
486{ 475{
487 u32 ale_entry[ALE_ENTRY_WORDS]; 476 u32 ale_entry[ALE_ENTRY_WORDS];
488 int type, idx;
489 int unreg_mcast = 0; 477 int unreg_mcast = 0;
490 478 int type, idx;
491 /* Only bother doing the work if the setting is actually changing */
492 if (ale->allmulti == allmulti)
493 return;
494
495 /* Remember the new setting to check against next time */
496 ale->allmulti = allmulti;
497 479
498 for (idx = 0; idx < ale->params.ale_entries; idx++) { 480 for (idx = 0; idx < ale->params.ale_entries; idx++) {
481 int vlan_members;
482
499 cpsw_ale_read(ale, idx, ale_entry); 483 cpsw_ale_read(ale, idx, ale_entry);
500 type = cpsw_ale_get_entry_type(ale_entry); 484 type = cpsw_ale_get_entry_type(ale_entry);
501 if (type != ALE_TYPE_VLAN) 485 if (type != ALE_TYPE_VLAN)
502 continue; 486 continue;
487 vlan_members =
488 cpsw_ale_get_vlan_member_list(ale_entry,
489 ale->vlan_field_bits);
490
491 if (port != -1 && !(vlan_members & BIT(port)))
492 continue;
503 493
504 unreg_mcast = 494 unreg_mcast =
505 cpsw_ale_get_vlan_unreg_mcast(ale_entry, 495 cpsw_ale_get_vlan_unreg_mcast(ale_entry,
506 ale->vlan_field_bits); 496 ale->vlan_field_bits);
507 if (allmulti) 497 if (allmulti)
508 unreg_mcast |= 1; 498 unreg_mcast |= ALE_PORT_HOST;
509 else 499 else
510 unreg_mcast &= ~1; 500 unreg_mcast &= ~ALE_PORT_HOST;
511 cpsw_ale_set_vlan_unreg_mcast(ale_entry, unreg_mcast, 501 cpsw_ale_set_vlan_unreg_mcast(ale_entry, unreg_mcast,
512 ale->vlan_field_bits); 502 ale->vlan_field_bits);
513 cpsw_ale_write(ale, idx, ale_entry); 503 cpsw_ale_write(ale, idx, ale_entry);
514 } 504 }
515} 505}
516EXPORT_SYMBOL_GPL(cpsw_ale_set_allmulti);
517 506
518struct ale_control_info { 507struct ale_control_info {
519 const char *name; 508 const char *name;
@@ -739,7 +728,6 @@ int cpsw_ale_control_set(struct cpsw_ale *ale, int port, int control,
739 728
740 return 0; 729 return 0;
741} 730}
742EXPORT_SYMBOL_GPL(cpsw_ale_control_set);
743 731
744int cpsw_ale_control_get(struct cpsw_ale *ale, int port, int control) 732int cpsw_ale_control_get(struct cpsw_ale *ale, int port, int control)
745{ 733{
@@ -763,7 +751,6 @@ int cpsw_ale_control_get(struct cpsw_ale *ale, int port, int control)
763 tmp = readl_relaxed(ale->params.ale_regs + offset) >> shift; 751 tmp = readl_relaxed(ale->params.ale_regs + offset) >> shift;
764 return tmp & BITMASK(info->bits); 752 return tmp & BITMASK(info->bits);
765} 753}
766EXPORT_SYMBOL_GPL(cpsw_ale_control_get);
767 754
768static void cpsw_ale_timer(struct timer_list *t) 755static void cpsw_ale_timer(struct timer_list *t)
769{ 756{
@@ -788,14 +775,12 @@ void cpsw_ale_start(struct cpsw_ale *ale)
788 add_timer(&ale->timer); 775 add_timer(&ale->timer);
789 } 776 }
790} 777}
791EXPORT_SYMBOL_GPL(cpsw_ale_start);
792 778
793void cpsw_ale_stop(struct cpsw_ale *ale) 779void cpsw_ale_stop(struct cpsw_ale *ale)
794{ 780{
795 del_timer_sync(&ale->timer); 781 del_timer_sync(&ale->timer);
796 cpsw_ale_control_set(ale, 0, ALE_ENABLE, 0); 782 cpsw_ale_control_set(ale, 0, ALE_ENABLE, 0);
797} 783}
798EXPORT_SYMBOL_GPL(cpsw_ale_stop);
799 784
800struct cpsw_ale *cpsw_ale_create(struct cpsw_ale_params *params) 785struct cpsw_ale *cpsw_ale_create(struct cpsw_ale_params *params)
801{ 786{
@@ -879,7 +864,6 @@ struct cpsw_ale *cpsw_ale_create(struct cpsw_ale_params *params)
879 864
880 return ale; 865 return ale;
881} 866}
882EXPORT_SYMBOL_GPL(cpsw_ale_create);
883 867
884void cpsw_ale_dump(struct cpsw_ale *ale, u32 *data) 868void cpsw_ale_dump(struct cpsw_ale *ale, u32 *data)
885{ 869{
@@ -890,8 +874,3 @@ void cpsw_ale_dump(struct cpsw_ale *ale, u32 *data)
890 data += ALE_ENTRY_WORDS; 874 data += ALE_ENTRY_WORDS;
891 } 875 }
892} 876}
893EXPORT_SYMBOL_GPL(cpsw_ale_dump);
894
895MODULE_LICENSE("GPL v2");
896MODULE_DESCRIPTION("TI CPSW ALE driver");
897MODULE_AUTHOR("Texas Instruments");
diff --git a/drivers/net/ethernet/ti/cpsw_ale.h b/drivers/net/ethernet/ti/cpsw_ale.h
index cd07a3e96d57..370df254eb12 100644
--- a/drivers/net/ethernet/ti/cpsw_ale.h
+++ b/drivers/net/ethernet/ti/cpsw_ale.h
@@ -1,16 +1,9 @@
1/* SPDX-License-Identifier: GPL-2.0 */
1/* 2/*
2 * Texas Instruments N-Port Ethernet Switch Address Lookup Engine APIs 3 * Texas Instruments N-Port Ethernet Switch Address Lookup Engine APIs
3 * 4 *
4 * Copyright (C) 2012 Texas Instruments 5 * Copyright (C) 2012 Texas Instruments
5 * 6 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */ 7 */
15#ifndef __TI_CPSW_ALE_H__ 8#ifndef __TI_CPSW_ALE_H__
16#define __TI_CPSW_ALE_H__ 9#define __TI_CPSW_ALE_H__
@@ -37,7 +30,6 @@ struct cpsw_ale {
37 struct cpsw_ale_params params; 30 struct cpsw_ale_params params;
38 struct timer_list timer; 31 struct timer_list timer;
39 unsigned long ageout; 32 unsigned long ageout;
40 int allmulti;
41 u32 version; 33 u32 version;
42 /* These bits are different on NetCP NU Switch ALE */ 34 /* These bits are different on NetCP NU Switch ALE */
43 u32 port_mask_bits; 35 u32 port_mask_bits;
@@ -116,7 +108,7 @@ int cpsw_ale_del_mcast(struct cpsw_ale *ale, const u8 *addr, int port_mask,
116int cpsw_ale_add_vlan(struct cpsw_ale *ale, u16 vid, int port, int untag, 108int cpsw_ale_add_vlan(struct cpsw_ale *ale, u16 vid, int port, int untag,
117 int reg_mcast, int unreg_mcast); 109 int reg_mcast, int unreg_mcast);
118int cpsw_ale_del_vlan(struct cpsw_ale *ale, u16 vid, int port); 110int cpsw_ale_del_vlan(struct cpsw_ale *ale, u16 vid, int port);
119void cpsw_ale_set_allmulti(struct cpsw_ale *ale, int allmulti); 111void cpsw_ale_set_allmulti(struct cpsw_ale *ale, int allmulti, int port);
120 112
121int cpsw_ale_control_get(struct cpsw_ale *ale, int port, int control); 113int cpsw_ale_control_get(struct cpsw_ale *ale, int port, int control);
122int cpsw_ale_control_set(struct cpsw_ale *ale, int port, 114int cpsw_ale_control_set(struct cpsw_ale *ale, int port,
diff --git a/drivers/net/ethernet/ti/cpsw_ethtool.c b/drivers/net/ethernet/ti/cpsw_ethtool.c
new file mode 100644
index 000000000000..a4a7ec0d2531
--- /dev/null
+++ b/drivers/net/ethernet/ti/cpsw_ethtool.c
@@ -0,0 +1,719 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Texas Instruments Ethernet Switch Driver ethtool intf
4 *
5 * Copyright (C) 2019 Texas Instruments
6 */
7
8#include <linux/if_ether.h>
9#include <linux/if_vlan.h>
10#include <linux/kmemleak.h>
11#include <linux/module.h>
12#include <linux/netdevice.h>
13#include <linux/net_tstamp.h>
14#include <linux/phy.h>
15#include <linux/pm_runtime.h>
16#include <linux/skbuff.h>
17
18#include "cpsw.h"
19#include "cpts.h"
20#include "cpsw_ale.h"
21#include "cpsw_priv.h"
22#include "davinci_cpdma.h"
23
24struct cpsw_hw_stats {
25 u32 rxgoodframes;
26 u32 rxbroadcastframes;
27 u32 rxmulticastframes;
28 u32 rxpauseframes;
29 u32 rxcrcerrors;
30 u32 rxaligncodeerrors;
31 u32 rxoversizedframes;
32 u32 rxjabberframes;
33 u32 rxundersizedframes;
34 u32 rxfragments;
35 u32 __pad_0[2];
36 u32 rxoctets;
37 u32 txgoodframes;
38 u32 txbroadcastframes;
39 u32 txmulticastframes;
40 u32 txpauseframes;
41 u32 txdeferredframes;
42 u32 txcollisionframes;
43 u32 txsinglecollframes;
44 u32 txmultcollframes;
45 u32 txexcessivecollisions;
46 u32 txlatecollisions;
47 u32 txunderrun;
48 u32 txcarriersenseerrors;
49 u32 txoctets;
50 u32 octetframes64;
51 u32 octetframes65t127;
52 u32 octetframes128t255;
53 u32 octetframes256t511;
54 u32 octetframes512t1023;
55 u32 octetframes1024tup;
56 u32 netoctets;
57 u32 rxsofoverruns;
58 u32 rxmofoverruns;
59 u32 rxdmaoverruns;
60};
61
62struct cpsw_stats {
63 char stat_string[ETH_GSTRING_LEN];
64 int type;
65 int sizeof_stat;
66 int stat_offset;
67};
68
69enum {
70 CPSW_STATS,
71 CPDMA_RX_STATS,
72 CPDMA_TX_STATS,
73};
74
75#define CPSW_STAT(m) CPSW_STATS, \
76 FIELD_SIZEOF(struct cpsw_hw_stats, m), \
77 offsetof(struct cpsw_hw_stats, m)
78#define CPDMA_RX_STAT(m) CPDMA_RX_STATS, \
79 FIELD_SIZEOF(struct cpdma_chan_stats, m), \
80 offsetof(struct cpdma_chan_stats, m)
81#define CPDMA_TX_STAT(m) CPDMA_TX_STATS, \
82 FIELD_SIZEOF(struct cpdma_chan_stats, m), \
83 offsetof(struct cpdma_chan_stats, m)
84
85static const struct cpsw_stats cpsw_gstrings_stats[] = {
86 { "Good Rx Frames", CPSW_STAT(rxgoodframes) },
87 { "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes) },
88 { "Multicast Rx Frames", CPSW_STAT(rxmulticastframes) },
89 { "Pause Rx Frames", CPSW_STAT(rxpauseframes) },
90 { "Rx CRC Errors", CPSW_STAT(rxcrcerrors) },
91 { "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors) },
92 { "Oversize Rx Frames", CPSW_STAT(rxoversizedframes) },
93 { "Rx Jabbers", CPSW_STAT(rxjabberframes) },
94 { "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes) },
95 { "Rx Fragments", CPSW_STAT(rxfragments) },
96 { "Rx Octets", CPSW_STAT(rxoctets) },
97 { "Good Tx Frames", CPSW_STAT(txgoodframes) },
98 { "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes) },
99 { "Multicast Tx Frames", CPSW_STAT(txmulticastframes) },
100 { "Pause Tx Frames", CPSW_STAT(txpauseframes) },
101 { "Deferred Tx Frames", CPSW_STAT(txdeferredframes) },
102 { "Collisions", CPSW_STAT(txcollisionframes) },
103 { "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes) },
104 { "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes) },
105 { "Excessive Collisions", CPSW_STAT(txexcessivecollisions) },
106 { "Late Collisions", CPSW_STAT(txlatecollisions) },
107 { "Tx Underrun", CPSW_STAT(txunderrun) },
108 { "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors) },
109 { "Tx Octets", CPSW_STAT(txoctets) },
110 { "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64) },
111 { "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127) },
112 { "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255) },
113 { "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511) },
114 { "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023) },
115 { "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup) },
116 { "Net Octets", CPSW_STAT(netoctets) },
117 { "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns) },
118 { "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns) },
119 { "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns) },
120};
121
122static const struct cpsw_stats cpsw_gstrings_ch_stats[] = {
123 { "head_enqueue", CPDMA_RX_STAT(head_enqueue) },
124 { "tail_enqueue", CPDMA_RX_STAT(tail_enqueue) },
125 { "pad_enqueue", CPDMA_RX_STAT(pad_enqueue) },
126 { "misqueued", CPDMA_RX_STAT(misqueued) },
127 { "desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail) },
128 { "pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail) },
129 { "runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff) },
130 { "runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff) },
131 { "empty_dequeue", CPDMA_RX_STAT(empty_dequeue) },
132 { "busy_dequeue", CPDMA_RX_STAT(busy_dequeue) },
133 { "good_dequeue", CPDMA_RX_STAT(good_dequeue) },
134 { "requeue", CPDMA_RX_STAT(requeue) },
135 { "teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) },
136};
137
138#define CPSW_STATS_COMMON_LEN ARRAY_SIZE(cpsw_gstrings_stats)
139#define CPSW_STATS_CH_LEN ARRAY_SIZE(cpsw_gstrings_ch_stats)
140
141u32 cpsw_get_msglevel(struct net_device *ndev)
142{
143 struct cpsw_priv *priv = netdev_priv(ndev);
144
145 return priv->msg_enable;
146}
147
148void cpsw_set_msglevel(struct net_device *ndev, u32 value)
149{
150 struct cpsw_priv *priv = netdev_priv(ndev);
151
152 priv->msg_enable = value;
153}
154
155int cpsw_get_coalesce(struct net_device *ndev, struct ethtool_coalesce *coal)
156{
157 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
158
159 coal->rx_coalesce_usecs = cpsw->coal_intvl;
160 return 0;
161}
162
163int cpsw_set_coalesce(struct net_device *ndev, struct ethtool_coalesce *coal)
164{
165 struct cpsw_priv *priv = netdev_priv(ndev);
166 u32 int_ctrl;
167 u32 num_interrupts = 0;
168 u32 prescale = 0;
169 u32 addnl_dvdr = 1;
170 u32 coal_intvl = 0;
171 struct cpsw_common *cpsw = priv->cpsw;
172
173 coal_intvl = coal->rx_coalesce_usecs;
174
175 int_ctrl = readl(&cpsw->wr_regs->int_control);
176 prescale = cpsw->bus_freq_mhz * 4;
177
178 if (!coal->rx_coalesce_usecs) {
179 int_ctrl &= ~(CPSW_INTPRESCALE_MASK | CPSW_INTPACEEN);
180 goto update_return;
181 }
182
183 if (coal_intvl < CPSW_CMINTMIN_INTVL)
184 coal_intvl = CPSW_CMINTMIN_INTVL;
185
186 if (coal_intvl > CPSW_CMINTMAX_INTVL) {
187 /* Interrupt pacer works with 4us Pulse, we can
188 * throttle further by dilating the 4us pulse.
189 */
190 addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale;
191
192 if (addnl_dvdr > 1) {
193 prescale *= addnl_dvdr;
194 if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr))
195 coal_intvl = (CPSW_CMINTMAX_INTVL
196 * addnl_dvdr);
197 } else {
198 addnl_dvdr = 1;
199 coal_intvl = CPSW_CMINTMAX_INTVL;
200 }
201 }
202
203 num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
204 writel(num_interrupts, &cpsw->wr_regs->rx_imax);
205 writel(num_interrupts, &cpsw->wr_regs->tx_imax);
206
207 int_ctrl |= CPSW_INTPACEEN;
208 int_ctrl &= (~CPSW_INTPRESCALE_MASK);
209 int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK);
210
211update_return:
212 writel(int_ctrl, &cpsw->wr_regs->int_control);
213
214 cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl);
215 cpsw->coal_intvl = coal_intvl;
216
217 return 0;
218}
219
220int cpsw_get_sset_count(struct net_device *ndev, int sset)
221{
222 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
223
224 switch (sset) {
225 case ETH_SS_STATS:
226 return (CPSW_STATS_COMMON_LEN +
227 (cpsw->rx_ch_num + cpsw->tx_ch_num) *
228 CPSW_STATS_CH_LEN);
229 default:
230 return -EOPNOTSUPP;
231 }
232}
233
234static void cpsw_add_ch_strings(u8 **p, int ch_num, int rx_dir)
235{
236 int ch_stats_len;
237 int line;
238 int i;
239
240 ch_stats_len = CPSW_STATS_CH_LEN * ch_num;
241 for (i = 0; i < ch_stats_len; i++) {
242 line = i % CPSW_STATS_CH_LEN;
243 snprintf(*p, ETH_GSTRING_LEN,
244 "%s DMA chan %ld: %s", rx_dir ? "Rx" : "Tx",
245 (long)(i / CPSW_STATS_CH_LEN),
246 cpsw_gstrings_ch_stats[line].stat_string);
247 *p += ETH_GSTRING_LEN;
248 }
249}
250
251void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
252{
253 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
254 u8 *p = data;
255 int i;
256
257 switch (stringset) {
258 case ETH_SS_STATS:
259 for (i = 0; i < CPSW_STATS_COMMON_LEN; i++) {
260 memcpy(p, cpsw_gstrings_stats[i].stat_string,
261 ETH_GSTRING_LEN);
262 p += ETH_GSTRING_LEN;
263 }
264
265 cpsw_add_ch_strings(&p, cpsw->rx_ch_num, 1);
266 cpsw_add_ch_strings(&p, cpsw->tx_ch_num, 0);
267 break;
268 }
269}
270
271void cpsw_get_ethtool_stats(struct net_device *ndev,
272 struct ethtool_stats *stats, u64 *data)
273{
274 u8 *p;
275 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
276 struct cpdma_chan_stats ch_stats;
277 int i, l, ch;
278
279 /* Collect Davinci CPDMA stats for Rx and Tx Channel */
280 for (l = 0; l < CPSW_STATS_COMMON_LEN; l++)
281 data[l] = readl(cpsw->hw_stats +
282 cpsw_gstrings_stats[l].stat_offset);
283
284 for (ch = 0; ch < cpsw->rx_ch_num; ch++) {
285 cpdma_chan_get_stats(cpsw->rxv[ch].ch, &ch_stats);
286 for (i = 0; i < CPSW_STATS_CH_LEN; i++, l++) {
287 p = (u8 *)&ch_stats +
288 cpsw_gstrings_ch_stats[i].stat_offset;
289 data[l] = *(u32 *)p;
290 }
291 }
292
293 for (ch = 0; ch < cpsw->tx_ch_num; ch++) {
294 cpdma_chan_get_stats(cpsw->txv[ch].ch, &ch_stats);
295 for (i = 0; i < CPSW_STATS_CH_LEN; i++, l++) {
296 p = (u8 *)&ch_stats +
297 cpsw_gstrings_ch_stats[i].stat_offset;
298 data[l] = *(u32 *)p;
299 }
300 }
301}
302
303void cpsw_get_pauseparam(struct net_device *ndev,
304 struct ethtool_pauseparam *pause)
305{
306 struct cpsw_priv *priv = netdev_priv(ndev);
307
308 pause->autoneg = AUTONEG_DISABLE;
309 pause->rx_pause = priv->rx_pause ? true : false;
310 pause->tx_pause = priv->tx_pause ? true : false;
311}
312
313void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
314{
315 struct cpsw_priv *priv = netdev_priv(ndev);
316 struct cpsw_common *cpsw = priv->cpsw;
317 int slave_no = cpsw_slave_index(cpsw, priv);
318
319 wol->supported = 0;
320 wol->wolopts = 0;
321
322 if (cpsw->slaves[slave_no].phy)
323 phy_ethtool_get_wol(cpsw->slaves[slave_no].phy, wol);
324}
325
326int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
327{
328 struct cpsw_priv *priv = netdev_priv(ndev);
329 struct cpsw_common *cpsw = priv->cpsw;
330 int slave_no = cpsw_slave_index(cpsw, priv);
331
332 if (cpsw->slaves[slave_no].phy)
333 return phy_ethtool_set_wol(cpsw->slaves[slave_no].phy, wol);
334 else
335 return -EOPNOTSUPP;
336}
337
338int cpsw_get_regs_len(struct net_device *ndev)
339{
340 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
341
342 return cpsw->data.ale_entries * ALE_ENTRY_WORDS * sizeof(u32);
343}
344
345void cpsw_get_regs(struct net_device *ndev, struct ethtool_regs *regs, void *p)
346{
347 u32 *reg = p;
348 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
349
350 /* update CPSW IP version */
351 regs->version = cpsw->version;
352
353 cpsw_ale_dump(cpsw->ale, reg);
354}
355
356int cpsw_ethtool_op_begin(struct net_device *ndev)
357{
358 struct cpsw_priv *priv = netdev_priv(ndev);
359 struct cpsw_common *cpsw = priv->cpsw;
360 int ret;
361
362 ret = pm_runtime_get_sync(cpsw->dev);
363 if (ret < 0) {
364 cpsw_err(priv, drv, "ethtool begin failed %d\n", ret);
365 pm_runtime_put_noidle(cpsw->dev);
366 }
367
368 return ret;
369}
370
371void cpsw_ethtool_op_complete(struct net_device *ndev)
372{
373 struct cpsw_priv *priv = netdev_priv(ndev);
374 int ret;
375
376 ret = pm_runtime_put(priv->cpsw->dev);
377 if (ret < 0)
378 cpsw_err(priv, drv, "ethtool complete failed %d\n", ret);
379}
380
381void cpsw_get_channels(struct net_device *ndev, struct ethtool_channels *ch)
382{
383 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
384
385 ch->max_rx = cpsw->quirk_irq ? 1 : CPSW_MAX_QUEUES;
386 ch->max_tx = cpsw->quirk_irq ? 1 : CPSW_MAX_QUEUES;
387 ch->max_combined = 0;
388 ch->max_other = 0;
389 ch->other_count = 0;
390 ch->rx_count = cpsw->rx_ch_num;
391 ch->tx_count = cpsw->tx_ch_num;
392 ch->combined_count = 0;
393}
394
395int cpsw_get_link_ksettings(struct net_device *ndev,
396 struct ethtool_link_ksettings *ecmd)
397{
398 struct cpsw_priv *priv = netdev_priv(ndev);
399 struct cpsw_common *cpsw = priv->cpsw;
400 int slave_no = cpsw_slave_index(cpsw, priv);
401
402 if (!cpsw->slaves[slave_no].phy)
403 return -EOPNOTSUPP;
404
405 phy_ethtool_ksettings_get(cpsw->slaves[slave_no].phy, ecmd);
406 return 0;
407}
408
409int cpsw_set_link_ksettings(struct net_device *ndev,
410 const struct ethtool_link_ksettings *ecmd)
411{
412 struct cpsw_priv *priv = netdev_priv(ndev);
413 struct cpsw_common *cpsw = priv->cpsw;
414 int slave_no = cpsw_slave_index(cpsw, priv);
415
416 if (!cpsw->slaves[slave_no].phy)
417 return -EOPNOTSUPP;
418
419 return phy_ethtool_ksettings_set(cpsw->slaves[slave_no].phy, ecmd);
420}
421
422int cpsw_get_eee(struct net_device *ndev, struct ethtool_eee *edata)
423{
424 struct cpsw_priv *priv = netdev_priv(ndev);
425 struct cpsw_common *cpsw = priv->cpsw;
426 int slave_no = cpsw_slave_index(cpsw, priv);
427
428 if (cpsw->slaves[slave_no].phy)
429 return phy_ethtool_get_eee(cpsw->slaves[slave_no].phy, edata);
430 else
431 return -EOPNOTSUPP;
432}
433
434int cpsw_set_eee(struct net_device *ndev, struct ethtool_eee *edata)
435{
436 struct cpsw_priv *priv = netdev_priv(ndev);
437 struct cpsw_common *cpsw = priv->cpsw;
438 int slave_no = cpsw_slave_index(cpsw, priv);
439
440 if (cpsw->slaves[slave_no].phy)
441 return phy_ethtool_set_eee(cpsw->slaves[slave_no].phy, edata);
442 else
443 return -EOPNOTSUPP;
444}
445
446int cpsw_nway_reset(struct net_device *ndev)
447{
448 struct cpsw_priv *priv = netdev_priv(ndev);
449 struct cpsw_common *cpsw = priv->cpsw;
450 int slave_no = cpsw_slave_index(cpsw, priv);
451
452 if (cpsw->slaves[slave_no].phy)
453 return genphy_restart_aneg(cpsw->slaves[slave_no].phy);
454 else
455 return -EOPNOTSUPP;
456}
457
458static void cpsw_suspend_data_pass(struct net_device *ndev)
459{
460 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
461 struct cpsw_slave *slave;
462 int i;
463
464 /* Disable NAPI scheduling */
465 cpsw_intr_disable(cpsw);
466
467 /* Stop all transmit queues for every network device.
468 * Disable re-using rx descriptors with dormant_on.
469 */
470 for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++) {
471 if (!(slave->ndev && netif_running(slave->ndev)))
472 continue;
473
474 netif_tx_stop_all_queues(slave->ndev);
475 netif_dormant_on(slave->ndev);
476 }
477
478 /* Handle rest of tx packets and stop cpdma channels */
479 cpdma_ctlr_stop(cpsw->dma);
480}
481
482static int cpsw_resume_data_pass(struct net_device *ndev)
483{
484 struct cpsw_priv *priv = netdev_priv(ndev);
485 struct cpsw_common *cpsw = priv->cpsw;
486 struct cpsw_slave *slave;
487 int i, ret;
488
489 /* Allow rx packets handling */
490 for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++)
491 if (slave->ndev && netif_running(slave->ndev))
492 netif_dormant_off(slave->ndev);
493
494 /* After this receive is started */
495 if (cpsw->usage_count) {
496 ret = cpsw_fill_rx_channels(priv);
497 if (ret)
498 return ret;
499
500 cpdma_ctlr_start(cpsw->dma);
501 cpsw_intr_enable(cpsw);
502 }
503
504 /* Resume transmit for every affected interface */
505 for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++)
506 if (slave->ndev && netif_running(slave->ndev))
507 netif_tx_start_all_queues(slave->ndev);
508
509 return 0;
510}
511
512static int cpsw_check_ch_settings(struct cpsw_common *cpsw,
513 struct ethtool_channels *ch)
514{
515 if (cpsw->quirk_irq) {
516 dev_err(cpsw->dev, "Maximum one tx/rx queue is allowed");
517 return -EOPNOTSUPP;
518 }
519
520 if (ch->combined_count)
521 return -EINVAL;
522
523 /* verify we have at least one channel in each direction */
524 if (!ch->rx_count || !ch->tx_count)
525 return -EINVAL;
526
527 if (ch->rx_count > cpsw->data.channels ||
528 ch->tx_count > cpsw->data.channels)
529 return -EINVAL;
530
531 return 0;
532}
533
534static int cpsw_update_channels_res(struct cpsw_priv *priv, int ch_num, int rx,
535 cpdma_handler_fn rx_handler)
536{
537 struct cpsw_common *cpsw = priv->cpsw;
538 void (*handler)(void *, int, int);
539 struct netdev_queue *queue;
540 struct cpsw_vector *vec;
541 int ret, *ch, vch;
542
543 if (rx) {
544 ch = &cpsw->rx_ch_num;
545 vec = cpsw->rxv;
546 handler = rx_handler;
547 } else {
548 ch = &cpsw->tx_ch_num;
549 vec = cpsw->txv;
550 handler = cpsw_tx_handler;
551 }
552
553 while (*ch < ch_num) {
554 vch = rx ? *ch : 7 - *ch;
555 vec[*ch].ch = cpdma_chan_create(cpsw->dma, vch, handler, rx);
556 queue = netdev_get_tx_queue(priv->ndev, *ch);
557 queue->tx_maxrate = 0;
558
559 if (IS_ERR(vec[*ch].ch))
560 return PTR_ERR(vec[*ch].ch);
561
562 if (!vec[*ch].ch)
563 return -EINVAL;
564
565 cpsw_info(priv, ifup, "created new %d %s channel\n", *ch,
566 (rx ? "rx" : "tx"));
567 (*ch)++;
568 }
569
570 while (*ch > ch_num) {
571 (*ch)--;
572
573 ret = cpdma_chan_destroy(vec[*ch].ch);
574 if (ret)
575 return ret;
576
577 cpsw_info(priv, ifup, "destroyed %d %s channel\n", *ch,
578 (rx ? "rx" : "tx"));
579 }
580
581 return 0;
582}
583
584int cpsw_set_channels_common(struct net_device *ndev,
585 struct ethtool_channels *chs,
586 cpdma_handler_fn rx_handler)
587{
588 struct cpsw_priv *priv = netdev_priv(ndev);
589 struct cpsw_common *cpsw = priv->cpsw;
590 struct cpsw_slave *slave;
591 int i, ret;
592
593 ret = cpsw_check_ch_settings(cpsw, chs);
594 if (ret < 0)
595 return ret;
596
597 cpsw_suspend_data_pass(ndev);
598
599 ret = cpsw_update_channels_res(priv, chs->rx_count, 1, rx_handler);
600 if (ret)
601 goto err;
602
603 ret = cpsw_update_channels_res(priv, chs->tx_count, 0, rx_handler);
604 if (ret)
605 goto err;
606
607 for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++) {
608 if (!(slave->ndev && netif_running(slave->ndev)))
609 continue;
610
611 /* Inform stack about new count of queues */
612 ret = netif_set_real_num_tx_queues(slave->ndev,
613 cpsw->tx_ch_num);
614 if (ret) {
615 dev_err(priv->dev, "cannot set real number of tx queues\n");
616 goto err;
617 }
618
619 ret = netif_set_real_num_rx_queues(slave->ndev,
620 cpsw->rx_ch_num);
621 if (ret) {
622 dev_err(priv->dev, "cannot set real number of rx queues\n");
623 goto err;
624 }
625 }
626
627 if (cpsw->usage_count)
628 cpsw_split_res(cpsw);
629
630 ret = cpsw_resume_data_pass(ndev);
631 if (!ret)
632 return 0;
633err:
634 dev_err(priv->dev, "cannot update channels number, closing device\n");
635 dev_close(ndev);
636 return ret;
637}
638
639void cpsw_get_ringparam(struct net_device *ndev,
640 struct ethtool_ringparam *ering)
641{
642 struct cpsw_priv *priv = netdev_priv(ndev);
643 struct cpsw_common *cpsw = priv->cpsw;
644
645 /* not supported */
646 ering->tx_max_pending = 0;
647 ering->tx_pending = cpdma_get_num_tx_descs(cpsw->dma);
648 ering->rx_max_pending = cpsw->descs_pool_size - CPSW_MAX_QUEUES;
649 ering->rx_pending = cpdma_get_num_rx_descs(cpsw->dma);
650}
651
652int cpsw_set_ringparam(struct net_device *ndev,
653 struct ethtool_ringparam *ering)
654{
655 struct cpsw_priv *priv = netdev_priv(ndev);
656 struct cpsw_common *cpsw = priv->cpsw;
657 int ret;
658
659 /* ignore ering->tx_pending - only rx_pending adjustment is supported */
660
661 if (ering->rx_mini_pending || ering->rx_jumbo_pending ||
662 ering->rx_pending < CPSW_MAX_QUEUES ||
663 ering->rx_pending > (cpsw->descs_pool_size - CPSW_MAX_QUEUES))
664 return -EINVAL;
665
666 if (ering->rx_pending == cpdma_get_num_rx_descs(cpsw->dma))
667 return 0;
668
669 cpsw_suspend_data_pass(ndev);
670
671 cpdma_set_num_rx_descs(cpsw->dma, ering->rx_pending);
672
673 if (cpsw->usage_count)
674 cpdma_chan_split_pool(cpsw->dma);
675
676 ret = cpsw_resume_data_pass(ndev);
677 if (!ret)
678 return 0;
679
680 dev_err(cpsw->dev, "cannot set ring params, closing device\n");
681 dev_close(ndev);
682 return ret;
683}
684
685#if IS_ENABLED(CONFIG_TI_CPTS)
686int cpsw_get_ts_info(struct net_device *ndev, struct ethtool_ts_info *info)
687{
688 struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
689
690 info->so_timestamping =
691 SOF_TIMESTAMPING_TX_HARDWARE |
692 SOF_TIMESTAMPING_TX_SOFTWARE |
693 SOF_TIMESTAMPING_RX_HARDWARE |
694 SOF_TIMESTAMPING_RX_SOFTWARE |
695 SOF_TIMESTAMPING_SOFTWARE |
696 SOF_TIMESTAMPING_RAW_HARDWARE;
697 info->phc_index = cpsw->cpts->phc_index;
698 info->tx_types =
699 (1 << HWTSTAMP_TX_OFF) |
700 (1 << HWTSTAMP_TX_ON);
701 info->rx_filters =
702 (1 << HWTSTAMP_FILTER_NONE) |
703 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
704 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
705 return 0;
706}
707#else
708int cpsw_get_ts_info(struct net_device *ndev, struct ethtool_ts_info *info)
709{
710 info->so_timestamping =
711 SOF_TIMESTAMPING_TX_SOFTWARE |
712 SOF_TIMESTAMPING_RX_SOFTWARE |
713 SOF_TIMESTAMPING_SOFTWARE;
714 info->phc_index = -1;
715 info->tx_types = 0;
716 info->rx_filters = 0;
717 return 0;
718}
719#endif
diff --git a/drivers/net/ethernet/ti/cpsw_priv.c b/drivers/net/ethernet/ti/cpsw_priv.c
new file mode 100644
index 000000000000..476d050a022c
--- /dev/null
+++ b/drivers/net/ethernet/ti/cpsw_priv.c
@@ -0,0 +1,132 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Texas Instruments Ethernet Switch Driver
4 *
5 * Copyright (C) 2019 Texas Instruments
6 */
7
8#include <linux/if_ether.h>
9#include <linux/if_vlan.h>
10#include <linux/module.h>
11#include <linux/netdevice.h>
12#include <linux/phy.h>
13#include <linux/platform_device.h>
14#include <linux/skbuff.h>
15
16#include "cpts.h"
17#include "cpsw_ale.h"
18#include "cpsw_priv.h"
19#include "cpsw_sl.h"
20#include "davinci_cpdma.h"
21
22int cpsw_init_common(struct cpsw_common *cpsw, void __iomem *ss_regs,
23 int ale_ageout, phys_addr_t desc_mem_phys,
24 int descs_pool_size)
25{
26 u32 slave_offset, sliver_offset, slave_size;
27 struct cpsw_ale_params ale_params;
28 struct cpsw_platform_data *data;
29 struct cpdma_params dma_params;
30 struct device *dev = cpsw->dev;
31 void __iomem *cpts_regs;
32 int ret = 0, i;
33
34 data = &cpsw->data;
35 cpsw->rx_ch_num = 1;
36 cpsw->tx_ch_num = 1;
37
38 cpsw->version = readl(&cpsw->regs->id_ver);
39
40 memset(&dma_params, 0, sizeof(dma_params));
41 memset(&ale_params, 0, sizeof(ale_params));
42
43 switch (cpsw->version) {
44 case CPSW_VERSION_1:
45 cpsw->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET;
46 cpts_regs = ss_regs + CPSW1_CPTS_OFFSET;
47 cpsw->hw_stats = ss_regs + CPSW1_HW_STATS;
48 dma_params.dmaregs = ss_regs + CPSW1_CPDMA_OFFSET;
49 dma_params.txhdp = ss_regs + CPSW1_STATERAM_OFFSET;
50 ale_params.ale_regs = ss_regs + CPSW1_ALE_OFFSET;
51 slave_offset = CPSW1_SLAVE_OFFSET;
52 slave_size = CPSW1_SLAVE_SIZE;
53 sliver_offset = CPSW1_SLIVER_OFFSET;
54 dma_params.desc_mem_phys = 0;
55 break;
56 case CPSW_VERSION_2:
57 case CPSW_VERSION_3:
58 case CPSW_VERSION_4:
59 cpsw->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET;
60 cpts_regs = ss_regs + CPSW2_CPTS_OFFSET;
61 cpsw->hw_stats = ss_regs + CPSW2_HW_STATS;
62 dma_params.dmaregs = ss_regs + CPSW2_CPDMA_OFFSET;
63 dma_params.txhdp = ss_regs + CPSW2_STATERAM_OFFSET;
64 ale_params.ale_regs = ss_regs + CPSW2_ALE_OFFSET;
65 slave_offset = CPSW2_SLAVE_OFFSET;
66 slave_size = CPSW2_SLAVE_SIZE;
67 sliver_offset = CPSW2_SLIVER_OFFSET;
68 dma_params.desc_mem_phys = desc_mem_phys;
69 break;
70 default:
71 dev_err(dev, "unknown version 0x%08x\n", cpsw->version);
72 return -ENODEV;
73 }
74
75 for (i = 0; i < cpsw->data.slaves; i++) {
76 struct cpsw_slave *slave = &cpsw->slaves[i];
77 void __iomem *regs = cpsw->regs;
78
79 slave->slave_num = i;
80 slave->data = &cpsw->data.slave_data[i];
81 slave->regs = regs + slave_offset;
82 slave->port_vlan = slave->data->dual_emac_res_vlan;
83 slave->mac_sl = cpsw_sl_get("cpsw", dev, regs + sliver_offset);
84 if (IS_ERR(slave->mac_sl))
85 return PTR_ERR(slave->mac_sl);
86
87 slave_offset += slave_size;
88 sliver_offset += SLIVER_SIZE;
89 }
90
91 ale_params.dev = dev;
92 ale_params.ale_ageout = ale_ageout;
93 ale_params.ale_entries = data->ale_entries;
94 ale_params.ale_ports = CPSW_ALE_PORTS_NUM;
95
96 cpsw->ale = cpsw_ale_create(&ale_params);
97 if (!cpsw->ale) {
98 dev_err(dev, "error initializing ale engine\n");
99 return -ENODEV;
100 }
101
102 dma_params.dev = dev;
103 dma_params.rxthresh = dma_params.dmaregs + CPDMA_RXTHRESH;
104 dma_params.rxfree = dma_params.dmaregs + CPDMA_RXFREE;
105 dma_params.rxhdp = dma_params.txhdp + CPDMA_RXHDP;
106 dma_params.txcp = dma_params.txhdp + CPDMA_TXCP;
107 dma_params.rxcp = dma_params.txhdp + CPDMA_RXCP;
108
109 dma_params.num_chan = data->channels;
110 dma_params.has_soft_reset = true;
111 dma_params.min_packet_size = CPSW_MIN_PACKET_SIZE;
112 dma_params.desc_mem_size = data->bd_ram_size;
113 dma_params.desc_align = 16;
114 dma_params.has_ext_regs = true;
115 dma_params.desc_hw_addr = dma_params.desc_mem_phys;
116 dma_params.bus_freq_mhz = cpsw->bus_freq_mhz;
117 dma_params.descs_pool_size = descs_pool_size;
118
119 cpsw->dma = cpdma_ctlr_create(&dma_params);
120 if (!cpsw->dma) {
121 dev_err(dev, "error initializing dma\n");
122 return -ENOMEM;
123 }
124
125 cpsw->cpts = cpts_create(cpsw->dev, cpts_regs, cpsw->dev->of_node);
126 if (IS_ERR(cpsw->cpts)) {
127 ret = PTR_ERR(cpsw->cpts);
128 cpdma_ctlr_destroy(cpsw->dma);
129 }
130
131 return ret;
132}
diff --git a/drivers/net/ethernet/ti/cpsw_priv.h b/drivers/net/ethernet/ti/cpsw_priv.h
new file mode 100644
index 000000000000..04795b97ee71
--- /dev/null
+++ b/drivers/net/ethernet/ti/cpsw_priv.h
@@ -0,0 +1,429 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Texas Instruments Ethernet Switch Driver
4 */
5
6#ifndef DRIVERS_NET_ETHERNET_TI_CPSW_PRIV_H_
7#define DRIVERS_NET_ETHERNET_TI_CPSW_PRIV_H_
8
9#include "davinci_cpdma.h"
10
11#define CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_WOL | \
12 NETIF_MSG_DRV | NETIF_MSG_LINK | \
13 NETIF_MSG_IFUP | NETIF_MSG_INTR | \
14 NETIF_MSG_PROBE | NETIF_MSG_TIMER | \
15 NETIF_MSG_IFDOWN | NETIF_MSG_RX_ERR | \
16 NETIF_MSG_TX_ERR | NETIF_MSG_TX_DONE | \
17 NETIF_MSG_PKTDATA | NETIF_MSG_TX_QUEUED | \
18 NETIF_MSG_RX_STATUS)
19
20#define cpsw_info(priv, type, format, ...) \
21do { \
22 if (netif_msg_##type(priv) && net_ratelimit()) \
23 dev_info(priv->dev, format, ## __VA_ARGS__); \
24} while (0)
25
26#define cpsw_err(priv, type, format, ...) \
27do { \
28 if (netif_msg_##type(priv) && net_ratelimit()) \
29 dev_err(priv->dev, format, ## __VA_ARGS__); \
30} while (0)
31
32#define cpsw_dbg(priv, type, format, ...) \
33do { \
34 if (netif_msg_##type(priv) && net_ratelimit()) \
35 dev_dbg(priv->dev, format, ## __VA_ARGS__); \
36} while (0)
37
38#define cpsw_notice(priv, type, format, ...) \
39do { \
40 if (netif_msg_##type(priv) && net_ratelimit()) \
41 dev_notice(priv->dev, format, ## __VA_ARGS__); \
42} while (0)
43
44#define ALE_ALL_PORTS 0x7
45
46#define CPSW_MAJOR_VERSION(reg) (reg >> 8 & 0x7)
47#define CPSW_MINOR_VERSION(reg) (reg & 0xff)
48#define CPSW_RTL_VERSION(reg) ((reg >> 11) & 0x1f)
49
50#define CPSW_VERSION_1 0x19010a
51#define CPSW_VERSION_2 0x19010c
52#define CPSW_VERSION_3 0x19010f
53#define CPSW_VERSION_4 0x190112
54
55#define HOST_PORT_NUM 0
56#define CPSW_ALE_PORTS_NUM 3
57#define SLIVER_SIZE 0x40
58
59#define CPSW1_HOST_PORT_OFFSET 0x028
60#define CPSW1_SLAVE_OFFSET 0x050
61#define CPSW1_SLAVE_SIZE 0x040
62#define CPSW1_CPDMA_OFFSET 0x100
63#define CPSW1_STATERAM_OFFSET 0x200
64#define CPSW1_HW_STATS 0x400
65#define CPSW1_CPTS_OFFSET 0x500
66#define CPSW1_ALE_OFFSET 0x600
67#define CPSW1_SLIVER_OFFSET 0x700
68
69#define CPSW2_HOST_PORT_OFFSET 0x108
70#define CPSW2_SLAVE_OFFSET 0x200
71#define CPSW2_SLAVE_SIZE 0x100
72#define CPSW2_CPDMA_OFFSET 0x800
73#define CPSW2_HW_STATS 0x900
74#define CPSW2_STATERAM_OFFSET 0xa00
75#define CPSW2_CPTS_OFFSET 0xc00
76#define CPSW2_ALE_OFFSET 0xd00
77#define CPSW2_SLIVER_OFFSET 0xd80
78#define CPSW2_BD_OFFSET 0x2000
79
80#define CPDMA_RXTHRESH 0x0c0
81#define CPDMA_RXFREE 0x0e0
82#define CPDMA_TXHDP 0x00
83#define CPDMA_RXHDP 0x20
84#define CPDMA_TXCP 0x40
85#define CPDMA_RXCP 0x60
86
87#define CPSW_POLL_WEIGHT 64
88#define CPSW_RX_VLAN_ENCAP_HDR_SIZE 4
89#define CPSW_MIN_PACKET_SIZE (VLAN_ETH_ZLEN)
90#define CPSW_MAX_PACKET_SIZE (VLAN_ETH_FRAME_LEN +\
91 ETH_FCS_LEN +\
92 CPSW_RX_VLAN_ENCAP_HDR_SIZE)
93
94#define RX_PRIORITY_MAPPING 0x76543210
95#define TX_PRIORITY_MAPPING 0x33221100
96#define CPDMA_TX_PRIORITY_MAP 0x76543210
97
98#define CPSW_VLAN_AWARE BIT(1)
99#define CPSW_RX_VLAN_ENCAP BIT(2)
100#define CPSW_ALE_VLAN_AWARE 1
101
102#define CPSW_FIFO_NORMAL_MODE (0 << 16)
103#define CPSW_FIFO_DUAL_MAC_MODE (1 << 16)
104#define CPSW_FIFO_RATE_LIMIT_MODE (2 << 16)
105
106#define CPSW_INTPACEEN (0x3f << 16)
107#define CPSW_INTPRESCALE_MASK (0x7FF << 0)
108#define CPSW_CMINTMAX_CNT 63
109#define CPSW_CMINTMIN_CNT 2
110#define CPSW_CMINTMAX_INTVL (1000 / CPSW_CMINTMIN_CNT)
111#define CPSW_CMINTMIN_INTVL ((1000 / CPSW_CMINTMAX_CNT) + 1)
112
113#define IRQ_NUM 2
114#define CPSW_MAX_QUEUES 8
115#define CPSW_CPDMA_DESCS_POOL_SIZE_DEFAULT 256
116#define CPSW_FIFO_QUEUE_TYPE_SHIFT 16
117#define CPSW_FIFO_SHAPE_EN_SHIFT 16
118#define CPSW_FIFO_RATE_EN_SHIFT 20
119#define CPSW_TC_NUM 4
120#define CPSW_FIFO_SHAPERS_NUM (CPSW_TC_NUM - 1)
121#define CPSW_PCT_MASK 0x7f
122
123#define CPSW_RX_VLAN_ENCAP_HDR_PRIO_SHIFT 29
124#define CPSW_RX_VLAN_ENCAP_HDR_PRIO_MSK GENMASK(2, 0)
125#define CPSW_RX_VLAN_ENCAP_HDR_VID_SHIFT 16
126#define CPSW_RX_VLAN_ENCAP_HDR_PKT_TYPE_SHIFT 8
127#define CPSW_RX_VLAN_ENCAP_HDR_PKT_TYPE_MSK GENMASK(1, 0)
128enum {
129 CPSW_RX_VLAN_ENCAP_HDR_PKT_VLAN_TAG = 0,
130 CPSW_RX_VLAN_ENCAP_HDR_PKT_RESERV,
131 CPSW_RX_VLAN_ENCAP_HDR_PKT_PRIO_TAG,
132 CPSW_RX_VLAN_ENCAP_HDR_PKT_UNTAG,
133};
134
135struct cpsw_wr_regs {
136 u32 id_ver;
137 u32 soft_reset;
138 u32 control;
139 u32 int_control;
140 u32 rx_thresh_en;
141 u32 rx_en;
142 u32 tx_en;
143 u32 misc_en;
144 u32 mem_allign1[8];
145 u32 rx_thresh_stat;
146 u32 rx_stat;
147 u32 tx_stat;
148 u32 misc_stat;
149 u32 mem_allign2[8];
150 u32 rx_imax;
151 u32 tx_imax;
152
153};
154
155struct cpsw_ss_regs {
156 u32 id_ver;
157 u32 control;
158 u32 soft_reset;
159 u32 stat_port_en;
160 u32 ptype;
161 u32 soft_idle;
162 u32 thru_rate;
163 u32 gap_thresh;
164 u32 tx_start_wds;
165 u32 flow_control;
166 u32 vlan_ltype;
167 u32 ts_ltype;
168 u32 dlr_ltype;
169};
170
171/* CPSW_PORT_V1 */
172#define CPSW1_MAX_BLKS 0x00 /* Maximum FIFO Blocks */
173#define CPSW1_BLK_CNT 0x04 /* FIFO Block Usage Count (Read Only) */
174#define CPSW1_TX_IN_CTL 0x08 /* Transmit FIFO Control */
175#define CPSW1_PORT_VLAN 0x0c /* VLAN Register */
176#define CPSW1_TX_PRI_MAP 0x10 /* Tx Header Priority to Switch Pri Mapping */
177#define CPSW1_TS_CTL 0x14 /* Time Sync Control */
178#define CPSW1_TS_SEQ_LTYPE 0x18 /* Time Sync Sequence ID Offset and Msg Type */
179#define CPSW1_TS_VLAN 0x1c /* Time Sync VLAN1 and VLAN2 */
180
181/* CPSW_PORT_V2 */
182#define CPSW2_CONTROL 0x00 /* Control Register */
183#define CPSW2_MAX_BLKS 0x08 /* Maximum FIFO Blocks */
184#define CPSW2_BLK_CNT 0x0c /* FIFO Block Usage Count (Read Only) */
185#define CPSW2_TX_IN_CTL 0x10 /* Transmit FIFO Control */
186#define CPSW2_PORT_VLAN 0x14 /* VLAN Register */
187#define CPSW2_TX_PRI_MAP 0x18 /* Tx Header Priority to Switch Pri Mapping */
188#define CPSW2_TS_SEQ_MTYPE 0x1c /* Time Sync Sequence ID Offset and Msg Type */
189
190/* CPSW_PORT_V1 and V2 */
191#define SA_LO 0x20 /* CPGMAC_SL Source Address Low */
192#define SA_HI 0x24 /* CPGMAC_SL Source Address High */
193#define SEND_PERCENT 0x28 /* Transmit Queue Send Percentages */
194
195/* CPSW_PORT_V2 only */
196#define RX_DSCP_PRI_MAP0 0x30 /* Rx DSCP Priority to Rx Packet Mapping */
197#define RX_DSCP_PRI_MAP1 0x34 /* Rx DSCP Priority to Rx Packet Mapping */
198#define RX_DSCP_PRI_MAP2 0x38 /* Rx DSCP Priority to Rx Packet Mapping */
199#define RX_DSCP_PRI_MAP3 0x3c /* Rx DSCP Priority to Rx Packet Mapping */
200#define RX_DSCP_PRI_MAP4 0x40 /* Rx DSCP Priority to Rx Packet Mapping */
201#define RX_DSCP_PRI_MAP5 0x44 /* Rx DSCP Priority to Rx Packet Mapping */
202#define RX_DSCP_PRI_MAP6 0x48 /* Rx DSCP Priority to Rx Packet Mapping */
203#define RX_DSCP_PRI_MAP7 0x4c /* Rx DSCP Priority to Rx Packet Mapping */
204
205/* Bit definitions for the CPSW2_CONTROL register */
206#define PASS_PRI_TAGGED BIT(24) /* Pass Priority Tagged */
207#define VLAN_LTYPE2_EN BIT(21) /* VLAN LTYPE 2 enable */
208#define VLAN_LTYPE1_EN BIT(20) /* VLAN LTYPE 1 enable */
209#define DSCP_PRI_EN BIT(16) /* DSCP Priority Enable */
210#define TS_107 BIT(15) /* Tyme Sync Dest IP Address 107 */
211#define TS_320 BIT(14) /* Time Sync Dest Port 320 enable */
212#define TS_319 BIT(13) /* Time Sync Dest Port 319 enable */
213#define TS_132 BIT(12) /* Time Sync Dest IP Addr 132 enable */
214#define TS_131 BIT(11) /* Time Sync Dest IP Addr 131 enable */
215#define TS_130 BIT(10) /* Time Sync Dest IP Addr 130 enable */
216#define TS_129 BIT(9) /* Time Sync Dest IP Addr 129 enable */
217#define TS_TTL_NONZERO BIT(8) /* Time Sync Time To Live Non-zero enable */
218#define TS_ANNEX_F_EN BIT(6) /* Time Sync Annex F enable */
219#define TS_ANNEX_D_EN BIT(4) /* Time Sync Annex D enable */
220#define TS_LTYPE2_EN BIT(3) /* Time Sync LTYPE 2 enable */
221#define TS_LTYPE1_EN BIT(2) /* Time Sync LTYPE 1 enable */
222#define TS_TX_EN BIT(1) /* Time Sync Transmit Enable */
223#define TS_RX_EN BIT(0) /* Time Sync Receive Enable */
224
225#define CTRL_V2_TS_BITS \
226 (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
227 TS_TTL_NONZERO | TS_ANNEX_D_EN | TS_LTYPE1_EN | VLAN_LTYPE1_EN)
228
229#define CTRL_V2_ALL_TS_MASK (CTRL_V2_TS_BITS | TS_TX_EN | TS_RX_EN)
230#define CTRL_V2_TX_TS_BITS (CTRL_V2_TS_BITS | TS_TX_EN)
231#define CTRL_V2_RX_TS_BITS (CTRL_V2_TS_BITS | TS_RX_EN)
232
233
234#define CTRL_V3_TS_BITS \
235 (TS_107 | TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
236 TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\
237 TS_LTYPE1_EN | VLAN_LTYPE1_EN)
238
239#define CTRL_V3_ALL_TS_MASK (CTRL_V3_TS_BITS | TS_TX_EN | TS_RX_EN)
240#define CTRL_V3_TX_TS_BITS (CTRL_V3_TS_BITS | TS_TX_EN)
241#define CTRL_V3_RX_TS_BITS (CTRL_V3_TS_BITS | TS_RX_EN)
242
243/* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */
244#define TS_SEQ_ID_OFFSET_SHIFT (16) /* Time Sync Sequence ID Offset */
245#define TS_SEQ_ID_OFFSET_MASK (0x3f)
246#define TS_MSG_TYPE_EN_SHIFT (0) /* Time Sync Message Type Enable */
247#define TS_MSG_TYPE_EN_MASK (0xffff)
248
249/* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
250#define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3))
251
252/* Bit definitions for the CPSW1_TS_CTL register */
253#define CPSW_V1_TS_RX_EN BIT(0)
254#define CPSW_V1_TS_TX_EN BIT(4)
255#define CPSW_V1_MSG_TYPE_OFS 16
256
257/* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */
258#define CPSW_V1_SEQ_ID_OFS_SHIFT 16
259
260#define CPSW_MAX_BLKS_TX 15
261#define CPSW_MAX_BLKS_TX_SHIFT 4
262#define CPSW_MAX_BLKS_RX 5
263
264struct cpsw_host_regs {
265 u32 max_blks;
266 u32 blk_cnt;
267 u32 tx_in_ctl;
268 u32 port_vlan;
269 u32 tx_pri_map;
270 u32 cpdma_tx_pri_map;
271 u32 cpdma_rx_chan_map;
272};
273
274struct cpsw_slave_data {
275 struct device_node *phy_node;
276 char phy_id[MII_BUS_ID_SIZE];
277 int phy_if;
278 u8 mac_addr[ETH_ALEN];
279 u16 dual_emac_res_vlan; /* Reserved VLAN for DualEMAC */
280 struct phy *ifphy;
281};
282
283struct cpsw_platform_data {
284 struct cpsw_slave_data *slave_data;
285 u32 ss_reg_ofs; /* Subsystem control register offset */
286 u32 channels; /* number of cpdma channels (symmetric) */
287 u32 slaves; /* number of slave cpgmac ports */
288 u32 active_slave; /* time stamping, ethtool and SIOCGMIIPHY slave */
289 u32 ale_entries; /* ale table size */
290 u32 bd_ram_size; /*buffer descriptor ram size */
291 u32 mac_control; /* Mac control register */
292 u16 default_vlan; /* Def VLAN for ALE lookup in VLAN aware mode*/
293 bool dual_emac; /* Enable Dual EMAC mode */
294};
295
296struct cpsw_slave {
297 void __iomem *regs;
298 int slave_num;
299 u32 mac_control;
300 struct cpsw_slave_data *data;
301 struct phy_device *phy;
302 struct net_device *ndev;
303 u32 port_vlan;
304 struct cpsw_sl *mac_sl;
305};
306
307static inline u32 slave_read(struct cpsw_slave *slave, u32 offset)
308{
309 return readl_relaxed(slave->regs + offset);
310}
311
312static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset)
313{
314 writel_relaxed(val, slave->regs + offset);
315}
316
317struct cpsw_vector {
318 struct cpdma_chan *ch;
319 int budget;
320};
321
322struct cpsw_common {
323 struct device *dev;
324 struct cpsw_platform_data data;
325 struct napi_struct napi_rx;
326 struct napi_struct napi_tx;
327 struct cpsw_ss_regs __iomem *regs;
328 struct cpsw_wr_regs __iomem *wr_regs;
329 u8 __iomem *hw_stats;
330 struct cpsw_host_regs __iomem *host_port_regs;
331 u32 version;
332 u32 coal_intvl;
333 u32 bus_freq_mhz;
334 int rx_packet_max;
335 int descs_pool_size;
336 struct cpsw_slave *slaves;
337 struct cpdma_ctlr *dma;
338 struct cpsw_vector txv[CPSW_MAX_QUEUES];
339 struct cpsw_vector rxv[CPSW_MAX_QUEUES];
340 struct cpsw_ale *ale;
341 bool quirk_irq;
342 bool rx_irq_disabled;
343 bool tx_irq_disabled;
344 u32 irqs_table[IRQ_NUM];
345 struct cpts *cpts;
346 int rx_ch_num, tx_ch_num;
347 int speed;
348 int usage_count;
349};
350
351struct cpsw_priv {
352 struct net_device *ndev;
353 struct device *dev;
354 u32 msg_enable;
355 u8 mac_addr[ETH_ALEN];
356 bool rx_pause;
357 bool tx_pause;
358 bool mqprio_hw;
359 int fifo_bw[CPSW_TC_NUM];
360 int shp_cfg_speed;
361 int tx_ts_enabled;
362 int rx_ts_enabled;
363 u32 emac_port;
364 struct cpsw_common *cpsw;
365};
366
367#define ndev_to_cpsw(ndev) (((struct cpsw_priv *)netdev_priv(ndev))->cpsw)
368#define napi_to_cpsw(napi) container_of(napi, struct cpsw_common, napi)
369
370#define cpsw_slave_index(cpsw, priv) \
371 ((cpsw->data.dual_emac) ? priv->emac_port : \
372 cpsw->data.active_slave)
373
374static inline int cpsw_get_slave_port(u32 slave_num)
375{
376 return slave_num + 1;
377}
378
379struct addr_sync_ctx {
380 struct net_device *ndev;
381 const u8 *addr; /* address to be synched */
382 int consumed; /* number of address instances */
383 int flush; /* flush flag */
384};
385
386int cpsw_init_common(struct cpsw_common *cpsw, void __iomem *ss_regs,
387 int ale_ageout, phys_addr_t desc_mem_phys,
388 int descs_pool_size);
389void cpsw_split_res(struct cpsw_common *cpsw);
390int cpsw_fill_rx_channels(struct cpsw_priv *priv);
391void cpsw_intr_enable(struct cpsw_common *cpsw);
392void cpsw_intr_disable(struct cpsw_common *cpsw);
393void cpsw_tx_handler(void *token, int len, int status);
394
395/* ethtool */
396u32 cpsw_get_msglevel(struct net_device *ndev);
397void cpsw_set_msglevel(struct net_device *ndev, u32 value);
398int cpsw_get_coalesce(struct net_device *ndev, struct ethtool_coalesce *coal);
399int cpsw_set_coalesce(struct net_device *ndev, struct ethtool_coalesce *coal);
400int cpsw_get_sset_count(struct net_device *ndev, int sset);
401void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data);
402void cpsw_get_ethtool_stats(struct net_device *ndev,
403 struct ethtool_stats *stats, u64 *data);
404void cpsw_get_pauseparam(struct net_device *ndev,
405 struct ethtool_pauseparam *pause);
406void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol);
407int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol);
408int cpsw_get_regs_len(struct net_device *ndev);
409void cpsw_get_regs(struct net_device *ndev, struct ethtool_regs *regs, void *p);
410int cpsw_ethtool_op_begin(struct net_device *ndev);
411void cpsw_ethtool_op_complete(struct net_device *ndev);
412void cpsw_get_channels(struct net_device *ndev, struct ethtool_channels *ch);
413int cpsw_get_link_ksettings(struct net_device *ndev,
414 struct ethtool_link_ksettings *ecmd);
415int cpsw_set_link_ksettings(struct net_device *ndev,
416 const struct ethtool_link_ksettings *ecmd);
417int cpsw_get_eee(struct net_device *ndev, struct ethtool_eee *edata);
418int cpsw_set_eee(struct net_device *ndev, struct ethtool_eee *edata);
419int cpsw_nway_reset(struct net_device *ndev);
420void cpsw_get_ringparam(struct net_device *ndev,
421 struct ethtool_ringparam *ering);
422int cpsw_set_ringparam(struct net_device *ndev,
423 struct ethtool_ringparam *ering);
424int cpsw_set_channels_common(struct net_device *ndev,
425 struct ethtool_channels *chs,
426 cpdma_handler_fn rx_handler);
427int cpsw_get_ts_info(struct net_device *ndev, struct ethtool_ts_info *info);
428
429#endif /* DRIVERS_NET_ETHERNET_TI_CPSW_PRIV_H_ */
diff --git a/drivers/net/ethernet/ti/cpsw_sl.c b/drivers/net/ethernet/ti/cpsw_sl.c
new file mode 100644
index 000000000000..0c7531cb0f39
--- /dev/null
+++ b/drivers/net/ethernet/ti/cpsw_sl.c
@@ -0,0 +1,328 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Texas Instruments Ethernet Switch media-access-controller (MAC) submodule/
4 * Ethernet MAC Sliver (CPGMAC_SL)
5 *
6 * Copyright (C) 2019 Texas Instruments
7 *
8 */
9
10#include <linux/delay.h>
11#include <linux/io.h>
12#include <linux/kernel.h>
13
14#include "cpsw_sl.h"
15
16#define CPSW_SL_REG_NOTUSED U16_MAX
17
18static const u16 cpsw_sl_reg_map_cpsw[] = {
19 [CPSW_SL_IDVER] = 0x00,
20 [CPSW_SL_MACCONTROL] = 0x04,
21 [CPSW_SL_MACSTATUS] = 0x08,
22 [CPSW_SL_SOFT_RESET] = 0x0c,
23 [CPSW_SL_RX_MAXLEN] = 0x10,
24 [CPSW_SL_BOFFTEST] = 0x14,
25 [CPSW_SL_RX_PAUSE] = 0x18,
26 [CPSW_SL_TX_PAUSE] = 0x1c,
27 [CPSW_SL_EMCONTROL] = 0x20,
28 [CPSW_SL_RX_PRI_MAP] = 0x24,
29 [CPSW_SL_TX_GAP] = 0x28,
30};
31
32static const u16 cpsw_sl_reg_map_66ak2hk[] = {
33 [CPSW_SL_IDVER] = 0x00,
34 [CPSW_SL_MACCONTROL] = 0x04,
35 [CPSW_SL_MACSTATUS] = 0x08,
36 [CPSW_SL_SOFT_RESET] = 0x0c,
37 [CPSW_SL_RX_MAXLEN] = 0x10,
38 [CPSW_SL_BOFFTEST] = CPSW_SL_REG_NOTUSED,
39 [CPSW_SL_RX_PAUSE] = 0x18,
40 [CPSW_SL_TX_PAUSE] = 0x1c,
41 [CPSW_SL_EMCONTROL] = 0x20,
42 [CPSW_SL_RX_PRI_MAP] = 0x24,
43 [CPSW_SL_TX_GAP] = CPSW_SL_REG_NOTUSED,
44};
45
46static const u16 cpsw_sl_reg_map_66ak2x_xgbe[] = {
47 [CPSW_SL_IDVER] = 0x00,
48 [CPSW_SL_MACCONTROL] = 0x04,
49 [CPSW_SL_MACSTATUS] = 0x08,
50 [CPSW_SL_SOFT_RESET] = 0x0c,
51 [CPSW_SL_RX_MAXLEN] = 0x10,
52 [CPSW_SL_BOFFTEST] = CPSW_SL_REG_NOTUSED,
53 [CPSW_SL_RX_PAUSE] = 0x18,
54 [CPSW_SL_TX_PAUSE] = 0x1c,
55 [CPSW_SL_EMCONTROL] = 0x20,
56 [CPSW_SL_RX_PRI_MAP] = CPSW_SL_REG_NOTUSED,
57 [CPSW_SL_TX_GAP] = 0x28,
58};
59
60static const u16 cpsw_sl_reg_map_66ak2elg_am65[] = {
61 [CPSW_SL_IDVER] = CPSW_SL_REG_NOTUSED,
62 [CPSW_SL_MACCONTROL] = 0x00,
63 [CPSW_SL_MACSTATUS] = 0x04,
64 [CPSW_SL_SOFT_RESET] = 0x08,
65 [CPSW_SL_RX_MAXLEN] = CPSW_SL_REG_NOTUSED,
66 [CPSW_SL_BOFFTEST] = 0x0c,
67 [CPSW_SL_RX_PAUSE] = 0x10,
68 [CPSW_SL_TX_PAUSE] = 0x40,
69 [CPSW_SL_EMCONTROL] = 0x70,
70 [CPSW_SL_RX_PRI_MAP] = CPSW_SL_REG_NOTUSED,
71 [CPSW_SL_TX_GAP] = 0x74,
72};
73
74#define CPSW_SL_SOFT_RESET_BIT BIT(0)
75
76#define CPSW_SL_STATUS_PN_IDLE BIT(31)
77#define CPSW_SL_AM65_STATUS_PN_E_IDLE BIT(30)
78#define CPSW_SL_AM65_STATUS_PN_P_IDLE BIT(29)
79#define CPSW_SL_AM65_STATUS_PN_TX_IDLE BIT(28)
80
81#define CPSW_SL_STATUS_IDLE_MASK_BASE (CPSW_SL_STATUS_PN_IDLE)
82
83#define CPSW_SL_STATUS_IDLE_MASK_K3 \
84 (CPSW_SL_STATUS_IDLE_MASK_BASE | CPSW_SL_AM65_STATUS_PN_E_IDLE | \
85 CPSW_SL_AM65_STATUS_PN_P_IDLE | CPSW_SL_AM65_STATUS_PN_TX_IDLE)
86
87#define CPSW_SL_CTL_FUNC_BASE \
88 (CPSW_SL_CTL_FULLDUPLEX |\
89 CPSW_SL_CTL_LOOPBACK |\
90 CPSW_SL_CTL_RX_FLOW_EN |\
91 CPSW_SL_CTL_TX_FLOW_EN |\
92 CPSW_SL_CTL_GMII_EN |\
93 CPSW_SL_CTL_TX_PACE |\
94 CPSW_SL_CTL_GIG |\
95 CPSW_SL_CTL_CMD_IDLE |\
96 CPSW_SL_CTL_IFCTL_A |\
97 CPSW_SL_CTL_IFCTL_B |\
98 CPSW_SL_CTL_GIG_FORCE |\
99 CPSW_SL_CTL_EXT_EN |\
100 CPSW_SL_CTL_RX_CEF_EN |\
101 CPSW_SL_CTL_RX_CSF_EN |\
102 CPSW_SL_CTL_RX_CMF_EN)
103
104struct cpsw_sl {
105 struct device *dev;
106 void __iomem *sl_base;
107 const u16 *regs;
108 u32 control_features;
109 u32 idle_mask;
110};
111
112struct cpsw_sl_dev_id {
113 const char *device_id;
114 const u16 *regs;
115 const u32 control_features;
116 const u32 regs_offset;
117 const u32 idle_mask;
118};
119
120static const struct cpsw_sl_dev_id cpsw_sl_id_match[] = {
121 {
122 .device_id = "cpsw",
123 .regs = cpsw_sl_reg_map_cpsw,
124 .control_features = CPSW_SL_CTL_FUNC_BASE |
125 CPSW_SL_CTL_MTEST |
126 CPSW_SL_CTL_TX_SHORT_GAP_EN |
127 CPSW_SL_CTL_TX_SG_LIM_EN,
128 .idle_mask = CPSW_SL_STATUS_IDLE_MASK_BASE,
129 },
130 {
131 .device_id = "66ak2hk",
132 .regs = cpsw_sl_reg_map_66ak2hk,
133 .control_features = CPSW_SL_CTL_FUNC_BASE |
134 CPSW_SL_CTL_TX_SHORT_GAP_EN,
135 .idle_mask = CPSW_SL_STATUS_IDLE_MASK_BASE,
136 },
137 {
138 .device_id = "66ak2x_xgbe",
139 .regs = cpsw_sl_reg_map_66ak2x_xgbe,
140 .control_features = CPSW_SL_CTL_FUNC_BASE |
141 CPSW_SL_CTL_XGIG |
142 CPSW_SL_CTL_TX_SHORT_GAP_EN |
143 CPSW_SL_CTL_CRC_TYPE |
144 CPSW_SL_CTL_XGMII_EN,
145 .idle_mask = CPSW_SL_STATUS_IDLE_MASK_BASE,
146 },
147 {
148 .device_id = "66ak2el",
149 .regs = cpsw_sl_reg_map_66ak2elg_am65,
150 .regs_offset = 0x330,
151 .control_features = CPSW_SL_CTL_FUNC_BASE |
152 CPSW_SL_CTL_MTEST |
153 CPSW_SL_CTL_TX_SHORT_GAP_EN |
154 CPSW_SL_CTL_CRC_TYPE |
155 CPSW_SL_CTL_EXT_EN_RX_FLO |
156 CPSW_SL_CTL_EXT_EN_TX_FLO |
157 CPSW_SL_CTL_TX_SG_LIM_EN,
158 .idle_mask = CPSW_SL_STATUS_IDLE_MASK_BASE,
159 },
160 {
161 .device_id = "66ak2g",
162 .regs = cpsw_sl_reg_map_66ak2elg_am65,
163 .regs_offset = 0x330,
164 .control_features = CPSW_SL_CTL_FUNC_BASE |
165 CPSW_SL_CTL_MTEST |
166 CPSW_SL_CTL_CRC_TYPE |
167 CPSW_SL_CTL_EXT_EN_RX_FLO |
168 CPSW_SL_CTL_EXT_EN_TX_FLO,
169 },
170 {
171 .device_id = "am65",
172 .regs = cpsw_sl_reg_map_66ak2elg_am65,
173 .regs_offset = 0x330,
174 .control_features = CPSW_SL_CTL_FUNC_BASE |
175 CPSW_SL_CTL_MTEST |
176 CPSW_SL_CTL_XGIG |
177 CPSW_SL_CTL_TX_SHORT_GAP_EN |
178 CPSW_SL_CTL_CRC_TYPE |
179 CPSW_SL_CTL_XGMII_EN |
180 CPSW_SL_CTL_EXT_EN_RX_FLO |
181 CPSW_SL_CTL_EXT_EN_TX_FLO |
182 CPSW_SL_CTL_TX_SG_LIM_EN |
183 CPSW_SL_CTL_EXT_EN_XGIG,
184 .idle_mask = CPSW_SL_STATUS_IDLE_MASK_K3,
185 },
186 { },
187};
188
189u32 cpsw_sl_reg_read(struct cpsw_sl *sl, enum cpsw_sl_regs reg)
190{
191 int val;
192
193 if (sl->regs[reg] == CPSW_SL_REG_NOTUSED) {
194 dev_err(sl->dev, "cpsw_sl: not sup r reg: %04X\n",
195 sl->regs[reg]);
196 return 0;
197 }
198
199 val = readl(sl->sl_base + sl->regs[reg]);
200 dev_dbg(sl->dev, "cpsw_sl: reg: %04X r 0x%08X\n", sl->regs[reg], val);
201 return val;
202}
203
204void cpsw_sl_reg_write(struct cpsw_sl *sl, enum cpsw_sl_regs reg, u32 val)
205{
206 if (sl->regs[reg] == CPSW_SL_REG_NOTUSED) {
207 dev_err(sl->dev, "cpsw_sl: not sup w reg: %04X\n",
208 sl->regs[reg]);
209 return;
210 }
211
212 dev_dbg(sl->dev, "cpsw_sl: reg: %04X w 0x%08X\n", sl->regs[reg], val);
213 writel(val, sl->sl_base + sl->regs[reg]);
214}
215
216static const struct cpsw_sl_dev_id *cpsw_sl_match_id(
217 const struct cpsw_sl_dev_id *id,
218 const char *device_id)
219{
220 if (!id || !device_id)
221 return NULL;
222
223 while (id->device_id) {
224 if (strcmp(device_id, id->device_id) == 0)
225 return id;
226 id++;
227 }
228 return NULL;
229}
230
231struct cpsw_sl *cpsw_sl_get(const char *device_id, struct device *dev,
232 void __iomem *sl_base)
233{
234 const struct cpsw_sl_dev_id *sl_dev_id;
235 struct cpsw_sl *sl;
236
237 sl = devm_kzalloc(dev, sizeof(struct cpsw_sl), GFP_KERNEL);
238 if (!sl)
239 return ERR_PTR(-ENOMEM);
240 sl->dev = dev;
241 sl->sl_base = sl_base;
242
243 sl_dev_id = cpsw_sl_match_id(cpsw_sl_id_match, device_id);
244 if (!sl_dev_id) {
245 dev_err(sl->dev, "cpsw_sl: dev_id %s not found.\n", device_id);
246 return ERR_PTR(-EINVAL);
247 }
248 sl->regs = sl_dev_id->regs;
249 sl->control_features = sl_dev_id->control_features;
250 sl->idle_mask = sl_dev_id->idle_mask;
251 sl->sl_base += sl_dev_id->regs_offset;
252
253 return sl;
254}
255
256void cpsw_sl_reset(struct cpsw_sl *sl, unsigned long tmo)
257{
258 unsigned long timeout = jiffies + msecs_to_jiffies(tmo);
259
260 /* Set the soft reset bit */
261 cpsw_sl_reg_write(sl, CPSW_SL_SOFT_RESET, CPSW_SL_SOFT_RESET_BIT);
262
263 /* Wait for the bit to clear */
264 do {
265 usleep_range(100, 200);
266 } while ((cpsw_sl_reg_read(sl, CPSW_SL_SOFT_RESET) &
267 CPSW_SL_SOFT_RESET_BIT) &&
268 time_after(timeout, jiffies));
269
270 if (cpsw_sl_reg_read(sl, CPSW_SL_SOFT_RESET) & CPSW_SL_SOFT_RESET_BIT)
271 dev_err(sl->dev, "cpsw_sl failed to soft-reset.\n");
272}
273
274u32 cpsw_sl_ctl_set(struct cpsw_sl *sl, u32 ctl_funcs)
275{
276 u32 val;
277
278 if (ctl_funcs & ~sl->control_features) {
279 dev_err(sl->dev, "cpsw_sl: unsupported func 0x%08X\n",
280 ctl_funcs & (~sl->control_features));
281 return -EINVAL;
282 }
283
284 val = cpsw_sl_reg_read(sl, CPSW_SL_MACCONTROL);
285 val |= ctl_funcs;
286 cpsw_sl_reg_write(sl, CPSW_SL_MACCONTROL, val);
287
288 return 0;
289}
290
291u32 cpsw_sl_ctl_clr(struct cpsw_sl *sl, u32 ctl_funcs)
292{
293 u32 val;
294
295 if (ctl_funcs & ~sl->control_features) {
296 dev_err(sl->dev, "cpsw_sl: unsupported func 0x%08X\n",
297 ctl_funcs & (~sl->control_features));
298 return -EINVAL;
299 }
300
301 val = cpsw_sl_reg_read(sl, CPSW_SL_MACCONTROL);
302 val &= ~ctl_funcs;
303 cpsw_sl_reg_write(sl, CPSW_SL_MACCONTROL, val);
304
305 return 0;
306}
307
308void cpsw_sl_ctl_reset(struct cpsw_sl *sl)
309{
310 cpsw_sl_reg_write(sl, CPSW_SL_MACCONTROL, 0);
311}
312
313int cpsw_sl_wait_for_idle(struct cpsw_sl *sl, unsigned long tmo)
314{
315 unsigned long timeout = jiffies + msecs_to_jiffies(tmo);
316
317 do {
318 usleep_range(100, 200);
319 } while (!(cpsw_sl_reg_read(sl, CPSW_SL_MACSTATUS) &
320 sl->idle_mask) && time_after(timeout, jiffies));
321
322 if (!(cpsw_sl_reg_read(sl, CPSW_SL_MACSTATUS) & sl->idle_mask)) {
323 dev_err(sl->dev, "cpsw_sl failed to soft-reset.\n");
324 return -ETIMEDOUT;
325 }
326
327 return 0;
328}
diff --git a/drivers/net/ethernet/ti/cpsw_sl.h b/drivers/net/ethernet/ti/cpsw_sl.h
new file mode 100644
index 000000000000..a6d06a5a420f
--- /dev/null
+++ b/drivers/net/ethernet/ti/cpsw_sl.h
@@ -0,0 +1,73 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Texas Instruments Ethernet Switch media-access-controller (MAC) submodule/
4 * Ethernet MAC Sliver (CPGMAC_SL) APIs
5 *
6 * Copyright (C) 2019 Texas Instruments
7 *
8 */
9
10#ifndef __TI_CPSW_SL_H__
11#define __TI_CPSW_SL_H__
12
13#include <linux/device.h>
14
15enum cpsw_sl_regs {
16 CPSW_SL_IDVER,
17 CPSW_SL_MACCONTROL,
18 CPSW_SL_MACSTATUS,
19 CPSW_SL_SOFT_RESET,
20 CPSW_SL_RX_MAXLEN,
21 CPSW_SL_BOFFTEST,
22 CPSW_SL_RX_PAUSE,
23 CPSW_SL_TX_PAUSE,
24 CPSW_SL_EMCONTROL,
25 CPSW_SL_RX_PRI_MAP,
26 CPSW_SL_TX_GAP,
27};
28
29enum {
30 CPSW_SL_CTL_FULLDUPLEX = BIT(0), /* Full Duplex mode */
31 CPSW_SL_CTL_LOOPBACK = BIT(1), /* Loop Back Mode */
32 CPSW_SL_CTL_MTEST = BIT(2), /* Manufacturing Test mode */
33 CPSW_SL_CTL_RX_FLOW_EN = BIT(3), /* Receive Flow Control Enable */
34 CPSW_SL_CTL_TX_FLOW_EN = BIT(4), /* Transmit Flow Control Enable */
35 CPSW_SL_CTL_GMII_EN = BIT(5), /* GMII Enable */
36 CPSW_SL_CTL_TX_PACE = BIT(6), /* Transmit Pacing Enable */
37 CPSW_SL_CTL_GIG = BIT(7), /* Gigabit Mode */
38 CPSW_SL_CTL_XGIG = BIT(8), /* 10 Gigabit Mode */
39 CPSW_SL_CTL_TX_SHORT_GAP_EN = BIT(10), /* Transmit Short Gap Enable */
40 CPSW_SL_CTL_CMD_IDLE = BIT(11), /* Command Idle */
41 CPSW_SL_CTL_CRC_TYPE = BIT(12), /* Port CRC Type */
42 CPSW_SL_CTL_XGMII_EN = BIT(13), /* XGMII Enable */
43 CPSW_SL_CTL_IFCTL_A = BIT(15), /* Interface Control A */
44 CPSW_SL_CTL_IFCTL_B = BIT(16), /* Interface Control B */
45 CPSW_SL_CTL_GIG_FORCE = BIT(17), /* Gigabit Mode Force */
46 CPSW_SL_CTL_EXT_EN = BIT(18), /* External Control Enable */
47 CPSW_SL_CTL_EXT_EN_RX_FLO = BIT(19), /* Ext RX Flow Control Enable */
48 CPSW_SL_CTL_EXT_EN_TX_FLO = BIT(20), /* Ext TX Flow Control Enable */
49 CPSW_SL_CTL_TX_SG_LIM_EN = BIT(21), /* TXt Short Gap Limit Enable */
50 CPSW_SL_CTL_RX_CEF_EN = BIT(22), /* RX Copy Error Frames Enable */
51 CPSW_SL_CTL_RX_CSF_EN = BIT(23), /* RX Copy Short Frames Enable */
52 CPSW_SL_CTL_RX_CMF_EN = BIT(24), /* RX Copy MAC Control Frames Enable */
53 CPSW_SL_CTL_EXT_EN_XGIG = BIT(25), /* Ext XGIG Control En, k3 only */
54
55 CPSW_SL_CTL_FUNCS_COUNT
56};
57
58struct cpsw_sl;
59
60struct cpsw_sl *cpsw_sl_get(const char *device_id, struct device *dev,
61 void __iomem *sl_base);
62
63void cpsw_sl_reset(struct cpsw_sl *sl, unsigned long tmo);
64
65u32 cpsw_sl_ctl_set(struct cpsw_sl *sl, u32 ctl_funcs);
66u32 cpsw_sl_ctl_clr(struct cpsw_sl *sl, u32 ctl_funcs);
67void cpsw_sl_ctl_reset(struct cpsw_sl *sl);
68int cpsw_sl_wait_for_idle(struct cpsw_sl *sl, unsigned long tmo);
69
70u32 cpsw_sl_reg_read(struct cpsw_sl *sl, enum cpsw_sl_regs reg);
71void cpsw_sl_reg_write(struct cpsw_sl *sl, enum cpsw_sl_regs reg, u32 val);
72
73#endif /* __TI_CPSW_SL_H__ */
diff --git a/drivers/net/ethernet/ti/cpts.c b/drivers/net/ethernet/ti/cpts.c
index 2a9ba4acd7fa..e257018ada71 100644
--- a/drivers/net/ethernet/ti/cpts.c
+++ b/drivers/net/ethernet/ti/cpts.c
@@ -1,21 +1,9 @@
1// SPDX-License-Identifier: GPL-2.0+
1/* 2/*
2 * TI Common Platform Time Sync 3 * TI Common Platform Time Sync
3 * 4 *
4 * Copyright (C) 2012 Richard Cochran <richardcochran@gmail.com> 5 * Copyright (C) 2012 Richard Cochran <richardcochran@gmail.com>
5 * 6 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */ 7 */
20#include <linux/err.h> 8#include <linux/err.h>
21#include <linux/if.h> 9#include <linux/if.h>
diff --git a/drivers/net/ethernet/ti/cpts.h b/drivers/net/ethernet/ti/cpts.h
index d2c7decd59b6..024aab6af12f 100644
--- a/drivers/net/ethernet/ti/cpts.h
+++ b/drivers/net/ethernet/ti/cpts.h
@@ -1,21 +1,9 @@
1/* SPDX-License-Identifier: GPL-2.0+ */
1/* 2/*
2 * TI Common Platform Time Sync 3 * TI Common Platform Time Sync
3 * 4 *
4 * Copyright (C) 2012 Richard Cochran <richardcochran@gmail.com> 5 * Copyright (C) 2012 Richard Cochran <richardcochran@gmail.com>
5 * 6 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */ 7 */
20#ifndef _TI_CPTS_H_ 8#ifndef _TI_CPTS_H_
21#define _TI_CPTS_H_ 9#define _TI_CPTS_H_
diff --git a/drivers/net/ethernet/ti/davinci_cpdma.c b/drivers/net/ethernet/ti/davinci_cpdma.c
index 4236dcdd5634..35bf14d8e7af 100644
--- a/drivers/net/ethernet/ti/davinci_cpdma.c
+++ b/drivers/net/ethernet/ti/davinci_cpdma.c
@@ -1,16 +1,9 @@
1// SPDX-License-Identifier: GPL-2.0
1/* 2/*
2 * Texas Instruments CPDMA Driver 3 * Texas Instruments CPDMA Driver
3 * 4 *
4 * Copyright (C) 2010 Texas Instruments 5 * Copyright (C) 2010 Texas Instruments
5 * 6 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */ 7 */
15#include <linux/kernel.h> 8#include <linux/kernel.h>
16#include <linux/spinlock.h> 9#include <linux/spinlock.h>
@@ -527,7 +520,6 @@ struct cpdma_ctlr *cpdma_ctlr_create(struct cpdma_params *params)
527 ctlr->num_chan = CPDMA_MAX_CHANNELS; 520 ctlr->num_chan = CPDMA_MAX_CHANNELS;
528 return ctlr; 521 return ctlr;
529} 522}
530EXPORT_SYMBOL_GPL(cpdma_ctlr_create);
531 523
532int cpdma_ctlr_start(struct cpdma_ctlr *ctlr) 524int cpdma_ctlr_start(struct cpdma_ctlr *ctlr)
533{ 525{
@@ -588,7 +580,6 @@ int cpdma_ctlr_start(struct cpdma_ctlr *ctlr)
588 spin_unlock_irqrestore(&ctlr->lock, flags); 580 spin_unlock_irqrestore(&ctlr->lock, flags);
589 return 0; 581 return 0;
590} 582}
591EXPORT_SYMBOL_GPL(cpdma_ctlr_start);
592 583
593int cpdma_ctlr_stop(struct cpdma_ctlr *ctlr) 584int cpdma_ctlr_stop(struct cpdma_ctlr *ctlr)
594{ 585{
@@ -621,7 +612,6 @@ int cpdma_ctlr_stop(struct cpdma_ctlr *ctlr)
621 spin_unlock_irqrestore(&ctlr->lock, flags); 612 spin_unlock_irqrestore(&ctlr->lock, flags);
622 return 0; 613 return 0;
623} 614}
624EXPORT_SYMBOL_GPL(cpdma_ctlr_stop);
625 615
626int cpdma_ctlr_destroy(struct cpdma_ctlr *ctlr) 616int cpdma_ctlr_destroy(struct cpdma_ctlr *ctlr)
627{ 617{
@@ -639,7 +629,6 @@ int cpdma_ctlr_destroy(struct cpdma_ctlr *ctlr)
639 cpdma_desc_pool_destroy(ctlr); 629 cpdma_desc_pool_destroy(ctlr);
640 return ret; 630 return ret;
641} 631}
642EXPORT_SYMBOL_GPL(cpdma_ctlr_destroy);
643 632
644int cpdma_ctlr_int_ctrl(struct cpdma_ctlr *ctlr, bool enable) 633int cpdma_ctlr_int_ctrl(struct cpdma_ctlr *ctlr, bool enable)
645{ 634{
@@ -660,25 +649,21 @@ int cpdma_ctlr_int_ctrl(struct cpdma_ctlr *ctlr, bool enable)
660 spin_unlock_irqrestore(&ctlr->lock, flags); 649 spin_unlock_irqrestore(&ctlr->lock, flags);
661 return 0; 650 return 0;
662} 651}
663EXPORT_SYMBOL_GPL(cpdma_ctlr_int_ctrl);
664 652
665void cpdma_ctlr_eoi(struct cpdma_ctlr *ctlr, u32 value) 653void cpdma_ctlr_eoi(struct cpdma_ctlr *ctlr, u32 value)
666{ 654{
667 dma_reg_write(ctlr, CPDMA_MACEOIVECTOR, value); 655 dma_reg_write(ctlr, CPDMA_MACEOIVECTOR, value);
668} 656}
669EXPORT_SYMBOL_GPL(cpdma_ctlr_eoi);
670 657
671u32 cpdma_ctrl_rxchs_state(struct cpdma_ctlr *ctlr) 658u32 cpdma_ctrl_rxchs_state(struct cpdma_ctlr *ctlr)
672{ 659{
673 return dma_reg_read(ctlr, CPDMA_RXINTSTATMASKED); 660 return dma_reg_read(ctlr, CPDMA_RXINTSTATMASKED);
674} 661}
675EXPORT_SYMBOL_GPL(cpdma_ctrl_rxchs_state);
676 662
677u32 cpdma_ctrl_txchs_state(struct cpdma_ctlr *ctlr) 663u32 cpdma_ctrl_txchs_state(struct cpdma_ctlr *ctlr)
678{ 664{
679 return dma_reg_read(ctlr, CPDMA_TXINTSTATMASKED); 665 return dma_reg_read(ctlr, CPDMA_TXINTSTATMASKED);
680} 666}
681EXPORT_SYMBOL_GPL(cpdma_ctrl_txchs_state);
682 667
683static void cpdma_chan_set_descs(struct cpdma_ctlr *ctlr, 668static void cpdma_chan_set_descs(struct cpdma_ctlr *ctlr,
684 int rx, int desc_num, 669 int rx, int desc_num,
@@ -774,7 +759,6 @@ int cpdma_chan_split_pool(struct cpdma_ctlr *ctlr)
774 759
775 return 0; 760 return 0;
776} 761}
777EXPORT_SYMBOL_GPL(cpdma_chan_split_pool);
778 762
779 763
780/* cpdma_chan_set_weight - set weight of a channel in percentage. 764/* cpdma_chan_set_weight - set weight of a channel in percentage.
@@ -807,7 +791,6 @@ int cpdma_chan_set_weight(struct cpdma_chan *ch, int weight)
807 spin_unlock_irqrestore(&ctlr->lock, flags); 791 spin_unlock_irqrestore(&ctlr->lock, flags);
808 return ret; 792 return ret;
809} 793}
810EXPORT_SYMBOL_GPL(cpdma_chan_set_weight);
811 794
812/* cpdma_chan_get_min_rate - get minimum allowed rate for channel 795/* cpdma_chan_get_min_rate - get minimum allowed rate for channel
813 * Should be called before cpdma_chan_set_rate. 796 * Should be called before cpdma_chan_set_rate.
@@ -822,7 +805,6 @@ u32 cpdma_chan_get_min_rate(struct cpdma_ctlr *ctlr)
822 805
823 return DIV_ROUND_UP(divident, divisor); 806 return DIV_ROUND_UP(divident, divisor);
824} 807}
825EXPORT_SYMBOL_GPL(cpdma_chan_get_min_rate);
826 808
827/* cpdma_chan_set_rate - limits bandwidth for transmit channel. 809/* cpdma_chan_set_rate - limits bandwidth for transmit channel.
828 * The bandwidth * limited channels have to be in order beginning from lowest. 810 * The bandwidth * limited channels have to be in order beginning from lowest.
@@ -867,7 +849,6 @@ err:
867 spin_unlock_irqrestore(&ctlr->lock, flags); 849 spin_unlock_irqrestore(&ctlr->lock, flags);
868 return ret; 850 return ret;
869} 851}
870EXPORT_SYMBOL_GPL(cpdma_chan_set_rate);
871 852
872u32 cpdma_chan_get_rate(struct cpdma_chan *ch) 853u32 cpdma_chan_get_rate(struct cpdma_chan *ch)
873{ 854{
@@ -880,7 +861,6 @@ u32 cpdma_chan_get_rate(struct cpdma_chan *ch)
880 861
881 return rate; 862 return rate;
882} 863}
883EXPORT_SYMBOL_GPL(cpdma_chan_get_rate);
884 864
885struct cpdma_chan *cpdma_chan_create(struct cpdma_ctlr *ctlr, int chan_num, 865struct cpdma_chan *cpdma_chan_create(struct cpdma_ctlr *ctlr, int chan_num,
886 cpdma_handler_fn handler, int rx_type) 866 cpdma_handler_fn handler, int rx_type)
@@ -940,7 +920,6 @@ struct cpdma_chan *cpdma_chan_create(struct cpdma_ctlr *ctlr, int chan_num,
940 spin_unlock_irqrestore(&ctlr->lock, flags); 920 spin_unlock_irqrestore(&ctlr->lock, flags);
941 return chan; 921 return chan;
942} 922}
943EXPORT_SYMBOL_GPL(cpdma_chan_create);
944 923
945int cpdma_chan_get_rx_buf_num(struct cpdma_chan *chan) 924int cpdma_chan_get_rx_buf_num(struct cpdma_chan *chan)
946{ 925{
@@ -953,7 +932,6 @@ int cpdma_chan_get_rx_buf_num(struct cpdma_chan *chan)
953 932
954 return desc_num; 933 return desc_num;
955} 934}
956EXPORT_SYMBOL_GPL(cpdma_chan_get_rx_buf_num);
957 935
958int cpdma_chan_destroy(struct cpdma_chan *chan) 936int cpdma_chan_destroy(struct cpdma_chan *chan)
959{ 937{
@@ -975,7 +953,6 @@ int cpdma_chan_destroy(struct cpdma_chan *chan)
975 spin_unlock_irqrestore(&ctlr->lock, flags); 953 spin_unlock_irqrestore(&ctlr->lock, flags);
976 return 0; 954 return 0;
977} 955}
978EXPORT_SYMBOL_GPL(cpdma_chan_destroy);
979 956
980int cpdma_chan_get_stats(struct cpdma_chan *chan, 957int cpdma_chan_get_stats(struct cpdma_chan *chan,
981 struct cpdma_chan_stats *stats) 958 struct cpdma_chan_stats *stats)
@@ -988,7 +965,6 @@ int cpdma_chan_get_stats(struct cpdma_chan *chan,
988 spin_unlock_irqrestore(&chan->lock, flags); 965 spin_unlock_irqrestore(&chan->lock, flags);
989 return 0; 966 return 0;
990} 967}
991EXPORT_SYMBOL_GPL(cpdma_chan_get_stats);
992 968
993static void __cpdma_chan_submit(struct cpdma_chan *chan, 969static void __cpdma_chan_submit(struct cpdma_chan *chan,
994 struct cpdma_desc __iomem *desc) 970 struct cpdma_desc __iomem *desc)
@@ -1095,7 +1071,6 @@ unlock_ret:
1095 spin_unlock_irqrestore(&chan->lock, flags); 1071 spin_unlock_irqrestore(&chan->lock, flags);
1096 return ret; 1072 return ret;
1097} 1073}
1098EXPORT_SYMBOL_GPL(cpdma_chan_submit);
1099 1074
1100bool cpdma_check_free_tx_desc(struct cpdma_chan *chan) 1075bool cpdma_check_free_tx_desc(struct cpdma_chan *chan)
1101{ 1076{
@@ -1110,7 +1085,6 @@ bool cpdma_check_free_tx_desc(struct cpdma_chan *chan)
1110 spin_unlock_irqrestore(&chan->lock, flags); 1085 spin_unlock_irqrestore(&chan->lock, flags);
1111 return free_tx_desc; 1086 return free_tx_desc;
1112} 1087}
1113EXPORT_SYMBOL_GPL(cpdma_check_free_tx_desc);
1114 1088
1115static void __cpdma_chan_free(struct cpdma_chan *chan, 1089static void __cpdma_chan_free(struct cpdma_chan *chan,
1116 struct cpdma_desc __iomem *desc, 1090 struct cpdma_desc __iomem *desc,
@@ -1204,7 +1178,6 @@ int cpdma_chan_process(struct cpdma_chan *chan, int quota)
1204 } 1178 }
1205 return used; 1179 return used;
1206} 1180}
1207EXPORT_SYMBOL_GPL(cpdma_chan_process);
1208 1181
1209int cpdma_chan_start(struct cpdma_chan *chan) 1182int cpdma_chan_start(struct cpdma_chan *chan)
1210{ 1183{
@@ -1224,7 +1197,6 @@ int cpdma_chan_start(struct cpdma_chan *chan)
1224 1197
1225 return 0; 1198 return 0;
1226} 1199}
1227EXPORT_SYMBOL_GPL(cpdma_chan_start);
1228 1200
1229int cpdma_chan_stop(struct cpdma_chan *chan) 1201int cpdma_chan_stop(struct cpdma_chan *chan)
1230{ 1202{
@@ -1287,7 +1259,6 @@ int cpdma_chan_stop(struct cpdma_chan *chan)
1287 spin_unlock_irqrestore(&chan->lock, flags); 1259 spin_unlock_irqrestore(&chan->lock, flags);
1288 return 0; 1260 return 0;
1289} 1261}
1290EXPORT_SYMBOL_GPL(cpdma_chan_stop);
1291 1262
1292int cpdma_chan_int_ctrl(struct cpdma_chan *chan, bool enable) 1263int cpdma_chan_int_ctrl(struct cpdma_chan *chan, bool enable)
1293{ 1264{
@@ -1329,25 +1300,19 @@ int cpdma_control_set(struct cpdma_ctlr *ctlr, int control, int value)
1329 1300
1330 return ret; 1301 return ret;
1331} 1302}
1332EXPORT_SYMBOL_GPL(cpdma_control_set);
1333 1303
1334int cpdma_get_num_rx_descs(struct cpdma_ctlr *ctlr) 1304int cpdma_get_num_rx_descs(struct cpdma_ctlr *ctlr)
1335{ 1305{
1336 return ctlr->num_rx_desc; 1306 return ctlr->num_rx_desc;
1337} 1307}
1338EXPORT_SYMBOL_GPL(cpdma_get_num_rx_descs);
1339 1308
1340int cpdma_get_num_tx_descs(struct cpdma_ctlr *ctlr) 1309int cpdma_get_num_tx_descs(struct cpdma_ctlr *ctlr)
1341{ 1310{
1342 return ctlr->num_tx_desc; 1311 return ctlr->num_tx_desc;
1343} 1312}
1344EXPORT_SYMBOL_GPL(cpdma_get_num_tx_descs);
1345 1313
1346void cpdma_set_num_rx_descs(struct cpdma_ctlr *ctlr, int num_rx_desc) 1314void cpdma_set_num_rx_descs(struct cpdma_ctlr *ctlr, int num_rx_desc)
1347{ 1315{
1348 ctlr->num_rx_desc = num_rx_desc; 1316 ctlr->num_rx_desc = num_rx_desc;
1349 ctlr->num_tx_desc = ctlr->pool->num_desc - ctlr->num_rx_desc; 1317 ctlr->num_tx_desc = ctlr->pool->num_desc - ctlr->num_rx_desc;
1350} 1318}
1351EXPORT_SYMBOL_GPL(cpdma_set_num_rx_descs);
1352
1353MODULE_LICENSE("GPL");
diff --git a/drivers/net/ethernet/ti/davinci_cpdma.h b/drivers/net/ethernet/ti/davinci_cpdma.h
index d399af5389b8..10376062dafa 100644
--- a/drivers/net/ethernet/ti/davinci_cpdma.h
+++ b/drivers/net/ethernet/ti/davinci_cpdma.h
@@ -1,16 +1,9 @@
1/* SPDX-License-Identifier: GPL-2.0 */
1/* 2/*
2 * Texas Instruments CPDMA Driver 3 * Texas Instruments CPDMA Driver
3 * 4 *
4 * Copyright (C) 2010 Texas Instruments 5 * Copyright (C) 2010 Texas Instruments
5 * 6 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */ 7 */
15#ifndef __DAVINCI_CPDMA_H__ 8#ifndef __DAVINCI_CPDMA_H__
16#define __DAVINCI_CPDMA_H__ 9#define __DAVINCI_CPDMA_H__
@@ -34,8 +27,8 @@ struct cpdma_params {
34 int num_chan; 27 int num_chan;
35 bool has_soft_reset; 28 bool has_soft_reset;
36 int min_packet_size; 29 int min_packet_size;
37 u32 desc_mem_phys; 30 dma_addr_t desc_mem_phys;
38 u32 desc_hw_addr; 31 dma_addr_t desc_hw_addr;
39 int desc_mem_size; 32 int desc_mem_size;
40 int desc_align; 33 int desc_align;
41 u32 bus_freq_mhz; 34 u32 bus_freq_mhz;
diff --git a/drivers/net/ethernet/ti/davinci_emac.c b/drivers/net/ethernet/ti/davinci_emac.c
index 57450b174fc4..39075f5c73d5 100644
--- a/drivers/net/ethernet/ti/davinci_emac.c
+++ b/drivers/net/ethernet/ti/davinci_emac.c
@@ -1,3 +1,4 @@
1// SPDX-License-Identifier: GPL-2.0+
1/* 2/*
2 * DaVinci Ethernet Medium Access Controller 3 * DaVinci Ethernet Medium Access Controller
3 * 4 *
@@ -6,21 +7,6 @@
6 * Copyright (C) 2009 Texas Instruments. 7 * Copyright (C) 2009 Texas Instruments.
7 * 8 *
8 * --------------------------------------------------------------------------- 9 * ---------------------------------------------------------------------------
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 * ---------------------------------------------------------------------------
24 * History: 10 * History:
25 * 0-5 A number of folks worked on this driver in bits and pieces but the major 11 * 0-5 A number of folks worked on this driver in bits and pieces but the major
26 * contribution came from Suraj Iyer and Anant Gole 12 * contribution came from Suraj Iyer and Anant Gole
diff --git a/drivers/net/ethernet/ti/davinci_mdio.c b/drivers/net/ethernet/ti/davinci_mdio.c
index c2740dbe9154..11642721c123 100644
--- a/drivers/net/ethernet/ti/davinci_mdio.c
+++ b/drivers/net/ethernet/ti/davinci_mdio.c
@@ -1,3 +1,4 @@
1// SPDX-License-Identifier: GPL-2.0+
1/* 2/*
2 * DaVinci MDIO Module driver 3 * DaVinci MDIO Module driver
3 * 4 *
@@ -7,22 +8,6 @@
7 * 8 *
8 * Copyright (C) 2009 Texas Instruments. 9 * Copyright (C) 2009 Texas Instruments.
9 * 10 *
10 * ---------------------------------------------------------------------------
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 * ---------------------------------------------------------------------------
26 */ 11 */
27#include <linux/module.h> 12#include <linux/module.h>
28#include <linux/kernel.h> 13#include <linux/kernel.h>
@@ -412,7 +397,7 @@ static int davinci_mdio_probe(struct platform_device *pdev)
412 data->dev = dev; 397 data->dev = dev;
413 398
414 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 399 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
415 data->regs = devm_ioremap_resource(dev, res); 400 data->regs = devm_ioremap(dev, res->start, resource_size(res));
416 if (IS_ERR(data->regs)) 401 if (IS_ERR(data->regs))
417 return PTR_ERR(data->regs); 402 return PTR_ERR(data->regs);
418 403
diff --git a/drivers/net/ethernet/ti/netcp.h b/drivers/net/ethernet/ti/netcp.h
index c4ffdf47bad5..43d5cd59b56b 100644
--- a/drivers/net/ethernet/ti/netcp.h
+++ b/drivers/net/ethernet/ti/netcp.h
@@ -1,3 +1,4 @@
1/* SPDX-License-Identifier: GPL-2.0 */
1/* 2/*
2 * NetCP driver local header 3 * NetCP driver local header
3 * 4 *
@@ -8,15 +9,6 @@
8 * Santosh Shilimkar <santosh.shilimkar@ti.com> 9 * Santosh Shilimkar <santosh.shilimkar@ti.com>
9 * Wingman Kwok <w-kwok2@ti.com> 10 * Wingman Kwok <w-kwok2@ti.com>
10 * Murali Karicheri <m-karicheri2@ti.com> 11 * Murali Karicheri <m-karicheri2@ti.com>
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation version 2.
15 *
16 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
17 * kind, whether express or implied; without even the implied warranty
18 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 */ 12 */
21#ifndef __NETCP_H__ 13#ifndef __NETCP_H__
22#define __NETCP_H__ 14#define __NETCP_H__
diff --git a/drivers/net/ethernet/ti/netcp_core.c b/drivers/net/ethernet/ti/netcp_core.c
index d847f672a705..01d4ca331f8c 100644
--- a/drivers/net/ethernet/ti/netcp_core.c
+++ b/drivers/net/ethernet/ti/netcp_core.c
@@ -1,3 +1,4 @@
1// SPDX-License-Identifier: GPL-2.0
1/* 2/*
2 * Keystone NetCP Core driver 3 * Keystone NetCP Core driver
3 * 4 *
@@ -8,15 +9,6 @@
8 * Santosh Shilimkar <santosh.shilimkar@ti.com> 9 * Santosh Shilimkar <santosh.shilimkar@ti.com>
9 * Murali Karicheri <m-karicheri2@ti.com> 10 * Murali Karicheri <m-karicheri2@ti.com>
10 * Wingman Kwok <w-kwok2@ti.com> 11 * Wingman Kwok <w-kwok2@ti.com>
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation version 2.
15 *
16 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
17 * kind, whether express or implied; without even the implied warranty
18 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 */ 12 */
21 13
22#include <linux/io.h> 14#include <linux/io.h>
diff --git a/drivers/net/ethernet/ti/netcp_ethss.c b/drivers/net/ethernet/ti/netcp_ethss.c
index 0a920c5936b2..ec179700c184 100644
--- a/drivers/net/ethernet/ti/netcp_ethss.c
+++ b/drivers/net/ethernet/ti/netcp_ethss.c
@@ -1,3 +1,4 @@
1// SPDX-License-Identifier: GPL-2.0
1/* 2/*
2 * Keystone GBE and XGBE subsystem code 3 * Keystone GBE and XGBE subsystem code
3 * 4 *
@@ -7,15 +8,6 @@
7 * Cyril Chemparathy <cyril@ti.com> 8 * Cyril Chemparathy <cyril@ti.com>
8 * Santosh Shilimkar <santosh.shilimkar@ti.com> 9 * Santosh Shilimkar <santosh.shilimkar@ti.com>
9 * Wingman Kwok <w-kwok2@ti.com> 10 * Wingman Kwok <w-kwok2@ti.com>
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation version 2.
14 *
15 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
16 * kind, whether express or implied; without even the implied warranty
17 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 */ 11 */
20 12
21#include <linux/io.h> 13#include <linux/io.h>
diff --git a/drivers/net/ethernet/ti/netcp_sgmii.c b/drivers/net/ethernet/ti/netcp_sgmii.c
index 5d8419f658d0..f7cf56d6351d 100644
--- a/drivers/net/ethernet/ti/netcp_sgmii.c
+++ b/drivers/net/ethernet/ti/netcp_sgmii.c
@@ -1,3 +1,4 @@
1// SPDX-License-Identifier: GPL-2.0
1/* 2/*
2 * SGMI module initialisation 3 * SGMI module initialisation
3 * 4 *
@@ -6,14 +7,6 @@
6 * Sandeep Paulraj <s-paulraj@ti.com> 7 * Sandeep Paulraj <s-paulraj@ti.com>
7 * Wingman Kwok <w-kwok2@ti.com> 8 * Wingman Kwok <w-kwok2@ti.com>
8 * 9 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation version 2.
12 *
13 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
14 * kind, whether express or implied; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */ 10 */
18 11
19#include "netcp.h" 12#include "netcp.h"
diff --git a/drivers/net/ethernet/ti/netcp_xgbepcsr.c b/drivers/net/ethernet/ti/netcp_xgbepcsr.c
index 33571acc52b6..112778aedd8a 100644
--- a/drivers/net/ethernet/ti/netcp_xgbepcsr.c
+++ b/drivers/net/ethernet/ti/netcp_xgbepcsr.c
@@ -1,3 +1,4 @@
1// SPDX-License-Identifier: GPL-2.0
1/* 2/*
2 * XGE PCSR module initialisation 3 * XGE PCSR module initialisation
3 * 4 *
@@ -5,14 +6,6 @@
5 * Authors: Sandeep Nair <sandeep_n@ti.com> 6 * Authors: Sandeep Nair <sandeep_n@ti.com>
6 * WingMan Kwok <w-kwok2@ti.com> 7 * WingMan Kwok <w-kwok2@ti.com>
7 * 8 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation version 2.
11 *
12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
13 * kind, whether express or implied; without even the implied warranty
14 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */ 9 */
17#include "netcp.h" 10#include "netcp.h"
18 11
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-02 16:57:04 -0500