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authorBartosz Golaszewski <bgolaszewski@baylibre.com>2018-04-30 04:24:53 -0400
committerSekhar Nori <nsekhar@ti.com>2018-05-02 05:29:19 -0400
commit7c4db57cdb00a799722445b8dee8ca6fe12ec8d6 (patch)
tree0ff65d4f9a39014105c25eff241a38500a533c1a
parentfd0658063cd2a84e122f4cb20029f86a44c037a3 (diff)
ARM: davinci: aemif: stop using pdev->id as nand chipselect
All platforms now use the core_chipsel field in platform_data. Stop using pdev->id in the aemif code. Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
-rw-r--r--arch/arm/mach-davinci/aemif.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm/mach-davinci/aemif.c b/arch/arm/mach-davinci/aemif.c
index ff8b7e76b6e9..e4ab3f3a2a1f 100644
--- a/arch/arm/mach-davinci/aemif.c
+++ b/arch/arm/mach-davinci/aemif.c
@@ -189,7 +189,7 @@ int davinci_aemif_setup(struct platform_device *pdev)
189 * Setup Async configuration register in case we did not boot 189 * Setup Async configuration register in case we did not boot
190 * from NAND and so bootloader did not bother to set it up. 190 * from NAND and so bootloader did not bother to set it up.
191 */ 191 */
192 val = davinci_aemif_readl(base, A1CR_OFFSET + pdev->id * 4); 192 val = davinci_aemif_readl(base, A1CR_OFFSET + pdata->core_chipsel * 4);
193 /* 193 /*
194 * Extended Wait is not valid and Select Strobe mode is not 194 * Extended Wait is not valid and Select Strobe mode is not
195 * used 195 * used
@@ -198,13 +198,13 @@ int davinci_aemif_setup(struct platform_device *pdev)
198 if (pdata->options & NAND_BUSWIDTH_16) 198 if (pdata->options & NAND_BUSWIDTH_16)
199 val |= 0x1; 199 val |= 0x1;
200 200
201 davinci_aemif_writel(base, A1CR_OFFSET + pdev->id * 4, val); 201 davinci_aemif_writel(base, A1CR_OFFSET + pdata->core_chipsel * 4, val);
202 202
203 clkrate = clk_get_rate(clk); 203 clkrate = clk_get_rate(clk);
204 204
205 if (pdata->timing) 205 if (pdata->timing)
206 ret = davinci_aemif_setup_timing(pdata->timing, base, pdev->id, 206 ret = davinci_aemif_setup_timing(pdata->timing, base,
207 clkrate); 207 pdata->core_chipsel, clkrate);
208 208
209 if (ret < 0) 209 if (ret < 0)
210 dev_dbg(&pdev->dev, "NAND timing values setup fail\n"); 210 dev_dbg(&pdev->dev, "NAND timing values setup fail\n");