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authorYong Zhao <yong.zhao@amd.com>2017-09-15 18:20:37 -0400
committerAlex Deucher <alexander.deucher@amd.com>2017-09-26 15:14:21 -0400
commit7bdc53f925af085ffa0580f10489f82b36cc2f1c (patch)
tree8b760f772a29969ecce509371d55e22111a19627
parentdfe5c2b76b2a32cd37283809737e55f9208f8346 (diff)
drm/amdgpu: Fix a bug in amdgpu_fill_buffer()
When max_bytes is not 8 bytes aligned and bo size is larger than max_bytes, the last 8 bytes in a ttm node may be left unchanged. For example, on pre SDMA 4.0, max_bytes = 0x1fffff, and the bo size is 0x200000, the problem will happen. In order to fix the problem, we separately store the max nums of PTEs/PDEs a single operation can set in amdgpu_vm_pte_funcs structure, rather than inferring it from bytes limit of SDMA constant fill, i.e. fill_max_bytes. Together with the fix, we replace the hard code value "10" in amdgpu_vm_bo_update_mapping() with the corresponding values from structure amdgpu_vm_pte_funcs. Signed-off-by: Yong Zhao <yong.zhao@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu.h7
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c8
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c5
-rw-r--r--drivers/gpu/drm/amd/amdgpu/cik_sdma.c3
-rw-r--r--drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c3
-rw-r--r--drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c4
-rw-r--r--drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c3
-rw-r--r--drivers/gpu/drm/amd/amdgpu/si_dma.c3
8 files changed, 30 insertions, 6 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index f085c8c9f267..1bf42a8ef23e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -302,6 +302,13 @@ struct amdgpu_vm_pte_funcs {
302 void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe, 302 void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe,
303 uint64_t value, unsigned count, 303 uint64_t value, unsigned count,
304 uint32_t incr); 304 uint32_t incr);
305
306 /* maximum nums of PTEs/PDEs in a single operation */
307 uint32_t set_max_nums_pte_pde;
308
309 /* number of dw to reserve per operation */
310 unsigned set_pte_pde_num_dw;
311
305 /* for linear pte/pde updates without addr mapping */ 312 /* for linear pte/pde updates without addr mapping */
306 void (*set_pte_pde)(struct amdgpu_ib *ib, 313 void (*set_pte_pde)(struct amdgpu_ib *ib,
307 uint64_t pe, 314 uint64_t pe,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index ce435dbbb398..1086f039d8e3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1527,8 +1527,8 @@ int amdgpu_fill_buffer(struct amdgpu_bo *bo,
1527 struct dma_fence **fence) 1527 struct dma_fence **fence)
1528{ 1528{
1529 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 1529 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
1530 /* max_bytes applies to SDMA_OP_PTEPDE as well as SDMA_OP_CONST_FILL*/ 1530 uint32_t max_bytes = 8 *
1531 uint32_t max_bytes = adev->mman.buffer_funcs->fill_max_bytes; 1531 adev->vm_manager.vm_pte_funcs->set_max_nums_pte_pde;
1532 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; 1532 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
1533 1533
1534 struct drm_mm_node *mm_node; 1534 struct drm_mm_node *mm_node;
@@ -1560,8 +1560,8 @@ int amdgpu_fill_buffer(struct amdgpu_bo *bo,
1560 ++mm_node; 1560 ++mm_node;
1561 } 1561 }
1562 1562
1563 /* 10 double words for each SDMA_OP_PTEPDE cmd */ 1563 /* num of dwords for each SDMA_OP_PTEPDE cmd */
1564 num_dw = num_loops * 10; 1564 num_dw = num_loops * adev->vm_manager.vm_pte_funcs->set_pte_pde_num_dw;
1565 1565
1566 /* for IB padding */ 1566 /* for IB padding */
1567 num_dw += 64; 1567 num_dw += 64;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 6c1133298b17..28d16781377f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -1606,10 +1606,11 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
1606 1606
1607 } else { 1607 } else {
1608 /* set page commands needed */ 1608 /* set page commands needed */
1609 ndw += ncmds * 10; 1609 ndw += ncmds * adev->vm_manager.vm_pte_funcs->set_pte_pde_num_dw;
1610 1610
1611 /* extra commands for begin/end fragments */ 1611 /* extra commands for begin/end fragments */
1612 ndw += 2 * 10 * adev->vm_manager.fragment_size; 1612 ndw += 2 * adev->vm_manager.vm_pte_funcs->set_pte_pde_num_dw
1613 * adev->vm_manager.fragment_size;
1613 1614
1614 params.func = amdgpu_vm_do_set_ptes; 1615 params.func = amdgpu_vm_do_set_ptes;
1615 } 1616 }
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
index f508f4d01e4a..c64dcd1883b5 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
@@ -1389,6 +1389,9 @@ static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev)
1389static const struct amdgpu_vm_pte_funcs cik_sdma_vm_pte_funcs = { 1389static const struct amdgpu_vm_pte_funcs cik_sdma_vm_pte_funcs = {
1390 .copy_pte = cik_sdma_vm_copy_pte, 1390 .copy_pte = cik_sdma_vm_copy_pte,
1391 .write_pte = cik_sdma_vm_write_pte, 1391 .write_pte = cik_sdma_vm_write_pte,
1392
1393 .set_max_nums_pte_pde = 0x1fffff >> 3,
1394 .set_pte_pde_num_dw = 10,
1392 .set_pte_pde = cik_sdma_vm_set_pte_pde, 1395 .set_pte_pde = cik_sdma_vm_set_pte_pde,
1393}; 1396};
1394 1397
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
index f2d0710258cb..c05eb74d3404 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
@@ -1326,6 +1326,9 @@ static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device *adev)
1326static const struct amdgpu_vm_pte_funcs sdma_v2_4_vm_pte_funcs = { 1326static const struct amdgpu_vm_pte_funcs sdma_v2_4_vm_pte_funcs = {
1327 .copy_pte = sdma_v2_4_vm_copy_pte, 1327 .copy_pte = sdma_v2_4_vm_copy_pte,
1328 .write_pte = sdma_v2_4_vm_write_pte, 1328 .write_pte = sdma_v2_4_vm_write_pte,
1329
1330 .set_max_nums_pte_pde = 0x1fffff >> 3,
1331 .set_pte_pde_num_dw = 10,
1329 .set_pte_pde = sdma_v2_4_vm_set_pte_pde, 1332 .set_pte_pde = sdma_v2_4_vm_set_pte_pde,
1330}; 1333};
1331 1334
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
index 4858c9974c86..2079340656d2 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -1750,6 +1750,10 @@ static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev)
1750static const struct amdgpu_vm_pte_funcs sdma_v3_0_vm_pte_funcs = { 1750static const struct amdgpu_vm_pte_funcs sdma_v3_0_vm_pte_funcs = {
1751 .copy_pte = sdma_v3_0_vm_copy_pte, 1751 .copy_pte = sdma_v3_0_vm_copy_pte,
1752 .write_pte = sdma_v3_0_vm_write_pte, 1752 .write_pte = sdma_v3_0_vm_write_pte,
1753
1754 /* not 0x3fffff due to HW limitation */
1755 .set_max_nums_pte_pde = 0x3fffe0 >> 3,
1756 .set_pte_pde_num_dw = 10,
1753 .set_pte_pde = sdma_v3_0_vm_set_pte_pde, 1757 .set_pte_pde = sdma_v3_0_vm_set_pte_pde,
1754}; 1758};
1755 1759
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 3524060f8480..2605faf56dff 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -1716,6 +1716,9 @@ static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev)
1716static const struct amdgpu_vm_pte_funcs sdma_v4_0_vm_pte_funcs = { 1716static const struct amdgpu_vm_pte_funcs sdma_v4_0_vm_pte_funcs = {
1717 .copy_pte = sdma_v4_0_vm_copy_pte, 1717 .copy_pte = sdma_v4_0_vm_copy_pte,
1718 .write_pte = sdma_v4_0_vm_write_pte, 1718 .write_pte = sdma_v4_0_vm_write_pte,
1719
1720 .set_max_nums_pte_pde = 0x400000 >> 3,
1721 .set_pte_pde_num_dw = 10,
1719 .set_pte_pde = sdma_v4_0_vm_set_pte_pde, 1722 .set_pte_pde = sdma_v4_0_vm_set_pte_pde,
1720}; 1723};
1721 1724
diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdgpu/si_dma.c
index 112969f3301a..adb6ae7d63ef 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dma.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c
@@ -889,6 +889,9 @@ static void si_dma_set_buffer_funcs(struct amdgpu_device *adev)
889static const struct amdgpu_vm_pte_funcs si_dma_vm_pte_funcs = { 889static const struct amdgpu_vm_pte_funcs si_dma_vm_pte_funcs = {
890 .copy_pte = si_dma_vm_copy_pte, 890 .copy_pte = si_dma_vm_copy_pte,
891 .write_pte = si_dma_vm_write_pte, 891 .write_pte = si_dma_vm_write_pte,
892
893 .set_max_nums_pte_pde = 0xffff8 >> 3,
894 .set_pte_pde_num_dw = 9,
892 .set_pte_pde = si_dma_vm_set_pte_pde, 895 .set_pte_pde = si_dma_vm_set_pte_pde,
893}; 896};
894 897