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authorJunwei Zhang <Jerry.Zhang@amd.com>2018-06-25 00:51:14 -0400
committerAlex Deucher <alexander.deucher@amd.com>2018-07-10 15:15:39 -0400
commit7b7c6c81b3a370b46b0c48f4ab7ac3be83237a12 (patch)
treedd93e3098cbcce0051433e3a173c466dd241ddbf
parentb861686b18538eaaf3530255eb37b4133146fbe2 (diff)
drm/amdgpu: separate gpu address from bo pin
It could be got by amdgpu_bo_gpu_offset() if need Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c6
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c6
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_device.c5
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_display.c5
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c6
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_object.c17
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_object.h5
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_test.c6
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/dce_v10_0.c10
-rw-r--r--drivers/gpu/drm/amd/amdgpu/dce_v11_0.c10
-rw-r--r--drivers/gpu/drm/amd/amdgpu/dce_v6_0.c10
-rw-r--r--drivers/gpu/drm/amd/amdgpu/dce_v8_0.c10
-rw-r--r--drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c3
17 files changed, 50 insertions, 57 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
index 305143fcc1ce..98e3bf890d5b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
@@ -251,7 +251,6 @@ int alloc_gtt_mem(struct kgd_dev *kgd, size_t size,
251 struct amdgpu_bo *bo = NULL; 251 struct amdgpu_bo *bo = NULL;
252 struct amdgpu_bo_param bp; 252 struct amdgpu_bo_param bp;
253 int r; 253 int r;
254 uint64_t gpu_addr_tmp = 0;
255 void *cpu_ptr_tmp = NULL; 254 void *cpu_ptr_tmp = NULL;
256 255
257 memset(&bp, 0, sizeof(bp)); 256 memset(&bp, 0, sizeof(bp));
@@ -275,8 +274,7 @@ int alloc_gtt_mem(struct kgd_dev *kgd, size_t size,
275 goto allocate_mem_reserve_bo_failed; 274 goto allocate_mem_reserve_bo_failed;
276 } 275 }
277 276
278 r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT, 277 r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);
279 &gpu_addr_tmp);
280 if (r) { 278 if (r) {
281 dev_err(adev->dev, "(%d) failed to pin bo for amdkfd\n", r); 279 dev_err(adev->dev, "(%d) failed to pin bo for amdkfd\n", r);
282 goto allocate_mem_pin_bo_failed; 280 goto allocate_mem_pin_bo_failed;
@@ -290,7 +288,7 @@ int alloc_gtt_mem(struct kgd_dev *kgd, size_t size,
290 } 288 }
291 289
292 *mem_obj = bo; 290 *mem_obj = bo;
293 *gpu_addr = gpu_addr_tmp; 291 *gpu_addr = amdgpu_bo_gpu_offset(bo);
294 *cpu_ptr = cpu_ptr_tmp; 292 *cpu_ptr = cpu_ptr_tmp;
295 293
296 amdgpu_bo_unreserve(bo); 294 amdgpu_bo_unreserve(bo);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index ff8fd75f7ca5..079af8ac2636 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -1587,7 +1587,7 @@ int amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(struct kgd_dev *kgd,
1587 goto bo_reserve_failed; 1587 goto bo_reserve_failed;
1588 } 1588 }
1589 1589
1590 ret = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT, NULL); 1590 ret = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);
1591 if (ret) { 1591 if (ret) {
1592 pr_err("Failed to pin bo. ret %d\n", ret); 1592 pr_err("Failed to pin bo. ret %d\n", ret);
1593 goto pin_failed; 1593 goto pin_failed;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c
index 19cfff31f2e1..cb88d7e8b96b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c
@@ -95,7 +95,8 @@ static void amdgpu_benchmark_move(struct amdgpu_device *adev, unsigned size,
95 r = amdgpu_bo_reserve(sobj, false); 95 r = amdgpu_bo_reserve(sobj, false);
96 if (unlikely(r != 0)) 96 if (unlikely(r != 0))
97 goto out_cleanup; 97 goto out_cleanup;
98 r = amdgpu_bo_pin(sobj, sdomain, &saddr); 98 r = amdgpu_bo_pin(sobj, sdomain);
99 saddr = amdgpu_bo_gpu_offset(sobj);
99 amdgpu_bo_unreserve(sobj); 100 amdgpu_bo_unreserve(sobj);
100 if (r) { 101 if (r) {
101 goto out_cleanup; 102 goto out_cleanup;
@@ -108,7 +109,8 @@ static void amdgpu_benchmark_move(struct amdgpu_device *adev, unsigned size,
108 r = amdgpu_bo_reserve(dobj, false); 109 r = amdgpu_bo_reserve(dobj, false);
109 if (unlikely(r != 0)) 110 if (unlikely(r != 0))
110 goto out_cleanup; 111 goto out_cleanup;
111 r = amdgpu_bo_pin(dobj, ddomain, &daddr); 112 r = amdgpu_bo_pin(dobj, ddomain);
113 daddr = amdgpu_bo_gpu_offset(dobj);
112 amdgpu_bo_unreserve(dobj); 114 amdgpu_bo_unreserve(dobj);
113 if (r) { 115 if (r) {
114 goto out_cleanup; 116 goto out_cleanup;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 9883fa9bb41b..2720444ff23a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2758,11 +2758,10 @@ int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon)
2758 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); 2758 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2759 r = amdgpu_bo_reserve(aobj, true); 2759 r = amdgpu_bo_reserve(aobj, true);
2760 if (r == 0) { 2760 if (r == 0) {
2761 r = amdgpu_bo_pin(aobj, 2761 r = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM);
2762 AMDGPU_GEM_DOMAIN_VRAM,
2763 &amdgpu_crtc->cursor_addr);
2764 if (r != 0) 2762 if (r != 0)
2765 DRM_ERROR("Failed to pin cursor BO (%d)\n", r); 2763 DRM_ERROR("Failed to pin cursor BO (%d)\n", r);
2764 amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj);
2766 amdgpu_bo_unreserve(aobj); 2765 amdgpu_bo_unreserve(aobj);
2767 } 2766 }
2768 } 2767 }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
index 76ee8e04ff11..a80407cf099b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
@@ -157,7 +157,6 @@ int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc,
157 struct amdgpu_bo *new_abo; 157 struct amdgpu_bo *new_abo;
158 unsigned long flags; 158 unsigned long flags;
159 u64 tiling_flags; 159 u64 tiling_flags;
160 u64 base;
161 int i, r; 160 int i, r;
162 161
163 work = kzalloc(sizeof *work, GFP_KERNEL); 162 work = kzalloc(sizeof *work, GFP_KERNEL);
@@ -189,7 +188,7 @@ int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc,
189 goto cleanup; 188 goto cleanup;
190 } 189 }
191 190
192 r = amdgpu_bo_pin(new_abo, amdgpu_display_supported_domains(adev), &base); 191 r = amdgpu_bo_pin(new_abo, amdgpu_display_supported_domains(adev));
193 if (unlikely(r != 0)) { 192 if (unlikely(r != 0)) {
194 DRM_ERROR("failed to pin new abo buffer before flip\n"); 193 DRM_ERROR("failed to pin new abo buffer before flip\n");
195 goto unreserve; 194 goto unreserve;
@@ -206,7 +205,7 @@ int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc,
206 amdgpu_bo_get_tiling_flags(new_abo, &tiling_flags); 205 amdgpu_bo_get_tiling_flags(new_abo, &tiling_flags);
207 amdgpu_bo_unreserve(new_abo); 206 amdgpu_bo_unreserve(new_abo);
208 207
209 work->base = base; 208 work->base = amdgpu_bo_gpu_offset(new_abo);
210 work->target_vblank = target - (uint32_t)drm_crtc_vblank_count(crtc) + 209 work->target_vblank = target - (uint32_t)drm_crtc_vblank_count(crtc) +
211 amdgpu_get_vblank_counter_kms(dev, work->crtc_id); 210 amdgpu_get_vblank_counter_kms(dev, work->crtc_id);
212 211
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
index 811c62927c38..c93fd9a6b59c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
@@ -168,7 +168,7 @@ static int amdgpufb_create_pinned_object(struct amdgpu_fbdev *rfbdev,
168 } 168 }
169 169
170 170
171 ret = amdgpu_bo_pin(abo, domain, NULL); 171 ret = amdgpu_bo_pin(abo, domain);
172 if (ret) { 172 if (ret) {
173 amdgpu_bo_unreserve(abo); 173 amdgpu_bo_unreserve(abo);
174 goto out_unref; 174 goto out_unref;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
index 36113cb60ca2..a54d5655a191 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
@@ -143,14 +143,12 @@ int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev)
143 */ 143 */
144int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev) 144int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev)
145{ 145{
146 uint64_t gpu_addr;
147 int r; 146 int r;
148 147
149 r = amdgpu_bo_reserve(adev->gart.robj, false); 148 r = amdgpu_bo_reserve(adev->gart.robj, false);
150 if (unlikely(r != 0)) 149 if (unlikely(r != 0))
151 return r; 150 return r;
152 r = amdgpu_bo_pin(adev->gart.robj, 151 r = amdgpu_bo_pin(adev->gart.robj, AMDGPU_GEM_DOMAIN_VRAM);
153 AMDGPU_GEM_DOMAIN_VRAM, &gpu_addr);
154 if (r) { 152 if (r) {
155 amdgpu_bo_unreserve(adev->gart.robj); 153 amdgpu_bo_unreserve(adev->gart.robj);
156 return r; 154 return r;
@@ -159,7 +157,7 @@ int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev)
159 if (r) 157 if (r)
160 amdgpu_bo_unpin(adev->gart.robj); 158 amdgpu_bo_unpin(adev->gart.robj);
161 amdgpu_bo_unreserve(adev->gart.robj); 159 amdgpu_bo_unreserve(adev->gart.robj);
162 adev->gart.table_addr = gpu_addr; 160 adev->gart.table_addr = amdgpu_bo_gpu_offset(adev->gart.robj);
163 return r; 161 return r;
164} 162}
165 163
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 512f59836436..79cdbf1b9dc9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -252,11 +252,13 @@ int amdgpu_bo_create_reserved(struct amdgpu_device *adev,
252 goto error_free; 252 goto error_free;
253 } 253 }
254 254
255 r = amdgpu_bo_pin(*bo_ptr, domain, gpu_addr); 255 r = amdgpu_bo_pin(*bo_ptr, domain);
256 if (r) { 256 if (r) {
257 dev_err(adev->dev, "(%d) kernel bo pin failed\n", r); 257 dev_err(adev->dev, "(%d) kernel bo pin failed\n", r);
258 goto error_unreserve; 258 goto error_unreserve;
259 } 259 }
260 if (gpu_addr)
261 *gpu_addr = amdgpu_bo_gpu_offset(*bo_ptr);
260 262
261 if (cpu_addr) { 263 if (cpu_addr) {
262 r = amdgpu_bo_kmap(*bo_ptr, cpu_addr); 264 r = amdgpu_bo_kmap(*bo_ptr, cpu_addr);
@@ -817,7 +819,6 @@ void amdgpu_bo_unref(struct amdgpu_bo **bo)
817 * @domain: domain to be pinned to 819 * @domain: domain to be pinned to
818 * @min_offset: the start of requested address range 820 * @min_offset: the start of requested address range
819 * @max_offset: the end of requested address range 821 * @max_offset: the end of requested address range
820 * @gpu_addr: GPU offset of the &amdgpu_bo buffer object
821 * 822 *
822 * Pins the buffer object according to requested domain and address range. If 823 * Pins the buffer object according to requested domain and address range. If
823 * the memory is unbound gart memory, binds the pages into gart table. Adjusts 824 * the memory is unbound gart memory, binds the pages into gart table. Adjusts
@@ -835,8 +836,7 @@ void amdgpu_bo_unref(struct amdgpu_bo **bo)
835 * 0 for success or a negative error code on failure. 836 * 0 for success or a negative error code on failure.
836 */ 837 */
837int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain, 838int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
838 u64 min_offset, u64 max_offset, 839 u64 min_offset, u64 max_offset)
839 u64 *gpu_addr)
840{ 840{
841 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 841 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
842 struct ttm_operation_ctx ctx = { false, false }; 842 struct ttm_operation_ctx ctx = { false, false };
@@ -868,8 +868,6 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
868 return -EINVAL; 868 return -EINVAL;
869 869
870 bo->pin_count++; 870 bo->pin_count++;
871 if (gpu_addr)
872 *gpu_addr = amdgpu_bo_gpu_offset(bo);
873 871
874 if (max_offset != 0) { 872 if (max_offset != 0) {
875 u64 domain_start = bo->tbo.bdev->man[mem_type].gpu_offset; 873 u64 domain_start = bo->tbo.bdev->man[mem_type].gpu_offset;
@@ -912,8 +910,6 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
912 } 910 }
913 911
914 bo->pin_count = 1; 912 bo->pin_count = 1;
915 if (gpu_addr != NULL)
916 *gpu_addr = amdgpu_bo_gpu_offset(bo);
917 913
918 domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type); 914 domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
919 if (domain == AMDGPU_GEM_DOMAIN_VRAM) { 915 if (domain == AMDGPU_GEM_DOMAIN_VRAM) {
@@ -931,7 +927,6 @@ error:
931 * amdgpu_bo_pin - pin an &amdgpu_bo buffer object 927 * amdgpu_bo_pin - pin an &amdgpu_bo buffer object
932 * @bo: &amdgpu_bo buffer object to be pinned 928 * @bo: &amdgpu_bo buffer object to be pinned
933 * @domain: domain to be pinned to 929 * @domain: domain to be pinned to
934 * @gpu_addr: GPU offset of the &amdgpu_bo buffer object
935 * 930 *
936 * A simple wrapper to amdgpu_bo_pin_restricted(). 931 * A simple wrapper to amdgpu_bo_pin_restricted().
937 * Provides a simpler API for buffers that do not have any strict restrictions 932 * Provides a simpler API for buffers that do not have any strict restrictions
@@ -940,9 +935,9 @@ error:
940 * Returns: 935 * Returns:
941 * 0 for success or a negative error code on failure. 936 * 0 for success or a negative error code on failure.
942 */ 937 */
943int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain, u64 *gpu_addr) 938int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain)
944{ 939{
945 return amdgpu_bo_pin_restricted(bo, domain, 0, 0, gpu_addr); 940 return amdgpu_bo_pin_restricted(bo, domain, 0, 0);
946} 941}
947 942
948/** 943/**
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
index 731748033878..9c3e29a04eb1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
@@ -252,10 +252,9 @@ void *amdgpu_bo_kptr(struct amdgpu_bo *bo);
252void amdgpu_bo_kunmap(struct amdgpu_bo *bo); 252void amdgpu_bo_kunmap(struct amdgpu_bo *bo);
253struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo); 253struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo);
254void amdgpu_bo_unref(struct amdgpu_bo **bo); 254void amdgpu_bo_unref(struct amdgpu_bo **bo);
255int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain, u64 *gpu_addr); 255int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain);
256int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain, 256int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
257 u64 min_offset, u64 max_offset, 257 u64 min_offset, u64 max_offset);
258 u64 *gpu_addr);
259int amdgpu_bo_unpin(struct amdgpu_bo *bo); 258int amdgpu_bo_unpin(struct amdgpu_bo *bo);
260int amdgpu_bo_evict_vram(struct amdgpu_device *adev); 259int amdgpu_bo_evict_vram(struct amdgpu_device *adev);
261int amdgpu_bo_init(struct amdgpu_device *adev); 260int amdgpu_bo_init(struct amdgpu_device *adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
index df7226ad64b5..3ed02f472003 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
@@ -232,7 +232,7 @@ static int amdgpu_gem_map_attach(struct dma_buf *dma_buf,
232 } 232 }
233 233
234 /* pin buffer into GTT */ 234 /* pin buffer into GTT */
235 r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT, NULL); 235 r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);
236 if (r) 236 if (r)
237 goto error_unreserve; 237 goto error_unreserve;
238 238
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c
index 57b14dccd8e0..007d70cd69dd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c
@@ -76,11 +76,12 @@ static void amdgpu_do_test_moves(struct amdgpu_device *adev)
76 r = amdgpu_bo_reserve(vram_obj, false); 76 r = amdgpu_bo_reserve(vram_obj, false);
77 if (unlikely(r != 0)) 77 if (unlikely(r != 0))
78 goto out_unref; 78 goto out_unref;
79 r = amdgpu_bo_pin(vram_obj, AMDGPU_GEM_DOMAIN_VRAM, &vram_addr); 79 r = amdgpu_bo_pin(vram_obj, AMDGPU_GEM_DOMAIN_VRAM);
80 if (r) { 80 if (r) {
81 DRM_ERROR("Failed to pin VRAM object\n"); 81 DRM_ERROR("Failed to pin VRAM object\n");
82 goto out_unres; 82 goto out_unres;
83 } 83 }
84 vram_addr = amdgpu_bo_gpu_offset(vram_obj);
84 for (i = 0; i < n; i++) { 85 for (i = 0; i < n; i++) {
85 void *gtt_map, *vram_map; 86 void *gtt_map, *vram_map;
86 void **gart_start, **gart_end; 87 void **gart_start, **gart_end;
@@ -97,11 +98,12 @@ static void amdgpu_do_test_moves(struct amdgpu_device *adev)
97 r = amdgpu_bo_reserve(gtt_obj[i], false); 98 r = amdgpu_bo_reserve(gtt_obj[i], false);
98 if (unlikely(r != 0)) 99 if (unlikely(r != 0))
99 goto out_lclean_unref; 100 goto out_lclean_unref;
100 r = amdgpu_bo_pin(gtt_obj[i], AMDGPU_GEM_DOMAIN_GTT, &gart_addr); 101 r = amdgpu_bo_pin(gtt_obj[i], AMDGPU_GEM_DOMAIN_GTT);
101 if (r) { 102 if (r) {
102 DRM_ERROR("Failed to pin GTT object %d\n", i); 103 DRM_ERROR("Failed to pin GTT object %d\n", i);
103 goto out_lclean_unres; 104 goto out_lclean_unres;
104 } 105 }
106 gart_addr = amdgpu_bo_gpu_offset(gtt_obj[i]);
105 107
106 r = amdgpu_bo_kmap(gtt_obj[i], &gtt_map); 108 r = amdgpu_bo_kmap(gtt_obj[i], &gtt_map);
107 if (r) { 109 if (r) {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 0246cb87d9e4..0e47f15b0f97 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1695,7 +1695,7 @@ static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev)
1695 AMDGPU_GEM_DOMAIN_VRAM, 1695 AMDGPU_GEM_DOMAIN_VRAM,
1696 adev->fw_vram_usage.start_offset, 1696 adev->fw_vram_usage.start_offset,
1697 (adev->fw_vram_usage.start_offset + 1697 (adev->fw_vram_usage.start_offset +
1698 adev->fw_vram_usage.size), NULL); 1698 adev->fw_vram_usage.size));
1699 if (r) 1699 if (r)
1700 goto error_pin; 1700 goto error_pin;
1701 r = amdgpu_bo_kmap(adev->fw_vram_usage.reserved_bo, 1701 r = amdgpu_bo_kmap(adev->fw_vram_usage.reserved_bo,
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
index ada241bfeee9..ab043228d8da 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
@@ -1855,15 +1855,14 @@ static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc,
1855 if (unlikely(r != 0)) 1855 if (unlikely(r != 0))
1856 return r; 1856 return r;
1857 1857
1858 if (atomic) { 1858 if (!atomic) {
1859 fb_location = amdgpu_bo_gpu_offset(abo); 1859 r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM);
1860 } else {
1861 r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location);
1862 if (unlikely(r != 0)) { 1860 if (unlikely(r != 0)) {
1863 amdgpu_bo_unreserve(abo); 1861 amdgpu_bo_unreserve(abo);
1864 return -EINVAL; 1862 return -EINVAL;
1865 } 1863 }
1866 } 1864 }
1865 fb_location = amdgpu_bo_gpu_offset(abo);
1867 1866
1868 amdgpu_bo_get_tiling_flags(abo, &tiling_flags); 1867 amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
1869 amdgpu_bo_unreserve(abo); 1868 amdgpu_bo_unreserve(abo);
@@ -2370,13 +2369,14 @@ static int dce_v10_0_crtc_cursor_set2(struct drm_crtc *crtc,
2370 return ret; 2369 return ret;
2371 } 2370 }
2372 2371
2373 ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM, &amdgpu_crtc->cursor_addr); 2372 ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM);
2374 amdgpu_bo_unreserve(aobj); 2373 amdgpu_bo_unreserve(aobj);
2375 if (ret) { 2374 if (ret) {
2376 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret); 2375 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
2377 drm_gem_object_put_unlocked(obj); 2376 drm_gem_object_put_unlocked(obj);
2378 return ret; 2377 return ret;
2379 } 2378 }
2379 amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj);
2380 2380
2381 dce_v10_0_lock_cursor(crtc, true); 2381 dce_v10_0_lock_cursor(crtc, true);
2382 2382
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
index a5b96eac3033..177851264754 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
@@ -1897,15 +1897,14 @@ static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc,
1897 if (unlikely(r != 0)) 1897 if (unlikely(r != 0))
1898 return r; 1898 return r;
1899 1899
1900 if (atomic) { 1900 if (!atomic) {
1901 fb_location = amdgpu_bo_gpu_offset(abo); 1901 r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM);
1902 } else {
1903 r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location);
1904 if (unlikely(r != 0)) { 1902 if (unlikely(r != 0)) {
1905 amdgpu_bo_unreserve(abo); 1903 amdgpu_bo_unreserve(abo);
1906 return -EINVAL; 1904 return -EINVAL;
1907 } 1905 }
1908 } 1906 }
1907 fb_location = amdgpu_bo_gpu_offset(abo);
1909 1908
1910 amdgpu_bo_get_tiling_flags(abo, &tiling_flags); 1909 amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
1911 amdgpu_bo_unreserve(abo); 1910 amdgpu_bo_unreserve(abo);
@@ -2449,13 +2448,14 @@ static int dce_v11_0_crtc_cursor_set2(struct drm_crtc *crtc,
2449 return ret; 2448 return ret;
2450 } 2449 }
2451 2450
2452 ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM, &amdgpu_crtc->cursor_addr); 2451 ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM);
2453 amdgpu_bo_unreserve(aobj); 2452 amdgpu_bo_unreserve(aobj);
2454 if (ret) { 2453 if (ret) {
2455 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret); 2454 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
2456 drm_gem_object_put_unlocked(obj); 2455 drm_gem_object_put_unlocked(obj);
2457 return ret; 2456 return ret;
2458 } 2457 }
2458 amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj);
2459 2459
2460 dce_v11_0_lock_cursor(crtc, true); 2460 dce_v11_0_lock_cursor(crtc, true);
2461 2461
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
index 394cc1e8fe20..c9adc627305d 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
@@ -1811,15 +1811,14 @@ static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc,
1811 if (unlikely(r != 0)) 1811 if (unlikely(r != 0))
1812 return r; 1812 return r;
1813 1813
1814 if (atomic) { 1814 if (!atomic) {
1815 fb_location = amdgpu_bo_gpu_offset(abo); 1815 r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM);
1816 } else {
1817 r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location);
1818 if (unlikely(r != 0)) { 1816 if (unlikely(r != 0)) {
1819 amdgpu_bo_unreserve(abo); 1817 amdgpu_bo_unreserve(abo);
1820 return -EINVAL; 1818 return -EINVAL;
1821 } 1819 }
1822 } 1820 }
1821 fb_location = amdgpu_bo_gpu_offset(abo);
1823 1822
1824 amdgpu_bo_get_tiling_flags(abo, &tiling_flags); 1823 amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
1825 amdgpu_bo_unreserve(abo); 1824 amdgpu_bo_unreserve(abo);
@@ -2263,13 +2262,14 @@ static int dce_v6_0_crtc_cursor_set2(struct drm_crtc *crtc,
2263 return ret; 2262 return ret;
2264 } 2263 }
2265 2264
2266 ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM, &amdgpu_crtc->cursor_addr); 2265 ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM);
2267 amdgpu_bo_unreserve(aobj); 2266 amdgpu_bo_unreserve(aobj);
2268 if (ret) { 2267 if (ret) {
2269 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret); 2268 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
2270 drm_gem_object_put_unlocked(obj); 2269 drm_gem_object_put_unlocked(obj);
2271 return ret; 2270 return ret;
2272 } 2271 }
2272 amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj);
2273 2273
2274 dce_v6_0_lock_cursor(crtc, true); 2274 dce_v6_0_lock_cursor(crtc, true);
2275 2275
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
index c9b9ab8f1b05..50cd03beac7d 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
@@ -1786,15 +1786,14 @@ static int dce_v8_0_crtc_do_set_base(struct drm_crtc *crtc,
1786 if (unlikely(r != 0)) 1786 if (unlikely(r != 0))
1787 return r; 1787 return r;
1788 1788
1789 if (atomic) { 1789 if (!atomic) {
1790 fb_location = amdgpu_bo_gpu_offset(abo); 1790 r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM);
1791 } else {
1792 r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location);
1793 if (unlikely(r != 0)) { 1791 if (unlikely(r != 0)) {
1794 amdgpu_bo_unreserve(abo); 1792 amdgpu_bo_unreserve(abo);
1795 return -EINVAL; 1793 return -EINVAL;
1796 } 1794 }
1797 } 1795 }
1796 fb_location = amdgpu_bo_gpu_offset(abo);
1798 1797
1799 amdgpu_bo_get_tiling_flags(abo, &tiling_flags); 1798 amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
1800 amdgpu_bo_unreserve(abo); 1799 amdgpu_bo_unreserve(abo);
@@ -2274,13 +2273,14 @@ static int dce_v8_0_crtc_cursor_set2(struct drm_crtc *crtc,
2274 return ret; 2273 return ret;
2275 } 2274 }
2276 2275
2277 ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM, &amdgpu_crtc->cursor_addr); 2276 ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM);
2278 amdgpu_bo_unreserve(aobj); 2277 amdgpu_bo_unreserve(aobj);
2279 if (ret) { 2278 if (ret) {
2280 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret); 2279 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
2281 drm_gem_object_put_unlocked(obj); 2280 drm_gem_object_put_unlocked(obj);
2282 return ret; 2281 return ret;
2283 } 2282 }
2283 amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj);
2284 2284
2285 dce_v8_0_lock_cursor(crtc, true); 2285 dce_v8_0_lock_cursor(crtc, true);
2286 2286
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index ca017c1dd4da..02d83c97f10b 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -3094,7 +3094,7 @@ static int dm_plane_helper_prepare_fb(struct drm_plane *plane,
3094 else 3094 else
3095 domain = AMDGPU_GEM_DOMAIN_VRAM; 3095 domain = AMDGPU_GEM_DOMAIN_VRAM;
3096 3096
3097 r = amdgpu_bo_pin(rbo, domain, &afb->address); 3097 r = amdgpu_bo_pin(rbo, domain);
3098 amdgpu_bo_unreserve(rbo); 3098 amdgpu_bo_unreserve(rbo);
3099 3099
3100 if (unlikely(r != 0)) { 3100 if (unlikely(r != 0)) {
@@ -3102,6 +3102,7 @@ static int dm_plane_helper_prepare_fb(struct drm_plane *plane,
3102 DRM_ERROR("Failed to pin framebuffer with error %d\n", r); 3102 DRM_ERROR("Failed to pin framebuffer with error %d\n", r);
3103 return r; 3103 return r;
3104 } 3104 }
3105 afb->address = amdgpu_bo_gpu_offset(rbo);
3105 3106
3106 amdgpu_bo_ref(rbo); 3107 amdgpu_bo_ref(rbo);
3107 3108