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authorShawn Guo <shawnguo@kernel.org>2016-04-13 05:36:03 -0400
committerShawn Guo <shawnguo@kernel.org>2016-04-13 05:36:03 -0400
commit7b5ca4533f1ac023a16e44a2a1680121272723f9 (patch)
treec11b7e82d527a1ec8bf529a229dd2913fa88e75d
parentf55532a0c0b8bb6148f4e07853b876ef73bc69ca (diff)
parent69c542e8022ca53c5fee664548163809eb1777c3 (diff)
Merge tag 'imx-clk-4.7' into imx/dt-clkdep
The i.MX clock update for 4.7: - Register SAI clk as shared clocks to support SAI audio on i.MX6SX - Add the missing ckil clock for i.MX7 - Update clk-gate2 and vf610 clock driver to prepare for suspend support on VF610 - Fix DCU clock configurations and add TCON ipg clock to support DRM display on VF610
-rw-r--r--drivers/clk/imx/clk-gate2.c7
-rw-r--r--drivers/clk/imx/clk-imx6sx.c10
-rw-r--r--drivers/clk/imx/clk-imx7d.c3
-rw-r--r--drivers/clk/imx/clk-vf610.c60
-rw-r--r--drivers/clk/imx/clk.h13
-rw-r--r--include/dt-bindings/clock/imx7d-clock.h3
-rw-r--r--include/dt-bindings/clock/vf610-clock.h8
7 files changed, 89 insertions, 15 deletions
diff --git a/drivers/clk/imx/clk-gate2.c b/drivers/clk/imx/clk-gate2.c
index 8935bff99fe7..db44a198a0d9 100644
--- a/drivers/clk/imx/clk-gate2.c
+++ b/drivers/clk/imx/clk-gate2.c
@@ -31,6 +31,7 @@ struct clk_gate2 {
31 struct clk_hw hw; 31 struct clk_hw hw;
32 void __iomem *reg; 32 void __iomem *reg;
33 u8 bit_idx; 33 u8 bit_idx;
34 u8 cgr_val;
34 u8 flags; 35 u8 flags;
35 spinlock_t *lock; 36 spinlock_t *lock;
36 unsigned int *share_count; 37 unsigned int *share_count;
@@ -50,7 +51,8 @@ static int clk_gate2_enable(struct clk_hw *hw)
50 goto out; 51 goto out;
51 52
52 reg = readl(gate->reg); 53 reg = readl(gate->reg);
53 reg |= 3 << gate->bit_idx; 54 reg &= ~(3 << gate->bit_idx);
55 reg |= gate->cgr_val << gate->bit_idx;
54 writel(reg, gate->reg); 56 writel(reg, gate->reg);
55 57
56out: 58out:
@@ -125,7 +127,7 @@ static struct clk_ops clk_gate2_ops = {
125 127
126struct clk *clk_register_gate2(struct device *dev, const char *name, 128struct clk *clk_register_gate2(struct device *dev, const char *name,
127 const char *parent_name, unsigned long flags, 129 const char *parent_name, unsigned long flags,
128 void __iomem *reg, u8 bit_idx, 130 void __iomem *reg, u8 bit_idx, u8 cgr_val,
129 u8 clk_gate2_flags, spinlock_t *lock, 131 u8 clk_gate2_flags, spinlock_t *lock,
130 unsigned int *share_count) 132 unsigned int *share_count)
131{ 133{
@@ -140,6 +142,7 @@ struct clk *clk_register_gate2(struct device *dev, const char *name,
140 /* struct clk_gate2 assignments */ 142 /* struct clk_gate2 assignments */
141 gate->reg = reg; 143 gate->reg = reg;
142 gate->bit_idx = bit_idx; 144 gate->bit_idx = bit_idx;
145 gate->cgr_val = cgr_val;
143 gate->flags = clk_gate2_flags; 146 gate->flags = clk_gate2_flags;
144 gate->lock = lock; 147 gate->lock = lock;
145 gate->share_count = share_count; 148 gate->share_count = share_count;
diff --git a/drivers/clk/imx/clk-imx6sx.c b/drivers/clk/imx/clk-imx6sx.c
index fea125eb4330..97e742a8be17 100644
--- a/drivers/clk/imx/clk-imx6sx.c
+++ b/drivers/clk/imx/clk-imx6sx.c
@@ -134,6 +134,8 @@ static u32 share_count_esai;
134static u32 share_count_ssi1; 134static u32 share_count_ssi1;
135static u32 share_count_ssi2; 135static u32 share_count_ssi2;
136static u32 share_count_ssi3; 136static u32 share_count_ssi3;
137static u32 share_count_sai1;
138static u32 share_count_sai2;
137 139
138static struct clk ** const uart_clks[] __initconst = { 140static struct clk ** const uart_clks[] __initconst = {
139 &clks[IMX6SX_CLK_UART_IPG], 141 &clks[IMX6SX_CLK_UART_IPG],
@@ -469,10 +471,10 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
469 clks[IMX6SX_CLK_SSI3] = imx_clk_gate2_shared("ssi3", "ssi3_podf", base + 0x7c, 22, &share_count_ssi3); 471 clks[IMX6SX_CLK_SSI3] = imx_clk_gate2_shared("ssi3", "ssi3_podf", base + 0x7c, 22, &share_count_ssi3);
470 clks[IMX6SX_CLK_UART_IPG] = imx_clk_gate2("uart_ipg", "ipg", base + 0x7c, 24); 472 clks[IMX6SX_CLK_UART_IPG] = imx_clk_gate2("uart_ipg", "ipg", base + 0x7c, 24);
471 clks[IMX6SX_CLK_UART_SERIAL] = imx_clk_gate2("uart_serial", "uart_podf", base + 0x7c, 26); 473 clks[IMX6SX_CLK_UART_SERIAL] = imx_clk_gate2("uart_serial", "uart_podf", base + 0x7c, 26);
472 clks[IMX6SX_CLK_SAI1_IPG] = imx_clk_gate2("sai1_ipg", "ipg", base + 0x7c, 28); 474 clks[IMX6SX_CLK_SAI1_IPG] = imx_clk_gate2_shared("sai1_ipg", "ipg", base + 0x7c, 28, &share_count_sai1);
473 clks[IMX6SX_CLK_SAI2_IPG] = imx_clk_gate2("sai2_ipg", "ipg", base + 0x7c, 30); 475 clks[IMX6SX_CLK_SAI2_IPG] = imx_clk_gate2_shared("sai2_ipg", "ipg", base + 0x7c, 30, &share_count_sai2);
474 clks[IMX6SX_CLK_SAI1] = imx_clk_gate2("sai1", "ssi1_podf", base + 0x7c, 28); 476 clks[IMX6SX_CLK_SAI1] = imx_clk_gate2_shared("sai1", "ssi1_podf", base + 0x7c, 28, &share_count_sai1);
475 clks[IMX6SX_CLK_SAI2] = imx_clk_gate2("sai2", "ssi2_podf", base + 0x7c, 30); 477 clks[IMX6SX_CLK_SAI2] = imx_clk_gate2_shared("sai2", "ssi2_podf", base + 0x7c, 30, &share_count_sai2);
476 478
477 /* CCGR6 */ 479 /* CCGR6 */
478 clks[IMX6SX_CLK_USBOH3] = imx_clk_gate2("usboh3", "ipg", base + 0x80, 0); 480 clks[IMX6SX_CLK_USBOH3] = imx_clk_gate2("usboh3", "ipg", base + 0x80, 0);
diff --git a/drivers/clk/imx/clk-imx7d.c b/drivers/clk/imx/clk-imx7d.c
index fbb6a8c8653d..7912be83c4af 100644
--- a/drivers/clk/imx/clk-imx7d.c
+++ b/drivers/clk/imx/clk-imx7d.c
@@ -342,7 +342,7 @@ static const char *clko1_sel[] = { "osc", "pll_sys_main_clk",
342 342
343static const char *clko2_sel[] = { "osc", "pll_sys_main_240m_clk", 343static const char *clko2_sel[] = { "osc", "pll_sys_main_240m_clk",
344 "pll_sys_pfd0_392m_clk", "pll_sys_pfd1_166m_clk", "pll_sys_pfd4_clk", 344 "pll_sys_pfd0_392m_clk", "pll_sys_pfd1_166m_clk", "pll_sys_pfd4_clk",
345 "pll_audio_main_clk", "pll_video_main_clk", "osc_32k_clk", }; 345 "pll_audio_main_clk", "pll_video_main_clk", "ckil", };
346 346
347static const char *lvds1_sel[] = { "pll_arm_main_clk", 347static const char *lvds1_sel[] = { "pll_arm_main_clk",
348 "pll_sys_main_clk", "pll_sys_pfd0_392m_clk", "pll_sys_pfd1_332m_clk", 348 "pll_sys_main_clk", "pll_sys_pfd0_392m_clk", "pll_sys_pfd1_332m_clk",
@@ -382,6 +382,7 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
382 382
383 clks[IMX7D_CLK_DUMMY] = imx_clk_fixed("dummy", 0); 383 clks[IMX7D_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
384 clks[IMX7D_OSC_24M_CLK] = of_clk_get_by_name(ccm_node, "osc"); 384 clks[IMX7D_OSC_24M_CLK] = of_clk_get_by_name(ccm_node, "osc");
385 clks[IMX7D_CKIL] = of_clk_get_by_name(ccm_node, "ckil");
385 386
386 np = of_find_compatible_node(NULL, NULL, "fsl,imx7d-anatop"); 387 np = of_find_compatible_node(NULL, NULL, "fsl,imx7d-anatop");
387 base = of_iomap(np, 0); 388 base = of_iomap(np, 0);
diff --git a/drivers/clk/imx/clk-vf610.c b/drivers/clk/imx/clk-vf610.c
index 0a94d9661d91..3a1f24475ee4 100644
--- a/drivers/clk/imx/clk-vf610.c
+++ b/drivers/clk/imx/clk-vf610.c
@@ -10,6 +10,7 @@
10 10
11#include <linux/of_address.h> 11#include <linux/of_address.h>
12#include <linux/clk.h> 12#include <linux/clk.h>
13#include <linux/syscore_ops.h>
13#include <dt-bindings/clock/vf610-clock.h> 14#include <dt-bindings/clock/vf610-clock.h>
14 15
15#include "clk.h" 16#include "clk.h"
@@ -40,6 +41,7 @@
40#define CCM_CCGR9 (ccm_base + 0x64) 41#define CCM_CCGR9 (ccm_base + 0x64)
41#define CCM_CCGR10 (ccm_base + 0x68) 42#define CCM_CCGR10 (ccm_base + 0x68)
42#define CCM_CCGR11 (ccm_base + 0x6c) 43#define CCM_CCGR11 (ccm_base + 0x6c)
44#define CCM_CCGRx(x) (CCM_CCGR0 + (x) * 4)
43#define CCM_CMEOR0 (ccm_base + 0x70) 45#define CCM_CMEOR0 (ccm_base + 0x70)
44#define CCM_CMEOR1 (ccm_base + 0x74) 46#define CCM_CMEOR1 (ccm_base + 0x74)
45#define CCM_CMEOR2 (ccm_base + 0x78) 47#define CCM_CMEOR2 (ccm_base + 0x78)
@@ -115,10 +117,19 @@ static struct clk_div_table pll4_audio_div_table[] = {
115static struct clk *clk[VF610_CLK_END]; 117static struct clk *clk[VF610_CLK_END];
116static struct clk_onecell_data clk_data; 118static struct clk_onecell_data clk_data;
117 119
120static u32 cscmr1;
121static u32 cscmr2;
122static u32 cscdr1;
123static u32 cscdr2;
124static u32 cscdr3;
125static u32 ccgr[12];
126
118static unsigned int const clks_init_on[] __initconst = { 127static unsigned int const clks_init_on[] __initconst = {
119 VF610_CLK_SYS_BUS, 128 VF610_CLK_SYS_BUS,
120 VF610_CLK_DDR_SEL, 129 VF610_CLK_DDR_SEL,
121 VF610_CLK_DAP, 130 VF610_CLK_DAP,
131 VF610_CLK_DDRMC,
132 VF610_CLK_WKPU,
122}; 133};
123 134
124static struct clk * __init vf610_get_fixed_clock( 135static struct clk * __init vf610_get_fixed_clock(
@@ -132,6 +143,43 @@ static struct clk * __init vf610_get_fixed_clock(
132 return clk; 143 return clk;
133}; 144};
134 145
146static int vf610_clk_suspend(void)
147{
148 int i;
149
150 cscmr1 = readl_relaxed(CCM_CSCMR1);
151 cscmr2 = readl_relaxed(CCM_CSCMR2);
152
153 cscdr1 = readl_relaxed(CCM_CSCDR1);
154 cscdr2 = readl_relaxed(CCM_CSCDR2);
155 cscdr3 = readl_relaxed(CCM_CSCDR3);
156
157 for (i = 0; i < 12; i++)
158 ccgr[i] = readl_relaxed(CCM_CCGRx(i));
159
160 return 0;
161}
162
163static void vf610_clk_resume(void)
164{
165 int i;
166
167 writel_relaxed(cscmr1, CCM_CSCMR1);
168 writel_relaxed(cscmr2, CCM_CSCMR2);
169
170 writel_relaxed(cscdr1, CCM_CSCDR1);
171 writel_relaxed(cscdr2, CCM_CSCDR2);
172 writel_relaxed(cscdr3, CCM_CSCDR3);
173
174 for (i = 0; i < 12; i++)
175 writel_relaxed(ccgr[i], CCM_CCGRx(i));
176}
177
178static struct syscore_ops vf610_clk_syscore_ops = {
179 .suspend = vf610_clk_suspend,
180 .resume = vf610_clk_resume,
181};
182
135static void __init vf610_clocks_init(struct device_node *ccm_node) 183static void __init vf610_clocks_init(struct device_node *ccm_node)
136{ 184{
137 struct device_node *np; 185 struct device_node *np;
@@ -233,6 +281,9 @@ static void __init vf610_clocks_init(struct device_node *ccm_node)
233 clk[VF610_CLK_PLL4_MAIN_DIV] = clk_register_divider_table(NULL, "pll4_audio_div", "pll4_audio", 0, CCM_CACRR, 6, 3, 0, pll4_audio_div_table, &imx_ccm_lock); 281 clk[VF610_CLK_PLL4_MAIN_DIV] = clk_register_divider_table(NULL, "pll4_audio_div", "pll4_audio", 0, CCM_CACRR, 6, 3, 0, pll4_audio_div_table, &imx_ccm_lock);
234 clk[VF610_CLK_PLL6_MAIN_DIV] = imx_clk_divider("pll6_video_div", "pll6_video", CCM_CACRR, 21, 1); 282 clk[VF610_CLK_PLL6_MAIN_DIV] = imx_clk_divider("pll6_video_div", "pll6_video", CCM_CACRR, 21, 1);
235 283
284 clk[VF610_CLK_DDRMC] = imx_clk_gate2_cgr("ddrmc", "ddr_sel", CCM_CCGR6, CCM_CCGRx_CGn(14), 0x2);
285 clk[VF610_CLK_WKPU] = imx_clk_gate2_cgr("wkpu", "ipg_bus", CCM_CCGR4, CCM_CCGRx_CGn(10), 0x2);
286
236 clk[VF610_CLK_USBPHY0] = imx_clk_gate("usbphy0", "pll3_usb_otg", PLL3_CTRL, 6); 287 clk[VF610_CLK_USBPHY0] = imx_clk_gate("usbphy0", "pll3_usb_otg", PLL3_CTRL, 6);
237 clk[VF610_CLK_USBPHY1] = imx_clk_gate("usbphy1", "pll7_usb_host", PLL7_CTRL, 6); 288 clk[VF610_CLK_USBPHY1] = imx_clk_gate("usbphy1", "pll7_usb_host", PLL7_CTRL, 6);
238 289
@@ -321,11 +372,14 @@ static void __init vf610_clocks_init(struct device_node *ccm_node)
321 clk[VF610_CLK_DCU0_SEL] = imx_clk_mux("dcu0_sel", CCM_CSCMR1, 28, 1, dcu_sels, 2); 372 clk[VF610_CLK_DCU0_SEL] = imx_clk_mux("dcu0_sel", CCM_CSCMR1, 28, 1, dcu_sels, 2);
322 clk[VF610_CLK_DCU0_EN] = imx_clk_gate("dcu0_en", "dcu0_sel", CCM_CSCDR3, 19); 373 clk[VF610_CLK_DCU0_EN] = imx_clk_gate("dcu0_en", "dcu0_sel", CCM_CSCDR3, 19);
323 clk[VF610_CLK_DCU0_DIV] = imx_clk_divider("dcu0_div", "dcu0_en", CCM_CSCDR3, 16, 3); 374 clk[VF610_CLK_DCU0_DIV] = imx_clk_divider("dcu0_div", "dcu0_en", CCM_CSCDR3, 16, 3);
324 clk[VF610_CLK_DCU0] = imx_clk_gate2("dcu0", "dcu0_div", CCM_CCGR3, CCM_CCGRx_CGn(8)); 375 clk[VF610_CLK_DCU0] = imx_clk_gate2("dcu0", "ipg_bus", CCM_CCGR3, CCM_CCGRx_CGn(8));
325 clk[VF610_CLK_DCU1_SEL] = imx_clk_mux("dcu1_sel", CCM_CSCMR1, 29, 1, dcu_sels, 2); 376 clk[VF610_CLK_DCU1_SEL] = imx_clk_mux("dcu1_sel", CCM_CSCMR1, 29, 1, dcu_sels, 2);
326 clk[VF610_CLK_DCU1_EN] = imx_clk_gate("dcu1_en", "dcu1_sel", CCM_CSCDR3, 23); 377 clk[VF610_CLK_DCU1_EN] = imx_clk_gate("dcu1_en", "dcu1_sel", CCM_CSCDR3, 23);
327 clk[VF610_CLK_DCU1_DIV] = imx_clk_divider("dcu1_div", "dcu1_en", CCM_CSCDR3, 20, 3); 378 clk[VF610_CLK_DCU1_DIV] = imx_clk_divider("dcu1_div", "dcu1_en", CCM_CSCDR3, 20, 3);
328 clk[VF610_CLK_DCU1] = imx_clk_gate2("dcu1", "dcu1_div", CCM_CCGR9, CCM_CCGRx_CGn(8)); 379 clk[VF610_CLK_DCU1] = imx_clk_gate2("dcu1", "ipg_bus", CCM_CCGR9, CCM_CCGRx_CGn(8));
380
381 clk[VF610_CLK_TCON0] = imx_clk_gate2("tcon0", "platform_bus", CCM_CCGR1, CCM_CCGRx_CGn(13));
382 clk[VF610_CLK_TCON1] = imx_clk_gate2("tcon1", "platform_bus", CCM_CCGR7, CCM_CCGRx_CGn(13));
329 383
330 clk[VF610_CLK_ESAI_SEL] = imx_clk_mux("esai_sel", CCM_CSCMR1, 20, 2, esai_sels, 4); 384 clk[VF610_CLK_ESAI_SEL] = imx_clk_mux("esai_sel", CCM_CSCMR1, 20, 2, esai_sels, 4);
331 clk[VF610_CLK_ESAI_EN] = imx_clk_gate("esai_en", "esai_sel", CCM_CSCDR2, 30); 385 clk[VF610_CLK_ESAI_EN] = imx_clk_gate("esai_en", "esai_sel", CCM_CSCDR2, 30);
@@ -409,6 +463,8 @@ static void __init vf610_clocks_init(struct device_node *ccm_node)
409 for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) 463 for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
410 clk_prepare_enable(clk[clks_init_on[i]]); 464 clk_prepare_enable(clk[clks_init_on[i]]);
411 465
466 register_syscore_ops(&vf610_clk_syscore_ops);
467
412 /* Add the clocks to provider list */ 468 /* Add the clocks to provider list */
413 clk_data.clks = clk; 469 clk_data.clks = clk;
414 clk_data.clk_num = ARRAY_SIZE(clk); 470 clk_data.clk_num = ARRAY_SIZE(clk);
diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
index d942f5748d08..508d0fad84cf 100644
--- a/drivers/clk/imx/clk.h
+++ b/drivers/clk/imx/clk.h
@@ -41,7 +41,7 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
41 41
42struct clk *clk_register_gate2(struct device *dev, const char *name, 42struct clk *clk_register_gate2(struct device *dev, const char *name,
43 const char *parent_name, unsigned long flags, 43 const char *parent_name, unsigned long flags,
44 void __iomem *reg, u8 bit_idx, 44 void __iomem *reg, u8 bit_idx, u8 cgr_val,
45 u8 clk_gate_flags, spinlock_t *lock, 45 u8 clk_gate_flags, spinlock_t *lock,
46 unsigned int *share_count); 46 unsigned int *share_count);
47 47
@@ -55,7 +55,7 @@ static inline struct clk *imx_clk_gate2(const char *name, const char *parent,
55 void __iomem *reg, u8 shift) 55 void __iomem *reg, u8 shift)
56{ 56{
57 return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg, 57 return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
58 shift, 0, &imx_ccm_lock, NULL); 58 shift, 0x3, 0, &imx_ccm_lock, NULL);
59} 59}
60 60
61static inline struct clk *imx_clk_gate2_shared(const char *name, 61static inline struct clk *imx_clk_gate2_shared(const char *name,
@@ -63,7 +63,14 @@ static inline struct clk *imx_clk_gate2_shared(const char *name,
63 unsigned int *share_count) 63 unsigned int *share_count)
64{ 64{
65 return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg, 65 return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
66 shift, 0, &imx_ccm_lock, share_count); 66 shift, 0x3, 0, &imx_ccm_lock, share_count);
67}
68
69static inline struct clk *imx_clk_gate2_cgr(const char *name, const char *parent,
70 void __iomem *reg, u8 shift, u8 cgr_val)
71{
72 return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
73 shift, cgr_val, 0, &imx_ccm_lock, NULL);
67} 74}
68 75
69struct clk *imx_clk_pfd(const char *name, const char *parent_name, 76struct clk *imx_clk_pfd(const char *name, const char *parent_name,
diff --git a/include/dt-bindings/clock/imx7d-clock.h b/include/dt-bindings/clock/imx7d-clock.h
index edca8985c50e..1183347c383f 100644
--- a/include/dt-bindings/clock/imx7d-clock.h
+++ b/include/dt-bindings/clock/imx7d-clock.h
@@ -448,5 +448,6 @@
448#define IMX7D_PLL_DRAM_TEST_DIV 435 448#define IMX7D_PLL_DRAM_TEST_DIV 435
449#define IMX7D_ADC_ROOT_CLK 436 449#define IMX7D_ADC_ROOT_CLK 436
450#define IMX7D_CLK_ARM 437 450#define IMX7D_CLK_ARM 437
451#define IMX7D_CLK_END 438 451#define IMX7D_CKIL 438
452#define IMX7D_CLK_END 439
452#endif /* __DT_BINDINGS_CLOCK_IMX7D_H */ 453#endif /* __DT_BINDINGS_CLOCK_IMX7D_H */
diff --git a/include/dt-bindings/clock/vf610-clock.h b/include/dt-bindings/clock/vf610-clock.h
index 56c16aaea112..45997750c8a0 100644
--- a/include/dt-bindings/clock/vf610-clock.h
+++ b/include/dt-bindings/clock/vf610-clock.h
@@ -194,7 +194,11 @@
194#define VF610_PLL7_BYPASS 181 194#define VF610_PLL7_BYPASS 181
195#define VF610_CLK_SNVS 182 195#define VF610_CLK_SNVS 182
196#define VF610_CLK_DAP 183 196#define VF610_CLK_DAP 183
197#define VF610_CLK_OCOTP 184 197#define VF610_CLK_OCOTP 184
198#define VF610_CLK_END 185 198#define VF610_CLK_DDRMC 185
199#define VF610_CLK_WKPU 186
200#define VF610_CLK_TCON0 187
201#define VF610_CLK_TCON1 188
202#define VF610_CLK_END 189
199 203
200#endif /* __DT_BINDINGS_CLOCK_VF610_H */ 204#endif /* __DT_BINDINGS_CLOCK_VF610_H */