diff options
| author | Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> | 2019-03-28 01:31:32 -0400 |
|---|---|---|
| committer | Mauro Carvalho Chehab <mchehab+samsung@kernel.org> | 2019-04-25 11:07:05 -0400 |
| commit | 7afa8db323e37b9174cf78a1c9ab0ae7a9f5e7dd (patch) | |
| tree | 48d65dceba0d555aa6f62673b6c52b8a9c7f4db9 | |
| parent | 4735c16b8bdd3051227ca9c617b94009e4614e21 (diff) | |
media: vsp1: Add support for missing 16-bit RGB555 formats
Add support for the V4L2_PIX_FMT_RGBA555, V4L2_PIX_FMT_RGBX555,
V4L2_PIX_FMT_ABGR555, V4L2_PIX_FMT_XBGR555, V4L2_PIX_FMT_BGRA555 and
V4L2_PIX_FMT_BGRX555 formats to the VSP driver.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Reviewed-by: Jacopo Mondi <jacopo@jmondi.org>
Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
| -rw-r--r-- | drivers/media/platform/vsp1/vsp1_pipe.c | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/drivers/media/platform/vsp1/vsp1_pipe.c b/drivers/media/platform/vsp1/vsp1_pipe.c index 4332c138ee22..f72ac01c21ea 100644 --- a/drivers/media/platform/vsp1/vsp1_pipe.c +++ b/drivers/media/platform/vsp1/vsp1_pipe.c | |||
| @@ -74,6 +74,30 @@ static const struct vsp1_format_info vsp1_video_formats[] = { | |||
| 74 | VI6_FMT_XRGB_1555, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | | 74 | VI6_FMT_XRGB_1555, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | |
| 75 | VI6_RPF_DSWAP_P_WDS, | 75 | VI6_RPF_DSWAP_P_WDS, |
| 76 | 1, { 16, 0, 0 }, false, false, 1, 1, false }, | 76 | 1, { 16, 0, 0 }, false, false, 1, 1, false }, |
| 77 | { V4L2_PIX_FMT_RGBA555, MEDIA_BUS_FMT_ARGB8888_1X32, | ||
| 78 | VI6_FMT_RGBA_5551, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | | ||
| 79 | VI6_RPF_DSWAP_P_WDS, | ||
| 80 | 1, { 16, 0, 0 }, false, false, 1, 1, true }, | ||
| 81 | { V4L2_PIX_FMT_RGBX555, MEDIA_BUS_FMT_ARGB8888_1X32, | ||
| 82 | VI6_FMT_RGBX_5551, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | | ||
| 83 | VI6_RPF_DSWAP_P_WDS, | ||
| 84 | 1, { 16, 0, 0 }, false, false, 1, 1, false }, | ||
| 85 | { V4L2_PIX_FMT_ABGR555, MEDIA_BUS_FMT_ARGB8888_1X32, | ||
| 86 | VI6_FMT_ABGR_1555, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | | ||
| 87 | VI6_RPF_DSWAP_P_WDS, | ||
| 88 | 1, { 16, 0, 0 }, false, false, 1, 1, true }, | ||
| 89 | { V4L2_PIX_FMT_XBGR555, MEDIA_BUS_FMT_ARGB8888_1X32, | ||
| 90 | VI6_FMT_ABGR_1555, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | | ||
| 91 | VI6_RPF_DSWAP_P_WDS, | ||
| 92 | 1, { 16, 0, 0 }, false, false, 1, 1, false }, | ||
| 93 | { V4L2_PIX_FMT_BGRA555, MEDIA_BUS_FMT_ARGB8888_1X32, | ||
| 94 | VI6_FMT_BGRA_5551, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | | ||
| 95 | VI6_RPF_DSWAP_P_WDS, | ||
| 96 | 1, { 16, 0, 0 }, false, false, 1, 1, true }, | ||
| 97 | { V4L2_PIX_FMT_BGRX555, MEDIA_BUS_FMT_ARGB8888_1X32, | ||
| 98 | VI6_FMT_BGRA_5551, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | | ||
| 99 | VI6_RPF_DSWAP_P_WDS, | ||
| 100 | 1, { 16, 0, 0 }, false, false, 1, 1, false }, | ||
| 77 | { V4L2_PIX_FMT_RGB565, MEDIA_BUS_FMT_ARGB8888_1X32, | 101 | { V4L2_PIX_FMT_RGB565, MEDIA_BUS_FMT_ARGB8888_1X32, |
| 78 | VI6_FMT_RGB_565, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | | 102 | VI6_FMT_RGB_565, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS | |
| 79 | VI6_RPF_DSWAP_P_WDS, | 103 | VI6_RPF_DSWAP_P_WDS, |