Merge branch 'drm-fixes-4.9' of git://people.freedesktop.org/~agd5f/linux into drm-fixes

one small powerplay fix and one regression fix for older PX systems and d3cold

* 'drm-fixes-4.9' of git://people.freedesktop.org/~agd5f/linux:
  drm/radeon: fix power state when port pm is unavailable (v2)
  drm/amdgpu: fix power state when port pm is unavailable
  drm/amd/powerplay: avoid out of bounds access on array ps.

3 files changed, 22 insertions, 8 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c
index dae35a96a694..02ca5dd978f6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c
@@ -34,6 +34,7 @@ struct amdgpu_atpx {
 
 static struct amdgpu_atpx_priv {
         bool atpx_detected;
+        bool bridge_pm_usable;
         /* handle for device - and atpx */
         acpi_handle dhandle;
         acpi_handle other_handle;
@@ -205,7 +206,11 @@ static int amdgpu_atpx_validate(struct amdgpu_atpx *atpx)
         atpx->is_hybrid = false;
         if (valid_bits & ATPX_MS_HYBRID_GFX_SUPPORTED) {
                 printk("ATPX Hybrid Graphics\n");
-                atpx->functions.power_cntl = false;
+                /*
+                 * Disable legacy PM methods only when pcie port PM is usable,
+                 * otherwise the device might fail to power off or power on.
+                 */
+                atpx->functions.power_cntl = !amdgpu_atpx_priv.bridge_pm_usable;
                 atpx->is_hybrid = true;
         }
 
@@ -480,6 +485,7 @@ static int amdgpu_atpx_power_state(enum vga_switcheroo_client_id id,
  */
 static bool amdgpu_atpx_pci_probe_handle(struct pci_dev *pdev)
 {
+        struct pci_dev *parent_pdev = pci_upstream_bridge(pdev);
         acpi_handle dhandle, atpx_handle;
         acpi_status status;
 
@@ -494,6 +500,7 @@ static bool amdgpu_atpx_pci_probe_handle(struct pci_dev *pdev)
         }
         amdgpu_atpx_priv.dhandle = dhandle;
         amdgpu_atpx_priv.atpx.handle = atpx_handle;
+        amdgpu_atpx_priv.bridge_pm_usable = parent_pdev && parent_pdev->bridge_d3;
         return true;
 }
 
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index 13f2b705ea49..08cd0bd3ebe5 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -2984,19 +2984,19 @@ static int smu7_get_pp_table_entry_callback_func_v0(struct pp_hwmgr *hwmgr,
         if (!(data->mc_micro_code_feature & DISABLE_MC_LOADMICROCODE) && memory_clock > data->highest_mclk)
                 data->highest_mclk = memory_clock;
 
-        performance_level = &(ps->performance_levels
-                        [ps->performance_level_count++]);
-
         PP_ASSERT_WITH_CODE(
                         (ps->performance_level_count < smum_get_mac_definition(hwmgr->smumgr, SMU_MAX_LEVELS_GRAPHICS)),
                         "Performance levels exceeds SMC limit!",
                         return -EINVAL);
 
         PP_ASSERT_WITH_CODE(
-                        (ps->performance_level_count <=
+                        (ps->performance_level_count <
                                         hwmgr->platform_descriptor.hardwareActivityPerformanceLevels),
-                        "Performance levels exceeds Driver limit!",
-                        return -EINVAL);
+                        "Performance levels exceeds Driver limit, Skip!",
+                        return 0);
+
+        performance_level = &(ps->performance_levels
+                        [ps->performance_level_count++]);
 
         /* Performance levels are arranged from low to high. */
         performance_level->memory_clock = memory_clock;
diff --git a/drivers/gpu/drm/radeon/radeon_atpx_handler.c b/drivers/gpu/drm/radeon/radeon_atpx_handler.c
index 2fdcd04bc93f..4129b12521a6 100644
--- a/drivers/gpu/drm/radeon/radeon_atpx_handler.c
+++ b/drivers/gpu/drm/radeon/radeon_atpx_handler.c
@@ -34,6 +34,7 @@ struct radeon_atpx {
 
 static struct radeon_atpx_priv {
         bool atpx_detected;
+        bool bridge_pm_usable;
         /* handle for device - and atpx */
         acpi_handle dhandle;
         struct radeon_atpx atpx;
@@ -203,7 +204,11 @@ static int radeon_atpx_validate(struct radeon_atpx *atpx)
         atpx->is_hybrid = false;
         if (valid_bits & ATPX_MS_HYBRID_GFX_SUPPORTED) {
                 printk("ATPX Hybrid Graphics\n");
-                atpx->functions.power_cntl = false;
+                /*
+                 * Disable legacy PM methods only when pcie port PM is usable,
+                 * otherwise the device might fail to power off or power on.
+                 */
+                atpx->functions.power_cntl = !radeon_atpx_priv.bridge_pm_usable;
                 atpx->is_hybrid = true;
         }
 
@@ -474,6 +479,7 @@ static int radeon_atpx_power_state(enum vga_switcheroo_client_id id,
  */
 static bool radeon_atpx_pci_probe_handle(struct pci_dev *pdev)
 {
+        struct pci_dev *parent_pdev = pci_upstream_bridge(pdev);
         acpi_handle dhandle, atpx_handle;
         acpi_status status;
 
@@ -487,6 +493,7 @@ static bool radeon_atpx_pci_probe_handle(struct pci_dev *pdev)
 
         radeon_atpx_priv.dhandle = dhandle;
         radeon_atpx_priv.atpx.handle = atpx_handle;
+        radeon_atpx_priv.bridge_pm_usable = parent_pdev && parent_pdev->bridge_d3;
         return true;
 }