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authorGeert Uytterhoeven <geert+renesas@glider.be>2018-09-06 08:41:01 -0400
committerSimon Horman <horms+renesas@verge.net.au>2018-09-13 03:48:12 -0400
commit7acc17b1a3e96d1e541c48abd89fa74d1e752f15 (patch)
treeaf3b7dda5c88f674eca568a82738f7959a39385c
parent9bc03b57277c4272a9ef7c8c22672109d4416944 (diff)
arm64: dts: renesas: draak: Sort device nodes
- Device nodes with unit addresses are sorted by unit address, - Device nodes without unit addresses and references are sorted alphabetically. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
-rw-r--r--arch/arm64/boot/dts/renesas/r8a77995-draak.dts276
1 files changed, 138 insertions, 138 deletions
diff --git a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
index a8e8f2669d4c..e39b73005381 100644
--- a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
@@ -24,38 +24,6 @@
24 stdout-path = "serial0:115200n8"; 24 stdout-path = "serial0:115200n8";
25 }; 25 };
26 26
27 vga {
28 compatible = "vga-connector";
29
30 port {
31 vga_in: endpoint {
32 remote-endpoint = <&adv7123_out>;
33 };
34 };
35 };
36
37 vga-encoder {
38 compatible = "adi,adv7123";
39
40 ports {
41 #address-cells = <1>;
42 #size-cells = <0>;
43
44 port@0 {
45 reg = <0>;
46 adv7123_in: endpoint {
47 remote-endpoint = <&du_out_rgb>;
48 };
49 };
50 port@1 {
51 reg = <1>;
52 adv7123_out: endpoint {
53 remote-endpoint = <&vga_in>;
54 };
55 };
56 };
57 };
58
59 composite-in { 27 composite-in {
60 compatible = "composite-video-connector"; 28 compatible = "composite-video-connector";
61 29
@@ -101,76 +69,86 @@
101 regulator-always-on; 69 regulator-always-on;
102 }; 70 };
103 71
104 x12_clk: x12 { 72 vga {
105 compatible = "fixed-clock"; 73 compatible = "vga-connector";
106 #clock-cells = <0>;
107 clock-frequency = <74250000>;
108 };
109};
110
111&extal_clk {
112 clock-frequency = <48000000>;
113};
114 74
115&pfc { 75 port {
116 avb0_pins: avb { 76 vga_in: endpoint {
117 mux { 77 remote-endpoint = <&adv7123_out>;
118 groups = "avb0_link", "avb0_mdio", "avb0_mii"; 78 };
119 function = "avb0";
120 }; 79 };
121 }; 80 };
122 81
123 du_pins: du { 82 vga-encoder {
124 groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0"; 83 compatible = "adi,adv7123";
125 function = "du";
126 };
127 84
128 i2c0_pins: i2c0 { 85 ports {
129 groups = "i2c0"; 86 #address-cells = <1>;
130 function = "i2c0"; 87 #size-cells = <0>;
131 };
132 88
133 i2c1_pins: i2c1 { 89 port@0 {
134 groups = "i2c1"; 90 reg = <0>;
135 function = "i2c1"; 91 adv7123_in: endpoint {
92 remote-endpoint = <&du_out_rgb>;
93 };
94 };
95 port@1 {
96 reg = <1>;
97 adv7123_out: endpoint {
98 remote-endpoint = <&vga_in>;
99 };
100 };
101 };
136 }; 102 };
137 103
138 pwm0_pins: pwm0 { 104 x12_clk: x12 {
139 groups = "pwm0_c"; 105 compatible = "fixed-clock";
140 function = "pwm0"; 106 #clock-cells = <0>;
107 clock-frequency = <74250000>;
141 }; 108 };
109};
142 110
143 pwm1_pins: pwm1 { 111&avb {
144 groups = "pwm1_c"; 112 pinctrl-0 = <&avb0_pins>;
145 function = "pwm1"; 113 pinctrl-names = "default";
146 }; 114 renesas,no-ether-link;
115 phy-handle = <&phy0>;
116 phy-mode = "rgmii-txid";
117 status = "okay";
147 118
148 scif2_pins: scif2 { 119 phy0: ethernet-phy@0 {
149 groups = "scif2_data"; 120 rxc-skew-ps = <1500>;
150 function = "scif2"; 121 reg = <0>;
122 interrupt-parent = <&gpio5>;
123 interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
151 }; 124 };
125};
152 126
153 sdhi2_pins: sd2 { 127&du {
154 groups = "mmc_data8", "mmc_ctrl"; 128 pinctrl-0 = <&du_pins>;
155 function = "mmc"; 129 pinctrl-names = "default";
156 power-source = <1800>; 130 status = "okay";
157 };
158 131
159 sdhi2_pins_uhs: sd2_uhs { 132 clocks = <&cpg CPG_MOD 724>,
160 groups = "mmc_data8", "mmc_ctrl"; 133 <&cpg CPG_MOD 723>,
161 function = "mmc"; 134 <&x12_clk>;
162 power-source = <1800>; 135 clock-names = "du.0", "du.1", "dclkin.0";
163 };
164 136
165 usb0_pins: usb0 { 137 ports {
166 groups = "usb0"; 138 port@0 {
167 function = "usb0"; 139 endpoint {
140 remote-endpoint = <&adv7123_in>;
141 };
142 };
168 }; 143 };
144};
169 145
170 vin4_pins_cvbs: vin4 { 146&ehci0 {
171 groups = "vin4_data8", "vin4_sync", "vin4_clk"; 147 status = "okay";
172 function = "vin4"; 148};
173 }; 149
150&extal_clk {
151 clock-frequency = <48000000>;
174}; 152};
175 153
176&i2c0 { 154&i2c0 {
@@ -178,12 +156,6 @@
178 pinctrl-names = "default"; 156 pinctrl-names = "default";
179 status = "okay"; 157 status = "okay";
180 158
181 eeprom@50 {
182 compatible = "rohm,br24t01", "atmel,24c01";
183 reg = <0x50>;
184 pagesize = <8>;
185 };
186
187 composite-in@20 { 159 composite-in@20 {
188 compatible = "adi,adv7180cp"; 160 compatible = "adi,adv7180cp";
189 reg = <0x20>; 161 reg = <0x20>;
@@ -254,6 +226,12 @@
254 }; 226 };
255 }; 227 };
256 }; 228 };
229
230 eeprom@50 {
231 compatible = "rohm,br24t01", "atmel,24c01";
232 reg = <0x50>;
233 pagesize = <8>;
234 };
257}; 235};
258 236
259&i2c1 { 237&i2c1 {
@@ -262,47 +240,88 @@
262 status = "okay"; 240 status = "okay";
263}; 241};
264 242
265&du { 243&ohci0 {
266 pinctrl-0 = <&du_pins>;
267 pinctrl-names = "default";
268 status = "okay"; 244 status = "okay";
245};
269 246
270 clocks = <&cpg CPG_MOD 724>, 247&pfc {
271 <&cpg CPG_MOD 723>, 248 avb0_pins: avb {
272 <&x12_clk>; 249 mux {
273 clock-names = "du.0", "du.1", "dclkin.0"; 250 groups = "avb0_link", "avb0_mdio", "avb0_mii";
274 251 function = "avb0";
275 ports {
276 port@0 {
277 endpoint {
278 remote-endpoint = <&adv7123_in>;
279 };
280 }; 252 };
281 }; 253 };
282};
283 254
284&ehci0 { 255 du_pins: du {
285 status = "okay"; 256 groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
257 function = "du";
258 };
259
260 i2c0_pins: i2c0 {
261 groups = "i2c0";
262 function = "i2c0";
263 };
264
265 i2c1_pins: i2c1 {
266 groups = "i2c1";
267 function = "i2c1";
268 };
269
270 pwm0_pins: pwm0 {
271 groups = "pwm0_c";
272 function = "pwm0";
273 };
274
275 pwm1_pins: pwm1 {
276 groups = "pwm1_c";
277 function = "pwm1";
278 };
279
280 scif2_pins: scif2 {
281 groups = "scif2_data";
282 function = "scif2";
283 };
284
285 sdhi2_pins: sd2 {
286 groups = "mmc_data8", "mmc_ctrl";
287 function = "mmc";
288 power-source = <1800>;
289 };
290
291 sdhi2_pins_uhs: sd2_uhs {
292 groups = "mmc_data8", "mmc_ctrl";
293 function = "mmc";
294 power-source = <1800>;
295 };
296
297 usb0_pins: usb0 {
298 groups = "usb0";
299 function = "usb0";
300 };
301
302 vin4_pins_cvbs: vin4 {
303 groups = "vin4_data8", "vin4_sync", "vin4_clk";
304 function = "vin4";
305 };
286}; 306};
287 307
288&ohci0 { 308&pwm0 {
309 pinctrl-0 = <&pwm0_pins>;
310 pinctrl-names = "default";
311
289 status = "okay"; 312 status = "okay";
290}; 313};
291 314
292&avb { 315&pwm1 {
293 pinctrl-0 = <&avb0_pins>; 316 pinctrl-0 = <&pwm1_pins>;
294 pinctrl-names = "default"; 317 pinctrl-names = "default";
295 renesas,no-ether-link; 318
296 phy-handle = <&phy0>;
297 phy-mode = "rgmii-txid";
298 status = "okay"; 319 status = "okay";
320};
299 321
300 phy0: ethernet-phy@0 { 322&rwdt {
301 rxc-skew-ps = <1500>; 323 timeout-sec = <60>;
302 reg = <0>; 324 status = "okay";
303 interrupt-parent = <&gpio5>;
304 interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
305 };
306}; 325};
307 326
308&scif2 { 327&scif2 {
@@ -333,25 +352,6 @@
333 status = "okay"; 352 status = "okay";
334}; 353};
335 354
336&pwm0 {
337 pinctrl-0 = <&pwm0_pins>;
338 pinctrl-names = "default";
339
340 status = "okay";
341};
342
343&pwm1 {
344 pinctrl-0 = <&pwm1_pins>;
345 pinctrl-names = "default";
346
347 status = "okay";
348};
349
350&rwdt {
351 timeout-sec = <60>;
352 status = "okay";
353};
354
355&vin4 { 355&vin4 {
356 pinctrl-0 = <&vin4_pins_cvbs>; 356 pinctrl-0 = <&vin4_pins_cvbs>;
357 pinctrl-names = "default"; 357 pinctrl-names = "default";