diff options
author | Shinobu Uehara <shinobu.uehara.xc@renesas.com> | 2015-06-05 18:36:50 -0400 |
---|---|---|
committer | Linus Walleij <linus.walleij@linaro.org> | 2015-06-16 04:55:09 -0400 |
commit | 7ac91bda80a05122ca86240b1da3a68a4cdaa982 (patch) | |
tree | ddecbf95c4a1482e40e2a6814502c3e9b63df88f | |
parent | f1f74b640c952e311aebaa594d9d81fecb72cc17 (diff) |
pinctrl: sh-pfc: r8a7794: add SDHI pin groups
Add SDHI0/1/2 pin groups to R8A7794 PFC driver.
Signed-off-by: Shinobu Uehara <shinobu.uehara.xc@renesas.com>
[Sergei: renamed SD data pins to match the driver, rebased, renamed, added
changelog.]
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
-rw-r--r-- | drivers/pinctrl/sh-pfc/pfc-r8a7794.c | 153 |
1 files changed, 153 insertions, 0 deletions
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7794.c b/drivers/pinctrl/sh-pfc/pfc-r8a7794.c index 4679ca01f976..bfdcac4b3bc4 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7794.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7794.c | |||
@@ -2659,6 +2659,117 @@ static const unsigned int scifb2_ctrl_pins[] = { | |||
2659 | static const unsigned int scifb2_ctrl_mux[] = { | 2659 | static const unsigned int scifb2_ctrl_mux[] = { |
2660 | SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK, | 2660 | SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK, |
2661 | }; | 2661 | }; |
2662 | /* - SDHI0 ------------------------------------------------------------------ */ | ||
2663 | static const unsigned int sdhi0_data1_pins[] = { | ||
2664 | /* D0 */ | ||
2665 | RCAR_GP_PIN(6, 2), | ||
2666 | }; | ||
2667 | static const unsigned int sdhi0_data1_mux[] = { | ||
2668 | SD0_DATA0_MARK, | ||
2669 | }; | ||
2670 | static const unsigned int sdhi0_data4_pins[] = { | ||
2671 | /* D[0:3] */ | ||
2672 | RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3), | ||
2673 | RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5), | ||
2674 | }; | ||
2675 | static const unsigned int sdhi0_data4_mux[] = { | ||
2676 | SD0_DATA0_MARK, SD0_DATA1_MARK, SD0_DATA2_MARK, SD0_DATA3_MARK, | ||
2677 | }; | ||
2678 | static const unsigned int sdhi0_ctrl_pins[] = { | ||
2679 | /* CLK, CMD */ | ||
2680 | RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1), | ||
2681 | }; | ||
2682 | static const unsigned int sdhi0_ctrl_mux[] = { | ||
2683 | SD0_CLK_MARK, SD0_CMD_MARK, | ||
2684 | }; | ||
2685 | static const unsigned int sdhi0_cd_pins[] = { | ||
2686 | /* CD */ | ||
2687 | RCAR_GP_PIN(6, 6), | ||
2688 | }; | ||
2689 | static const unsigned int sdhi0_cd_mux[] = { | ||
2690 | SD0_CD_MARK, | ||
2691 | }; | ||
2692 | static const unsigned int sdhi0_wp_pins[] = { | ||
2693 | /* WP */ | ||
2694 | RCAR_GP_PIN(6, 7), | ||
2695 | }; | ||
2696 | static const unsigned int sdhi0_wp_mux[] = { | ||
2697 | SD0_WP_MARK, | ||
2698 | }; | ||
2699 | /* - SDHI1 ------------------------------------------------------------------ */ | ||
2700 | static const unsigned int sdhi1_data1_pins[] = { | ||
2701 | /* D0 */ | ||
2702 | RCAR_GP_PIN(6, 10), | ||
2703 | }; | ||
2704 | static const unsigned int sdhi1_data1_mux[] = { | ||
2705 | SD1_DATA0_MARK, | ||
2706 | }; | ||
2707 | static const unsigned int sdhi1_data4_pins[] = { | ||
2708 | /* D[0:3] */ | ||
2709 | RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11), | ||
2710 | RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13), | ||
2711 | }; | ||
2712 | static const unsigned int sdhi1_data4_mux[] = { | ||
2713 | SD1_DATA0_MARK, SD1_DATA1_MARK, SD1_DATA2_MARK, SD1_DATA3_MARK, | ||
2714 | }; | ||
2715 | static const unsigned int sdhi1_ctrl_pins[] = { | ||
2716 | /* CLK, CMD */ | ||
2717 | RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), | ||
2718 | }; | ||
2719 | static const unsigned int sdhi1_ctrl_mux[] = { | ||
2720 | SD1_CLK_MARK, SD1_CMD_MARK, | ||
2721 | }; | ||
2722 | static const unsigned int sdhi1_cd_pins[] = { | ||
2723 | /* CD */ | ||
2724 | RCAR_GP_PIN(6, 14), | ||
2725 | }; | ||
2726 | static const unsigned int sdhi1_cd_mux[] = { | ||
2727 | SD1_CD_MARK, | ||
2728 | }; | ||
2729 | static const unsigned int sdhi1_wp_pins[] = { | ||
2730 | /* WP */ | ||
2731 | RCAR_GP_PIN(6, 15), | ||
2732 | }; | ||
2733 | static const unsigned int sdhi1_wp_mux[] = { | ||
2734 | SD1_WP_MARK, | ||
2735 | }; | ||
2736 | /* - SDHI2 ------------------------------------------------------------------ */ | ||
2737 | static const unsigned int sdhi2_data1_pins[] = { | ||
2738 | /* D0 */ | ||
2739 | RCAR_GP_PIN(6, 18), | ||
2740 | }; | ||
2741 | static const unsigned int sdhi2_data1_mux[] = { | ||
2742 | SD2_DATA0_MARK, | ||
2743 | }; | ||
2744 | static const unsigned int sdhi2_data4_pins[] = { | ||
2745 | /* D[0:3] */ | ||
2746 | RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19), | ||
2747 | RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21), | ||
2748 | }; | ||
2749 | static const unsigned int sdhi2_data4_mux[] = { | ||
2750 | SD2_DATA0_MARK, SD2_DATA1_MARK, SD2_DATA2_MARK, SD2_DATA3_MARK, | ||
2751 | }; | ||
2752 | static const unsigned int sdhi2_ctrl_pins[] = { | ||
2753 | /* CLK, CMD */ | ||
2754 | RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17), | ||
2755 | }; | ||
2756 | static const unsigned int sdhi2_ctrl_mux[] = { | ||
2757 | SD2_CLK_MARK, SD2_CMD_MARK, | ||
2758 | }; | ||
2759 | static const unsigned int sdhi2_cd_pins[] = { | ||
2760 | /* CD */ | ||
2761 | RCAR_GP_PIN(6, 22), | ||
2762 | }; | ||
2763 | static const unsigned int sdhi2_cd_mux[] = { | ||
2764 | SD2_CD_MARK, | ||
2765 | }; | ||
2766 | static const unsigned int sdhi2_wp_pins[] = { | ||
2767 | /* WP */ | ||
2768 | RCAR_GP_PIN(6, 23), | ||
2769 | }; | ||
2770 | static const unsigned int sdhi2_wp_mux[] = { | ||
2771 | SD2_WP_MARK, | ||
2772 | }; | ||
2662 | 2773 | ||
2663 | static const struct sh_pfc_pin_group pinmux_groups[] = { | 2774 | static const struct sh_pfc_pin_group pinmux_groups[] = { |
2664 | SH_PFC_PIN_GROUP(eth_link), | 2775 | SH_PFC_PIN_GROUP(eth_link), |
@@ -2819,6 +2930,21 @@ static const struct sh_pfc_pin_group pinmux_groups[] = { | |||
2819 | SH_PFC_PIN_GROUP(scifb2_data), | 2930 | SH_PFC_PIN_GROUP(scifb2_data), |
2820 | SH_PFC_PIN_GROUP(scifb2_clk), | 2931 | SH_PFC_PIN_GROUP(scifb2_clk), |
2821 | SH_PFC_PIN_GROUP(scifb2_ctrl), | 2932 | SH_PFC_PIN_GROUP(scifb2_ctrl), |
2933 | SH_PFC_PIN_GROUP(sdhi0_data1), | ||
2934 | SH_PFC_PIN_GROUP(sdhi0_data4), | ||
2935 | SH_PFC_PIN_GROUP(sdhi0_ctrl), | ||
2936 | SH_PFC_PIN_GROUP(sdhi0_cd), | ||
2937 | SH_PFC_PIN_GROUP(sdhi0_wp), | ||
2938 | SH_PFC_PIN_GROUP(sdhi1_data1), | ||
2939 | SH_PFC_PIN_GROUP(sdhi1_data4), | ||
2940 | SH_PFC_PIN_GROUP(sdhi1_ctrl), | ||
2941 | SH_PFC_PIN_GROUP(sdhi1_cd), | ||
2942 | SH_PFC_PIN_GROUP(sdhi1_wp), | ||
2943 | SH_PFC_PIN_GROUP(sdhi2_data1), | ||
2944 | SH_PFC_PIN_GROUP(sdhi2_data4), | ||
2945 | SH_PFC_PIN_GROUP(sdhi2_ctrl), | ||
2946 | SH_PFC_PIN_GROUP(sdhi2_cd), | ||
2947 | SH_PFC_PIN_GROUP(sdhi2_wp), | ||
2822 | }; | 2948 | }; |
2823 | 2949 | ||
2824 | static const char * const eth_groups[] = { | 2950 | static const char * const eth_groups[] = { |
@@ -3069,6 +3195,30 @@ static const char * const scifb2_groups[] = { | |||
3069 | "scifb2_ctrl", | 3195 | "scifb2_ctrl", |
3070 | }; | 3196 | }; |
3071 | 3197 | ||
3198 | static const char * const sdhi0_groups[] = { | ||
3199 | "sdhi0_data1", | ||
3200 | "sdhi0_data4", | ||
3201 | "sdhi0_ctrl", | ||
3202 | "sdhi0_cd", | ||
3203 | "sdhi0_wp", | ||
3204 | }; | ||
3205 | |||
3206 | static const char * const sdhi1_groups[] = { | ||
3207 | "sdhi1_data1", | ||
3208 | "sdhi1_data4", | ||
3209 | "sdhi1_ctrl", | ||
3210 | "sdhi1_cd", | ||
3211 | "sdhi1_wp", | ||
3212 | }; | ||
3213 | |||
3214 | static const char * const sdhi2_groups[] = { | ||
3215 | "sdhi2_data1", | ||
3216 | "sdhi2_data4", | ||
3217 | "sdhi2_ctrl", | ||
3218 | "sdhi2_cd", | ||
3219 | "sdhi2_wp", | ||
3220 | }; | ||
3221 | |||
3072 | static const struct sh_pfc_function pinmux_functions[] = { | 3222 | static const struct sh_pfc_function pinmux_functions[] = { |
3073 | SH_PFC_FUNCTION(eth), | 3223 | SH_PFC_FUNCTION(eth), |
3074 | SH_PFC_FUNCTION(hscif0), | 3224 | SH_PFC_FUNCTION(hscif0), |
@@ -3100,6 +3250,9 @@ static const struct sh_pfc_function pinmux_functions[] = { | |||
3100 | SH_PFC_FUNCTION(scifb0), | 3250 | SH_PFC_FUNCTION(scifb0), |
3101 | SH_PFC_FUNCTION(scifb1), | 3251 | SH_PFC_FUNCTION(scifb1), |
3102 | SH_PFC_FUNCTION(scifb2), | 3252 | SH_PFC_FUNCTION(scifb2), |
3253 | SH_PFC_FUNCTION(sdhi0), | ||
3254 | SH_PFC_FUNCTION(sdhi1), | ||
3255 | SH_PFC_FUNCTION(sdhi2), | ||
3103 | }; | 3256 | }; |
3104 | 3257 | ||
3105 | static const struct pinmux_cfg_reg pinmux_config_regs[] = { | 3258 | static const struct pinmux_cfg_reg pinmux_config_regs[] = { |