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authorScott Wood <oss@buserror.net>2016-03-15 02:47:38 -0400
committerMichael Ellerman <mpe@ellerman.id.au>2016-03-16 00:22:16 -0400
commit7a25d91214cb22e642b9ed6e4434bfaf74adad28 (patch)
tree9336b5dee251126703e6ea2ec90126c9b08f60df
parenta1b5344620a3e6291afaf7542714ba9c391ef1c7 (diff)
powerpc/book3e-64: Use hardcoded mttmr opcode
This preserves the ability to build using older binutils (reportedly <= 2.22). Fixes: 6becef7ea04a ("powerpc/mpc85xx: Add CPU hotplug support for E6500") Signed-off-by: Scott Wood <oss@buserror.net> Cc: chenhui.zhao@freescale.com Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
-rw-r--r--arch/powerpc/kernel/head_64.S9
1 files changed, 5 insertions, 4 deletions
diff --git a/arch/powerpc/kernel/head_64.S b/arch/powerpc/kernel/head_64.S
index 291628320fbe..4286775cbde9 100644
--- a/arch/powerpc/kernel/head_64.S
+++ b/arch/powerpc/kernel/head_64.S
@@ -41,6 +41,7 @@
41#include <asm/ptrace.h> 41#include <asm/ptrace.h>
42#include <asm/hw_irq.h> 42#include <asm/hw_irq.h>
43#include <asm/cputhreads.h> 43#include <asm/cputhreads.h>
44#include <asm/ppc-opcode.h>
44 45
45/* The physical memory is laid out such that the secondary processor 46/* The physical memory is laid out such that the secondary processor
46 * spin code sits at 0x0000...0x00ff. On server, the vectors follow 47 * spin code sits at 0x0000...0x00ff. On server, the vectors follow
@@ -207,12 +208,12 @@ _GLOBAL(book3e_start_thread)
207 /* If the thread id is invalid, just exit. */ 208 /* If the thread id is invalid, just exit. */
208 b 13f 209 b 13f
20910: 21010:
210 mttmr TMRN_IMSR0, r5 211 MTTMR(TMRN_IMSR0, 5)
211 mttmr TMRN_INIA0, r4 212 MTTMR(TMRN_INIA0, 4)
212 b 12f 213 b 12f
21311: 21411:
214 mttmr TMRN_IMSR1, r5 215 MTTMR(TMRN_IMSR1, 5)
215 mttmr TMRN_INIA1, r4 216 MTTMR(TMRN_INIA1, 4)
21612: 21712:
217 isync 218 isync
218 li r6, 1 219 li r6, 1