Merge branch 'drm-next-4.7' of git://people.freedesktop.org/~agd5f/linux into drm-next

AMD GPU bugfixes:
- Various powerplay bug fixes
- Add some new polaris pci ids
- misc bug fixes and code cleanups

* 'drm-next-4.7' of git://people.freedesktop.org/~agd5f/linux: (27 commits)
  drm/amd: add Kconfig dependency for ACP on DRM_AMDGPU
  drm/amdgpu: Fix hdmi deep color support.
  drm/amdgpu: fix bug in fence driver fini
  drm/amd/powerplay/hwmgr: use kmemdup
  drm/amd/powerplay/hwmgr: use kmemdup
  drm/amd/powerplay/hwmgr: use kmemdup
  drm/amd/powerplay: fix bugs of checking if dpm is running on Tonga
  drm/amdgpu: update Polaris11 golden setting
  drm/amdgpu: Add more Polaris 11 PCI IDs
  drm/amdgpu: update Polaris10 golden setting
  drm/amdgpu: add more Polaris10 DID
  drm/amd/amdgpu : Remove unused variable
  drm/amd/amdgpu : Remove unused variable
  drm/amd/amdgpu : Remove unused variable
  drm/amd/amdgpu/cz_dpm: Remove unused variable
  drm/amd/amdgpu : Remove unused variable
  drm/amd/powerplay: use ARRAY_SIZE() to calculate array size.
  drm/amdgpu: fix array out of bounds
  drm/radeon: fix array out of bounds
  drm/amd/powerplay: fix a bug on updating sclk for Tonga
  ...

22 files changed, 183 insertions, 182 deletions

diff --git a/drivers/gpu/drm/amd/acp/Kconfig b/drivers/gpu/drm/amd/acp/Kconfig
index ca77ec10147c..e503e3d6d920 100644
--- a/drivers/gpu/drm/amd/acp/Kconfig
+++ b/drivers/gpu/drm/amd/acp/Kconfig
@@ -2,6 +2,7 @@ menu "ACP (Audio CoProcessor) Configuration"
 
 config DRM_AMD_ACP
        bool "Enable AMD Audio CoProcessor IP support"
+       depends on DRM_AMDGPU
        select MFD_CORE
        select PM_GENERIC_DOMAINS if PM
        help
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 2a009c398dcb..992f00b65be4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -602,6 +602,8 @@ int amdgpu_sync_wait(struct amdgpu_sync *sync);
 void amdgpu_sync_free(struct amdgpu_sync *sync);
 int amdgpu_sync_init(void);
 void amdgpu_sync_fini(void);
+int amdgpu_fence_slab_init(void);
+void amdgpu_fence_slab_fini(void);
 
 /*
  * GART structures, functions & helpers
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
index 60a0c9ac11b2..cb07da41152b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
@@ -194,12 +194,12 @@ int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector)
                                 bpc = 8;
                                 DRM_DEBUG("%s: HDMI deep color 10 bpc exceeds max tmds clock. Using %d bpc.\n",
                                           connector->name, bpc);
-                        } else if (bpc > 8) {
-                                /* max_tmds_clock missing, but hdmi spec mandates it for deep color. */
-                                DRM_DEBUG("%s: Required max tmds clock for HDMI deep color missing. Using 8 bpc.\n",
-                                          connector->name);
-                                bpc = 8;
                         }
+                } else if (bpc > 8) {
+                        /* max_tmds_clock missing, but hdmi spec mandates it for deep color. */
+                        DRM_DEBUG("%s: Required max tmds clock for HDMI deep color missing. Using 8 bpc.\n",
+                                  connector->name);
+                        bpc = 8;
                 }
         }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 1dab5f2b725b..f888c015f76c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -50,9 +50,11 @@
  * KMS wrapper.
  * - 3.0.0 - initial driver
  * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP)
+ * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same
+ *           at the end of IBs.
  */
 #define KMS_DRIVER_MAJOR        3
-#define KMS_DRIVER_MINOR        1
+#define KMS_DRIVER_MINOR        2
 #define KMS_DRIVER_PATCHLEVEL   0
 
 int amdgpu_vram_limit = 0;
@@ -279,14 +281,26 @@ static const struct pci_device_id pciidlist[] = {
         {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU},
         /* Polaris11 */
         {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
-        {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
+        {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
         {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
-        {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
         {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
+        {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
         {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
+        {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
+        {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
+        {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
         /* Polaris10 */
         {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
+        {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
+        {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
+        {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
+        {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
         {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
+        {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
+        {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
+        {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
+        {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
+        {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
 
         {0, 0, 0}
 };
@@ -563,9 +577,12 @@ static struct pci_driver amdgpu_kms_pci_driver = {
         .driver.pm = &amdgpu_pm_ops,
 };
 
+
+
 static int __init amdgpu_init(void)
 {
         amdgpu_sync_init();
+        amdgpu_fence_slab_init();
         if (vgacon_text_force()) {
                 DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n");
                 return -EINVAL;
@@ -576,7 +593,6 @@ static int __init amdgpu_init(void)
         driver->driver_features |= DRIVER_MODESET;
         driver->num_ioctls = amdgpu_max_kms_ioctl;
         amdgpu_register_atpx_handler();
-
         /* let modprobe override vga console setting */
         return drm_pci_init(driver, pdriver);
 }
@@ -587,6 +603,7 @@ static void __exit amdgpu_exit(void)
         drm_pci_exit(driver, pdriver);
         amdgpu_unregister_atpx_handler();
         amdgpu_sync_fini();
+        amdgpu_fence_slab_fini();
 }
 
 module_init(amdgpu_init);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
index ba9c04283d01..d1558768cfb7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
@@ -55,8 +55,21 @@ struct amdgpu_fence {
 };
 
 static struct kmem_cache *amdgpu_fence_slab;
-static atomic_t amdgpu_fence_slab_ref = ATOMIC_INIT(0);
 
+int amdgpu_fence_slab_init(void)
+{
+        amdgpu_fence_slab = kmem_cache_create(
+                "amdgpu_fence", sizeof(struct amdgpu_fence), 0,
+                SLAB_HWCACHE_ALIGN, NULL);
+        if (!amdgpu_fence_slab)
+                return -ENOMEM;
+        return 0;
+}
+
+void amdgpu_fence_slab_fini(void)
+{
+        kmem_cache_destroy(amdgpu_fence_slab);
+}
 /*
  * Cast helper
  */
@@ -396,13 +409,6 @@ int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring,
  */
 int amdgpu_fence_driver_init(struct amdgpu_device *adev)
 {
-        if (atomic_inc_return(&amdgpu_fence_slab_ref) == 1) {
-                amdgpu_fence_slab = kmem_cache_create(
-                        "amdgpu_fence", sizeof(struct amdgpu_fence), 0,
-                        SLAB_HWCACHE_ALIGN, NULL);
-                if (!amdgpu_fence_slab)
-                        return -ENOMEM;
-        }
         if (amdgpu_debugfs_fence_init(adev))
                 dev_err(adev->dev, "fence debugfs file creation failed\n");
 
@@ -437,13 +443,10 @@ void amdgpu_fence_driver_fini(struct amdgpu_device *adev)
                 amd_sched_fini(&ring->sched);
                 del_timer_sync(&ring->fence_drv.fallback_timer);
                 for (j = 0; j <= ring->fence_drv.num_fences_mask; ++j)
-                        fence_put(ring->fence_drv.fences[i]);
+                        fence_put(ring->fence_drv.fences[j]);
                 kfree(ring->fence_drv.fences);
                 ring->fence_drv.initialized = false;
         }
-
-        if (atomic_dec_and_test(&amdgpu_fence_slab_ref))
-                kmem_cache_destroy(amdgpu_fence_slab);
 }
 
 /**
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index ea708cb94862..9f36ed30ba11 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -53,6 +53,18 @@
 /* Special value that no flush is necessary */
 #define AMDGPU_VM_NO_FLUSH (~0ll)
 
+/* Local structure. Encapsulate some VM table update parameters to reduce
+ * the number of function parameters
+ */
+struct amdgpu_vm_update_params {
+        /* address where to copy page table entries from */
+        uint64_t src;
+        /* DMA addresses to use for mapping */
+        dma_addr_t *pages_addr;
+        /* indirect buffer to fill with commands */
+        struct amdgpu_ib *ib;
+};
+
 /**
  * amdgpu_vm_num_pde - return the number of page directory entries
  *
@@ -389,9 +401,7 @@ struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
  * amdgpu_vm_update_pages - helper to call the right asic function
  *
  * @adev: amdgpu_device pointer
- * @src: address where to copy page table entries from
- * @pages_addr: DMA addresses to use for mapping
- * @ib: indirect buffer to fill with commands
+ * @vm_update_params: see amdgpu_vm_update_params definition
  * @pe: addr of the page entry
  * @addr: dst addr to write into pe
  * @count: number of page entries to update
@@ -402,29 +412,29 @@ struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
  * to setup the page table using the DMA.
  */
 static void amdgpu_vm_update_pages(struct amdgpu_device *adev,
-                                   uint64_t src,
-                                   dma_addr_t *pages_addr,
-                                   struct amdgpu_ib *ib,
+                                   struct amdgpu_vm_update_params
+                                        *vm_update_params,
                                    uint64_t pe, uint64_t addr,
                                    unsigned count, uint32_t incr,
                                    uint32_t flags)
 {
         trace_amdgpu_vm_set_page(pe, addr, count, incr, flags);
 
-        if (src) {
-                src += (addr >> 12) * 8;
-                amdgpu_vm_copy_pte(adev, ib, pe, src, count);
+        if (vm_update_params->src) {
+                amdgpu_vm_copy_pte(adev, vm_update_params->ib,
+                        pe, (vm_update_params->src + (addr >> 12) * 8), count);
 
-        } else if (pages_addr) {
-                amdgpu_vm_write_pte(adev, ib, pages_addr, pe, addr,
-                                    count, incr, flags);
+        } else if (vm_update_params->pages_addr) {
+                amdgpu_vm_write_pte(adev, vm_update_params->ib,
+                        vm_update_params->pages_addr,
+                        pe, addr, count, incr, flags);
 
         } else if (count < 3) {
-                amdgpu_vm_write_pte(adev, ib, NULL, pe, addr,
+                amdgpu_vm_write_pte(adev, vm_update_params->ib, NULL, pe, addr,
                                     count, incr, flags);
 
         } else {
-                amdgpu_vm_set_pte_pde(adev, ib, pe, addr,
+                amdgpu_vm_set_pte_pde(adev, vm_update_params->ib, pe, addr,
                                       count, incr, flags);
         }
 }
@@ -444,10 +454,12 @@ static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
         struct amdgpu_ring *ring;
         struct fence *fence = NULL;
         struct amdgpu_job *job;
+        struct amdgpu_vm_update_params vm_update_params;
         unsigned entries;
         uint64_t addr;
         int r;
 
+        memset(&vm_update_params, 0, sizeof(vm_update_params));
         ring = container_of(vm->entity.sched, struct amdgpu_ring, sched);
 
         r = reservation_object_reserve_shared(bo->tbo.resv);
@@ -465,7 +477,8 @@ static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
         if (r)
                 goto error;
 
-        amdgpu_vm_update_pages(adev, 0, NULL, &job->ibs[0], addr, 0, entries,
+        vm_update_params.ib = &job->ibs[0];
+        amdgpu_vm_update_pages(adev, &vm_update_params, addr, 0, entries,
                                0, 0);
         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
 
@@ -538,11 +551,12 @@ int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
         uint64_t last_pde = ~0, last_pt = ~0;
         unsigned count = 0, pt_idx, ndw;
         struct amdgpu_job *job;
-        struct amdgpu_ib *ib;
+        struct amdgpu_vm_update_params vm_update_params;
         struct fence *fence = NULL;
 
         int r;
 
+        memset(&vm_update_params, 0, sizeof(vm_update_params));
         ring = container_of(vm->entity.sched, struct amdgpu_ring, sched);
 
         /* padding, etc. */
@@ -555,7 +569,7 @@ int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
         if (r)
                 return r;
 
-        ib = &job->ibs[0];
+        vm_update_params.ib = &job->ibs[0];
 
         /* walk over the address space and update the page directory */
         for (pt_idx = 0; pt_idx <= vm->max_pde_used; ++pt_idx) {
@@ -575,7 +589,7 @@ int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
                     ((last_pt + incr * count) != pt)) {
 
                         if (count) {
-                                amdgpu_vm_update_pages(adev, 0, NULL, ib,
+                                amdgpu_vm_update_pages(adev, &vm_update_params,
                                                        last_pde, last_pt,
                                                        count, incr,
                                                        AMDGPU_PTE_VALID);
@@ -590,14 +604,15 @@ int amdgpu_vm_update_page_directory(struct amdgpu_device *adev,
         }
 
         if (count)
-                amdgpu_vm_update_pages(adev, 0, NULL, ib, last_pde, last_pt,
-                                       count, incr, AMDGPU_PTE_VALID);
+                amdgpu_vm_update_pages(adev, &vm_update_params,
+                                        last_pde, last_pt,
+                                        count, incr, AMDGPU_PTE_VALID);
 
-        if (ib->length_dw != 0) {
-                amdgpu_ring_pad_ib(ring, ib);
+        if (vm_update_params.ib->length_dw != 0) {
+                amdgpu_ring_pad_ib(ring, vm_update_params.ib);
                 amdgpu_sync_resv(adev, &job->sync, pd->tbo.resv,
                                  AMDGPU_FENCE_OWNER_VM);
-                WARN_ON(ib->length_dw > ndw);
+                WARN_ON(vm_update_params.ib->length_dw > ndw);
                 r = amdgpu_job_submit(job, ring, &vm->entity,
                                       AMDGPU_FENCE_OWNER_VM, &fence);
                 if (r)
@@ -623,18 +638,15 @@ error_free:
  * amdgpu_vm_frag_ptes - add fragment information to PTEs
  *
  * @adev: amdgpu_device pointer
- * @src: address where to copy page table entries from
- * @pages_addr: DMA addresses to use for mapping
- * @ib: IB for the update
+ * @vm_update_params: see amdgpu_vm_update_params definition
  * @pe_start: first PTE to handle
  * @pe_end: last PTE to handle
  * @addr: addr those PTEs should point to
  * @flags: hw mapping flags
  */
 static void amdgpu_vm_frag_ptes(struct amdgpu_device *adev,
-                                uint64_t src,
-                                dma_addr_t *pages_addr,
-                                struct amdgpu_ib *ib,
+                                struct amdgpu_vm_update_params
+                                        *vm_update_params,
                                 uint64_t pe_start, uint64_t pe_end,
                                 uint64_t addr, uint32_t flags)
 {
@@ -671,11 +683,11 @@ static void amdgpu_vm_frag_ptes(struct amdgpu_device *adev,
                 return;
 
         /* system pages are non continuously */
-        if (src || pages_addr || !(flags & AMDGPU_PTE_VALID) ||
-            (frag_start >= frag_end)) {
+        if (vm_update_params->src || vm_update_params->pages_addr ||
+                !(flags & AMDGPU_PTE_VALID) || (frag_start >= frag_end)) {
 
                 count = (pe_end - pe_start) / 8;
-                amdgpu_vm_update_pages(adev, src, pages_addr, ib, pe_start,
+                amdgpu_vm_update_pages(adev, vm_update_params, pe_start,
                                        addr, count, AMDGPU_GPU_PAGE_SIZE,
                                        flags);
                 return;
@@ -684,21 +696,21 @@ static void amdgpu_vm_frag_ptes(struct amdgpu_device *adev,
         /* handle the 4K area at the beginning */
         if (pe_start != frag_start) {
                 count = (frag_start - pe_start) / 8;
-                amdgpu_vm_update_pages(adev, 0, NULL, ib, pe_start, addr,
+                amdgpu_vm_update_pages(adev, vm_update_params, pe_start, addr,
                                        count, AMDGPU_GPU_PAGE_SIZE, flags);
                 addr += AMDGPU_GPU_PAGE_SIZE * count;
         }
 
         /* handle the area in the middle */
         count = (frag_end - frag_start) / 8;
-        amdgpu_vm_update_pages(adev, 0, NULL, ib, frag_start, addr, count,
+        amdgpu_vm_update_pages(adev, vm_update_params, frag_start, addr, count,
                                AMDGPU_GPU_PAGE_SIZE, flags | frag_flags);
 
         /* handle the 4K area at the end */
         if (frag_end != pe_end) {
                 addr += AMDGPU_GPU_PAGE_SIZE * count;
                 count = (pe_end - frag_end) / 8;
-                amdgpu_vm_update_pages(adev, 0, NULL, ib, frag_end, addr,
+                amdgpu_vm_update_pages(adev, vm_update_params, frag_end, addr,
                                        count, AMDGPU_GPU_PAGE_SIZE, flags);
         }
 }
@@ -707,8 +719,7 @@ static void amdgpu_vm_frag_ptes(struct amdgpu_device *adev,
  * amdgpu_vm_update_ptes - make sure that page tables are valid
  *
  * @adev: amdgpu_device pointer
- * @src: address where to copy page table entries from
- * @pages_addr: DMA addresses to use for mapping
+ * @vm_update_params: see amdgpu_vm_update_params definition
  * @vm: requested vm
  * @start: start of GPU address range
  * @end: end of GPU address range
@@ -718,10 +729,9 @@ static void amdgpu_vm_frag_ptes(struct amdgpu_device *adev,
  * Update the page tables in the range @start - @end.
  */
 static void amdgpu_vm_update_ptes(struct amdgpu_device *adev,
-                                  uint64_t src,
-                                  dma_addr_t *pages_addr,
+                                  struct amdgpu_vm_update_params
+                                        *vm_update_params,
                                   struct amdgpu_vm *vm,
-                                  struct amdgpu_ib *ib,
                                   uint64_t start, uint64_t end,
                                   uint64_t dst, uint32_t flags)
 {
@@ -747,7 +757,7 @@ static void amdgpu_vm_update_ptes(struct amdgpu_device *adev,
 
                 if (last_pe_end != pe_start) {
 
-                        amdgpu_vm_frag_ptes(adev, src, pages_addr, ib,
+                        amdgpu_vm_frag_ptes(adev, vm_update_params,
                                             last_pe_start, last_pe_end,
                                             last_dst, flags);
 
@@ -762,7 +772,7 @@ static void amdgpu_vm_update_ptes(struct amdgpu_device *adev,
                 dst += nptes * AMDGPU_GPU_PAGE_SIZE;
         }
 
-        amdgpu_vm_frag_ptes(adev, src, pages_addr, ib, last_pe_start,
+        amdgpu_vm_frag_ptes(adev, vm_update_params, last_pe_start,
                             last_pe_end, last_dst, flags);
 }
 
@@ -794,11 +804,14 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
         void *owner = AMDGPU_FENCE_OWNER_VM;
         unsigned nptes, ncmds, ndw;
         struct amdgpu_job *job;
-        struct amdgpu_ib *ib;
+        struct amdgpu_vm_update_params vm_update_params;
         struct fence *f = NULL;
         int r;
 
         ring = container_of(vm->entity.sched, struct amdgpu_ring, sched);
+        memset(&vm_update_params, 0, sizeof(vm_update_params));
+        vm_update_params.src = src;
+        vm_update_params.pages_addr = pages_addr;
 
         /* sync to everything on unmapping */
         if (!(flags & AMDGPU_PTE_VALID))
@@ -815,11 +828,11 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
         /* padding, etc. */
         ndw = 64;
 
-        if (src) {
+        if (vm_update_params.src) {
                 /* only copy commands needed */
                 ndw += ncmds * 7;
 
-        } else if (pages_addr) {
+        } else if (vm_update_params.pages_addr) {
                 /* header for write data commands */
                 ndw += ncmds * 4;
 
@@ -838,7 +851,7 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
         if (r)
                 return r;
 
-        ib = &job->ibs[0];
+        vm_update_params.ib = &job->ibs[0];
 
         r = amdgpu_sync_resv(adev, &job->sync, vm->page_directory->tbo.resv,
                              owner);
@@ -849,11 +862,11 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
         if (r)
                 goto error_free;
 
-        amdgpu_vm_update_ptes(adev, src, pages_addr, vm, ib, start,
+        amdgpu_vm_update_ptes(adev, &vm_update_params, vm, start,
                               last + 1, addr, flags);
 
-        amdgpu_ring_pad_ib(ring, ib);
-        WARN_ON(ib->length_dw > ndw);
+        amdgpu_ring_pad_ib(ring, vm_update_params.ib);
+        WARN_ON(vm_update_params.ib->length_dw > ndw);
         r = amdgpu_job_submit(job, ring, &vm->entity,
                               AMDGPU_FENCE_OWNER_VM, &f);
         if (r)
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_ih.c b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
index 845c21b1b2ee..be3d6f79a864 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
@@ -103,7 +103,6 @@ static void cik_ih_disable_interrupts(struct amdgpu_device *adev)
  */
 static int cik_ih_irq_init(struct amdgpu_device *adev)
 {
-        int ret = 0;
         int rb_bufsz;
         u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
         u64 wptr_off;
@@ -156,7 +155,7 @@ static int cik_ih_irq_init(struct amdgpu_device *adev)
         /* enable irqs */
         cik_ih_enable_interrupts(adev);
 
-        return ret;
+        return 0;
 }
 
 /**
diff --git a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
index fa4449e126e6..933e425a8154 100644
--- a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
@@ -1579,7 +1579,6 @@ static int cz_dpm_update_sclk_limit(struct amdgpu_device *adev)
 
 static int cz_dpm_set_deep_sleep_sclk_threshold(struct amdgpu_device *adev)
 {
-        int ret = 0;
         struct cz_power_info *pi = cz_get_pi(adev);
 
         if (pi->caps_sclk_ds) {
@@ -1588,20 +1587,19 @@ static int cz_dpm_set_deep_sleep_sclk_threshold(struct amdgpu_device *adev)
                                 CZ_MIN_DEEP_SLEEP_SCLK);
         }
 
-        return ret;
+        return 0;
 }
 
 /* ?? without dal support, is this still needed in setpowerstate list*/
 static int cz_dpm_set_watermark_threshold(struct amdgpu_device *adev)
 {
-        int ret = 0;
         struct cz_power_info *pi = cz_get_pi(adev);
 
         cz_send_msg_to_smc_with_parameter(adev,
                         PPSMC_MSG_SetWatermarkFrequency,
                         pi->sclk_dpm.soft_max_clk);
 
-        return ret;
+        return 0;
 }
 
 static int cz_dpm_enable_nbdpm(struct amdgpu_device *adev)
@@ -1636,7 +1634,6 @@ static void cz_dpm_nbdpm_lm_pstate_enable(struct amdgpu_device *adev,
 
 static int cz_dpm_update_low_memory_pstate(struct amdgpu_device *adev)
 {
-        int ret = 0;
         struct cz_power_info *pi = cz_get_pi(adev);
         struct cz_ps *ps = &pi->requested_ps;
 
@@ -1647,21 +1644,19 @@ static int cz_dpm_update_low_memory_pstate(struct amdgpu_device *adev)
                         cz_dpm_nbdpm_lm_pstate_enable(adev, true);
         }
 
-        return ret;
+        return 0;
 }
 
 /* with dpm enabled */
 static int cz_dpm_set_power_state(struct amdgpu_device *adev)
 {
-        int ret = 0;
-
         cz_dpm_update_sclk_limit(adev);
         cz_dpm_set_deep_sleep_sclk_threshold(adev);
         cz_dpm_set_watermark_threshold(adev);
         cz_dpm_enable_nbdpm(adev);
         cz_dpm_update_low_memory_pstate(adev);
 
-        return ret;
+        return 0;
 }
 
 static void cz_dpm_post_set_power_state(struct amdgpu_device *adev)
diff --git a/drivers/gpu/drm/amd/amdgpu/cz_ih.c b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
index 863cb16f6126..3d23a70b6432 100644
--- a/drivers/gpu/drm/amd/amdgpu/cz_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
@@ -103,7 +103,6 @@ static void cz_ih_disable_interrupts(struct amdgpu_device *adev)
  */
 static int cz_ih_irq_init(struct amdgpu_device *adev)
 {
-        int ret = 0;
         int rb_bufsz;
         u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
         u64 wptr_off;
@@ -157,7 +156,7 @@ static int cz_ih_irq_init(struct amdgpu_device *adev)
         /* enable interrupts */
         cz_ih_enable_interrupts(adev);
 
-        return ret;
+        return 0;
 }
 
 /**
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
index c11b6007af80..af26ec0bc59d 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
@@ -137,7 +137,7 @@ static const u32 polaris11_golden_settings_a11[] =
         mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
         mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
         mmFBC_DEBUG1, 0xffffffff, 0x00000008,
-        mmFBC_MISC, 0x9f313fff, 0x14300008,
+        mmFBC_MISC, 0x9f313fff, 0x14302008,
         mmHDMI_CONTROL, 0x313f031f, 0x00000011,
 };
 
@@ -145,7 +145,7 @@ static const u32 polaris10_golden_settings_a11[] =
 {
         mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
         mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
-        mmFBC_MISC, 0x9f313fff, 0x14300008,
+        mmFBC_MISC, 0x9f313fff, 0x14302008,
         mmHDMI_CONTROL, 0x313f031f, 0x00000011,
 };
 
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 92647fbf5b8b..f19bab68fd83 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -267,10 +267,13 @@ static const u32 tonga_mgcg_cgcg_init[] =
 
 static const u32 golden_settings_polaris11_a11[] =
 {
+        mmCB_HW_CONTROL, 0xfffdf3cf, 0x00006208,
         mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
         mmDB_DEBUG2, 0xf00fffff, 0x00000400,
         mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
         mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
+        mmPA_SC_RASTER_CONFIG, 0x3f3fffff, 0x16000012,
+        mmPA_SC_RASTER_CONFIG_1, 0x0000003f, 0x00000000,
         mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
         mmRLC_CGCG_CGLS_CTRL_3D, 0xffffffff, 0x0001003c,
         mmSQ_CONFIG, 0x07f80000, 0x07180000,
@@ -284,8 +287,6 @@ static const u32 golden_settings_polaris11_a11[] =
 static const u32 polaris11_golden_common_all[] =
 {
         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
-        mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x16000012,
-        mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
         mmGB_ADDR_CONFIG, 0xffffffff, 0x22011002,
         mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
         mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
@@ -296,6 +297,7 @@ static const u32 polaris11_golden_common_all[] =
 static const u32 golden_settings_polaris10_a11[] =
 {
         mmATC_MISC_CG, 0x000c0fc0, 0x000c0200,
+        mmCB_HW_CONTROL, 0xfffdf3cf, 0x00006208,
         mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
         mmDB_DEBUG2, 0xf00fffff, 0x00000400,
         mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
@@ -5725,6 +5727,7 @@ static void gfx_v8_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr,
         amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
         amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
                                  EOP_TC_ACTION_EN |
+                                 EOP_TC_WB_ACTION_EN |
                                  EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
                                  EVENT_INDEX(5)));
         amdgpu_ring_write(ring, addr & 0xfffffffc);
diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
index 39bfc52d0b42..3b8906ce3511 100644
--- a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
@@ -103,7 +103,6 @@ static void iceland_ih_disable_interrupts(struct amdgpu_device *adev)
  */
 static int iceland_ih_irq_init(struct amdgpu_device *adev)
 {
-        int ret = 0;
         int rb_bufsz;
         u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
         u64 wptr_off;
@@ -157,7 +156,7 @@ static int iceland_ih_irq_init(struct amdgpu_device *adev)
         /* enable interrupts */
         iceland_ih_enable_interrupts(adev);
 
-        return ret;
+        return 0;
 }
 
 /**
diff --git a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
index b45f54714574..a789a863d677 100644
--- a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
@@ -2252,7 +2252,7 @@ static void kv_apply_state_adjust_rules(struct amdgpu_device *adev,
         if (pi->caps_stable_p_state) {
                 stable_p_state_sclk = (max_limits->sclk * 75) / 100;
 
-                for (i = table->count - 1; i >= 0; i++) {
+                for (i = table->count - 1; i >= 0; i--) {
                         if (stable_p_state_sclk >= table->entries[i].clk) {
                                 stable_p_state_sclk = table->entries[i].clk;
                                 break;
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
index 063f08a9957a..31d99b0010f7 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -109,10 +109,12 @@ static const u32 fiji_mgcg_cgcg_init[] =
 static const u32 golden_settings_polaris11_a11[] =
 {
         mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
+        mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
         mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
         mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
         mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
         mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
+        mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
         mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
         mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
         mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
index f036af937fbc..c92055805a45 100644
--- a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
@@ -99,7 +99,6 @@ static void tonga_ih_disable_interrupts(struct amdgpu_device *adev)
  */
 static int tonga_ih_irq_init(struct amdgpu_device *adev)
 {
-        int ret = 0;
         int rb_bufsz;
         u32 interrupt_cntl, ih_rb_cntl, ih_doorbell_rtpr;
         u64 wptr_off;
@@ -165,7 +164,7 @@ static int tonga_ih_irq_init(struct amdgpu_device *adev)
         /* enable interrupts */
         tonga_ih_enable_interrupts(adev);
 
-        return ret;
+        return 0;
 }
 
 /**
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
index c94f9faa220a..24a16e49b571 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
@@ -3573,46 +3573,11 @@ static int fiji_force_dpm_highest(struct pp_hwmgr *hwmgr)
         return 0;
 }
 
-static void fiji_apply_dal_min_voltage_request(struct pp_hwmgr *hwmgr)
-{
-        struct phm_ppt_v1_information *table_info =
-                        (struct phm_ppt_v1_information *)hwmgr->pptable;
-        struct phm_clock_voltage_dependency_table *table =
-                                table_info->vddc_dep_on_dal_pwrl;
-        struct phm_ppt_v1_clock_voltage_dependency_table *vddc_table;
-        enum PP_DAL_POWERLEVEL dal_power_level = hwmgr->dal_power_level;
-        uint32_t req_vddc = 0, req_volt, i;
-
-        if (!table && !(dal_power_level >= PP_DAL_POWERLEVEL_ULTRALOW &&
-                        dal_power_level <= PP_DAL_POWERLEVEL_PERFORMANCE))
-                return;
-
-        for (i= 0; i < table->count; i++) {
-                if (dal_power_level == table->entries[i].clk) {
-                        req_vddc = table->entries[i].v;
-                        break;
-                }
-        }
-
-        vddc_table = table_info->vdd_dep_on_sclk;
-        for (i= 0; i < vddc_table->count; i++) {
-                if (req_vddc <= vddc_table->entries[i].vddc) {
-                        req_volt = (((uint32_t)vddc_table->entries[i].vddc) * VOLTAGE_SCALE)
-                                        << VDDC_SHIFT;
-                        smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-                                        PPSMC_MSG_VddC_Request, req_volt);
-                        return;
-                }
-        }
-        printk(KERN_ERR "DAL requested level can not"
-                        " found a available voltage in VDDC DPM Table \n");
-}
-
 static int fiji_upload_dpmlevel_enable_mask(struct pp_hwmgr *hwmgr)
 {
         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
 
-        fiji_apply_dal_min_voltage_request(hwmgr);
+        phm_apply_dal_min_voltage_request(hwmgr);
 
         if (!data->sclk_dpm_key_disabled) {
                 if (data->dpm_level_enable_mask.sclk_dpm_enable_mask)
@@ -4349,7 +4314,7 @@ static int fiji_populate_and_upload_sclk_mclk_dpm_levels(
 
         if (data->need_update_smu7_dpm_table &
                         (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK)) {
-                result = fiji_populate_all_memory_levels(hwmgr);
+                result = fiji_populate_all_graphic_levels(hwmgr);
                 PP_ASSERT_WITH_CODE((0 == result),
                                 "Failed to populate SCLK during PopulateNewDPMClocksStates Function!",
                                 return result);
@@ -5109,11 +5074,11 @@ static int fiji_get_pp_table(struct pp_hwmgr *hwmgr, char **table)
         struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
 
         if (!data->soft_pp_table) {
-                data->soft_pp_table = kzalloc(hwmgr->soft_pp_table_size, GFP_KERNEL);
+                data->soft_pp_table = kmemdup(hwmgr->soft_pp_table,
+                                              hwmgr->soft_pp_table_size,
+                                              GFP_KERNEL);
                 if (!data->soft_pp_table)
                         return -ENOMEM;
-                memcpy(data->soft_pp_table, hwmgr->soft_pp_table,
-                                hwmgr->soft_pp_table_size);
         }
 
         *table = (char *)&data->soft_pp_table;
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
index 7d69ed635bc2..1c48917da3cf 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
@@ -30,6 +30,9 @@
 #include "pppcielanes.h"
 #include "pp_debug.h"
 #include "ppatomctrl.h"
+#include "ppsmc.h"
+
+#define VOLTAGE_SCALE               4
 
 extern int cz_hwmgr_init(struct pp_hwmgr *hwmgr);
 extern int tonga_hwmgr_init(struct pp_hwmgr *hwmgr);
@@ -566,3 +569,38 @@ uint32_t phm_get_lowest_enabled_level(struct pp_hwmgr *hwmgr, uint32_t mask)
 
         return level;
 }
+
+void phm_apply_dal_min_voltage_request(struct pp_hwmgr *hwmgr)
+{
+        struct phm_ppt_v1_information *table_info =
+                        (struct phm_ppt_v1_information *)hwmgr->pptable;
+        struct phm_clock_voltage_dependency_table *table =
+                                table_info->vddc_dep_on_dal_pwrl;
+        struct phm_ppt_v1_clock_voltage_dependency_table *vddc_table;
+        enum PP_DAL_POWERLEVEL dal_power_level = hwmgr->dal_power_level;
+        uint32_t req_vddc = 0, req_volt, i;
+
+        if (!table || table->count <= 0
+                || dal_power_level < PP_DAL_POWERLEVEL_ULTRALOW
+                || dal_power_level > PP_DAL_POWERLEVEL_PERFORMANCE)
+                return;
+
+        for (i = 0; i < table->count; i++) {
+                if (dal_power_level == table->entries[i].clk) {
+                        req_vddc = table->entries[i].v;
+                        break;
+                }
+        }
+
+        vddc_table = table_info->vdd_dep_on_sclk;
+        for (i = 0; i < vddc_table->count; i++) {
+                if (req_vddc <= vddc_table->entries[i].vddc) {
+                        req_volt = (((uint32_t)vddc_table->entries[i].vddc) * VOLTAGE_SCALE);
+                        smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
+                                        PPSMC_MSG_VddC_Request, req_volt);
+                        return;
+                }
+        }
+        printk(KERN_ERR "DAL requested level can not"
+                        " found a available voltage in VDDC DPM Table \n");
+}
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
index 93768fa1dcdc..aa6be033f21b 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
@@ -189,41 +189,6 @@ int phm_get_current_pcie_lane_number(struct pp_hwmgr *hwmgr)
         return decode_pcie_lane_width(link_width);
 }
 
-void phm_apply_dal_min_voltage_request(struct pp_hwmgr *hwmgr)
-{
-        struct phm_ppt_v1_information *table_info =
-                        (struct phm_ppt_v1_information *)hwmgr->pptable;
-        struct phm_clock_voltage_dependency_table *table =
-                                table_info->vddc_dep_on_dal_pwrl;
-        struct phm_ppt_v1_clock_voltage_dependency_table *vddc_table;
-        enum PP_DAL_POWERLEVEL dal_power_level = hwmgr->dal_power_level;
-        uint32_t req_vddc = 0, req_volt, i;
-
-        if (!table && !(dal_power_level >= PP_DAL_POWERLEVEL_ULTRALOW &&
-                        dal_power_level <= PP_DAL_POWERLEVEL_PERFORMANCE))
-                return;
-
-        for (i = 0; i < table->count; i++) {
-                if (dal_power_level == table->entries[i].clk) {
-                        req_vddc = table->entries[i].v;
-                        break;
-                }
-        }
-
-        vddc_table = table_info->vdd_dep_on_sclk;
-        for (i = 0; i < vddc_table->count; i++) {
-                if (req_vddc <= vddc_table->entries[i].vddc) {
-                        req_volt = (((uint32_t)vddc_table->entries[i].vddc) * VOLTAGE_SCALE)
-                                        << VDDC_SHIFT;
-                        smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
-                                        PPSMC_MSG_VddC_Request, req_volt);
-                        return;
-                }
-        }
-        printk(KERN_ERR "DAL requested level can not"
-                        " found a available voltage in VDDC DPM Table \n");
-}
-
 /**
 * Enable voltage control
 *
@@ -2091,7 +2056,7 @@ static int polaris10_init_smc_table(struct pp_hwmgr *hwmgr)
                                 "Failed to populate Clock Stretcher Data Table!",
                                 return result);
         }
-
+        table->CurrSclkPllRange = 0xff;
         table->GraphicsVoltageChangeEnable  = 1;
         table->GraphicsThermThrottleEnable  = 1;
         table->GraphicsInterval = 1;
@@ -2184,6 +2149,7 @@ static int polaris10_init_smc_table(struct pp_hwmgr *hwmgr)
         CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask1);
         CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask2);
         CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize);
+        CONVERT_FROM_HOST_TO_SMC_UL(table->CurrSclkPllRange);
         CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh);
         CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow);
         CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime);
@@ -4760,11 +4726,11 @@ static int polaris10_get_pp_table(struct pp_hwmgr *hwmgr, char **table)
         struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
 
         if (!data->soft_pp_table) {
-                data->soft_pp_table = kzalloc(hwmgr->soft_pp_table_size, GFP_KERNEL);
+                data->soft_pp_table = kmemdup(hwmgr->soft_pp_table,
+                                              hwmgr->soft_pp_table_size,
+                                              GFP_KERNEL);
                 if (!data->soft_pp_table)
                         return -ENOMEM;
-                memcpy(data->soft_pp_table, hwmgr->soft_pp_table,
-                                hwmgr->soft_pp_table_size);
         }
 
         *table = (char *)&data->soft_pp_table;
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
index 1faad92b50d3..16fed487973b 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
@@ -5331,7 +5331,7 @@ static int tonga_freeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
                 (data->need_update_smu7_dpm_table &
                 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
                 PP_ASSERT_WITH_CODE(
-                        true == tonga_is_dpm_running(hwmgr),
+                        0 == tonga_is_dpm_running(hwmgr),
                         "Trying to freeze SCLK DPM when DPM is disabled",
                         );
                 PP_ASSERT_WITH_CODE(
@@ -5344,7 +5344,7 @@ static int tonga_freeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
         if ((0 == data->mclk_dpm_key_disabled) &&
                 (data->need_update_smu7_dpm_table &
                  DPMTABLE_OD_UPDATE_MCLK)) {
-                PP_ASSERT_WITH_CODE(true == tonga_is_dpm_running(hwmgr),
+                PP_ASSERT_WITH_CODE(0 == tonga_is_dpm_running(hwmgr),
                         "Trying to freeze MCLK DPM when DPM is disabled",
                         );
                 PP_ASSERT_WITH_CODE(
@@ -5445,7 +5445,7 @@ static int tonga_populate_and_upload_sclk_mclk_dpm_levels(struct pp_hwmgr *hwmgr
         }
 
         if (data->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK)) {
-                result = tonga_populate_all_memory_levels(hwmgr);
+                result = tonga_populate_all_graphic_levels(hwmgr);
                 PP_ASSERT_WITH_CODE((0 == result),
                         "Failed to populate SCLK during PopulateNewDPMClocksStates Function!",
                         return result);
@@ -5647,7 +5647,7 @@ static int tonga_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
                 (data->need_update_smu7_dpm_table &
                 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) {
 
-                PP_ASSERT_WITH_CODE(true == tonga_is_dpm_running(hwmgr),
+                PP_ASSERT_WITH_CODE(0 == tonga_is_dpm_running(hwmgr),
                         "Trying to Unfreeze SCLK DPM when DPM is disabled",
                         );
                 PP_ASSERT_WITH_CODE(
@@ -5661,7 +5661,7 @@ static int tonga_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
                 (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
 
                 PP_ASSERT_WITH_CODE(
-                                true == tonga_is_dpm_running(hwmgr),
+                                0 == tonga_is_dpm_running(hwmgr),
                                 "Trying to Unfreeze MCLK DPM when DPM is disabled",
                                 );
                 PP_ASSERT_WITH_CODE(
@@ -6056,11 +6056,11 @@ static int tonga_get_pp_table(struct pp_hwmgr *hwmgr, char **table)
         struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
 
         if (!data->soft_pp_table) {
-                data->soft_pp_table = kzalloc(hwmgr->soft_pp_table_size, GFP_KERNEL);
+                data->soft_pp_table = kmemdup(hwmgr->soft_pp_table,
+                                              hwmgr->soft_pp_table_size,
+                                              GFP_KERNEL);
                 if (!data->soft_pp_table)
                         return -ENOMEM;
-                memcpy(data->soft_pp_table, hwmgr->soft_pp_table,
-                                hwmgr->soft_pp_table_size);
         }
 
         *table = (char *)&data->soft_pp_table;
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index fd4ce7aaeee9..28f571449495 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -673,7 +673,7 @@ extern int phm_get_sclk_for_voltage_evv(struct pp_hwmgr *hwmgr, phm_ppt_v1_volta
 extern int phm_initializa_dynamic_state_adjustment_rule_settings(struct pp_hwmgr *hwmgr);
 extern int phm_hwmgr_backend_fini(struct pp_hwmgr *hwmgr);
 extern uint32_t phm_get_lowest_enabled_level(struct pp_hwmgr *hwmgr, uint32_t mask);
-
+extern void phm_apply_dal_min_voltage_request(struct pp_hwmgr *hwmgr);
 
 #define PHM_ENTIRE_REGISTER_MASK 0xFFFFFFFFU
 
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c
index da18f44fd1c8..87c023e518ab 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c
@@ -639,7 +639,7 @@ static int cz_smu_populate_firmware_entries(struct pp_smumgr *smumgr)
 
         cz_smu->driver_buffer_length = 0;
 
-        for (i = 0; i < sizeof(firmware_list)/sizeof(*firmware_list); i++) {
+        for (i = 0; i < ARRAY_SIZE(firmware_list); i++) {
 
                 firmware_type = cz_translate_firmware_enum_to_arg(smumgr,
                                         firmware_list[i]);
diff --git a/drivers/gpu/drm/radeon/kv_dpm.c b/drivers/gpu/drm/radeon/kv_dpm.c
index d0240743a17c..a7e978677937 100644
--- a/drivers/gpu/drm/radeon/kv_dpm.c
+++ b/drivers/gpu/drm/radeon/kv_dpm.c
@@ -2164,7 +2164,7 @@ static void kv_apply_state_adjust_rules(struct radeon_device *rdev,
         if (pi->caps_stable_p_state) {
                 stable_p_state_sclk = (max_limits->sclk * 75) / 100;
 
-                for (i = table->count - 1; i >= 0; i++) {
+                for (i = table->count - 1; i >= 0; i--) {
                         if (stable_p_state_sclk >= table->entries[i].clk) {
                                 stable_p_state_sclk = table->entries[i].clk;
                                 break;