Merge tag 'gvt-fixes-2017-01-10' of https://github.com/01org/gvt-linux into drm-intel-fixes

GVT-g fixes from Zhenya, "Please pull GVT-g device model fixes for
rc4. This is based on rc3 with new vfio/mdev interface change."

Signed-off-by: Jani Nikula <jani.nikula@intel.com>

10 files changed, 73 insertions, 87 deletions

diff --git a/drivers/gpu/drm/i915/gvt/aperture_gm.c b/drivers/gpu/drm/i915/gvt/aperture_gm.c
index 0d41ebc4aea6..65200313515c 100644
--- a/drivers/gpu/drm/i915/gvt/aperture_gm.c
+++ b/drivers/gpu/drm/i915/gvt/aperture_gm.c
@@ -37,13 +37,6 @@
 #include "i915_drv.h"
 #include "gvt.h"
 
-#define MB_TO_BYTES(mb) ((mb) << 20ULL)
-#define BYTES_TO_MB(b) ((b) >> 20ULL)
-
-#define HOST_LOW_GM_SIZE MB_TO_BYTES(128)
-#define HOST_HIGH_GM_SIZE MB_TO_BYTES(384)
-#define HOST_FENCE 4
-
 static int alloc_gm(struct intel_vgpu *vgpu, bool high_gm)
 {
         struct intel_gvt *gvt = vgpu->gvt;
diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
index 6c5fdf5b2ce2..3cf0df0bb391 100644
--- a/drivers/gpu/drm/i915/gvt/gtt.c
+++ b/drivers/gpu/drm/i915/gvt/gtt.c
@@ -240,15 +240,8 @@ static inline int get_pse_type(int type)
 static u64 read_pte64(struct drm_i915_private *dev_priv, unsigned long index)
 {
         void __iomem *addr = (gen8_pte_t __iomem *)dev_priv->ggtt.gsm + index;
-        u64 pte;
 
-#ifdef readq
-        pte = readq(addr);
-#else
-        pte = ioread32(addr);
-        pte |= (u64)ioread32(addr + 4) << 32;
-#endif
-        return pte;
+        return readq(addr);
 }
 
 static void write_pte64(struct drm_i915_private *dev_priv,
@@ -256,12 +249,8 @@ static void write_pte64(struct drm_i915_private *dev_priv,
 {
         void __iomem *addr = (gen8_pte_t __iomem *)dev_priv->ggtt.gsm + index;
 
-#ifdef writeq
         writeq(pte, addr);
-#else
-        iowrite32((u32)pte, addr);
-        iowrite32(pte >> 32, addr + 4);
-#endif
+
         I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
         POSTING_READ(GFX_FLSH_CNTL_GEN6);
 }
@@ -1380,8 +1369,7 @@ static int gen8_mm_alloc_page_table(struct intel_vgpu_mm *mm)
                         info->gtt_entry_size;
                 mem = kzalloc(mm->has_shadow_page_table ?
                         mm->page_table_entry_size * 2
-                                : mm->page_table_entry_size,
-                        GFP_ATOMIC);
+                                : mm->page_table_entry_size, GFP_KERNEL);
                 if (!mem)
                         return -ENOMEM;
                 mm->virtual_page_table = mem;
@@ -1532,7 +1520,7 @@ struct intel_vgpu_mm *intel_vgpu_create_mm(struct intel_vgpu *vgpu,
         struct intel_vgpu_mm *mm;
         int ret;
 
-        mm = kzalloc(sizeof(*mm), GFP_ATOMIC);
+        mm = kzalloc(sizeof(*mm), GFP_KERNEL);
         if (!mm) {
                 ret = -ENOMEM;
                 goto fail;
@@ -1886,30 +1874,27 @@ static int alloc_scratch_pages(struct intel_vgpu *vgpu,
         struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
         int page_entry_num = GTT_PAGE_SIZE >>
                                 vgpu->gvt->device_info.gtt_entry_size_shift;
-        struct page *scratch_pt;
+        void *scratch_pt;
         unsigned long mfn;
         int i;
-        void *p;
 
         if (WARN_ON(type < GTT_TYPE_PPGTT_PTE_PT || type >= GTT_TYPE_MAX))
                 return -EINVAL;
 
-        scratch_pt = alloc_page(GFP_KERNEL | GFP_ATOMIC | __GFP_ZERO);
+        scratch_pt = (void *)get_zeroed_page(GFP_KERNEL);
         if (!scratch_pt) {
                 gvt_err("fail to allocate scratch page\n");
                 return -ENOMEM;
         }
 
-        p = kmap_atomic(scratch_pt);
-        mfn = intel_gvt_hypervisor_virt_to_mfn(p);
+        mfn = intel_gvt_hypervisor_virt_to_mfn(scratch_pt);
         if (mfn == INTEL_GVT_INVALID_ADDR) {
-                gvt_err("fail to translate vaddr:0x%llx\n", (u64)p);
-                kunmap_atomic(p);
-                __free_page(scratch_pt);
+                gvt_err("fail to translate vaddr:0x%lx\n", (unsigned long)scratch_pt);
+                free_page((unsigned long)scratch_pt);
                 return -EFAULT;
         }
         gtt->scratch_pt[type].page_mfn = mfn;
-        gtt->scratch_pt[type].page = scratch_pt;
+        gtt->scratch_pt[type].page = virt_to_page(scratch_pt);
         gvt_dbg_mm("vgpu%d create scratch_pt: type %d mfn=0x%lx\n",
                         vgpu->id, type, mfn);
 
@@ -1918,7 +1903,7 @@ static int alloc_scratch_pages(struct intel_vgpu *vgpu,
          * scratch_pt[type] indicate the scratch pt/scratch page used by the
          * 'type' pt.
          * e.g. scratch_pt[GTT_TYPE_PPGTT_PDE_PT] is used by
-         * GTT_TYPE_PPGTT_PDE_PT level pt, that means this scatch_pt it self
+         * GTT_TYPE_PPGTT_PDE_PT level pt, that means this scratch_pt it self
          * is GTT_TYPE_PPGTT_PTE_PT, and full filled by scratch page mfn.
          */
         if (type > GTT_TYPE_PPGTT_PTE_PT && type < GTT_TYPE_MAX) {
@@ -1936,11 +1921,9 @@ static int alloc_scratch_pages(struct intel_vgpu *vgpu,
                         se.val64 |= PPAT_CACHED_INDEX;
 
                 for (i = 0; i < page_entry_num; i++)
-                        ops->set_entry(p, &se, i, false, 0, vgpu);
+                        ops->set_entry(scratch_pt, &se, i, false, 0, vgpu);
         }
 
-        kunmap_atomic(p);
-
         return 0;
 }
 
@@ -2208,7 +2191,7 @@ int intel_vgpu_g2v_destroy_ppgtt_mm(struct intel_vgpu *vgpu,
 int intel_gvt_init_gtt(struct intel_gvt *gvt)
 {
         int ret;
-        void *page_addr;
+        void *page;
 
         gvt_dbg_core("init gtt\n");
 
@@ -2221,17 +2204,14 @@ int intel_gvt_init_gtt(struct intel_gvt *gvt)
                 return -ENODEV;
         }
 
-        gvt->gtt.scratch_ggtt_page =
-                alloc_page(GFP_KERNEL | GFP_ATOMIC | __GFP_ZERO);
-        if (!gvt->gtt.scratch_ggtt_page) {
+        page = (void *)get_zeroed_page(GFP_KERNEL);
+        if (!page) {
                 gvt_err("fail to allocate scratch ggtt page\n");
                 return -ENOMEM;
         }
+        gvt->gtt.scratch_ggtt_page = virt_to_page(page);
 
-        page_addr = page_address(gvt->gtt.scratch_ggtt_page);
-
-        gvt->gtt.scratch_ggtt_mfn =
-                intel_gvt_hypervisor_virt_to_mfn(page_addr);
+        gvt->gtt.scratch_ggtt_mfn = intel_gvt_hypervisor_virt_to_mfn(page);
         if (gvt->gtt.scratch_ggtt_mfn == INTEL_GVT_INVALID_ADDR) {
                 gvt_err("fail to translate scratch ggtt page\n");
                 __free_page(gvt->gtt.scratch_ggtt_page);
diff --git a/drivers/gpu/drm/i915/gvt/gvt.c b/drivers/gpu/drm/i915/gvt/gvt.c
index 398877c3d2fd..e6bf5c533fbe 100644
--- a/drivers/gpu/drm/i915/gvt/gvt.c
+++ b/drivers/gpu/drm/i915/gvt/gvt.c
@@ -201,6 +201,8 @@ void intel_gvt_clean_device(struct drm_i915_private *dev_priv)
         intel_gvt_hypervisor_host_exit(&dev_priv->drm.pdev->dev, gvt);
         intel_gvt_clean_vgpu_types(gvt);
 
+        idr_destroy(&gvt->vgpu_idr);
+
         kfree(dev_priv->gvt);
         dev_priv->gvt = NULL;
 }
@@ -237,6 +239,8 @@ int intel_gvt_init_device(struct drm_i915_private *dev_priv)
 
         gvt_dbg_core("init gvt device\n");
 
+        idr_init(&gvt->vgpu_idr);
+
         mutex_init(&gvt->lock);
         gvt->dev_priv = dev_priv;
 
@@ -244,7 +248,7 @@ int intel_gvt_init_device(struct drm_i915_private *dev_priv)
 
         ret = intel_gvt_setup_mmio_info(gvt);
         if (ret)
-                return ret;
+                goto out_clean_idr;
 
         ret = intel_gvt_load_firmware(gvt);
         if (ret)
@@ -313,6 +317,8 @@ out_free_firmware:
         intel_gvt_free_firmware(gvt);
 out_clean_mmio_info:
         intel_gvt_clean_mmio_info(gvt);
+out_clean_idr:
+        idr_destroy(&gvt->vgpu_idr);
         kfree(gvt);
         return ret;
 }
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index 522809710312..8cbaf1c83720 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -93,7 +93,8 @@ static void write_vreg(struct intel_vgpu *vgpu, unsigned int offset,
 static int new_mmio_info(struct intel_gvt *gvt,
                 u32 offset, u32 flags, u32 size,
                 u32 addr_mask, u32 ro_mask, u32 device,
-                void *read, void *write)
+                int (*read)(struct intel_vgpu *, unsigned int, void *, unsigned int),
+                int (*write)(struct intel_vgpu *, unsigned int, void *, unsigned int))
 {
         struct intel_gvt_mmio_info *info, *p;
         u32 start, end, i;
@@ -219,7 +220,7 @@ static int mul_force_wake_write(struct intel_vgpu *vgpu,
                 default:
                         /*should not hit here*/
                         gvt_err("invalid forcewake offset 0x%x\n", offset);
-                        return 1;
+                        return -EINVAL;
                 }
         } else {
                 ack_reg_offset = FORCEWAKE_ACK_HSW_REG;
@@ -974,7 +975,7 @@ static int sbi_data_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
         return 0;
 }
 
-static bool sbi_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
+static int sbi_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
                 void *p_data, unsigned int bytes)
 {
         u32 data;
@@ -1366,7 +1367,6 @@ static int ring_mode_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
 static int gvt_reg_tlb_control_handler(struct intel_vgpu *vgpu,
                 unsigned int offset, void *p_data, unsigned int bytes)
 {
-        int rc = 0;
         unsigned int id = 0;
 
         write_vreg(vgpu, offset, p_data, bytes);
@@ -1389,12 +1389,11 @@ static int gvt_reg_tlb_control_handler(struct intel_vgpu *vgpu,
                 id = VECS;
                 break;
         default:
-                rc = -EINVAL;
-                break;
+                return -EINVAL;
         }
         set_bit(id, (void *)vgpu->tlb_handle_pending);
 
-        return rc;
+        return 0;
 }
 
 static int ring_reset_ctl_write(struct intel_vgpu *vgpu,
diff --git a/drivers/gpu/drm/i915/gvt/kvmgt.c b/drivers/gpu/drm/i915/gvt/kvmgt.c
index faaae07ae487..0c9234a87a20 100644
--- a/drivers/gpu/drm/i915/gvt/kvmgt.c
+++ b/drivers/gpu/drm/i915/gvt/kvmgt.c
@@ -398,6 +398,7 @@ static int intel_vgpu_create(struct kobject *kobj, struct mdev_device *mdev)
         struct intel_vgpu_type *type;
         struct device *pdev;
         void *gvt;
+        int ret;
 
         pdev = mdev_parent_dev(mdev);
         gvt = kdev_to_i915(pdev)->gvt;
@@ -406,13 +407,15 @@ static int intel_vgpu_create(struct kobject *kobj, struct mdev_device *mdev)
         if (!type) {
                 gvt_err("failed to find type %s to create\n",
                                                 kobject_name(kobj));
-                return -EINVAL;
+                ret = -EINVAL;
+                goto out;
         }
 
         vgpu = intel_gvt_ops->vgpu_create(gvt, type);
         if (IS_ERR_OR_NULL(vgpu)) {
-                gvt_err("create intel vgpu failed\n");
-                return -EINVAL;
+                ret = vgpu == NULL ? -EFAULT : PTR_ERR(vgpu);
+                gvt_err("failed to create intel vgpu: %d\n", ret);
+                goto out;
         }
 
         INIT_WORK(&vgpu->vdev.release_work, intel_vgpu_release_work);
@@ -422,7 +425,10 @@ static int intel_vgpu_create(struct kobject *kobj, struct mdev_device *mdev)
 
         gvt_dbg_core("intel_vgpu_create succeeded for mdev: %s\n",
                      dev_name(mdev_dev(mdev)));
-        return 0;
+        ret = 0;
+
+out:
+        return ret;
 }
 
 static int intel_vgpu_remove(struct mdev_device *mdev)
diff --git a/drivers/gpu/drm/i915/gvt/mmio.c b/drivers/gpu/drm/i915/gvt/mmio.c
index 09c9450a1946..e60701397ac2 100644
--- a/drivers/gpu/drm/i915/gvt/mmio.c
+++ b/drivers/gpu/drm/i915/gvt/mmio.c
@@ -125,25 +125,12 @@ int intel_vgpu_emulate_mmio_read(struct intel_vgpu *vgpu, uint64_t pa,
         if (WARN_ON(!reg_is_mmio(gvt, offset + bytes - 1)))
                 goto err;
 
-        mmio = intel_gvt_find_mmio_info(gvt, rounddown(offset, 4));
-        if (!mmio && !vgpu->mmio.disable_warn_untrack) {
-                gvt_err("vgpu%d: read untracked MMIO %x len %d val %x\n",
-                                vgpu->id, offset, bytes, *(u32 *)p_data);
-
-                if (offset == 0x206c) {
-                        gvt_err("------------------------------------------\n");
-                        gvt_err("vgpu%d: likely triggers a gfx reset\n",
-                        vgpu->id);
-                        gvt_err("------------------------------------------\n");
-                        vgpu->mmio.disable_warn_untrack = true;
-                }
-        }
-
         if (!intel_gvt_mmio_is_unalign(gvt, offset)) {
                 if (WARN_ON(!IS_ALIGNED(offset, bytes)))
                         goto err;
         }
 
+        mmio = intel_gvt_find_mmio_info(gvt, rounddown(offset, 4));
         if (mmio) {
                 if (!intel_gvt_mmio_is_unalign(gvt, mmio->offset)) {
                         if (WARN_ON(offset + bytes > mmio->offset + mmio->size))
@@ -152,9 +139,23 @@ int intel_vgpu_emulate_mmio_read(struct intel_vgpu *vgpu, uint64_t pa,
                                 goto err;
                 }
                 ret = mmio->read(vgpu, offset, p_data, bytes);
-        } else
+        } else {
                 ret = intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes);
 
+                if (!vgpu->mmio.disable_warn_untrack) {
+                        gvt_err("vgpu%d: read untracked MMIO %x(%dB) val %x\n",
+                                vgpu->id, offset, bytes, *(u32 *)p_data);
+
+                        if (offset == 0x206c) {
+                                gvt_err("------------------------------------------\n");
+                                gvt_err("vgpu%d: likely triggers a gfx reset\n",
+                                        vgpu->id);
+                                gvt_err("------------------------------------------\n");
+                                vgpu->mmio.disable_warn_untrack = true;
+                        }
+                }
+        }
+
         if (ret)
                 goto err;
 
diff --git a/drivers/gpu/drm/i915/gvt/opregion.c b/drivers/gpu/drm/i915/gvt/opregion.c
index 81cd921770c6..d9fb41ab7119 100644
--- a/drivers/gpu/drm/i915/gvt/opregion.c
+++ b/drivers/gpu/drm/i915/gvt/opregion.c
@@ -36,9 +36,9 @@ static int init_vgpu_opregion(struct intel_vgpu *vgpu, u32 gpa)
                         vgpu->id))
                 return -EINVAL;
 
-        vgpu_opregion(vgpu)->va = (void *)__get_free_pages(GFP_ATOMIC |
-                        GFP_DMA32 | __GFP_ZERO,
-                        INTEL_GVT_OPREGION_PORDER);
+        vgpu_opregion(vgpu)->va = (void *)__get_free_pages(GFP_KERNEL |
+                        __GFP_ZERO,
+                        get_order(INTEL_GVT_OPREGION_SIZE));
 
         if (!vgpu_opregion(vgpu)->va)
                 return -ENOMEM;
@@ -97,7 +97,7 @@ void intel_vgpu_clean_opregion(struct intel_vgpu *vgpu)
         if (intel_gvt_host.hypervisor_type == INTEL_GVT_HYPERVISOR_XEN) {
                 map_vgpu_opregion(vgpu, false);
                 free_pages((unsigned long)vgpu_opregion(vgpu)->va,
-                                INTEL_GVT_OPREGION_PORDER);
+                                get_order(INTEL_GVT_OPREGION_SIZE));
 
                 vgpu_opregion(vgpu)->va = NULL;
         }
diff --git a/drivers/gpu/drm/i915/gvt/reg.h b/drivers/gpu/drm/i915/gvt/reg.h
index 0dfe789d8f02..fbd023a16f18 100644
--- a/drivers/gpu/drm/i915/gvt/reg.h
+++ b/drivers/gpu/drm/i915/gvt/reg.h
@@ -50,8 +50,7 @@
 #define INTEL_GVT_OPREGION_PARM                   0x204
 
 #define INTEL_GVT_OPREGION_PAGES        2
-#define INTEL_GVT_OPREGION_PORDER       1
-#define INTEL_GVT_OPREGION_SIZE         (2 * 4096)
+#define INTEL_GVT_OPREGION_SIZE         (INTEL_GVT_OPREGION_PAGES * PAGE_SIZE)
 
 #define VGT_SPRSTRIDE(pipe)     _PIPE(pipe, _SPRA_STRIDE, _PLANE_STRIDE_2_B)
 
diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c b/drivers/gpu/drm/i915/gvt/scheduler.c
index 4db242250235..e91885dffeff 100644
--- a/drivers/gpu/drm/i915/gvt/scheduler.c
+++ b/drivers/gpu/drm/i915/gvt/scheduler.c
@@ -350,13 +350,15 @@ static void complete_current_workload(struct intel_gvt *gvt, int ring_id)
 {
         struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
         struct intel_vgpu_workload *workload;
+        struct intel_vgpu *vgpu;
         int event;
 
         mutex_lock(&gvt->lock);
 
         workload = scheduler->current_workload[ring_id];
+        vgpu = workload->vgpu;
 
-        if (!workload->status && !workload->vgpu->resetting) {
+        if (!workload->status && !vgpu->resetting) {
                 wait_event(workload->shadow_ctx_status_wq,
                            !atomic_read(&workload->shadow_ctx_active));
 
@@ -364,8 +366,7 @@ static void complete_current_workload(struct intel_gvt *gvt, int ring_id)
 
                 for_each_set_bit(event, workload->pending_events,
                                  INTEL_GVT_EVENT_MAX)
-                        intel_vgpu_trigger_virtual_event(workload->vgpu,
-                                        event);
+                        intel_vgpu_trigger_virtual_event(vgpu, event);
         }
 
         gvt_dbg_sched("ring id %d complete workload %p status %d\n",
@@ -373,11 +374,10 @@ static void complete_current_workload(struct intel_gvt *gvt, int ring_id)
 
         scheduler->current_workload[ring_id] = NULL;
 
-        atomic_dec(&workload->vgpu->running_workload_num);
-
         list_del_init(&workload->list);
         workload->complete(workload);
 
+        atomic_dec(&vgpu->running_workload_num);
         wake_up(&scheduler->workload_complete_wq);
         mutex_unlock(&gvt->lock);
 }
@@ -459,11 +459,11 @@ complete:
                 gvt_dbg_sched("will complete workload %p\n, status: %d\n",
                                 workload, workload->status);
 
-                complete_current_workload(gvt, ring_id);
-
                 if (workload->req)
                         i915_gem_request_put(fetch_and_zero(&workload->req));
 
+                complete_current_workload(gvt, ring_id);
+
                 if (need_force_wake)
                         intel_uncore_forcewake_put(gvt->dev_priv,
                                         FORCEWAKE_ALL);
diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgpu.c
index 536d2b9d5777..f0e86123e45b 100644
--- a/drivers/gpu/drm/i915/gvt/vgpu.c
+++ b/drivers/gpu/drm/i915/gvt/vgpu.c
@@ -177,7 +177,7 @@ int intel_gvt_init_vgpu_types(struct intel_gvt *gvt)
                 if (low_avail / min_low == 0)
                         break;
                 gvt->types[i].low_gm_size = min_low;
-                gvt->types[i].high_gm_size = 3 * gvt->types[i].low_gm_size;
+                gvt->types[i].high_gm_size = max((min_low<<3), MB_TO_BYTES(384U));
                 gvt->types[i].fence = 4;
                 gvt->types[i].max_instance = low_avail / min_low;
                 gvt->types[i].avail_instance = gvt->types[i].max_instance;
@@ -217,7 +217,7 @@ static void intel_gvt_update_vgpu_types(struct intel_gvt *gvt)
          */
         low_gm_avail = MB_TO_BYTES(256) - HOST_LOW_GM_SIZE -
                 gvt->gm.vgpu_allocated_low_gm_size;
-        high_gm_avail = MB_TO_BYTES(256) * 3 - HOST_HIGH_GM_SIZE -
+        high_gm_avail = MB_TO_BYTES(256) * 8UL - HOST_HIGH_GM_SIZE -
                 gvt->gm.vgpu_allocated_high_gm_size;
         fence_avail = gvt_fence_sz(gvt) - HOST_FENCE -
                 gvt->fence.vgpu_allocated_fence_num;
@@ -304,7 +304,7 @@ static struct intel_vgpu *__intel_gvt_create_vgpu(struct intel_gvt *gvt,
 
         ret = setup_vgpu_mmio(vgpu);
         if (ret)
-                goto out_free_vgpu;
+                goto out_clean_idr;
 
         ret = intel_vgpu_alloc_resource(vgpu, param);
         if (ret)
@@ -355,6 +355,8 @@ out_clean_vgpu_resource:
         intel_vgpu_free_resource(vgpu);
 out_clean_vgpu_mmio:
         clean_vgpu_mmio(vgpu);
+out_clean_idr:
+        idr_remove(&gvt->vgpu_idr, vgpu->id);
 out_free_vgpu:
         vfree(vgpu);
         mutex_unlock(&gvt->lock);