diff options
author | Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> | 2018-01-12 15:12:04 -0500 |
---|---|---|
committer | Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> | 2018-02-14 12:56:30 -0500 |
commit | 796ceb9269626afaed3b4955c40d2c3d7a8c5d01 (patch) | |
tree | e31e81852361a4fa71ec9f22c9c1974288982f70 | |
parent | 8525d04ba8a6a9ecfa4bd619c988ca873a5fc2a4 (diff) |
drm: rcar-du: lvds: Fix LVDS startup on R-Car Gen3
According to the latest revisions of the R-Car Gen3 manual, the LVDS mode
must be set before the LVDS I/O pins are enabled, not after -- fix the
Gen3 LVDS startup sequence accordingly.
Fixes: e947eccbeba4 ("drm: rcar-du: Add support for LVDS mode selection")
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
[Updated comment in rcar_du_lvdsenc_start_gen3()]
[Moved Gen2 startup comment update to separate commit]
[Fixed =| typo]
Tested-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
-rw-r--r-- | drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c b/drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c index dcffd3b59b69..01ef0f728e94 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c | |||
@@ -95,7 +95,7 @@ static void rcar_du_lvdsenc_start_gen3(struct rcar_du_lvdsenc *lvds, | |||
95 | u32 lvdcr0; | 95 | u32 lvdcr0; |
96 | u32 pllcr; | 96 | u32 pllcr; |
97 | 97 | ||
98 | /* PLL clock configuration */ | 98 | /* Set the PLL clock configuration and LVDS mode. */ |
99 | if (freq < 42000) | 99 | if (freq < 42000) |
100 | pllcr = LVDPLLCR_PLLDIVCNT_42M; | 100 | pllcr = LVDPLLCR_PLLDIVCNT_42M; |
101 | else if (freq < 85000) | 101 | else if (freq < 85000) |
@@ -107,6 +107,9 @@ static void rcar_du_lvdsenc_start_gen3(struct rcar_du_lvdsenc *lvds, | |||
107 | 107 | ||
108 | rcar_lvds_write(lvds, LVDPLLCR, pllcr); | 108 | rcar_lvds_write(lvds, LVDPLLCR, pllcr); |
109 | 109 | ||
110 | lvdcr0 = lvds->mode << LVDCR0_LVMD_SHIFT; | ||
111 | rcar_lvds_write(lvds, LVDCR0, lvdcr0); | ||
112 | |||
110 | /* Turn all the channels on. */ | 113 | /* Turn all the channels on. */ |
111 | rcar_lvds_write(lvds, LVDCR1, | 114 | rcar_lvds_write(lvds, LVDCR1, |
112 | LVDCR1_CHSTBY(3) | LVDCR1_CHSTBY(2) | | 115 | LVDCR1_CHSTBY(3) | LVDCR1_CHSTBY(2) | |
@@ -116,7 +119,7 @@ static void rcar_du_lvdsenc_start_gen3(struct rcar_du_lvdsenc *lvds, | |||
116 | * Turn the PLL on, set it to LVDS normal mode, wait for the startup | 119 | * Turn the PLL on, set it to LVDS normal mode, wait for the startup |
117 | * delay and turn the output on. | 120 | * delay and turn the output on. |
118 | */ | 121 | */ |
119 | lvdcr0 = (lvds->mode << LVDCR0_LVMD_SHIFT) | LVDCR0_PLLON; | 122 | lvdcr0 |= LVDCR0_PLLON; |
120 | rcar_lvds_write(lvds, LVDCR0, lvdcr0); | 123 | rcar_lvds_write(lvds, LVDCR0, lvdcr0); |
121 | 124 | ||
122 | lvdcr0 |= LVDCR0_PWD; | 125 | lvdcr0 |= LVDCR0_PWD; |