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authorKen Wang <Qingqing.Wang@amd.com>2016-07-06 21:56:53 -0400
committerAlex Deucher <alexander.deucher@amd.com>2016-07-14 16:39:30 -0400
commit795c2109c287123dfc3bc987d20daef32d77e4d1 (patch)
tree97231702c82c6c34bfbe4a3a5a93c2555675b605
parent39c8859418d5d2d29482fcd7d58daba6e299fac5 (diff)
drm/amdgpu: Add a missing register to Polaris golden setting
Signed-off-by: Ken Wang <Qingqing.Wang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index b2ebd4fef6cf..42e303151e61 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -284,6 +284,7 @@ static const u32 golden_settings_polaris11_a11[] =
284 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f3, 284 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f3,
285 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000, 285 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
286 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003210, 286 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003210,
287 mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
287}; 288};
288 289
289static const u32 polaris11_golden_common_all[] = 290static const u32 polaris11_golden_common_all[] =
@@ -314,6 +315,7 @@ static const u32 golden_settings_polaris10_a11[] =
314 mmTCC_CTRL, 0x00100000, 0xf31fff7f, 315 mmTCC_CTRL, 0x00100000, 0xf31fff7f,
315 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f7, 316 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f7,
316 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000, 317 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000,
318 mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
317}; 319};
318 320
319static const u32 polaris10_golden_common_all[] = 321static const u32 polaris10_golden_common_all[] =