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authorTakeshi Kihara <takeshi.kihara.df@renesas.com>2017-08-09 08:19:41 -0400
committerGeert Uytterhoeven <geert+renesas@glider.be>2017-08-16 08:26:30 -0400
commit794a6711764658a1adc0fed95abed628ea72091d (patch)
tree4aa15479695127d93351fcfbdb8d7b6f9b5b87bd
parentafdf04c151a6f07f8b631650c96be07baf8dd7de (diff)
pinctrl: sh-pfc: Initial R8A77995 PFC support
This patch adds initial pinctrl driver to support for the R8A77995 SoC. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> [geert: whitespace] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat
-rw-r--r--Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt1
-rw-r--r--drivers/pinctrl/sh-pfc/Kconfig5
-rw-r--r--drivers/pinctrl/sh-pfc/Makefile1
-rw-r--r--drivers/pinctrl/sh-pfc/core.c6
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a77995.c1412
-rw-r--r--drivers/pinctrl/sh-pfc/sh_pfc.h1
6 files changed, 1426 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
index 645082f03259..f4d127df980d 100644
--- a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
@@ -24,6 +24,7 @@ Required Properties:
24 - "renesas,pfc-r8a7794": for R8A7794 (R-Car E2) compatible pin-controller. 24 - "renesas,pfc-r8a7794": for R8A7794 (R-Car E2) compatible pin-controller.
25 - "renesas,pfc-r8a7795": for R8A7795 (R-Car H3) compatible pin-controller. 25 - "renesas,pfc-r8a7795": for R8A7795 (R-Car H3) compatible pin-controller.
26 - "renesas,pfc-r8a7796": for R8A7796 (R-Car M3-W) compatible pin-controller. 26 - "renesas,pfc-r8a7796": for R8A7796 (R-Car M3-W) compatible pin-controller.
27 - "renesas,pfc-r8a77995": for R8A77995 (R-Car D3) compatible pin-controller.
27 - "renesas,pfc-sh73a0": for SH73A0 (SH-Mobile AG5) compatible pin-controller. 28 - "renesas,pfc-sh73a0": for SH73A0 (SH-Mobile AG5) compatible pin-controller.
28 29
29 - reg: Base address and length of each memory resource used by the pin 30 - reg: Base address and length of each memory resource used by the pin
diff --git a/drivers/pinctrl/sh-pfc/Kconfig b/drivers/pinctrl/sh-pfc/Kconfig
index 24f76a05a5a9..5d5312eb7102 100644
--- a/drivers/pinctrl/sh-pfc/Kconfig
+++ b/drivers/pinctrl/sh-pfc/Kconfig
@@ -89,6 +89,11 @@ config PINCTRL_PFC_R8A7796
89 depends on ARCH_R8A7796 89 depends on ARCH_R8A7796
90 select PINCTRL_SH_PFC 90 select PINCTRL_SH_PFC
91 91
92config PINCTRL_PFC_R8A77995
93 def_bool y
94 depends on ARCH_R8A77995
95 select PINCTRL_SH_PFC
96
92config PINCTRL_PFC_SH7203 97config PINCTRL_PFC_SH7203
93 def_bool y 98 def_bool y
94 depends on CPU_SUBTYPE_SH7203 99 depends on CPU_SUBTYPE_SH7203
diff --git a/drivers/pinctrl/sh-pfc/Makefile b/drivers/pinctrl/sh-pfc/Makefile
index 33d28eed9ba3..1d4f05a96bd4 100644
--- a/drivers/pinctrl/sh-pfc/Makefile
+++ b/drivers/pinctrl/sh-pfc/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_PINCTRL_PFC_R8A7794) += pfc-r8a7794.o
15obj-$(CONFIG_PINCTRL_PFC_R8A7795) += pfc-r8a7795.o 15obj-$(CONFIG_PINCTRL_PFC_R8A7795) += pfc-r8a7795.o
16obj-$(CONFIG_PINCTRL_PFC_R8A7795) += pfc-r8a7795-es1.o 16obj-$(CONFIG_PINCTRL_PFC_R8A7795) += pfc-r8a7795-es1.o
17obj-$(CONFIG_PINCTRL_PFC_R8A7796) += pfc-r8a7796.o 17obj-$(CONFIG_PINCTRL_PFC_R8A7796) += pfc-r8a7796.o
18obj-$(CONFIG_PINCTRL_PFC_R8A77995) += pfc-r8a77995.o
18obj-$(CONFIG_PINCTRL_PFC_SH7203) += pfc-sh7203.o 19obj-$(CONFIG_PINCTRL_PFC_SH7203) += pfc-sh7203.o
19obj-$(CONFIG_PINCTRL_PFC_SH7264) += pfc-sh7264.o 20obj-$(CONFIG_PINCTRL_PFC_SH7264) += pfc-sh7264.o
20obj-$(CONFIG_PINCTRL_PFC_SH7269) += pfc-sh7269.o 21obj-$(CONFIG_PINCTRL_PFC_SH7269) += pfc-sh7269.o
diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c
index e72391d5e57d..0c5e952461fd 100644
--- a/drivers/pinctrl/sh-pfc/core.c
+++ b/drivers/pinctrl/sh-pfc/core.c
@@ -551,6 +551,12 @@ static const struct of_device_id sh_pfc_of_table[] = {
551 .data = &r8a7796_pinmux_info, 551 .data = &r8a7796_pinmux_info,
552 }, 552 },
553#endif 553#endif
554#ifdef CONFIG_PINCTRL_PFC_R8A77995
555 {
556 .compatible = "renesas,pfc-r8a77995",
557 .data = &r8a77995_pinmux_info,
558 },
559#endif
554#ifdef CONFIG_PINCTRL_PFC_SH73A0 560#ifdef CONFIG_PINCTRL_PFC_SH73A0
555 { 561 {
556 .compatible = "renesas,pfc-sh73a0", 562 .compatible = "renesas,pfc-sh73a0",
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77995.c b/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
new file mode 100644
index 000000000000..67f9656ae4a1
--- /dev/null
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77995.c
@@ -0,0 +1,1412 @@
1/*
2 * R8A77995 processor support - PFC hardware block.
3 *
4 * Copyright (C) 2017 Renesas Electronics Corp.
5 *
6 * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7796.c
7 *
8 * R-Car Gen3 processor support - PFC hardware block.
9 *
10 * Copyright (C) 2015 Renesas Electronics Corporation
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; version 2 of the License.
15 */
16
17#include <linux/kernel.h>
18
19#include "core.h"
20#include "sh_pfc.h"
21
22#define CPU_ALL_PORT(fn, sfx) \
23 PORT_GP_9(0, fn, sfx), \
24 PORT_GP_32(1, fn, sfx), \
25 PORT_GP_32(2, fn, sfx), \
26 PORT_GP_10(3, fn, sfx), \
27 PORT_GP_32(4, fn, sfx), \
28 PORT_GP_21(5, fn, sfx), \
29 PORT_GP_14(6, fn, sfx)
30
31/*
32 * F_() : just information
33 * FM() : macro for FN_xxx / xxx_MARK
34 */
35
36/* GPSR0 */
37#define GPSR0_8 F_(MLB_SIG, IP0_27_24)
38#define GPSR0_7 F_(MLB_DAT, IP0_23_20)
39#define GPSR0_6 F_(MLB_CLK, IP0_19_16)
40#define GPSR0_5 F_(MSIOF2_RXD, IP0_15_12)
41#define GPSR0_4 F_(MSIOF2_TXD, IP0_11_8)
42#define GPSR0_3 F_(MSIOF2_SCK, IP0_7_4)
43#define GPSR0_2 F_(IRQ0_A, IP0_3_0)
44#define GPSR0_1 FM(USB0_OVC)
45#define GPSR0_0 FM(USB0_PWEN)
46
47/* GPSR1 */
48#define GPSR1_31 F_(QPOLB, IP4_27_24)
49#define GPSR1_30 F_(QPOLA, IP4_23_20)
50#define GPSR1_29 F_(DU_CDE, IP4_19_16)
51#define GPSR1_28 F_(DU_DISP_CDE, IP4_15_12)
52#define GPSR1_27 F_(DU_DISP, IP4_11_8)
53#define GPSR1_26 F_(DU_VSYNC, IP4_7_4)
54#define GPSR1_25 F_(DU_HSYNC, IP4_3_0)
55#define GPSR1_24 F_(DU_DOTCLKOUT0, IP3_31_28)
56#define GPSR1_23 F_(DU_DR7, IP3_27_24)
57#define GPSR1_22 F_(DU_DR6, IP3_23_20)
58#define GPSR1_21 F_(DU_DR5, IP3_19_16)
59#define GPSR1_20 F_(DU_DR4, IP3_15_12)
60#define GPSR1_19 F_(DU_DR3, IP3_11_8)
61#define GPSR1_18 F_(DU_DR2, IP3_7_4)
62#define GPSR1_17 F_(DU_DR1, IP3_3_0)
63#define GPSR1_16 F_(DU_DR0, IP2_31_28)
64#define GPSR1_15 F_(DU_DG7, IP2_27_24)
65#define GPSR1_14 F_(DU_DG6, IP2_23_20)
66#define GPSR1_13 F_(DU_DG5, IP2_19_16)
67#define GPSR1_12 F_(DU_DG4, IP2_15_12)
68#define GPSR1_11 F_(DU_DG3, IP2_11_8)
69#define GPSR1_10 F_(DU_DG2, IP2_7_4)
70#define GPSR1_9 F_(DU_DG1, IP2_3_0)
71#define GPSR1_8 F_(DU_DG0, IP1_31_28)
72#define GPSR1_7 F_(DU_DB7, IP1_27_24)
73#define GPSR1_6 F_(DU_DB6, IP1_23_20)
74#define GPSR1_5 F_(DU_DB5, IP1_19_16)
75#define GPSR1_4 F_(DU_DB4, IP1_15_12)
76#define GPSR1_3 F_(DU_DB3, IP1_11_8)
77#define GPSR1_2 F_(DU_DB2, IP1_7_4)
78#define GPSR1_1 F_(DU_DB1, IP1_3_0)
79#define GPSR1_0 F_(DU_DB0, IP0_31_28)
80
81/* GPSR2 */
82#define GPSR2_31 F_(NFCE_N, IP8_19_16)
83#define GPSR2_30 F_(NFCLE, IP8_15_12)
84#define GPSR2_29 F_(NFALE, IP8_11_8)
85#define GPSR2_28 F_(VI4_CLKENB, IP8_7_4)
86#define GPSR2_27 F_(VI4_FIELD, IP8_3_0)
87#define GPSR2_26 F_(VI4_HSYNC_N, IP7_31_28)
88#define GPSR2_25 F_(VI4_VSYNC_N, IP7_27_24)
89#define GPSR2_24 F_(VI4_DATA23, IP7_23_20)
90#define GPSR2_23 F_(VI4_DATA22, IP7_19_16)
91#define GPSR2_22 F_(VI4_DATA21, IP7_15_12)
92#define GPSR2_21 F_(VI4_DATA20, IP7_11_8)
93#define GPSR2_20 F_(VI4_DATA19, IP7_7_4)
94#define GPSR2_19 F_(VI4_DATA18, IP7_3_0)
95#define GPSR2_18 F_(VI4_DATA17, IP6_31_28)
96#define GPSR2_17 F_(VI4_DATA16, IP6_27_24)
97#define GPSR2_16 F_(VI4_DATA15, IP6_23_20)
98#define GPSR2_15 F_(VI4_DATA14, IP6_19_16)
99#define GPSR2_14 F_(VI4_DATA13, IP6_15_12)
100#define GPSR2_13 F_(VI4_DATA12, IP6_11_8)
101#define GPSR2_12 F_(VI4_DATA11, IP6_7_4)
102#define GPSR2_11 F_(VI4_DATA10, IP6_3_0)
103#define GPSR2_10 F_(VI4_DATA9, IP5_31_28)
104#define GPSR2_9 F_(VI4_DATA8, IP5_27_24)
105#define GPSR2_8 F_(VI4_DATA7, IP5_23_20)
106#define GPSR2_7 F_(VI4_DATA6, IP5_19_16)
107#define GPSR2_6 F_(VI4_DATA5, IP5_15_12)
108#define GPSR2_5 FM(VI4_DATA4)
109#define GPSR2_4 F_(VI4_DATA3, IP5_11_8)
110#define GPSR2_3 F_(VI4_DATA2, IP5_7_4)
111#define GPSR2_2 F_(VI4_DATA1, IP5_3_0)
112#define GPSR2_1 F_(VI4_DATA0, IP4_31_28)
113#define GPSR2_0 FM(VI4_CLK)
114
115/* GPSR3 */
116#define GPSR3_9 F_(NFDATA7, IP9_31_28)
117#define GPSR3_8 F_(NFDATA6, IP9_27_24)
118#define GPSR3_7 F_(NFDATA5, IP9_23_20)
119#define GPSR3_6 F_(NFDATA4, IP9_19_16)
120#define GPSR3_5 F_(NFDATA3, IP9_15_12)
121#define GPSR3_4 F_(NFDATA2, IP9_11_8)
122#define GPSR3_3 F_(NFDATA1, IP9_7_4)
123#define GPSR3_2 F_(NFDATA0, IP9_3_0)
124#define GPSR3_1 F_(NFWE_N, IP8_31_28)
125#define GPSR3_0 F_(NFRE_N, IP8_27_24)
126
127/* GPSR4 */
128#define GPSR4_31 F_(CAN0_RX_A, IP12_27_24)
129#define GPSR4_30 F_(CAN1_TX_A, IP13_7_4)
130#define GPSR4_29 F_(CAN1_RX_A, IP13_3_0)
131#define GPSR4_28 F_(CAN0_TX_A, IP12_31_28)
132#define GPSR4_27 FM(TX2)
133#define GPSR4_26 FM(RX2)
134#define GPSR4_25 F_(SCK2, IP12_11_8)
135#define GPSR4_24 F_(TX1_A, IP12_7_4)
136#define GPSR4_23 F_(RX1_A, IP12_3_0)
137#define GPSR4_22 F_(SCK1_A, IP11_31_28)
138#define GPSR4_21 F_(TX0_A, IP11_27_24)
139#define GPSR4_20 F_(RX0_A, IP11_23_20)
140#define GPSR4_19 F_(SCK0_A, IP11_19_16)
141#define GPSR4_18 F_(MSIOF1_RXD, IP11_15_12)
142#define GPSR4_17 F_(MSIOF1_TXD, IP11_11_8)
143#define GPSR4_16 F_(MSIOF1_SCK, IP11_7_4)
144#define GPSR4_15 FM(MSIOF0_RXD)
145#define GPSR4_14 FM(MSIOF0_TXD)
146#define GPSR4_13 FM(MSIOF0_SYNC)
147#define GPSR4_12 FM(MSIOF0_SCK)
148#define GPSR4_11 F_(SDA1, IP11_3_0)
149#define GPSR4_10 F_(SCL1, IP10_31_28)
150#define GPSR4_9 FM(SDA0)
151#define GPSR4_8 FM(SCL0)
152#define GPSR4_7 F_(SSI_WS4_A, IP10_27_24)
153#define GPSR4_6 F_(SSI_SDATA4_A, IP10_23_20)
154#define GPSR4_5 F_(SSI_SCK4_A, IP10_19_16)
155#define GPSR4_4 F_(SSI_WS34, IP10_15_12)
156#define GPSR4_3 F_(SSI_SDATA3, IP10_11_8)
157#define GPSR4_2 F_(SSI_SCK34, IP10_7_4)
158#define GPSR4_1 F_(AUDIO_CLKA, IP10_3_0)
159#define GPSR4_0 F_(NFRB_N, IP8_23_20)
160
161/* GPSR5 */
162#define GPSR5_20 FM(AVB0_LINK)
163#define GPSR5_19 FM(AVB0_PHY_INT)
164#define GPSR5_18 FM(AVB0_MAGIC)
165#define GPSR5_17 FM(AVB0_MDC)
166#define GPSR5_16 FM(AVB0_MDIO)
167#define GPSR5_15 FM(AVB0_TXCREFCLK)
168#define GPSR5_14 FM(AVB0_TD3)
169#define GPSR5_13 FM(AVB0_TD2)
170#define GPSR5_12 FM(AVB0_TD1)
171#define GPSR5_11 FM(AVB0_TD0)
172#define GPSR5_10 FM(AVB0_TXC)
173#define GPSR5_9 FM(AVB0_TX_CTL)
174#define GPSR5_8 FM(AVB0_RD3)
175#define GPSR5_7 FM(AVB0_RD2)
176#define GPSR5_6 FM(AVB0_RD1)
177#define GPSR5_5 FM(AVB0_RD0)
178#define GPSR5_4 FM(AVB0_RXC)
179#define GPSR5_3 FM(AVB0_RX_CTL)
180#define GPSR5_2 F_(CAN_CLK, IP12_23_20)
181#define GPSR5_1 F_(TPU0TO1_A, IP12_19_16)
182#define GPSR5_0 F_(TPU0TO0_A, IP12_15_12)
183
184/* GPSR6 */
185#define GPSR6_13 FM(RPC_INT_N)
186#define GPSR6_12 FM(RPC_RESET_N)
187#define GPSR6_11 FM(QSPI1_SSL)
188#define GPSR6_10 FM(QSPI1_IO3)
189#define GPSR6_9 FM(QSPI1_IO2)
190#define GPSR6_8 FM(QSPI1_MISO_IO1)
191#define GPSR6_7 FM(QSPI1_MOSI_IO0)
192#define GPSR6_6 FM(QSPI1_SPCLK)
193#define GPSR6_5 FM(QSPI0_SSL)
194#define GPSR6_4 FM(QSPI0_IO3)
195#define GPSR6_3 FM(QSPI0_IO2)
196#define GPSR6_2 FM(QSPI0_MISO_IO1)
197#define GPSR6_1 FM(QSPI0_MOSI_IO0)
198#define GPSR6_0 FM(QSPI0_SPCLK)
199
200/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
201#define IP0_3_0 FM(IRQ0_A) FM(MSIOF2_SYNC_B) FM(USB0_IDIN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
202#define IP0_7_4 FM(MSIOF2_SCK) F_(0, 0) FM(USB0_IDPU) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
203#define IP0_11_8 FM(MSIOF2_TXD) FM(SCL3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
204#define IP0_15_12 FM(MSIOF2_RXD) FM(SDA3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
205#define IP0_19_16 FM(MLB_CLK) FM(MSIOF2_SYNC_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
206#define IP0_23_20 FM(MLB_DAT) FM(MSIOF2_SS1) FM(RX5_A) FM(SCL3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
207#define IP0_27_24 FM(MLB_SIG) FM(MSIOF2_SS2) FM(TX5_A) FM(SDA3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
208#define IP0_31_28 FM(DU_DB0) FM(LCDOUT0) FM(MSIOF3_TXD_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
209#define IP1_3_0 FM(DU_DB1) FM(LCDOUT1) FM(MSIOF3_RXD_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
210#define IP1_7_4 FM(DU_DB2) FM(LCDOUT2) FM(IRQ0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
211#define IP1_11_8 FM(DU_DB3) FM(LCDOUT3) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
212#define IP1_15_12 FM(DU_DB4) FM(LCDOUT4) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
213#define IP1_19_16 FM(DU_DB5) FM(LCDOUT5) FM(TX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
214#define IP1_23_20 FM(DU_DB6) FM(LCDOUT6) FM(MSIOF3_SS1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
215#define IP1_27_24 FM(DU_DB7) FM(LCDOUT7) FM(MSIOF3_SS2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
216#define IP1_31_28 FM(DU_DG0) FM(LCDOUT8) FM(MSIOF3_SCK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
217#define IP2_3_0 FM(DU_DG1) FM(LCDOUT9) FM(MSIOF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
218#define IP2_7_4 FM(DU_DG2) FM(LCDOUT10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
219#define IP2_11_8 FM(DU_DG3) FM(LCDOUT11) FM(IRQ1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
220#define IP2_15_12 FM(DU_DG4) FM(LCDOUT12) FM(HSCK3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
221#define IP2_19_16 FM(DU_DG5) FM(LCDOUT13) FM(HTX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
222#define IP2_23_20 FM(DU_DG6) FM(LCDOUT14) FM(HRX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
223#define IP2_27_24 FM(DU_DG7) FM(LCDOUT15) FM(SCK4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
224#define IP2_31_28 FM(DU_DR0) FM(LCDOUT16) FM(RX4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
225#define IP3_3_0 FM(DU_DR1) FM(LCDOUT17) FM(TX4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
226#define IP3_7_4 FM(DU_DR2) FM(LCDOUT18) FM(PWM0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
227#define IP3_11_8 FM(DU_DR3) FM(LCDOUT19) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
228#define IP3_15_12 FM(DU_DR4) FM(LCDOUT20) FM(TCLK2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
229#define IP3_19_16 FM(DU_DR5) FM(LCDOUT21) FM(NMI) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
230#define IP3_23_20 FM(DU_DR6) FM(LCDOUT22) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
231#define IP3_27_24 FM(DU_DR7) FM(LCDOUT23) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
232#define IP3_31_28 FM(DU_DOTCLKOUT0) FM(QCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
233
234/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
235#define IP4_3_0 FM(DU_HSYNC) FM(QSTH_QHS) FM(IRQ3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
236#define IP4_7_4 FM(DU_VSYNC) FM(QSTVA_QVS) FM(IRQ4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
237#define IP4_11_8 FM(DU_DISP) FM(QSTVB_QVE) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
238#define IP4_15_12 FM(DU_DISP_CDE) FM(QCPV_QDE) FM(IRQ2_B) FM(DU_DOTCLKIN1)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
239#define IP4_19_16 FM(DU_CDE) FM(QSTB_QHE) FM(SCK3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
240#define IP4_23_20 FM(QPOLA) F_(0, 0) FM(RX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
241#define IP4_27_24 FM(QPOLB) F_(0, 0) FM(TX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
242#define IP4_31_28 FM(VI4_DATA0) FM(PWM0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
243#define IP5_3_0 FM(VI4_DATA1) FM(PWM1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
244#define IP5_7_4 FM(VI4_DATA2) FM(PWM2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
245#define IP5_11_8 FM(VI4_DATA3) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
246#define IP5_15_12 FM(VI4_DATA5) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
247#define IP5_19_16 FM(VI4_DATA6) FM(IRQ2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
248#define IP5_23_20 FM(VI4_DATA7) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
249#define IP5_27_24 FM(VI4_DATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
250#define IP5_31_28 FM(VI4_DATA9) FM(MSIOF3_SS2_A) FM(IRQ1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
251#define IP6_3_0 FM(VI4_DATA10) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
252#define IP6_7_4 FM(VI4_DATA11) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
253#define IP6_11_8 FM(VI4_DATA12) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
254#define IP6_15_12 FM(VI4_DATA13) FM(MSIOF3_SS1_A) FM(HCTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
255#define IP6_19_16 FM(VI4_DATA14) FM(SSI_SCK4_B) FM(HRTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
256#define IP6_23_20 FM(VI4_DATA15) FM(SSI_SDATA4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
257#define IP6_27_24 FM(VI4_DATA16) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
258#define IP6_31_28 FM(VI4_DATA17) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
259#define IP7_3_0 FM(VI4_DATA18) FM(HSCK3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
260#define IP7_7_4 FM(VI4_DATA19) FM(SSI_WS4_B) F_(0, 0) F_(0, 0) FM(NFDATA15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261#define IP7_11_8 FM(VI4_DATA20) FM(MSIOF3_SYNC_A) F_(0, 0) F_(0, 0) FM(NFDATA14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262#define IP7_15_12 FM(VI4_DATA21) FM(MSIOF3_TXD_A) F_(0, 0) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263#define IP7_19_16 FM(VI4_DATA22) FM(MSIOF3_RXD_A) F_(0, 0) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264#define IP7_23_20 FM(VI4_DATA23) FM(MSIOF3_SCK_A) F_(0, 0) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265#define IP7_27_24 FM(VI4_VSYNC_N) FM(SCK1_B) F_(0, 0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266#define IP7_31_28 FM(VI4_HSYNC_N) FM(RX1_B) F_(0, 0) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267
268/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
269#define IP8_3_0 FM(VI4_FIELD) FM(AUDIO_CLKB) FM(IRQ5_A) FM(SCIF_CLK) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270#define IP8_7_4 FM(VI4_CLKENB) FM(TX1_B) F_(0, 0) F_(0, 0) FM(NFWP_N) FM(DVC_MUTE_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271#define IP8_11_8 FM(NFALE) FM(SCL2_B) FM(IRQ3_B) FM(PWM0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272#define IP8_15_12 FM(NFCLE) FM(SDA2_B) FM(SCK3_A) FM(PWM1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273#define IP8_19_16 FM(NFCE_N) F_(0, 0) FM(RX3_A) FM(PWM2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
274#define IP8_23_20 FM(NFRB_N) F_(0, 0) FM(TX3_A) FM(PWM3_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
275#define IP8_27_24 FM(NFRE_N) FM(MMC_CMD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
276#define IP8_31_28 FM(NFWE_N) FM(MMC_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
277#define IP9_3_0 FM(NFDATA0) FM(MMC_D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
278#define IP9_7_4 FM(NFDATA1) FM(MMC_D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279#define IP9_11_8 FM(NFDATA2) FM(MMC_D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280#define IP9_15_12 FM(NFDATA3) FM(MMC_D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281#define IP9_19_16 FM(NFDATA4) FM(MMC_D4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282#define IP9_23_20 FM(NFDATA5) FM(MMC_D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283#define IP9_27_24 FM(NFDATA6) FM(MMC_D6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284#define IP9_31_28 FM(NFDATA7) FM(MMC_D7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285#define IP10_3_0 FM(AUDIO_CLKA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(DVC_MUTE_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286#define IP10_7_4 FM(SSI_SCK34) FM(FSO_CFE_0_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287#define IP10_11_8 FM(SSI_SDATA3) FM(FSO_CFE_1_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
288#define IP10_15_12 FM(SSI_WS34) FM(FSO_TOE_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289#define IP10_19_16 FM(SSI_SCK4_A) FM(HSCK0) FM(AUDIO_CLKOUT) FM(CAN0_RX_B) FM(IRQ4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290#define IP10_23_20 FM(SSI_SDATA4_A) FM(HTX0) FM(SCL2_A) FM(CAN1_RX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291#define IP10_27_24 FM(SSI_WS4_A) FM(HRX0) FM(SDA2_A) FM(CAN1_TX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292#define IP10_31_28 FM(SCL1) FM(CTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293#define IP11_3_0 FM(SDA1) FM(RTS1_N_TANS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294#define IP11_7_4 FM(MSIOF1_SCK) FM(AVB0_AVTP_PPS_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295#define IP11_11_8 FM(MSIOF1_TXD) FM(AVB0_AVTP_CAPTURE_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296#define IP11_15_12 FM(MSIOF1_RXD) FM(AVB0_AVTP_MATCH_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297#define IP11_19_16 FM(SCK0_A) FM(MSIOF1_SYNC) FM(FSO_CFE_0_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298#define IP11_23_20 FM(RX0_A) FM(MSIOF0_SS1) FM(FSO_CFE_1_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299#define IP11_27_24 FM(TX0_A) FM(MSIOF0_SS2) FM(FSO_TOE_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300#define IP11_31_28 FM(SCK1_A) FM(MSIOF1_SS2) FM(TPU0TO2_B) FM(CAN0_TX_B) FM(AUDIO_CLKOUT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301
302/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
303#define IP12_3_0 FM(RX1_A) FM(CTS0_N) FM(TPU0TO0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304#define IP12_7_4 FM(TX1_A) FM(RTS0_N_TANS) FM(TPU0TO1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305#define IP12_11_8 FM(SCK2) FM(MSIOF1_SS1) FM(TPU0TO3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306#define IP12_15_12 FM(TPU0TO0_A) FM(AVB0_AVTP_CAPTURE_A) FM(HCTS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
307#define IP12_19_16 FM(TPU0TO1_A) FM(AVB0_AVTP_MATCH_A) FM(HRTS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
308#define IP12_23_20 FM(CAN_CLK) FM(AVB0_AVTP_PPS_A) FM(SCK0_B) FM(IRQ5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309#define IP12_27_24 FM(CAN0_RX_A) FM(CANFD0_RX) FM(RX0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310#define IP12_31_28 FM(CAN0_TX_A) FM(CANFD0_TX) FM(TX0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
311#define IP13_3_0 FM(CAN1_RX_A) FM(CANFD1_RX) FM(TPU0TO2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
312#define IP13_7_4 FM(CAN1_TX_A) FM(CANFD1_TX) FM(TPU0TO3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
313
314#define PINMUX_GPSR \
315\
316 GPSR1_31 GPSR2_31 GPSR4_31 \
317 GPSR1_30 GPSR2_30 GPSR4_30 \
318 GPSR1_29 GPSR2_29 GPSR4_29 \
319 GPSR1_28 GPSR2_28 GPSR4_28 \
320 GPSR1_27 GPSR2_27 GPSR4_27 \
321 GPSR1_26 GPSR2_26 GPSR4_26 \
322 GPSR1_25 GPSR2_25 GPSR4_25 \
323 GPSR1_24 GPSR2_24 GPSR4_24 \
324 GPSR1_23 GPSR2_23 GPSR4_23 \
325 GPSR1_22 GPSR2_22 GPSR4_22 \
326 GPSR1_21 GPSR2_21 GPSR4_21 \
327 GPSR1_20 GPSR2_20 GPSR4_20 GPSR5_20 \
328 GPSR1_19 GPSR2_19 GPSR4_19 GPSR5_19 \
329 GPSR1_18 GPSR2_18 GPSR4_18 GPSR5_18 \
330 GPSR1_17 GPSR2_17 GPSR4_17 GPSR5_17 \
331 GPSR1_16 GPSR2_16 GPSR4_16 GPSR5_16 \
332 GPSR1_15 GPSR2_15 GPSR4_15 GPSR5_15 \
333 GPSR1_14 GPSR2_14 GPSR4_14 GPSR5_14 \
334 GPSR1_13 GPSR2_13 GPSR4_13 GPSR5_13 GPSR6_13 \
335 GPSR1_12 GPSR2_12 GPSR4_12 GPSR5_12 GPSR6_12 \
336 GPSR1_11 GPSR2_11 GPSR4_11 GPSR5_11 GPSR6_11 \
337 GPSR1_10 GPSR2_10 GPSR4_10 GPSR5_10 GPSR6_10 \
338 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
339GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
340GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
341GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
342GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
343GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
344GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 \
345GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 \
346GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 \
347GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0
348
349#define PINMUX_IPSR \
350\
351FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
352FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
353FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
354FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
355FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
356FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
357FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
358FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
359\
360FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
361FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
362FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
363FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \
364FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
365FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
366FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
367FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
368\
369FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
370FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
371FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
372FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
373FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
374FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
375FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
376FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
377\
378FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 \
379FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 \
380FM(IP12_11_8) IP12_11_8 \
381FM(IP12_15_12) IP12_15_12 \
382FM(IP12_19_16) IP12_19_16 \
383FM(IP12_23_20) IP12_23_20 \
384FM(IP12_27_24) IP12_27_24 \
385FM(IP12_31_28) IP12_31_28 \
386
387/* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */
388#define MOD_SEL0_30 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1)
389#define MOD_SEL0_29 FM(SEL_I2C3_0) FM(SEL_I2C3_1)
390#define MOD_SEL0_28 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
391#define MOD_SEL0_27 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1)
392#define MOD_SEL0_26 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1)
393#define MOD_SEL0_25 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1)
394#define MOD_SEL0_24_23 FM(SEL_PWM0_0) FM(SEL_PWM0_1) FM(SEL_PWM0_2) FM(SEL_PWM0_3)
395#define MOD_SEL0_22_21 FM(SEL_PWM1_0) FM(SEL_PWM1_1) FM(SEL_PWM1_2) FM(SEL_PWM1_3)
396#define MOD_SEL0_20_19 FM(SEL_PWM2_0) FM(SEL_PWM2_1) FM(SEL_PWM2_2) FM(SEL_PWM2_3)
397#define MOD_SEL0_18_17 FM(SEL_PWM3_0) FM(SEL_PWM3_1) FM(SEL_PWM3_2) FM(SEL_PWM3_3)
398#define MOD_SEL0_15 FM(SEL_IRQ_0_0) FM(SEL_IRQ_0_1)
399#define MOD_SEL0_14 FM(SEL_IRQ_1_0) FM(SEL_IRQ_1_1)
400#define MOD_SEL0_13 FM(SEL_IRQ_2_0) FM(SEL_IRQ_2_1)
401#define MOD_SEL0_12 FM(SEL_IRQ_3_0) FM(SEL_IRQ_3_1)
402#define MOD_SEL0_11 FM(SEL_IRQ_4_0) FM(SEL_IRQ_4_1)
403#define MOD_SEL0_10 FM(SEL_IRQ_5_0) FM(SEL_IRQ_5_1)
404#define MOD_SEL0_5 FM(SEL_TMU_0_0) FM(SEL_TMU_0_1)
405#define MOD_SEL0_4 FM(SEL_TMU_1_0) FM(SEL_TMU_1_1)
406#define MOD_SEL0_3 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
407#define MOD_SEL0_2 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
408#define MOD_SEL0_1 FM(SEL_SCU_0) FM(SEL_SCU_1)
409#define MOD_SEL0_0 FM(SEL_RFSO_0) FM(SEL_RFSO_1)
410
411#define MOD_SEL1_31 FM(SEL_CAN0_0) FM(SEL_CAN0_1)
412#define MOD_SEL1_30 FM(SEL_CAN1_0) FM(SEL_CAN1_1)
413#define MOD_SEL1_29 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
414#define MOD_SEL1_28 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
415#define MOD_SEL1_27 FM(SEL_SCIF0_0) FM(SEL_SCIF0_1)
416#define MOD_SEL1_26 FM(SEL_SSIF4_0) FM(SEL_SSIF4_1)
417
418
419#define PINMUX_MOD_SELS \
420\
421 MOD_SEL1_31 \
422MOD_SEL0_30 MOD_SEL1_30 \
423MOD_SEL0_29 MOD_SEL1_29 \
424MOD_SEL0_28 MOD_SEL1_28 \
425MOD_SEL0_27 MOD_SEL1_27 \
426MOD_SEL0_26 MOD_SEL1_26 \
427MOD_SEL0_25 \
428MOD_SEL0_24_23 \
429MOD_SEL0_22_21 \
430MOD_SEL0_20_19 \
431MOD_SEL0_18_17 \
432MOD_SEL0_15 \
433MOD_SEL0_14 \
434MOD_SEL0_13 \
435MOD_SEL0_12 \
436MOD_SEL0_11 \
437MOD_SEL0_10 \
438MOD_SEL0_5 \
439MOD_SEL0_4 \
440MOD_SEL0_3 \
441MOD_SEL0_2 \
442MOD_SEL0_1 \
443MOD_SEL0_0
444
445enum {
446 PINMUX_RESERVED = 0,
447
448 PINMUX_DATA_BEGIN,
449 GP_ALL(DATA),
450 PINMUX_DATA_END,
451
452#define F_(x, y)
453#define FM(x) FN_##x,
454 PINMUX_FUNCTION_BEGIN,
455 GP_ALL(FN),
456 PINMUX_GPSR
457 PINMUX_IPSR
458 PINMUX_MOD_SELS
459 PINMUX_FUNCTION_END,
460#undef F_
461#undef FM
462
463#define F_(x, y)
464#define FM(x) x##_MARK,
465 PINMUX_MARK_BEGIN,
466 PINMUX_GPSR
467 PINMUX_IPSR
468 PINMUX_MOD_SELS
469 PINMUX_MARK_END,
470#undef F_
471#undef FM
472};
473
474#define PINMUX_IPSR_MSEL2(ipsr, fn, msel1, msel2) \
475 PINMUX_DATA(fn##_MARK, FN_##msel1, FN_##msel2, FN_##fn, FN_##ipsr)
476
477#define PINMUX_IPSR_PHYS(ipsr, fn, msel) \
478 PINMUX_DATA(fn##_MARK, FN_##msel)
479
480static const u16 pinmux_data[] = {
481 PINMUX_DATA_GP_ALL(),
482
483 PINMUX_SINGLE(USB0_OVC),
484 PINMUX_SINGLE(USB0_PWEN),
485 PINMUX_SINGLE(VI4_DATA4),
486 PINMUX_SINGLE(VI4_CLK),
487 PINMUX_SINGLE(TX2),
488 PINMUX_SINGLE(RX2),
489 PINMUX_SINGLE(AVB0_LINK),
490 PINMUX_SINGLE(AVB0_PHY_INT),
491 PINMUX_SINGLE(AVB0_MAGIC),
492 PINMUX_SINGLE(AVB0_MDC),
493 PINMUX_SINGLE(AVB0_MDIO),
494 PINMUX_SINGLE(AVB0_TXCREFCLK),
495 PINMUX_SINGLE(AVB0_TD3),
496 PINMUX_SINGLE(AVB0_TD2),
497 PINMUX_SINGLE(AVB0_TD1),
498 PINMUX_SINGLE(AVB0_TD0),
499 PINMUX_SINGLE(AVB0_TXC),
500 PINMUX_SINGLE(AVB0_TX_CTL),
501 PINMUX_SINGLE(AVB0_RD3),
502 PINMUX_SINGLE(AVB0_RD2),
503 PINMUX_SINGLE(AVB0_RD1),
504 PINMUX_SINGLE(AVB0_RD0),
505 PINMUX_SINGLE(AVB0_RXC),
506 PINMUX_SINGLE(AVB0_RX_CTL),
507 PINMUX_SINGLE(RPC_INT_N),
508 PINMUX_SINGLE(RPC_RESET_N),
509 PINMUX_SINGLE(QSPI1_SSL),
510 PINMUX_SINGLE(QSPI1_IO3),
511 PINMUX_SINGLE(QSPI1_IO2),
512 PINMUX_SINGLE(QSPI1_MISO_IO1),
513 PINMUX_SINGLE(QSPI1_MOSI_IO0),
514 PINMUX_SINGLE(QSPI1_SPCLK),
515 PINMUX_SINGLE(QSPI0_SSL),
516 PINMUX_SINGLE(QSPI0_IO3),
517 PINMUX_SINGLE(QSPI0_IO2),
518 PINMUX_SINGLE(QSPI0_MISO_IO1),
519 PINMUX_SINGLE(QSPI0_MOSI_IO0),
520 PINMUX_SINGLE(QSPI0_SPCLK),
521
522 /* IPSR0 */
523 PINMUX_IPSR_MSEL(IP0_3_0, IRQ0_A, SEL_IRQ_0_0),
524 PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1),
525 PINMUX_IPSR_GPSR(IP0_3_0, USB0_IDIN),
526
527 PINMUX_IPSR_GPSR(IP0_7_4, MSIOF2_SCK),
528 PINMUX_IPSR_GPSR(IP0_7_4, USB0_IDPU),
529
530 PINMUX_IPSR_GPSR(IP0_11_8, MSIOF2_TXD),
531 PINMUX_IPSR_MSEL(IP0_11_8, SCL3_A, SEL_I2C3_0),
532
533 PINMUX_IPSR_GPSR(IP0_15_12, MSIOF2_RXD),
534 PINMUX_IPSR_MSEL(IP0_15_12, SDA3_A, SEL_I2C3_0),
535
536 PINMUX_IPSR_GPSR(IP0_19_16, MLB_CLK),
537 PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_SYNC_A, SEL_MSIOF2_0),
538 PINMUX_IPSR_MSEL(IP0_19_16, SCK5_A, SEL_SCIF5_0),
539
540 PINMUX_IPSR_GPSR(IP0_23_20, MLB_DAT),
541 PINMUX_IPSR_GPSR(IP0_23_20, MSIOF2_SS1),
542 PINMUX_IPSR_MSEL(IP0_23_20, RX5_A, SEL_SCIF5_0),
543 PINMUX_IPSR_MSEL(IP0_23_20, SCL3_B, SEL_I2C3_1),
544
545 PINMUX_IPSR_GPSR(IP0_27_24, MLB_SIG),
546 PINMUX_IPSR_GPSR(IP0_27_24, MSIOF2_SS2),
547 PINMUX_IPSR_MSEL(IP0_27_24, TX5_A, SEL_SCIF5_0),
548 PINMUX_IPSR_MSEL(IP0_27_24, SDA3_B, SEL_I2C3_1),
549
550 PINMUX_IPSR_GPSR(IP0_31_28, DU_DB0),
551 PINMUX_IPSR_GPSR(IP0_31_28, LCDOUT0),
552 PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_TXD_B, SEL_MSIOF3_1),
553
554 /* IPSR1 */
555 PINMUX_IPSR_GPSR(IP1_3_0, DU_DB1),
556 PINMUX_IPSR_GPSR(IP1_3_0, LCDOUT1),
557 PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_RXD_B, SEL_MSIOF3_1),
558
559 PINMUX_IPSR_GPSR(IP1_7_4, DU_DB2),
560 PINMUX_IPSR_GPSR(IP1_7_4, LCDOUT2),
561 PINMUX_IPSR_MSEL(IP1_7_4, IRQ0_B, SEL_IRQ_0_1),
562
563 PINMUX_IPSR_GPSR(IP1_11_8, DU_DB3),
564 PINMUX_IPSR_GPSR(IP1_11_8, LCDOUT3),
565 PINMUX_IPSR_MSEL(IP1_11_8, SCK5_B, SEL_SCIF5_1),
566
567 PINMUX_IPSR_GPSR(IP1_15_12, DU_DB4),
568 PINMUX_IPSR_GPSR(IP1_15_12, LCDOUT4),
569 PINMUX_IPSR_MSEL(IP1_15_12, RX5_B, SEL_SCIF5_1),
570
571 PINMUX_IPSR_GPSR(IP1_19_16, DU_DB5),
572 PINMUX_IPSR_GPSR(IP1_19_16, LCDOUT5),
573 PINMUX_IPSR_MSEL(IP1_19_16, TX5_B, SEL_SCIF5_1),
574
575 PINMUX_IPSR_GPSR(IP1_23_20, DU_DB6),
576 PINMUX_IPSR_GPSR(IP1_23_20, LCDOUT6),
577 PINMUX_IPSR_MSEL(IP1_23_20, MSIOF3_SS1_B, SEL_MSIOF3_1),
578
579 PINMUX_IPSR_GPSR(IP1_27_24, DU_DB7),
580 PINMUX_IPSR_GPSR(IP1_27_24, LCDOUT7),
581 PINMUX_IPSR_MSEL(IP1_27_24, MSIOF3_SS2_B, SEL_MSIOF3_1),
582
583 PINMUX_IPSR_GPSR(IP1_31_28, DU_DG0),
584 PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT8),
585 PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SCK_B, SEL_MSIOF3_1),
586
587 /* IPSR2 */
588 PINMUX_IPSR_GPSR(IP2_3_0, DU_DG1),
589 PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT9),
590 PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_SYNC_B, SEL_MSIOF3_1),
591
592 PINMUX_IPSR_GPSR(IP2_7_4, DU_DG2),
593 PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT10),
594
595 PINMUX_IPSR_GPSR(IP2_11_8, DU_DG3),
596 PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT11),
597 PINMUX_IPSR_MSEL(IP2_11_8, IRQ1_A, SEL_IRQ_1_0),
598
599 PINMUX_IPSR_GPSR(IP2_15_12, DU_DG4),
600 PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT12),
601 PINMUX_IPSR_MSEL(IP2_15_12, HSCK3_B, SEL_HSCIF3_1),
602
603 PINMUX_IPSR_GPSR(IP2_19_16, DU_DG5),
604 PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT13),
605 PINMUX_IPSR_MSEL(IP2_19_16, HTX3_B, SEL_HSCIF3_1),
606
607 PINMUX_IPSR_GPSR(IP2_23_20, DU_DG6),
608 PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT14),
609 PINMUX_IPSR_MSEL(IP2_23_20, HRX3_B, SEL_HSCIF3_1),
610
611 PINMUX_IPSR_GPSR(IP2_27_24, DU_DG7),
612 PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT15),
613 PINMUX_IPSR_MSEL(IP2_27_24, SCK4_B, SEL_SCIF4_1),
614
615 PINMUX_IPSR_GPSR(IP2_31_28, DU_DR0),
616 PINMUX_IPSR_GPSR(IP2_31_28, LCDOUT16),
617 PINMUX_IPSR_MSEL(IP2_31_28, RX4_B, SEL_SCIF4_1),
618
619 /* IPSR3 */
620 PINMUX_IPSR_GPSR(IP3_3_0, DU_DR1),
621 PINMUX_IPSR_GPSR(IP3_3_0, LCDOUT17),
622 PINMUX_IPSR_MSEL(IP3_3_0, TX4_B, SEL_SCIF4_1),
623
624 PINMUX_IPSR_GPSR(IP3_7_4, DU_DR2),
625 PINMUX_IPSR_GPSR(IP3_7_4, LCDOUT18),
626 PINMUX_IPSR_MSEL(IP3_7_4, PWM0_B, SEL_PWM0_2),
627
628 PINMUX_IPSR_GPSR(IP3_11_8, DU_DR3),
629 PINMUX_IPSR_GPSR(IP3_11_8, LCDOUT19),
630 PINMUX_IPSR_MSEL(IP3_11_8, PWM1_B, SEL_PWM1_2),
631
632 PINMUX_IPSR_GPSR(IP3_15_12, DU_DR4),
633 PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT20),
634 PINMUX_IPSR_MSEL(IP3_15_12, TCLK2_B, SEL_TMU_0_1),
635
636 PINMUX_IPSR_GPSR(IP3_19_16, DU_DR5),
637 PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT21),
638 PINMUX_IPSR_GPSR(IP3_19_16, NMI),
639
640 PINMUX_IPSR_GPSR(IP3_23_20, DU_DR6),
641 PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT22),
642 PINMUX_IPSR_MSEL(IP3_23_20, PWM2_B, SEL_PWM2_2),
643
644 PINMUX_IPSR_GPSR(IP3_27_24, DU_DR7),
645 PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT23),
646 PINMUX_IPSR_MSEL(IP3_27_24, TCLK1_B, SEL_TMU_1_1),
647
648 PINMUX_IPSR_GPSR(IP3_31_28, DU_DOTCLKOUT0),
649 PINMUX_IPSR_GPSR(IP3_31_28, QCLK),
650
651 /* IPSR4 */
652 PINMUX_IPSR_GPSR(IP4_3_0, DU_HSYNC),
653 PINMUX_IPSR_GPSR(IP4_3_0, QSTH_QHS),
654 PINMUX_IPSR_MSEL(IP4_3_0, IRQ3_A, SEL_IRQ_3_0),
655
656 PINMUX_IPSR_GPSR(IP4_7_4, DU_VSYNC),
657 PINMUX_IPSR_GPSR(IP4_7_4, QSTVA_QVS),
658 PINMUX_IPSR_MSEL(IP4_7_4, IRQ4_A, SEL_IRQ_4_0),
659
660 PINMUX_IPSR_GPSR(IP4_11_8, DU_DISP),
661 PINMUX_IPSR_GPSR(IP4_11_8, QSTVB_QVE),
662 PINMUX_IPSR_MSEL(IP4_11_8, PWM3_B, SEL_PWM3_2),
663
664 PINMUX_IPSR_GPSR(IP4_15_12, DU_DISP_CDE),
665 PINMUX_IPSR_GPSR(IP4_15_12, QCPV_QDE),
666 PINMUX_IPSR_MSEL(IP4_15_12, IRQ2_B, SEL_IRQ_2_1),
667 PINMUX_IPSR_GPSR(IP4_15_12, DU_DOTCLKIN1),
668
669 PINMUX_IPSR_GPSR(IP4_19_16, DU_CDE),
670 PINMUX_IPSR_GPSR(IP4_19_16, QSTB_QHE),
671 PINMUX_IPSR_MSEL(IP4_19_16, SCK3_B, SEL_SCIF3_1),
672
673 PINMUX_IPSR_GPSR(IP4_23_20, QPOLA),
674 PINMUX_IPSR_MSEL(IP4_23_20, RX3_B, SEL_SCIF3_1),
675
676 PINMUX_IPSR_GPSR(IP4_27_24, QPOLB),
677 PINMUX_IPSR_MSEL(IP4_27_24, TX3_B, SEL_SCIF3_1),
678
679 PINMUX_IPSR_GPSR(IP4_31_28, VI4_DATA0),
680 PINMUX_IPSR_MSEL(IP4_31_28, PWM0_A, SEL_PWM0_0),
681
682 /* IPSR5 */
683 PINMUX_IPSR_GPSR(IP5_3_0, VI4_DATA1),
684 PINMUX_IPSR_MSEL(IP5_3_0, PWM1_A, SEL_PWM1_0),
685
686 PINMUX_IPSR_GPSR(IP5_7_4, VI4_DATA2),
687 PINMUX_IPSR_MSEL(IP5_7_4, PWM2_A, SEL_PWM2_0),
688
689 PINMUX_IPSR_GPSR(IP5_11_8, VI4_DATA3),
690 PINMUX_IPSR_MSEL(IP5_11_8, PWM3_A, SEL_PWM3_0),
691
692 PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA5),
693 PINMUX_IPSR_MSEL(IP5_15_12, SCK4_A, SEL_SCIF4_0),
694
695 PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA6),
696 PINMUX_IPSR_MSEL(IP5_19_16, IRQ2_A, SEL_IRQ_2_0),
697
698 PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA7),
699 PINMUX_IPSR_MSEL(IP5_23_20, TCLK2_A, SEL_TMU_0_0),
700
701 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA8),
702
703 PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA9),
704 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF3_SS2_A, SEL_MSIOF3_0),
705 PINMUX_IPSR_MSEL(IP5_31_28, IRQ1_B, SEL_IRQ_1_1),
706
707 /* IPSR6 */
708 PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA10),
709 PINMUX_IPSR_MSEL(IP6_3_0, RX4_A, SEL_SCIF4_0),
710
711 PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA11),
712 PINMUX_IPSR_MSEL(IP6_7_4, TX4_A, SEL_SCIF4_0),
713
714 PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA12),
715 PINMUX_IPSR_MSEL(IP6_11_8, TCLK1_A, SEL_TMU_1_0),
716
717 PINMUX_IPSR_GPSR(IP6_15_12, VI4_DATA13),
718 PINMUX_IPSR_MSEL(IP6_15_12, MSIOF3_SS1_A, SEL_MSIOF3_0),
719 PINMUX_IPSR_GPSR(IP6_15_12, HCTS3_N),
720
721 PINMUX_IPSR_GPSR(IP6_19_16, VI4_DATA14),
722 PINMUX_IPSR_MSEL(IP6_19_16, SSI_SCK4_B, SEL_SSIF4_1),
723 PINMUX_IPSR_GPSR(IP6_19_16, HRTS3_N),
724
725 PINMUX_IPSR_GPSR(IP6_23_20, VI4_DATA15),
726 PINMUX_IPSR_MSEL(IP6_23_20, SSI_SDATA4_B, SEL_SSIF4_1),
727
728 PINMUX_IPSR_GPSR(IP6_27_24, VI4_DATA16),
729 PINMUX_IPSR_MSEL(IP6_27_24, HRX3_A, SEL_HSCIF3_0),
730
731 PINMUX_IPSR_GPSR(IP6_31_28, VI4_DATA17),
732 PINMUX_IPSR_MSEL(IP6_31_28, HTX3_A, SEL_HSCIF3_0),
733
734 /* IPSR7 */
735 PINMUX_IPSR_GPSR(IP7_3_0, VI4_DATA18),
736 PINMUX_IPSR_MSEL(IP7_3_0, HSCK3_A, SEL_HSCIF3_0),
737
738 PINMUX_IPSR_GPSR(IP7_7_4, VI4_DATA19),
739 PINMUX_IPSR_MSEL(IP7_7_4, SSI_WS4_B, SEL_SSIF4_1),
740 PINMUX_IPSR_GPSR(IP7_7_4, NFDATA15),
741
742 PINMUX_IPSR_GPSR(IP7_11_8, VI4_DATA20),
743 PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SYNC_A, SEL_MSIOF3_0),
744 PINMUX_IPSR_GPSR(IP7_11_8, NFDATA14),
745
746 PINMUX_IPSR_GPSR(IP7_15_12, VI4_DATA21),
747 PINMUX_IPSR_MSEL(IP7_15_12, MSIOF3_TXD_A, SEL_MSIOF3_0),
748
749 PINMUX_IPSR_GPSR(IP7_15_12, NFDATA13),
750 PINMUX_IPSR_GPSR(IP7_19_16, VI4_DATA22),
751 PINMUX_IPSR_MSEL(IP7_19_16, MSIOF3_RXD_A, SEL_MSIOF3_0),
752
753 PINMUX_IPSR_GPSR(IP7_19_16, NFDATA12),
754 PINMUX_IPSR_GPSR(IP7_23_20, VI4_DATA23),
755 PINMUX_IPSR_MSEL(IP7_23_20, MSIOF3_SCK_A, SEL_MSIOF3_0),
756
757 PINMUX_IPSR_GPSR(IP7_23_20, NFDATA11),
758
759 PINMUX_IPSR_GPSR(IP7_27_24, VI4_VSYNC_N),
760 PINMUX_IPSR_MSEL(IP7_27_24, SCK1_B, SEL_SCIF1_1),
761 PINMUX_IPSR_GPSR(IP7_27_24, NFDATA10),
762
763 PINMUX_IPSR_GPSR(IP7_31_28, VI4_HSYNC_N),
764 PINMUX_IPSR_MSEL(IP7_31_28, RX1_B, SEL_SCIF1_1),
765 PINMUX_IPSR_GPSR(IP7_31_28, NFDATA9),
766
767 /* IPSR8 */
768 PINMUX_IPSR_GPSR(IP8_3_0, VI4_FIELD),
769 PINMUX_IPSR_GPSR(IP8_3_0, AUDIO_CLKB),
770 PINMUX_IPSR_MSEL(IP8_3_0, IRQ5_A, SEL_IRQ_5_0),
771 PINMUX_IPSR_GPSR(IP8_3_0, SCIF_CLK),
772 PINMUX_IPSR_GPSR(IP8_3_0, NFDATA8),
773
774 PINMUX_IPSR_GPSR(IP8_7_4, VI4_CLKENB),
775 PINMUX_IPSR_MSEL(IP8_7_4, TX1_B, SEL_SCIF1_1),
776 PINMUX_IPSR_GPSR(IP8_7_4, NFWP_N),
777 PINMUX_IPSR_MSEL(IP8_7_4, DVC_MUTE_A, SEL_SCU_0),
778
779 PINMUX_IPSR_GPSR(IP8_11_8, NFALE),
780 PINMUX_IPSR_MSEL(IP8_11_8, SCL2_B, SEL_I2C2_1),
781 PINMUX_IPSR_MSEL(IP8_11_8, IRQ3_B, SEL_IRQ_3_1),
782 PINMUX_IPSR_MSEL(IP8_11_8, PWM0_C, SEL_PWM0_1),
783
784 PINMUX_IPSR_GPSR(IP8_15_12, NFCLE),
785 PINMUX_IPSR_MSEL(IP8_15_12, SDA2_B, SEL_I2C2_1),
786 PINMUX_IPSR_MSEL(IP8_15_12, SCK3_A, SEL_SCIF3_0),
787 PINMUX_IPSR_MSEL(IP8_15_12, PWM1_C, SEL_PWM1_1),
788
789 PINMUX_IPSR_GPSR(IP8_19_16, NFCE_N),
790 PINMUX_IPSR_MSEL(IP8_19_16, RX3_A, SEL_SCIF3_0),
791 PINMUX_IPSR_MSEL(IP8_19_16, PWM2_C, SEL_PWM2_1),
792
793 PINMUX_IPSR_GPSR(IP8_23_20, NFRB_N),
794 PINMUX_IPSR_MSEL(IP8_23_20, TX3_A, SEL_SCIF3_0),
795 PINMUX_IPSR_MSEL(IP8_23_20, PWM3_C, SEL_PWM3_1),
796
797 PINMUX_IPSR_GPSR(IP8_27_24, NFRE_N),
798 PINMUX_IPSR_GPSR(IP8_27_24, MMC_CMD),
799
800 PINMUX_IPSR_GPSR(IP8_31_28, NFWE_N),
801 PINMUX_IPSR_GPSR(IP8_31_28, MMC_CLK),
802
803 /* IPSR9 */
804 PINMUX_IPSR_GPSR(IP9_3_0, NFDATA0),
805 PINMUX_IPSR_GPSR(IP9_3_0, MMC_D0),
806
807 PINMUX_IPSR_GPSR(IP9_7_4, NFDATA1),
808 PINMUX_IPSR_GPSR(IP9_7_4, MMC_D1),
809
810 PINMUX_IPSR_GPSR(IP9_11_8, NFDATA2),
811 PINMUX_IPSR_GPSR(IP9_11_8, MMC_D2),
812
813 PINMUX_IPSR_GPSR(IP9_15_12, NFDATA3),
814 PINMUX_IPSR_GPSR(IP9_15_12, MMC_D3),
815
816 PINMUX_IPSR_GPSR(IP9_19_16, NFDATA4),
817 PINMUX_IPSR_GPSR(IP9_19_16, MMC_D4),
818
819 PINMUX_IPSR_GPSR(IP9_23_20, NFDATA5),
820 PINMUX_IPSR_GPSR(IP9_23_20, MMC_D5),
821
822 PINMUX_IPSR_GPSR(IP9_27_24, NFDATA6),
823 PINMUX_IPSR_GPSR(IP9_27_24, MMC_D6),
824
825 PINMUX_IPSR_GPSR(IP9_31_28, NFDATA7),
826 PINMUX_IPSR_GPSR(IP9_31_28, MMC_D7),
827
828 /* IPSR10 */
829 PINMUX_IPSR_GPSR(IP10_3_0, AUDIO_CLKA),
830 PINMUX_IPSR_MSEL(IP10_3_0, DVC_MUTE_B, SEL_SCU_1),
831
832 PINMUX_IPSR_GPSR(IP10_7_4, SSI_SCK34),
833 PINMUX_IPSR_MSEL(IP10_7_4, FSO_CFE_0_N_A, SEL_RFSO_0),
834
835 PINMUX_IPSR_GPSR(IP10_11_8, SSI_SDATA3),
836 PINMUX_IPSR_MSEL(IP10_11_8, FSO_CFE_1_N_A, SEL_RFSO_0),
837
838 PINMUX_IPSR_GPSR(IP10_15_12, SSI_WS34),
839 PINMUX_IPSR_MSEL(IP10_15_12, FSO_TOE_N_A, SEL_RFSO_0),
840
841 PINMUX_IPSR_MSEL(IP10_19_16, SSI_SCK4_A, SEL_SSIF4_0),
842 PINMUX_IPSR_GPSR(IP10_19_16, HSCK0),
843 PINMUX_IPSR_GPSR(IP10_19_16, AUDIO_CLKOUT),
844 PINMUX_IPSR_MSEL(IP10_19_16, CAN0_RX_B, SEL_CAN0_1),
845 PINMUX_IPSR_MSEL(IP10_19_16, IRQ4_B, SEL_IRQ_4_1),
846
847 PINMUX_IPSR_MSEL(IP10_23_20, SSI_SDATA4_A, SEL_SSIF4_0),
848 PINMUX_IPSR_GPSR(IP10_23_20, HTX0),
849 PINMUX_IPSR_MSEL(IP10_23_20, SCL2_A, SEL_I2C2_0),
850 PINMUX_IPSR_MSEL(IP10_23_20, CAN1_RX_B, SEL_CAN1_1),
851
852 PINMUX_IPSR_MSEL(IP10_27_24, SSI_WS4_A, SEL_SSIF4_0),
853 PINMUX_IPSR_GPSR(IP10_27_24, HRX0),
854 PINMUX_IPSR_MSEL(IP10_27_24, SDA2_A, SEL_I2C2_0),
855 PINMUX_IPSR_MSEL(IP10_27_24, CAN1_TX_B, SEL_CAN1_1),
856
857 PINMUX_IPSR_GPSR(IP10_31_28, SCL1),
858 PINMUX_IPSR_GPSR(IP10_31_28, CTS1_N),
859
860 /* IPSR11 */
861 PINMUX_IPSR_GPSR(IP11_3_0, SDA1),
862 PINMUX_IPSR_GPSR(IP11_3_0, RTS1_N_TANS),
863
864 PINMUX_IPSR_GPSR(IP11_7_4, MSIOF1_SCK),
865 PINMUX_IPSR_MSEL(IP11_7_4, AVB0_AVTP_PPS_B, SEL_ETHERAVB_1),
866
867 PINMUX_IPSR_GPSR(IP11_11_8, MSIOF1_TXD),
868 PINMUX_IPSR_MSEL(IP11_11_8, AVB0_AVTP_CAPTURE_B, SEL_ETHERAVB_1),
869
870 PINMUX_IPSR_GPSR(IP11_15_12, MSIOF1_RXD),
871 PINMUX_IPSR_MSEL(IP11_15_12, AVB0_AVTP_MATCH_B, SEL_ETHERAVB_1),
872
873 PINMUX_IPSR_MSEL(IP11_19_16, SCK0_A, SEL_SCIF0_0),
874 PINMUX_IPSR_GPSR(IP11_19_16, MSIOF1_SYNC),
875 PINMUX_IPSR_MSEL(IP11_19_16, FSO_CFE_0_N_B, SEL_RFSO_1),
876
877 PINMUX_IPSR_MSEL(IP11_23_20, RX0_A, SEL_SCIF0_0),
878 PINMUX_IPSR_GPSR(IP11_23_20, MSIOF0_SS1),
879 PINMUX_IPSR_MSEL(IP11_23_20, FSO_CFE_1_N_B, SEL_RFSO_1),
880
881 PINMUX_IPSR_MSEL(IP11_27_24, TX0_A, SEL_SCIF0_0),
882 PINMUX_IPSR_GPSR(IP11_27_24, MSIOF0_SS2),
883 PINMUX_IPSR_MSEL(IP11_27_24, FSO_TOE_N_B, SEL_RFSO_1),
884
885 PINMUX_IPSR_MSEL(IP11_31_28, SCK1_A, SEL_SCIF1_0),
886 PINMUX_IPSR_GPSR(IP11_31_28, MSIOF1_SS2),
887 PINMUX_IPSR_GPSR(IP11_31_28, TPU0TO2_B),
888 PINMUX_IPSR_MSEL(IP11_31_28, CAN0_TX_B, SEL_CAN0_1),
889 PINMUX_IPSR_GPSR(IP11_31_28, AUDIO_CLKOUT1),
890
891 /* IPSR12 */
892 PINMUX_IPSR_MSEL(IP12_3_0, RX1_A, SEL_SCIF1_0),
893 PINMUX_IPSR_GPSR(IP12_3_0, CTS0_N),
894 PINMUX_IPSR_GPSR(IP12_3_0, TPU0TO0_B),
895
896 PINMUX_IPSR_MSEL(IP12_7_4, TX1_A, SEL_SCIF1_0),
897 PINMUX_IPSR_GPSR(IP12_7_4, RTS0_N_TANS),
898 PINMUX_IPSR_GPSR(IP12_7_4, TPU0TO1_B),
899
900 PINMUX_IPSR_GPSR(IP12_11_8, SCK2),
901 PINMUX_IPSR_GPSR(IP12_11_8, MSIOF1_SS1),
902 PINMUX_IPSR_GPSR(IP12_11_8, TPU0TO3_B),
903
904 PINMUX_IPSR_GPSR(IP12_15_12, TPU0TO0_A),
905 PINMUX_IPSR_MSEL(IP12_15_12, AVB0_AVTP_CAPTURE_A, SEL_ETHERAVB_0),
906 PINMUX_IPSR_GPSR(IP12_15_12, HCTS0_N),
907
908 PINMUX_IPSR_GPSR(IP12_19_16, TPU0TO1_A),
909 PINMUX_IPSR_MSEL(IP12_19_16, AVB0_AVTP_MATCH_A, SEL_ETHERAVB_0),
910 PINMUX_IPSR_GPSR(IP12_19_16, HRTS0_N),
911
912 PINMUX_IPSR_GPSR(IP12_23_20, CAN_CLK),
913 PINMUX_IPSR_MSEL(IP12_23_20, AVB0_AVTP_PPS_A, SEL_ETHERAVB_0),
914 PINMUX_IPSR_MSEL(IP12_23_20, SCK0_B, SEL_SCIF0_1),
915 PINMUX_IPSR_MSEL(IP12_23_20, IRQ5_B, SEL_IRQ_5_1),
916
917 PINMUX_IPSR_MSEL(IP12_27_24, CAN0_RX_A, SEL_CAN0_0),
918 PINMUX_IPSR_GPSR(IP12_27_24, CANFD0_RX),
919 PINMUX_IPSR_MSEL(IP12_27_24, RX0_B, SEL_SCIF0_1),
920
921 PINMUX_IPSR_MSEL(IP12_31_28, CAN0_TX_A, SEL_CAN0_0),
922 PINMUX_IPSR_GPSR(IP12_31_28, CANFD0_TX),
923 PINMUX_IPSR_MSEL(IP12_31_28, TX0_B, SEL_SCIF0_1),
924
925 /* IPSR13 */
926 PINMUX_IPSR_MSEL(IP13_3_0, CAN1_RX_A, SEL_CAN1_0),
927 PINMUX_IPSR_GPSR(IP13_3_0, CANFD1_RX),
928 PINMUX_IPSR_GPSR(IP13_3_0, TPU0TO2_A),
929
930 PINMUX_IPSR_MSEL(IP13_7_4, CAN1_TX_A, SEL_CAN1_0),
931 PINMUX_IPSR_GPSR(IP13_7_4, CANFD1_TX),
932 PINMUX_IPSR_GPSR(IP13_7_4, TPU0TO3_A),
933};
934
935static const struct sh_pfc_pin pinmux_pins[] = {
936 PINMUX_GPIO_GP_ALL(),
937};
938
939static const struct sh_pfc_pin_group pinmux_groups[] = {
940};
941
942static const struct sh_pfc_function pinmux_functions[] = {
943};
944
945static const struct pinmux_cfg_reg pinmux_config_regs[] = {
946#define F_(x, y) FN_##y
947#define FM(x) FN_##x
948 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
949 0, 0,
950 0, 0,
951 0, 0,
952 0, 0,
953 0, 0,
954 0, 0,
955 0, 0,
956 0, 0,
957 0, 0,
958 0, 0,
959 0, 0,
960 0, 0,
961 0, 0,
962 0, 0,
963 0, 0,
964 0, 0,
965 0, 0,
966 0, 0,
967 0, 0,
968 0, 0,
969 0, 0,
970 0, 0,
971 0, 0,
972 GP_0_8_FN, GPSR0_8,
973 GP_0_7_FN, GPSR0_7,
974 GP_0_6_FN, GPSR0_6,
975 GP_0_5_FN, GPSR0_5,
976 GP_0_4_FN, GPSR0_4,
977 GP_0_3_FN, GPSR0_3,
978 GP_0_2_FN, GPSR0_2,
979 GP_0_1_FN, GPSR0_1,
980 GP_0_0_FN, GPSR0_0, }
981 },
982 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
983 GP_1_31_FN, GPSR1_31,
984 GP_1_30_FN, GPSR1_30,
985 GP_1_29_FN, GPSR1_29,
986 GP_1_28_FN, GPSR1_28,
987 GP_1_27_FN, GPSR1_27,
988 GP_1_26_FN, GPSR1_26,
989 GP_1_25_FN, GPSR1_25,
990 GP_1_24_FN, GPSR1_24,
991 GP_1_23_FN, GPSR1_23,
992 GP_1_22_FN, GPSR1_22,
993 GP_1_21_FN, GPSR1_21,
994 GP_1_20_FN, GPSR1_20,
995 GP_1_19_FN, GPSR1_19,
996 GP_1_18_FN, GPSR1_18,
997 GP_1_17_FN, GPSR1_17,
998 GP_1_16_FN, GPSR1_16,
999 GP_1_15_FN, GPSR1_15,
1000 GP_1_14_FN, GPSR1_14,
1001 GP_1_13_FN, GPSR1_13,
1002 GP_1_12_FN, GPSR1_12,
1003 GP_1_11_FN, GPSR1_11,
1004 GP_1_10_FN, GPSR1_10,
1005 GP_1_9_FN, GPSR1_9,
1006 GP_1_8_FN, GPSR1_8,
1007 GP_1_7_FN, GPSR1_7,
1008 GP_1_6_FN, GPSR1_6,
1009 GP_1_5_FN, GPSR1_5,
1010 GP_1_4_FN, GPSR1_4,
1011 GP_1_3_FN, GPSR1_3,
1012 GP_1_2_FN, GPSR1_2,
1013 GP_1_1_FN, GPSR1_1,
1014 GP_1_0_FN, GPSR1_0, }
1015 },
1016 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
1017 GP_2_31_FN, GPSR2_31,
1018 GP_2_30_FN, GPSR2_30,
1019 GP_2_29_FN, GPSR2_29,
1020 GP_2_28_FN, GPSR2_28,
1021 GP_2_27_FN, GPSR2_27,
1022 GP_2_26_FN, GPSR2_26,
1023 GP_2_25_FN, GPSR2_25,
1024 GP_2_24_FN, GPSR2_24,
1025 GP_2_23_FN, GPSR2_23,
1026 GP_2_22_FN, GPSR2_22,
1027 GP_2_21_FN, GPSR2_21,
1028 GP_2_20_FN, GPSR2_20,
1029 GP_2_19_FN, GPSR2_19,
1030 GP_2_18_FN, GPSR2_18,
1031 GP_2_17_FN, GPSR2_17,
1032 GP_2_16_FN, GPSR2_16,
1033 GP_2_15_FN, GPSR2_15,
1034 GP_2_14_FN, GPSR2_14,
1035 GP_2_13_FN, GPSR2_13,
1036 GP_2_12_FN, GPSR2_12,
1037 GP_2_11_FN, GPSR2_11,
1038 GP_2_10_FN, GPSR2_10,
1039 GP_2_9_FN, GPSR2_9,
1040 GP_2_8_FN, GPSR2_8,
1041 GP_2_7_FN, GPSR2_7,
1042 GP_2_6_FN, GPSR2_6,
1043 GP_2_5_FN, GPSR2_5,
1044 GP_2_4_FN, GPSR2_4,
1045 GP_2_3_FN, GPSR2_3,
1046 GP_2_2_FN, GPSR2_2,
1047 GP_2_1_FN, GPSR2_1,
1048 GP_2_0_FN, GPSR2_0, }
1049 },
1050 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
1051 0, 0,
1052 0, 0,
1053 0, 0,
1054 0, 0,
1055 0, 0,
1056 0, 0,
1057 0, 0,
1058 0, 0,
1059 0, 0,
1060 0, 0,
1061 0, 0,
1062 0, 0,
1063 0, 0,
1064 0, 0,
1065 0, 0,
1066 0, 0,
1067 0, 0,
1068 0, 0,
1069 0, 0,
1070 0, 0,
1071 0, 0,
1072 0, 0,
1073 GP_3_9_FN, GPSR3_9,
1074 GP_3_8_FN, GPSR3_8,
1075 GP_3_7_FN, GPSR3_7,
1076 GP_3_6_FN, GPSR3_6,
1077 GP_3_5_FN, GPSR3_5,
1078 GP_3_4_FN, GPSR3_4,
1079 GP_3_3_FN, GPSR3_3,
1080 GP_3_2_FN, GPSR3_2,
1081 GP_3_1_FN, GPSR3_1,
1082 GP_3_0_FN, GPSR3_0, }
1083 },
1084 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
1085 GP_4_31_FN, GPSR4_31,
1086 GP_4_30_FN, GPSR4_30,
1087 GP_4_29_FN, GPSR4_29,
1088 GP_4_28_FN, GPSR4_28,
1089 GP_4_27_FN, GPSR4_27,
1090 GP_4_26_FN, GPSR4_26,
1091 GP_4_25_FN, GPSR4_25,
1092 GP_4_24_FN, GPSR4_24,
1093 GP_4_23_FN, GPSR4_23,
1094 GP_4_22_FN, GPSR4_22,
1095 GP_4_21_FN, GPSR4_21,
1096 GP_4_20_FN, GPSR4_20,
1097 GP_4_19_FN, GPSR4_19,
1098 GP_4_18_FN, GPSR4_18,
1099 GP_4_17_FN, GPSR4_17,
1100 GP_4_16_FN, GPSR4_16,
1101 GP_4_15_FN, GPSR4_15,
1102 GP_4_14_FN, GPSR4_14,
1103 GP_4_13_FN, GPSR4_13,
1104 GP_4_12_FN, GPSR4_12,
1105 GP_4_11_FN, GPSR4_11,
1106 GP_4_10_FN, GPSR4_10,
1107 GP_4_9_FN, GPSR4_9,
1108 GP_4_8_FN, GPSR4_8,
1109 GP_4_7_FN, GPSR4_7,
1110 GP_4_6_FN, GPSR4_6,
1111 GP_4_5_FN, GPSR4_5,
1112 GP_4_4_FN, GPSR4_4,
1113 GP_4_3_FN, GPSR4_3,
1114 GP_4_2_FN, GPSR4_2,
1115 GP_4_1_FN, GPSR4_1,
1116 GP_4_0_FN, GPSR4_0, }
1117 },
1118 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
1119 0, 0,
1120 0, 0,
1121 0, 0,
1122 0, 0,
1123 0, 0,
1124 0, 0,
1125 0, 0,
1126 0, 0,
1127 0, 0,
1128 0, 0,
1129 0, 0,
1130 GP_5_20_FN, GPSR5_20,
1131 GP_5_19_FN, GPSR5_19,
1132 GP_5_18_FN, GPSR5_18,
1133 GP_5_17_FN, GPSR5_17,
1134 GP_5_16_FN, GPSR5_16,
1135 GP_5_15_FN, GPSR5_15,
1136 GP_5_14_FN, GPSR5_14,
1137 GP_5_13_FN, GPSR5_13,
1138 GP_5_12_FN, GPSR5_12,
1139 GP_5_11_FN, GPSR5_11,
1140 GP_5_10_FN, GPSR5_10,
1141 GP_5_9_FN, GPSR5_9,
1142 GP_5_8_FN, GPSR5_8,
1143 GP_5_7_FN, GPSR5_7,
1144 GP_5_6_FN, GPSR5_6,
1145 GP_5_5_FN, GPSR5_5,
1146 GP_5_4_FN, GPSR5_4,
1147 GP_5_3_FN, GPSR5_3,
1148 GP_5_2_FN, GPSR5_2,
1149 GP_5_1_FN, GPSR5_1,
1150 GP_5_0_FN, GPSR5_0, }
1151 },
1152 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) {
1153 0, 0,
1154 0, 0,
1155 0, 0,
1156 0, 0,
1157 0, 0,
1158 0, 0,
1159 0, 0,
1160 0, 0,
1161 0, 0,
1162 0, 0,
1163 0, 0,
1164 0, 0,
1165 0, 0,
1166 0, 0,
1167 0, 0,
1168 0, 0,
1169 0, 0,
1170 0, 0,
1171 GP_6_13_FN, GPSR6_13,
1172 GP_6_12_FN, GPSR6_12,
1173 GP_6_11_FN, GPSR6_11,
1174 GP_6_10_FN, GPSR6_10,
1175 GP_6_9_FN, GPSR6_9,
1176 GP_6_8_FN, GPSR6_8,
1177 GP_6_7_FN, GPSR6_7,
1178 GP_6_6_FN, GPSR6_6,
1179 GP_6_5_FN, GPSR6_5,
1180 GP_6_4_FN, GPSR6_4,
1181 GP_6_3_FN, GPSR6_3,
1182 GP_6_2_FN, GPSR6_2,
1183 GP_6_1_FN, GPSR6_1,
1184 GP_6_0_FN, GPSR6_0, }
1185 },
1186#undef F_
1187#undef FM
1188
1189#define F_(x, y) x,
1190#define FM(x) FN_##x,
1191 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
1192 IP0_31_28
1193 IP0_27_24
1194 IP0_23_20
1195 IP0_19_16
1196 IP0_15_12
1197 IP0_11_8
1198 IP0_7_4
1199 IP0_3_0 }
1200 },
1201 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
1202 IP1_31_28
1203 IP1_27_24
1204 IP1_23_20
1205 IP1_19_16
1206 IP1_15_12
1207 IP1_11_8
1208 IP1_7_4
1209 IP1_3_0 }
1210 },
1211 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
1212 IP2_31_28
1213 IP2_27_24
1214 IP2_23_20
1215 IP2_19_16
1216 IP2_15_12
1217 IP2_11_8
1218 IP2_7_4
1219 IP2_3_0 }
1220 },
1221 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
1222 IP3_31_28
1223 IP3_27_24
1224 IP3_23_20
1225 IP3_19_16
1226 IP3_15_12
1227 IP3_11_8
1228 IP3_7_4
1229 IP3_3_0 }
1230 },
1231 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
1232 IP4_31_28
1233 IP4_27_24
1234 IP4_23_20
1235 IP4_19_16
1236 IP4_15_12
1237 IP4_11_8
1238 IP4_7_4
1239 IP4_3_0 }
1240 },
1241 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
1242 IP5_31_28
1243 IP5_27_24
1244 IP5_23_20
1245 IP5_19_16
1246 IP5_15_12
1247 IP5_11_8
1248 IP5_7_4
1249 IP5_3_0 }
1250 },
1251 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
1252 IP6_31_28
1253 IP6_27_24
1254 IP6_23_20
1255 IP6_19_16
1256 IP6_15_12
1257 IP6_11_8
1258 IP6_7_4
1259 IP6_3_0 }
1260 },
1261 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
1262 IP7_31_28
1263 IP7_27_24
1264 IP7_23_20
1265 IP7_19_16
1266 IP7_15_12
1267 IP7_11_8
1268 IP7_7_4
1269 IP7_3_0 }
1270 },
1271 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
1272 IP8_31_28
1273 IP8_27_24
1274 IP8_23_20
1275 IP8_19_16
1276 IP8_15_12
1277 IP8_11_8
1278 IP8_7_4
1279 IP8_3_0 }
1280 },
1281 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) {
1282 IP9_31_28
1283 IP9_27_24
1284 IP9_23_20
1285 IP9_19_16
1286 IP9_15_12
1287 IP9_11_8
1288 IP9_7_4
1289 IP9_3_0 }
1290 },
1291 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) {
1292 IP10_31_28
1293 IP10_27_24
1294 IP10_23_20
1295 IP10_19_16
1296 IP10_15_12
1297 IP10_11_8
1298 IP10_7_4
1299 IP10_3_0 }
1300 },
1301 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) {
1302 IP11_31_28
1303 IP11_27_24
1304 IP11_23_20
1305 IP11_19_16
1306 IP11_15_12
1307 IP11_11_8
1308 IP11_7_4
1309 IP11_3_0 }
1310 },
1311 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) {
1312 IP12_31_28
1313 IP12_27_24
1314 IP12_23_20
1315 IP12_19_16
1316 IP12_15_12
1317 IP12_11_8
1318 IP12_7_4
1319 IP12_3_0 }
1320 },
1321 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) {
1322 /* IP13_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1323 /* IP13_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1324 /* IP13_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1325 /* IP13_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1326 /* IP13_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1327 /* IP13_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1328 IP13_7_4
1329 IP13_3_0 }
1330 },
1331#undef F_
1332#undef FM
1333
1334#define F_(x, y) x,
1335#define FM(x) FN_##x,
1336 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
1337 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 1,
1338 1, 1, 1, 1, 1, 1, 4, 1, 1, 1, 1, 1, 1) {
1339 /* RESERVED 31 */
1340 0, 0,
1341 MOD_SEL0_30
1342 MOD_SEL0_29
1343 MOD_SEL0_28
1344 MOD_SEL0_27
1345 MOD_SEL0_26
1346 MOD_SEL0_25
1347 MOD_SEL0_24_23
1348 MOD_SEL0_22_21
1349 MOD_SEL0_20_19
1350 MOD_SEL0_18_17
1351 /* RESERVED 16 */
1352 0, 0,
1353 MOD_SEL0_15
1354 MOD_SEL0_14
1355 MOD_SEL0_13
1356 MOD_SEL0_12
1357 MOD_SEL0_11
1358 MOD_SEL0_10
1359 /* RESERVED 9, 8, 7, 6 */
1360 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1361 MOD_SEL0_5
1362 MOD_SEL0_4
1363 MOD_SEL0_3
1364 MOD_SEL0_2
1365 MOD_SEL0_1
1366 MOD_SEL0_0 }
1367 },
1368 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
1369 1, 1, 1, 1, 1, 1, 2, 4, 4,
1370 4, 4, 4, 4) {
1371 MOD_SEL1_31
1372 MOD_SEL1_30
1373 MOD_SEL1_29
1374 MOD_SEL1_28
1375 MOD_SEL1_27
1376 MOD_SEL1_26
1377 /* RESERVED 25, 24 */
1378 0, 0, 0, 0,
1379 /* RESERVED 23, 22, 21, 20 */
1380 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1381 /* RESERVED 19, 18, 17, 16 */
1382 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1383 /* RESERVED 15, 14, 13, 12 */
1384 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1385 /* RESERVED 11, 10, 9, 8 */
1386 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1387 /* RESERVED 7, 6, 5, 4 */
1388 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1389 /* RESERVED 3, 2, 1, 0 */
1390 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
1391 },
1392 { },
1393};
1394
1395const struct sh_pfc_soc_info r8a77995_pinmux_info = {
1396 .name = "r8a77995_pfc",
1397 .unlock_reg = 0xe6060000, /* PMMR */
1398
1399 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
1400
1401 .pins = pinmux_pins,
1402 .nr_pins = ARRAY_SIZE(pinmux_pins),
1403 .groups = pinmux_groups,
1404 .nr_groups = ARRAY_SIZE(pinmux_groups),
1405 .functions = pinmux_functions,
1406 .nr_functions = ARRAY_SIZE(pinmux_functions),
1407
1408 .cfg_regs = pinmux_config_regs,
1409
1410 .pinmux_data = pinmux_data,
1411 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
1412};
diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h
index 89e77e59a3dc..8688b405e081 100644
--- a/drivers/pinctrl/sh-pfc/sh_pfc.h
+++ b/drivers/pinctrl/sh-pfc/sh_pfc.h
@@ -271,6 +271,7 @@ extern const struct sh_pfc_soc_info r8a7794_pinmux_info;
271extern const struct sh_pfc_soc_info r8a7795_pinmux_info; 271extern const struct sh_pfc_soc_info r8a7795_pinmux_info;
272extern const struct sh_pfc_soc_info r8a7795es1_pinmux_info; 272extern const struct sh_pfc_soc_info r8a7795es1_pinmux_info;
273extern const struct sh_pfc_soc_info r8a7796_pinmux_info; 273extern const struct sh_pfc_soc_info r8a7796_pinmux_info;
274extern const struct sh_pfc_soc_info r8a77995_pinmux_info;
274extern const struct sh_pfc_soc_info sh7203_pinmux_info; 275extern const struct sh_pfc_soc_info sh7203_pinmux_info;
275extern const struct sh_pfc_soc_info sh7264_pinmux_info; 276extern const struct sh_pfc_soc_info sh7264_pinmux_info;
276extern const struct sh_pfc_soc_info sh7269_pinmux_info; 277extern const struct sh_pfc_soc_info sh7269_pinmux_info;
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-17 14:37:26 -0400