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authorChen-Yu Tsai <wens@csie.org>2016-08-25 02:22:00 -0400
committerMaxime Ripard <maxime.ripard@free-electrons.com>2016-09-10 05:50:41 -0400
commit78a9f0dbcd6015cdd1114dc7d78554fd5bb28010 (patch)
treeb670cfe04ac9cae7f5366a53e71d020d3607ad6d
parentbdc2601b02d31974b5765b93ac263b2eeab2e07c (diff)
ARM: dts: sun6i: switch A31/A31s to new CCU clock bindings
Now that we have a different clock representation, switch to it. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat
-rw-r--r--arch/arm/boot/dts/sun6i-a31.dtsi424
1 files changed, 97 insertions, 327 deletions
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index 1867af24ff52..6a84fe7e9ab2 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -47,7 +47,9 @@
47#include <dt-bindings/interrupt-controller/arm-gic.h> 47#include <dt-bindings/interrupt-controller/arm-gic.h>
48#include <dt-bindings/thermal/thermal.h> 48#include <dt-bindings/thermal/thermal.h>
49 49
50#include <dt-bindings/clock/sun6i-a31-ccu.h>
50#include <dt-bindings/pinctrl/sun4i-a10.h> 51#include <dt-bindings/pinctrl/sun4i-a10.h>
52#include <dt-bindings/reset/sun6i-a31-ccu.h>
51 53
52/ { 54/ {
53 interrupt-parent = <&gic>; 55 interrupt-parent = <&gic>;
@@ -65,7 +67,10 @@
65 compatible = "allwinner,simple-framebuffer", 67 compatible = "allwinner,simple-framebuffer",
66 "simple-framebuffer"; 68 "simple-framebuffer";
67 allwinner,pipeline = "de_be0-lcd0-hdmi"; 69 allwinner,pipeline = "de_be0-lcd0-hdmi";
68 clocks = <&pll6 0>; 70 clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>,
71 <&ccu CLK_AHB1_HDMI>, <&ccu CLK_DRAM_BE0>,
72 <&ccu CLK_IEP_DRC0>, <&ccu CLK_BE0>,
73 <&ccu CLK_LCD0_CH1>, <&ccu CLK_HDMI>;
69 status = "disabled"; 74 status = "disabled";
70 }; 75 };
71 76
@@ -73,7 +78,9 @@
73 compatible = "allwinner,simple-framebuffer", 78 compatible = "allwinner,simple-framebuffer",
74 "simple-framebuffer"; 79 "simple-framebuffer";
75 allwinner,pipeline = "de_be0-lcd0"; 80 allwinner,pipeline = "de_be0-lcd0";
76 clocks = <&pll6 0>; 81 clocks = <&ccu CLK_AHB1_BE0>, <&ccu CLK_AHB1_LCD0>,
82 <&ccu CLK_DRAM_BE0>, <&ccu CLK_IEP_DRC0>,
83 <&ccu CLK_BE0>, <&ccu CLK_LCD0_CH0>;
77 status = "disabled"; 84 status = "disabled";
78 }; 85 };
79 }; 86 };
@@ -97,7 +104,7 @@
97 compatible = "arm,cortex-a7"; 104 compatible = "arm,cortex-a7";
98 device_type = "cpu"; 105 device_type = "cpu";
99 reg = <0>; 106 reg = <0>;
100 clocks = <&cpu>; 107 clocks = <&ccu CLK_CPU>;
101 clock-latency = <244144>; /* 8 32k periods */ 108 clock-latency = <244144>; /* 8 32k periods */
102 operating-points = < 109 operating-points = <
103 /* kHz uV */ 110 /* kHz uV */
@@ -192,235 +199,6 @@
192 clock-output-names = "osc32k"; 199 clock-output-names = "osc32k";
193 }; 200 };
194 201
195 pll1: clk@01c20000 {
196 #clock-cells = <0>;
197 compatible = "allwinner,sun6i-a31-pll1-clk";
198 reg = <0x01c20000 0x4>;
199 clocks = <&osc24M>;
200 clock-output-names = "pll1";
201 };
202
203 pll6: clk@01c20028 {
204 #clock-cells = <1>;
205 compatible = "allwinner,sun6i-a31-pll6-clk";
206 reg = <0x01c20028 0x4>;
207 clocks = <&osc24M>;
208 clock-output-names = "pll6", "pll6x2";
209 };
210
211 cpu: cpu@01c20050 {
212 #clock-cells = <0>;
213 compatible = "allwinner,sun4i-a10-cpu-clk";
214 reg = <0x01c20050 0x4>;
215
216 /*
217 * PLL1 is listed twice here.
218 * While it looks suspicious, it's actually documented
219 * that way both in the datasheet and in the code from
220 * Allwinner.
221 */
222 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
223 clock-output-names = "cpu";
224 };
225
226 axi: axi@01c20050 {
227 #clock-cells = <0>;
228 compatible = "allwinner,sun4i-a10-axi-clk";
229 reg = <0x01c20050 0x4>;
230 clocks = <&cpu>;
231 clock-output-names = "axi";
232 };
233
234 ahb1: ahb1@01c20054 {
235 #clock-cells = <0>;
236 compatible = "allwinner,sun6i-a31-ahb1-clk";
237 reg = <0x01c20054 0x4>;
238 clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
239 clock-output-names = "ahb1";
240
241 /*
242 * Clock AHB1 from PLL6, instead of CPU/AXI which
243 * has rate changes due to cpufreq. Also the DMA
244 * controller requires AHB1 clocked from PLL6.
245 */
246 assigned-clocks = <&ahb1>;
247 assigned-clock-parents = <&pll6 0>;
248 };
249
250 ahb1_gates: clk@01c20060 {
251 #clock-cells = <1>;
252 compatible = "allwinner,sun6i-a31-ahb1-gates-clk";
253 reg = <0x01c20060 0x8>;
254 clocks = <&ahb1>;
255 clock-indices = <1>, <5>,
256 <6>, <8>, <9>,
257 <10>, <11>, <12>,
258 <13>, <14>,
259 <17>, <18>, <19>,
260 <20>, <21>, <22>,
261 <23>, <24>, <26>,
262 <27>, <29>,
263 <30>, <31>, <32>,
264 <36>, <37>, <40>,
265 <43>, <44>, <45>,
266 <46>, <47>, <50>,
267 <52>, <55>, <56>,
268 <57>, <58>;
269 clock-output-names = "ahb1_mipidsi", "ahb1_ss",
270 "ahb1_dma", "ahb1_mmc0", "ahb1_mmc1",
271 "ahb1_mmc2", "ahb1_mmc3", "ahb1_nand1",
272 "ahb1_nand0", "ahb1_sdram",
273 "ahb1_gmac", "ahb1_ts", "ahb1_hstimer",
274 "ahb1_spi0", "ahb1_spi1", "ahb1_spi2",
275 "ahb1_spi3", "ahb1_otg", "ahb1_ehci0",
276 "ahb1_ehci1", "ahb1_ohci0",
277 "ahb1_ohci1", "ahb1_ohci2", "ahb1_ve",
278 "ahb1_lcd0", "ahb1_lcd1", "ahb1_csi",
279 "ahb1_hdmi", "ahb1_de0", "ahb1_de1",
280 "ahb1_fe0", "ahb1_fe1", "ahb1_mp",
281 "ahb1_gpu", "ahb1_deu0", "ahb1_deu1",
282 "ahb1_drc0", "ahb1_drc1";
283 };
284
285 apb1: apb1@01c20054 {
286 #clock-cells = <0>;
287 compatible = "allwinner,sun4i-a10-apb0-clk";
288 reg = <0x01c20054 0x4>;
289 clocks = <&ahb1>;
290 clock-output-names = "apb1";
291 };
292
293 apb1_gates: clk@01c20068 {
294 #clock-cells = <1>;
295 compatible = "allwinner,sun6i-a31-apb1-gates-clk";
296 reg = <0x01c20068 0x4>;
297 clocks = <&apb1>;
298 clock-indices = <0>, <4>,
299 <5>, <12>,
300 <13>;
301 clock-output-names = "apb1_codec", "apb1_digital_mic",
302 "apb1_pio", "apb1_daudio0",
303 "apb1_daudio1";
304 };
305
306 apb2: clk@01c20058 {
307 #clock-cells = <0>;
308 compatible = "allwinner,sun4i-a10-apb1-clk";
309 reg = <0x01c20058 0x4>;
310 clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
311 clock-output-names = "apb2";
312 };
313
314 apb2_gates: clk@01c2006c {
315 #clock-cells = <1>;
316 compatible = "allwinner,sun6i-a31-apb2-gates-clk";
317 reg = <0x01c2006c 0x4>;
318 clocks = <&apb2>;
319 clock-indices = <0>, <1>,
320 <2>, <3>, <16>,
321 <17>, <18>, <19>,
322 <20>, <21>;
323 clock-output-names = "apb2_i2c0", "apb2_i2c1",
324 "apb2_i2c2", "apb2_i2c3",
325 "apb2_uart0", "apb2_uart1",
326 "apb2_uart2", "apb2_uart3",
327 "apb2_uart4", "apb2_uart5";
328 };
329
330 mmc0_clk: clk@01c20088 {
331 #clock-cells = <1>;
332 compatible = "allwinner,sun4i-a10-mmc-clk";
333 reg = <0x01c20088 0x4>;
334 clocks = <&osc24M>, <&pll6 0>;
335 clock-output-names = "mmc0",
336 "mmc0_output",
337 "mmc0_sample";
338 };
339
340 mmc1_clk: clk@01c2008c {
341 #clock-cells = <1>;
342 compatible = "allwinner,sun4i-a10-mmc-clk";
343 reg = <0x01c2008c 0x4>;
344 clocks = <&osc24M>, <&pll6 0>;
345 clock-output-names = "mmc1",
346 "mmc1_output",
347 "mmc1_sample";
348 };
349
350 mmc2_clk: clk@01c20090 {
351 #clock-cells = <1>;
352 compatible = "allwinner,sun4i-a10-mmc-clk";
353 reg = <0x01c20090 0x4>;
354 clocks = <&osc24M>, <&pll6 0>;
355 clock-output-names = "mmc2",
356 "mmc2_output",
357 "mmc2_sample";
358 };
359
360 mmc3_clk: clk@01c20094 {
361 #clock-cells = <1>;
362 compatible = "allwinner,sun4i-a10-mmc-clk";
363 reg = <0x01c20094 0x4>;
364 clocks = <&osc24M>, <&pll6 0>;
365 clock-output-names = "mmc3",
366 "mmc3_output",
367 "mmc3_sample";
368 };
369
370 ss_clk: clk@01c2009c {
371 #clock-cells = <0>;
372 compatible = "allwinner,sun4i-a10-mod0-clk";
373 reg = <0x01c2009c 0x4>;
374 clocks = <&osc24M>, <&pll6 0>;
375 clock-output-names = "ss";
376 };
377
378 spi0_clk: clk@01c200a0 {
379 #clock-cells = <0>;
380 compatible = "allwinner,sun4i-a10-mod0-clk";
381 reg = <0x01c200a0 0x4>;
382 clocks = <&osc24M>, <&pll6 0>;
383 clock-output-names = "spi0";
384 };
385
386 spi1_clk: clk@01c200a4 {
387 #clock-cells = <0>;
388 compatible = "allwinner,sun4i-a10-mod0-clk";
389 reg = <0x01c200a4 0x4>;
390 clocks = <&osc24M>, <&pll6 0>;
391 clock-output-names = "spi1";
392 };
393
394 spi2_clk: clk@01c200a8 {
395 #clock-cells = <0>;
396 compatible = "allwinner,sun4i-a10-mod0-clk";
397 reg = <0x01c200a8 0x4>;
398 clocks = <&osc24M>, <&pll6 0>;
399 clock-output-names = "spi2";
400 };
401
402 spi3_clk: clk@01c200ac {
403 #clock-cells = <0>;
404 compatible = "allwinner,sun4i-a10-mod0-clk";
405 reg = <0x01c200ac 0x4>;
406 clocks = <&osc24M>, <&pll6 0>;
407 clock-output-names = "spi3";
408 };
409
410 usb_clk: clk@01c200cc {
411 #clock-cells = <1>;
412 #reset-cells = <1>;
413 compatible = "allwinner,sun6i-a31-usb-clk";
414 reg = <0x01c200cc 0x4>;
415 clocks = <&osc24M>;
416 clock-indices = <8>, <9>, <10>,
417 <16>, <17>,
418 <18>;
419 clock-output-names = "usb_phy0", "usb_phy1", "usb_phy2",
420 "usb_ohci0", "usb_ohci1",
421 "usb_ohci2";
422 };
423
424 /* 202 /*
425 * The following two are dummy clocks, placeholders 203 * The following two are dummy clocks, placeholders
426 * used in the gmac_tx clock. The gmac driver will 204 * used in the gmac_tx clock. The gmac driver will
@@ -463,23 +241,23 @@
463 compatible = "allwinner,sun6i-a31-dma"; 241 compatible = "allwinner,sun6i-a31-dma";
464 reg = <0x01c02000 0x1000>; 242 reg = <0x01c02000 0x1000>;
465 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 243 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
466 clocks = <&ahb1_gates 6>; 244 clocks = <&ccu CLK_AHB1_DMA>;
467 resets = <&ahb1_rst 6>; 245 resets = <&ccu RST_AHB1_DMA>;
468 #dma-cells = <1>; 246 #dma-cells = <1>;
469 }; 247 };
470 248
471 mmc0: mmc@01c0f000 { 249 mmc0: mmc@01c0f000 {
472 compatible = "allwinner,sun5i-a13-mmc"; 250 compatible = "allwinner,sun5i-a13-mmc";
473 reg = <0x01c0f000 0x1000>; 251 reg = <0x01c0f000 0x1000>;
474 clocks = <&ahb1_gates 8>, 252 clocks = <&ccu CLK_AHB1_MMC0>,
475 <&mmc0_clk 0>, 253 <&ccu CLK_MMC0>,
476 <&mmc0_clk 1>, 254 <&ccu CLK_MMC0_OUTPUT>,
477 <&mmc0_clk 2>; 255 <&ccu CLK_MMC0_SAMPLE>;
478 clock-names = "ahb", 256 clock-names = "ahb",
479 "mmc", 257 "mmc",
480 "output", 258 "output",
481 "sample"; 259 "sample";
482 resets = <&ahb1_rst 8>; 260 resets = <&ccu RST_AHB1_MMC0>;
483 reset-names = "ahb"; 261 reset-names = "ahb";
484 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 262 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
485 status = "disabled"; 263 status = "disabled";
@@ -490,15 +268,15 @@
490 mmc1: mmc@01c10000 { 268 mmc1: mmc@01c10000 {
491 compatible = "allwinner,sun5i-a13-mmc"; 269 compatible = "allwinner,sun5i-a13-mmc";
492 reg = <0x01c10000 0x1000>; 270 reg = <0x01c10000 0x1000>;
493 clocks = <&ahb1_gates 9>, 271 clocks = <&ccu CLK_AHB1_MMC1>,
494 <&mmc1_clk 0>, 272 <&ccu CLK_MMC1>,
495 <&mmc1_clk 1>, 273 <&ccu CLK_MMC1_OUTPUT>,
496 <&mmc1_clk 2>; 274 <&ccu CLK_MMC1_SAMPLE>;
497 clock-names = "ahb", 275 clock-names = "ahb",
498 "mmc", 276 "mmc",
499 "output", 277 "output",
500 "sample"; 278 "sample";
501 resets = <&ahb1_rst 9>; 279 resets = <&ccu RST_AHB1_MMC1>;
502 reset-names = "ahb"; 280 reset-names = "ahb";
503 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 281 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
504 status = "disabled"; 282 status = "disabled";
@@ -509,15 +287,15 @@
509 mmc2: mmc@01c11000 { 287 mmc2: mmc@01c11000 {
510 compatible = "allwinner,sun5i-a13-mmc"; 288 compatible = "allwinner,sun5i-a13-mmc";
511 reg = <0x01c11000 0x1000>; 289 reg = <0x01c11000 0x1000>;
512 clocks = <&ahb1_gates 10>, 290 clocks = <&ccu CLK_AHB1_MMC2>,
513 <&mmc2_clk 0>, 291 <&ccu CLK_MMC2>,
514 <&mmc2_clk 1>, 292 <&ccu CLK_MMC2_OUTPUT>,
515 <&mmc2_clk 2>; 293 <&ccu CLK_MMC2_SAMPLE>;
516 clock-names = "ahb", 294 clock-names = "ahb",
517 "mmc", 295 "mmc",
518 "output", 296 "output",
519 "sample"; 297 "sample";
520 resets = <&ahb1_rst 10>; 298 resets = <&ccu RST_AHB1_MMC2>;
521 reset-names = "ahb"; 299 reset-names = "ahb";
522 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 300 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
523 status = "disabled"; 301 status = "disabled";
@@ -528,15 +306,15 @@
528 mmc3: mmc@01c12000 { 306 mmc3: mmc@01c12000 {
529 compatible = "allwinner,sun5i-a13-mmc"; 307 compatible = "allwinner,sun5i-a13-mmc";
530 reg = <0x01c12000 0x1000>; 308 reg = <0x01c12000 0x1000>;
531 clocks = <&ahb1_gates 11>, 309 clocks = <&ccu CLK_AHB1_MMC3>,
532 <&mmc3_clk 0>, 310 <&ccu CLK_MMC3>,
533 <&mmc3_clk 1>, 311 <&ccu CLK_MMC3_OUTPUT>,
534 <&mmc3_clk 2>; 312 <&ccu CLK_MMC3_SAMPLE>;
535 clock-names = "ahb", 313 clock-names = "ahb",
536 "mmc", 314 "mmc",
537 "output", 315 "output",
538 "sample"; 316 "sample";
539 resets = <&ahb1_rst 11>; 317 resets = <&ccu RST_AHB1_MMC3>;
540 reset-names = "ahb"; 318 reset-names = "ahb";
541 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 319 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
542 status = "disabled"; 320 status = "disabled";
@@ -547,8 +325,8 @@
547 usb_otg: usb@01c19000 { 325 usb_otg: usb@01c19000 {
548 compatible = "allwinner,sun6i-a31-musb"; 326 compatible = "allwinner,sun6i-a31-musb";
549 reg = <0x01c19000 0x0400>; 327 reg = <0x01c19000 0x0400>;
550 clocks = <&ahb1_gates 24>; 328 clocks = <&ccu CLK_AHB1_OTG>;
551 resets = <&ahb1_rst 24>; 329 resets = <&ccu RST_AHB1_OTG>;
552 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 330 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
553 interrupt-names = "mc"; 331 interrupt-names = "mc";
554 phys = <&usbphy 0>; 332 phys = <&usbphy 0>;
@@ -565,15 +343,15 @@
565 reg-names = "phy_ctrl", 343 reg-names = "phy_ctrl",
566 "pmu1", 344 "pmu1",
567 "pmu2"; 345 "pmu2";
568 clocks = <&usb_clk 8>, 346 clocks = <&ccu CLK_USB_PHY0>,
569 <&usb_clk 9>, 347 <&ccu CLK_USB_PHY1>,
570 <&usb_clk 10>; 348 <&ccu CLK_USB_PHY2>;
571 clock-names = "usb0_phy", 349 clock-names = "usb0_phy",
572 "usb1_phy", 350 "usb1_phy",
573 "usb2_phy"; 351 "usb2_phy";
574 resets = <&usb_clk 0>, 352 resets = <&ccu RST_USB_PHY0>,
575 <&usb_clk 1>, 353 <&ccu RST_USB_PHY1>,
576 <&usb_clk 2>; 354 <&ccu RST_USB_PHY2>;
577 reset-names = "usb0_reset", 355 reset-names = "usb0_reset",
578 "usb1_reset", 356 "usb1_reset",
579 "usb2_reset"; 357 "usb2_reset";
@@ -585,8 +363,8 @@
585 compatible = "allwinner,sun6i-a31-ehci", "generic-ehci"; 363 compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
586 reg = <0x01c1a000 0x100>; 364 reg = <0x01c1a000 0x100>;
587 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 365 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
588 clocks = <&ahb1_gates 26>; 366 clocks = <&ccu CLK_AHB1_EHCI0>;
589 resets = <&ahb1_rst 26>; 367 resets = <&ccu RST_AHB1_EHCI0>;
590 phys = <&usbphy 1>; 368 phys = <&usbphy 1>;
591 phy-names = "usb"; 369 phy-names = "usb";
592 status = "disabled"; 370 status = "disabled";
@@ -596,8 +374,8 @@
596 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci"; 374 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
597 reg = <0x01c1a400 0x100>; 375 reg = <0x01c1a400 0x100>;
598 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 376 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
599 clocks = <&ahb1_gates 29>, <&usb_clk 16>; 377 clocks = <&ccu CLK_AHB1_OHCI0>, <&ccu CLK_USB_OHCI0>;
600 resets = <&ahb1_rst 29>; 378 resets = <&ccu RST_AHB1_OHCI0>;
601 phys = <&usbphy 1>; 379 phys = <&usbphy 1>;
602 phy-names = "usb"; 380 phy-names = "usb";
603 status = "disabled"; 381 status = "disabled";
@@ -607,8 +385,8 @@
607 compatible = "allwinner,sun6i-a31-ehci", "generic-ehci"; 385 compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
608 reg = <0x01c1b000 0x100>; 386 reg = <0x01c1b000 0x100>;
609 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 387 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
610 clocks = <&ahb1_gates 27>; 388 clocks = <&ccu CLK_AHB1_EHCI1>;
611 resets = <&ahb1_rst 27>; 389 resets = <&ccu RST_AHB1_EHCI1>;
612 phys = <&usbphy 2>; 390 phys = <&usbphy 2>;
613 phy-names = "usb"; 391 phy-names = "usb";
614 status = "disabled"; 392 status = "disabled";
@@ -618,8 +396,8 @@
618 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci"; 396 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
619 reg = <0x01c1b400 0x100>; 397 reg = <0x01c1b400 0x100>;
620 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 398 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
621 clocks = <&ahb1_gates 30>, <&usb_clk 17>; 399 clocks = <&ccu CLK_AHB1_OHCI1>, <&ccu CLK_USB_OHCI1>;
622 resets = <&ahb1_rst 30>; 400 resets = <&ccu RST_AHB1_OHCI1>;
623 phys = <&usbphy 2>; 401 phys = <&usbphy 2>;
624 phy-names = "usb"; 402 phy-names = "usb";
625 status = "disabled"; 403 status = "disabled";
@@ -629,11 +407,20 @@
629 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci"; 407 compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
630 reg = <0x01c1c400 0x100>; 408 reg = <0x01c1c400 0x100>;
631 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 409 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
632 clocks = <&ahb1_gates 31>, <&usb_clk 18>; 410 clocks = <&ccu CLK_AHB1_OHCI2>, <&ccu CLK_USB_OHCI2>;
633 resets = <&ahb1_rst 31>; 411 resets = <&ccu RST_AHB1_OHCI2>;
634 status = "disabled"; 412 status = "disabled";
635 }; 413 };
636 414
415 ccu: clock@01c20000 {
416 compatible = "allwinner,sun6i-a31-ccu";
417 reg = <0x01c20000 0x400>;
418 clocks = <&osc24M>, <&osc32k>;
419 clock-names = "hosc", "losc";
420 #clock-cells = <1>;
421 #reset-cells = <1>;
422 };
423
637 pio: pinctrl@01c20800 { 424 pio: pinctrl@01c20800 {
638 compatible = "allwinner,sun6i-a31-pinctrl"; 425 compatible = "allwinner,sun6i-a31-pinctrl";
639 reg = <0x01c20800 0x400>; 426 reg = <0x01c20800 0x400>;
@@ -641,7 +428,7 @@
641 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 428 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
642 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 429 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
643 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 430 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
644 clocks = <&apb1_gates 5>; 431 clocks = <&ccu CLK_APB1_PIO>;
645 gpio-controller; 432 gpio-controller;
646 interrupt-controller; 433 interrupt-controller;
647 #interrupt-cells = <3>; 434 #interrupt-cells = <3>;
@@ -762,24 +549,6 @@
762 }; 549 };
763 }; 550 };
764 551
765 ahb1_rst: reset@01c202c0 {
766 #reset-cells = <1>;
767 compatible = "allwinner,sun6i-a31-ahb1-reset";
768 reg = <0x01c202c0 0xc>;
769 };
770
771 apb1_rst: reset@01c202d0 {
772 #reset-cells = <1>;
773 compatible = "allwinner,sun6i-a31-clock-reset";
774 reg = <0x01c202d0 0x4>;
775 };
776
777 apb2_rst: reset@01c202d8 {
778 #reset-cells = <1>;
779 compatible = "allwinner,sun6i-a31-clock-reset";
780 reg = <0x01c202d8 0x4>;
781 };
782
783 timer@01c20c00 { 552 timer@01c20c00 {
784 compatible = "allwinner,sun4i-a10-timer"; 553 compatible = "allwinner,sun4i-a10-timer";
785 reg = <0x01c20c00 0xa0>; 554 reg = <0x01c20c00 0xa0>;
@@ -816,8 +585,8 @@
816 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 585 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
817 reg-shift = <2>; 586 reg-shift = <2>;
818 reg-io-width = <4>; 587 reg-io-width = <4>;
819 clocks = <&apb2_gates 16>; 588 clocks = <&ccu CLK_APB2_UART0>;
820 resets = <&apb2_rst 16>; 589 resets = <&ccu RST_APB2_UART0>;
821 dmas = <&dma 6>, <&dma 6>; 590 dmas = <&dma 6>, <&dma 6>;
822 dma-names = "rx", "tx"; 591 dma-names = "rx", "tx";
823 status = "disabled"; 592 status = "disabled";
@@ -829,8 +598,8 @@
829 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 598 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
830 reg-shift = <2>; 599 reg-shift = <2>;
831 reg-io-width = <4>; 600 reg-io-width = <4>;
832 clocks = <&apb2_gates 17>; 601 clocks = <&ccu CLK_APB2_UART1>;
833 resets = <&apb2_rst 17>; 602 resets = <&ccu RST_APB2_UART1>;
834 dmas = <&dma 7>, <&dma 7>; 603 dmas = <&dma 7>, <&dma 7>;
835 dma-names = "rx", "tx"; 604 dma-names = "rx", "tx";
836 status = "disabled"; 605 status = "disabled";
@@ -842,8 +611,8 @@
842 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 611 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
843 reg-shift = <2>; 612 reg-shift = <2>;
844 reg-io-width = <4>; 613 reg-io-width = <4>;
845 clocks = <&apb2_gates 18>; 614 clocks = <&ccu CLK_APB2_UART2>;
846 resets = <&apb2_rst 18>; 615 resets = <&ccu RST_APB2_UART2>;
847 dmas = <&dma 8>, <&dma 8>; 616 dmas = <&dma 8>, <&dma 8>;
848 dma-names = "rx", "tx"; 617 dma-names = "rx", "tx";
849 status = "disabled"; 618 status = "disabled";
@@ -855,8 +624,8 @@
855 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 624 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
856 reg-shift = <2>; 625 reg-shift = <2>;
857 reg-io-width = <4>; 626 reg-io-width = <4>;
858 clocks = <&apb2_gates 19>; 627 clocks = <&ccu CLK_APB2_UART3>;
859 resets = <&apb2_rst 19>; 628 resets = <&ccu RST_APB2_UART3>;
860 dmas = <&dma 9>, <&dma 9>; 629 dmas = <&dma 9>, <&dma 9>;
861 dma-names = "rx", "tx"; 630 dma-names = "rx", "tx";
862 status = "disabled"; 631 status = "disabled";
@@ -868,8 +637,8 @@
868 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 637 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
869 reg-shift = <2>; 638 reg-shift = <2>;
870 reg-io-width = <4>; 639 reg-io-width = <4>;
871 clocks = <&apb2_gates 20>; 640 clocks = <&ccu CLK_APB2_UART4>;
872 resets = <&apb2_rst 20>; 641 resets = <&ccu RST_APB2_UART4>;
873 dmas = <&dma 10>, <&dma 10>; 642 dmas = <&dma 10>, <&dma 10>;
874 dma-names = "rx", "tx"; 643 dma-names = "rx", "tx";
875 status = "disabled"; 644 status = "disabled";
@@ -881,8 +650,8 @@
881 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 650 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
882 reg-shift = <2>; 651 reg-shift = <2>;
883 reg-io-width = <4>; 652 reg-io-width = <4>;
884 clocks = <&apb2_gates 21>; 653 clocks = <&ccu CLK_APB2_UART5>;
885 resets = <&apb2_rst 21>; 654 resets = <&ccu RST_APB2_UART5>;
886 dmas = <&dma 22>, <&dma 22>; 655 dmas = <&dma 22>, <&dma 22>;
887 dma-names = "rx", "tx"; 656 dma-names = "rx", "tx";
888 status = "disabled"; 657 status = "disabled";
@@ -892,8 +661,8 @@
892 compatible = "allwinner,sun6i-a31-i2c"; 661 compatible = "allwinner,sun6i-a31-i2c";
893 reg = <0x01c2ac00 0x400>; 662 reg = <0x01c2ac00 0x400>;
894 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 663 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
895 clocks = <&apb2_gates 0>; 664 clocks = <&ccu CLK_APB2_I2C0>;
896 resets = <&apb2_rst 0>; 665 resets = <&ccu RST_APB2_I2C0>;
897 status = "disabled"; 666 status = "disabled";
898 #address-cells = <1>; 667 #address-cells = <1>;
899 #size-cells = <0>; 668 #size-cells = <0>;
@@ -903,8 +672,8 @@
903 compatible = "allwinner,sun6i-a31-i2c"; 672 compatible = "allwinner,sun6i-a31-i2c";
904 reg = <0x01c2b000 0x400>; 673 reg = <0x01c2b000 0x400>;
905 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 674 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
906 clocks = <&apb2_gates 1>; 675 clocks = <&ccu CLK_APB2_I2C1>;
907 resets = <&apb2_rst 1>; 676 resets = <&ccu RST_APB2_I2C1>;
908 status = "disabled"; 677 status = "disabled";
909 #address-cells = <1>; 678 #address-cells = <1>;
910 #size-cells = <0>; 679 #size-cells = <0>;
@@ -914,8 +683,8 @@
914 compatible = "allwinner,sun6i-a31-i2c"; 683 compatible = "allwinner,sun6i-a31-i2c";
915 reg = <0x01c2b400 0x400>; 684 reg = <0x01c2b400 0x400>;
916 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 685 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
917 clocks = <&apb2_gates 2>; 686 clocks = <&ccu CLK_APB2_I2C2>;
918 resets = <&apb2_rst 2>; 687 resets = <&ccu RST_APB2_I2C2>;
919 status = "disabled"; 688 status = "disabled";
920 #address-cells = <1>; 689 #address-cells = <1>;
921 #size-cells = <0>; 690 #size-cells = <0>;
@@ -925,8 +694,8 @@
925 compatible = "allwinner,sun6i-a31-i2c"; 694 compatible = "allwinner,sun6i-a31-i2c";
926 reg = <0x01c2b800 0x400>; 695 reg = <0x01c2b800 0x400>;
927 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 696 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
928 clocks = <&apb2_gates 3>; 697 clocks = <&ccu CLK_APB2_I2C3>;
929 resets = <&apb2_rst 3>; 698 resets = <&ccu RST_APB2_I2C3>;
930 status = "disabled"; 699 status = "disabled";
931 #address-cells = <1>; 700 #address-cells = <1>;
932 #size-cells = <0>; 701 #size-cells = <0>;
@@ -937,9 +706,9 @@
937 reg = <0x01c30000 0x1054>; 706 reg = <0x01c30000 0x1054>;
938 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 707 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
939 interrupt-names = "macirq"; 708 interrupt-names = "macirq";
940 clocks = <&ahb1_gates 17>, <&gmac_tx_clk>; 709 clocks = <&ccu CLK_AHB1_EMAC>, <&gmac_tx_clk>;
941 clock-names = "stmmaceth", "allwinner_gmac_tx"; 710 clock-names = "stmmaceth", "allwinner_gmac_tx";
942 resets = <&ahb1_rst 17>; 711 resets = <&ccu RST_AHB1_EMAC>;
943 reset-names = "stmmaceth"; 712 reset-names = "stmmaceth";
944 snps,pbl = <2>; 713 snps,pbl = <2>;
945 snps,fixed-burst; 714 snps,fixed-burst;
@@ -953,9 +722,9 @@
953 compatible = "allwinner,sun4i-a10-crypto"; 722 compatible = "allwinner,sun4i-a10-crypto";
954 reg = <0x01c15000 0x1000>; 723 reg = <0x01c15000 0x1000>;
955 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 724 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
956 clocks = <&ahb1_gates 5>, <&ss_clk>; 725 clocks = <&ccu CLK_AHB1_SS>, <&ccu CLK_SS>;
957 clock-names = "ahb", "mod"; 726 clock-names = "ahb", "mod";
958 resets = <&ahb1_rst 5>; 727 resets = <&ccu RST_AHB1_SS>;
959 reset-names = "ahb"; 728 reset-names = "ahb";
960 }; 729 };
961 730
@@ -967,19 +736,19 @@
967 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 736 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
968 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 737 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
969 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 738 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
970 clocks = <&ahb1_gates 19>; 739 clocks = <&ccu CLK_AHB1_HSTIMER>;
971 resets = <&ahb1_rst 19>; 740 resets = <&ccu RST_AHB1_HSTIMER>;
972 }; 741 };
973 742
974 spi0: spi@01c68000 { 743 spi0: spi@01c68000 {
975 compatible = "allwinner,sun6i-a31-spi"; 744 compatible = "allwinner,sun6i-a31-spi";
976 reg = <0x01c68000 0x1000>; 745 reg = <0x01c68000 0x1000>;
977 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 746 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
978 clocks = <&ahb1_gates 20>, <&spi0_clk>; 747 clocks = <&ccu CLK_AHB1_SPI0>, <&ccu CLK_SPI0>;
979 clock-names = "ahb", "mod"; 748 clock-names = "ahb", "mod";
980 dmas = <&dma 23>, <&dma 23>; 749 dmas = <&dma 23>, <&dma 23>;
981 dma-names = "rx", "tx"; 750 dma-names = "rx", "tx";
982 resets = <&ahb1_rst 20>; 751 resets = <&ccu RST_AHB1_SPI0>;
983 status = "disabled"; 752 status = "disabled";
984 }; 753 };
985 754
@@ -987,11 +756,11 @@
987 compatible = "allwinner,sun6i-a31-spi"; 756 compatible = "allwinner,sun6i-a31-spi";
988 reg = <0x01c69000 0x1000>; 757 reg = <0x01c69000 0x1000>;
989 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 758 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
990 clocks = <&ahb1_gates 21>, <&spi1_clk>; 759 clocks = <&ccu CLK_AHB1_SPI1>, <&ccu CLK_SPI1>;
991 clock-names = "ahb", "mod"; 760 clock-names = "ahb", "mod";
992 dmas = <&dma 24>, <&dma 24>; 761 dmas = <&dma 24>, <&dma 24>;
993 dma-names = "rx", "tx"; 762 dma-names = "rx", "tx";
994 resets = <&ahb1_rst 21>; 763 resets = <&ccu RST_AHB1_SPI1>;
995 status = "disabled"; 764 status = "disabled";
996 }; 765 };
997 766
@@ -999,11 +768,11 @@
999 compatible = "allwinner,sun6i-a31-spi"; 768 compatible = "allwinner,sun6i-a31-spi";
1000 reg = <0x01c6a000 0x1000>; 769 reg = <0x01c6a000 0x1000>;
1001 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 770 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
1002 clocks = <&ahb1_gates 22>, <&spi2_clk>; 771 clocks = <&ccu CLK_AHB1_SPI2>, <&ccu CLK_SPI2>;
1003 clock-names = "ahb", "mod"; 772 clock-names = "ahb", "mod";
1004 dmas = <&dma 25>, <&dma 25>; 773 dmas = <&dma 25>, <&dma 25>;
1005 dma-names = "rx", "tx"; 774 dma-names = "rx", "tx";
1006 resets = <&ahb1_rst 22>; 775 resets = <&ccu RST_AHB1_SPI2>;
1007 status = "disabled"; 776 status = "disabled";
1008 }; 777 };
1009 778
@@ -1011,11 +780,11 @@
1011 compatible = "allwinner,sun6i-a31-spi"; 780 compatible = "allwinner,sun6i-a31-spi";
1012 reg = <0x01c6b000 0x1000>; 781 reg = <0x01c6b000 0x1000>;
1013 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 782 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
1014 clocks = <&ahb1_gates 23>, <&spi3_clk>; 783 clocks = <&ccu CLK_AHB1_SPI3>, <&ccu CLK_SPI3>;
1015 clock-names = "ahb", "mod"; 784 clock-names = "ahb", "mod";
1016 dmas = <&dma 26>, <&dma 26>; 785 dmas = <&dma 26>, <&dma 26>;
1017 dma-names = "rx", "tx"; 786 dma-names = "rx", "tx";
1018 resets = <&ahb1_rst 23>; 787 resets = <&ccu RST_AHB1_SPI3>;
1019 status = "disabled"; 788 status = "disabled";
1020 }; 789 };
1021 790
@@ -1052,8 +821,9 @@
1052 ar100: ar100_clk { 821 ar100: ar100_clk {
1053 compatible = "allwinner,sun6i-a31-ar100-clk"; 822 compatible = "allwinner,sun6i-a31-ar100-clk";
1054 #clock-cells = <0>; 823 #clock-cells = <0>;
1055 clocks = <&osc32k>, <&osc24M>, <&pll6 0>, 824 clocks = <&osc32k>, <&osc24M>,
1056 <&pll6 0>; 825 <&ccu CLK_PLL_PERIPH>,
826 <&ccu CLK_PLL_PERIPH>;
1057 clock-output-names = "ar100"; 827 clock-output-names = "ar100";
1058 }; 828 };
1059 829
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-23 11:26:09 -0400