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authorLinus Torvalds <torvalds@linux-foundation.org>2016-07-22 23:32:50 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2016-07-22 23:32:50 -0400
commit7825e0c42943e16535ece82f3787b6b94a6c1652 (patch)
tree099b80c818c7a6070aa6b6c67fe7451faf7c3636
parent48d4ca5639507b8c37e3bd5711e70aedb05dee2c (diff)
parent5eb495349f5ec3b134f7341a2450392fc86d99d0 (diff)
Merge tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC fixes from Olof Johansson: "A handful of fixes before final release: Marvell Armada: - One to fix a typo in the devicetree specifying memory ranges for the crypto engine - Two to deal with marking PCI and device-memory as strongly ordered to avoid hardware deadlocks, in particular when enabling above crypto driver. - Compile fix for PM Allwinner: - DT clock fixes to deal with u-boot-enabled framebuffer (simplefb). - Make R8 (C.H.I.P. SoC) inherit system compatibility from A13 to make clocks register proper. Tegra: - Fix SD card voltage setting on the Tegra3 Beaver dev board Misc: - Two maintainers updates for STM32 and STi platforms" * tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: ARM: tegra: beaver: Allow SD card voltage to be changed MAINTAINERS: update STi maintainer list MAINTAINERS: update STM32 maintainers list ARM: mvebu: compile pm code conditionally ARM: dts: sun7i: Fix pll3x2 and pll7x2 not having a parent clock ARM: dts: sunxi: Add pll3 to simplefb nodes clocks lists ARM: dts: armada-38x: fix MBUS_ID for crypto SRAM on Armada 385 Linksys ARM: mvebu: map PCI I/O regions strongly ordered ARM: mvebu: fix HW I/O coherency related deadlocks ARM: sunxi/dt: make the CHIP inherit from allwinner,sun5i-a13
-rw-r--r--MAINTAINERS3
-rw-r--r--arch/arm/boot/dts/armada-385-linksys.dtsi4
-rw-r--r--arch/arm/boot/dts/sun4i-a10.dtsi21
-rw-r--r--arch/arm/boot/dts/sun5i-a10s.dtsi11
-rw-r--r--arch/arm/boot/dts/sun5i-r8-chip.dts2
-rw-r--r--arch/arm/boot/dts/sun7i-a20.dtsi13
-rw-r--r--arch/arm/boot/dts/tegra30-beaver.dts3
-rw-r--r--arch/arm/mach-mvebu/Makefile10
-rw-r--r--arch/arm/mach-mvebu/coherency.c23
9 files changed, 49 insertions, 41 deletions
diff --git a/MAINTAINERS b/MAINTAINERS
index 1d748377595f..4a728291f568 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1694,8 +1694,6 @@ S: Maintained
1694F: drivers/edac/altera_edac. 1694F: drivers/edac/altera_edac.
1695 1695
1696ARM/STI ARCHITECTURE 1696ARM/STI ARCHITECTURE
1697M: Srinivas Kandagatla <srinivas.kandagatla@gmail.com>
1698M: Maxime Coquelin <maxime.coquelin@st.com>
1699M: Patrice Chotard <patrice.chotard@st.com> 1697M: Patrice Chotard <patrice.chotard@st.com>
1700L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) 1698L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
1701L: kernel@stlinux.com 1699L: kernel@stlinux.com
@@ -1728,6 +1726,7 @@ F: drivers/ata/ahci_st.c
1728 1726
1729ARM/STM32 ARCHITECTURE 1727ARM/STM32 ARCHITECTURE
1730M: Maxime Coquelin <mcoquelin.stm32@gmail.com> 1728M: Maxime Coquelin <mcoquelin.stm32@gmail.com>
1729M: Alexandre Torgue <alexandre.torgue@st.com>
1731L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) 1730L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
1732S: Maintained 1731S: Maintained
1733T: git git://git.kernel.org/pub/scm/linux/kernel/git/mcoquelin/stm32.git 1732T: git git://git.kernel.org/pub/scm/linux/kernel/git/mcoquelin/stm32.git
diff --git a/arch/arm/boot/dts/armada-385-linksys.dtsi b/arch/arm/boot/dts/armada-385-linksys.dtsi
index 8450944b28e6..22f7a13e20b4 100644
--- a/arch/arm/boot/dts/armada-385-linksys.dtsi
+++ b/arch/arm/boot/dts/armada-385-linksys.dtsi
@@ -58,8 +58,8 @@
58 soc { 58 soc {
59 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000 59 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
60 MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000 60 MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
61 MBUS_ID(0x09, 0x09) 0 0xf1100000 0x10000 61 MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
62 MBUS_ID(0x09, 0x05) 0 0xf1110000 0x10000>; 62 MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>;
63 63
64 internal-regs { 64 internal-regs {
65 65
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index a03e56fb5dbc..ca58eb279d55 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -65,8 +65,9 @@
65 compatible = "allwinner,simple-framebuffer", 65 compatible = "allwinner,simple-framebuffer",
66 "simple-framebuffer"; 66 "simple-framebuffer";
67 allwinner,pipeline = "de_be0-lcd0-hdmi"; 67 allwinner,pipeline = "de_be0-lcd0-hdmi";
68 clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>, 68 clocks = <&pll3>, <&pll5 1>, <&ahb_gates 36>,
69 <&ahb_gates 44>, <&dram_gates 26>; 69 <&ahb_gates 43>, <&ahb_gates 44>,
70 <&dram_gates 26>;
70 status = "disabled"; 71 status = "disabled";
71 }; 72 };
72 73
@@ -74,8 +75,9 @@
74 compatible = "allwinner,simple-framebuffer", 75 compatible = "allwinner,simple-framebuffer",
75 "simple-framebuffer"; 76 "simple-framebuffer";
76 allwinner,pipeline = "de_fe0-de_be0-lcd0-hdmi"; 77 allwinner,pipeline = "de_fe0-de_be0-lcd0-hdmi";
77 clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>, 78 clocks = <&pll3>, <&pll5 1>, <&ahb_gates 36>,
78 <&ahb_gates 44>, <&ahb_gates 46>, 79 <&ahb_gates 43>, <&ahb_gates 44>,
80 <&ahb_gates 46>,
79 <&dram_gates 25>, <&dram_gates 26>; 81 <&dram_gates 25>, <&dram_gates 26>;
80 status = "disabled"; 82 status = "disabled";
81 }; 83 };
@@ -84,9 +86,9 @@
84 compatible = "allwinner,simple-framebuffer", 86 compatible = "allwinner,simple-framebuffer",
85 "simple-framebuffer"; 87 "simple-framebuffer";
86 allwinner,pipeline = "de_fe0-de_be0-lcd0"; 88 allwinner,pipeline = "de_fe0-de_be0-lcd0";
87 clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>, 89 clocks = <&pll3>, <&pll5 1>, <&ahb_gates 36>,
88 <&ahb_gates 46>, <&dram_gates 25>, 90 <&ahb_gates 44>, <&ahb_gates 46>,
89 <&dram_gates 26>; 91 <&dram_gates 25>, <&dram_gates 26>;
90 status = "disabled"; 92 status = "disabled";
91 }; 93 };
92 94
@@ -94,8 +96,9 @@
94 compatible = "allwinner,simple-framebuffer", 96 compatible = "allwinner,simple-framebuffer",
95 "simple-framebuffer"; 97 "simple-framebuffer";
96 allwinner,pipeline = "de_fe0-de_be0-lcd0-tve0"; 98 allwinner,pipeline = "de_fe0-de_be0-lcd0-tve0";
97 clocks = <&pll5 1>, <&ahb_gates 34>, <&ahb_gates 36>, 99 clocks = <&pll3>, <&pll5 1>, <&ahb_gates 34>,
98 <&ahb_gates 44>, <&ahb_gates 46>, 100 <&ahb_gates 36>, <&ahb_gates 44>,
101 <&ahb_gates 46>,
99 <&dram_gates 5>, <&dram_gates 25>, <&dram_gates 26>; 102 <&dram_gates 5>, <&dram_gates 25>, <&dram_gates 26>;
100 status = "disabled"; 103 status = "disabled";
101 }; 104 };
diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
index bddd0de88af6..367f33012493 100644
--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
@@ -65,8 +65,8 @@
65 compatible = "allwinner,simple-framebuffer", 65 compatible = "allwinner,simple-framebuffer",
66 "simple-framebuffer"; 66 "simple-framebuffer";
67 allwinner,pipeline = "de_be0-lcd0-hdmi"; 67 allwinner,pipeline = "de_be0-lcd0-hdmi";
68 clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>, 68 clocks = <&pll3>, <&pll5 1>, <&ahb_gates 36>,
69 <&ahb_gates 44>; 69 <&ahb_gates 43>, <&ahb_gates 44>;
70 status = "disabled"; 70 status = "disabled";
71 }; 71 };
72 72
@@ -74,7 +74,8 @@
74 compatible = "allwinner,simple-framebuffer", 74 compatible = "allwinner,simple-framebuffer",
75 "simple-framebuffer"; 75 "simple-framebuffer";
76 allwinner,pipeline = "de_be0-lcd0"; 76 allwinner,pipeline = "de_be0-lcd0";
77 clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>; 77 clocks = <&pll3>, <&pll5 1>, <&ahb_gates 36>,
78 <&ahb_gates 44>;
78 status = "disabled"; 79 status = "disabled";
79 }; 80 };
80 81
@@ -82,8 +83,8 @@
82 compatible = "allwinner,simple-framebuffer", 83 compatible = "allwinner,simple-framebuffer",
83 "simple-framebuffer"; 84 "simple-framebuffer";
84 allwinner,pipeline = "de_be0-lcd0-tve0"; 85 allwinner,pipeline = "de_be0-lcd0-tve0";
85 clocks = <&pll5 1>, <&ahb_gates 34>, <&ahb_gates 36>, 86 clocks = <&pll3>, <&pll5 1>, <&ahb_gates 34>,
86 <&ahb_gates 44>; 87 <&ahb_gates 36>, <&ahb_gates 44>;
87 status = "disabled"; 88 status = "disabled";
88 }; 89 };
89 }; 90 };
diff --git a/arch/arm/boot/dts/sun5i-r8-chip.dts b/arch/arm/boot/dts/sun5i-r8-chip.dts
index a8d8b4582397..f694482bdeb6 100644
--- a/arch/arm/boot/dts/sun5i-r8-chip.dts
+++ b/arch/arm/boot/dts/sun5i-r8-chip.dts
@@ -52,7 +52,7 @@
52 52
53/ { 53/ {
54 model = "NextThing C.H.I.P."; 54 model = "NextThing C.H.I.P.";
55 compatible = "nextthing,chip", "allwinner,sun5i-r8"; 55 compatible = "nextthing,chip", "allwinner,sun5i-r8", "allwinner,sun5i-a13";
56 56
57 aliases { 57 aliases {
58 i2c0 = &i2c0; 58 i2c0 = &i2c0;
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index febdf4c72fb0..2c34bbbb9570 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -67,8 +67,9 @@
67 compatible = "allwinner,simple-framebuffer", 67 compatible = "allwinner,simple-framebuffer",
68 "simple-framebuffer"; 68 "simple-framebuffer";
69 allwinner,pipeline = "de_be0-lcd0-hdmi"; 69 allwinner,pipeline = "de_be0-lcd0-hdmi";
70 clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>, 70 clocks = <&pll3>, <&pll5 1>, <&ahb_gates 36>,
71 <&ahb_gates 44>, <&dram_gates 26>; 71 <&ahb_gates 43>, <&ahb_gates 44>,
72 <&dram_gates 26>;
72 status = "disabled"; 73 status = "disabled";
73 }; 74 };
74 75
@@ -76,8 +77,8 @@
76 compatible = "allwinner,simple-framebuffer", 77 compatible = "allwinner,simple-framebuffer",
77 "simple-framebuffer"; 78 "simple-framebuffer";
78 allwinner,pipeline = "de_be0-lcd0"; 79 allwinner,pipeline = "de_be0-lcd0";
79 clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>, 80 clocks = <&pll3>, <&pll5 1>, <&ahb_gates 36>,
80 <&dram_gates 26>; 81 <&ahb_gates 44>, <&dram_gates 26>;
81 status = "disabled"; 82 status = "disabled";
82 }; 83 };
83 84
@@ -85,7 +86,7 @@
85 compatible = "allwinner,simple-framebuffer", 86 compatible = "allwinner,simple-framebuffer",
86 "simple-framebuffer"; 87 "simple-framebuffer";
87 allwinner,pipeline = "de_be0-lcd0-tve0"; 88 allwinner,pipeline = "de_be0-lcd0-tve0";
88 clocks = <&pll5 1>, 89 clocks = <&pll3>, <&pll5 1>,
89 <&ahb_gates 34>, <&ahb_gates 36>, <&ahb_gates 44>, 90 <&ahb_gates 34>, <&ahb_gates 36>, <&ahb_gates 44>,
90 <&dram_gates 5>, <&dram_gates 26>; 91 <&dram_gates 5>, <&dram_gates 26>;
91 status = "disabled"; 92 status = "disabled";
@@ -231,6 +232,7 @@
231 pll3x2: pll3x2_clk { 232 pll3x2: pll3x2_clk {
232 #clock-cells = <0>; 233 #clock-cells = <0>;
233 compatible = "fixed-factor-clock"; 234 compatible = "fixed-factor-clock";
235 clocks = <&pll3>;
234 clock-div = <1>; 236 clock-div = <1>;
235 clock-mult = <2>; 237 clock-mult = <2>;
236 clock-output-names = "pll3-2x"; 238 clock-output-names = "pll3-2x";
@@ -272,6 +274,7 @@
272 pll7x2: pll7x2_clk { 274 pll7x2: pll7x2_clk {
273 #clock-cells = <0>; 275 #clock-cells = <0>;
274 compatible = "fixed-factor-clock"; 276 compatible = "fixed-factor-clock";
277 clocks = <&pll7>;
275 clock-div = <1>; 278 clock-div = <1>;
276 clock-mult = <2>; 279 clock-mult = <2>;
277 clock-output-names = "pll7-2x"; 280 clock-output-names = "pll7-2x";
diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts
index 1eca3b28ac64..b6da15d823a6 100644
--- a/arch/arm/boot/dts/tegra30-beaver.dts
+++ b/arch/arm/boot/dts/tegra30-beaver.dts
@@ -1843,7 +1843,7 @@
1843 1843
1844 ldo5_reg: ldo5 { 1844 ldo5_reg: ldo5 {
1845 regulator-name = "vddio_sdmmc,avdd_vdac"; 1845 regulator-name = "vddio_sdmmc,avdd_vdac";
1846 regulator-min-microvolt = <3300000>; 1846 regulator-min-microvolt = <1800000>;
1847 regulator-max-microvolt = <3300000>; 1847 regulator-max-microvolt = <3300000>;
1848 regulator-always-on; 1848 regulator-always-on;
1849 }; 1849 };
@@ -1914,6 +1914,7 @@
1914 1914
1915 sdhci@78000000 { 1915 sdhci@78000000 {
1916 status = "okay"; 1916 status = "okay";
1917 vqmmc-supply = <&ldo5_reg>;
1917 cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; 1918 cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
1918 wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>; 1919 wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>;
1919 power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>; 1920 power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>;
diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile
index ecf9e0c3b107..e53c6cfcab51 100644
--- a/arch/arm/mach-mvebu/Makefile
+++ b/arch/arm/mach-mvebu/Makefile
@@ -7,9 +7,15 @@ CFLAGS_pmsu.o := -march=armv7-a
7obj-$(CONFIG_MACH_MVEBU_ANY) += system-controller.o mvebu-soc-id.o 7obj-$(CONFIG_MACH_MVEBU_ANY) += system-controller.o mvebu-soc-id.o
8 8
9ifeq ($(CONFIG_MACH_MVEBU_V7),y) 9ifeq ($(CONFIG_MACH_MVEBU_V7),y)
10obj-y += cpu-reset.o board-v7.o coherency.o coherency_ll.o pmsu.o pmsu_ll.o pm.o pm-board.o 10obj-y += cpu-reset.o board-v7.o coherency.o coherency_ll.o pmsu.o pmsu_ll.o
11
12obj-$(CONFIG_PM) += pm.o pm-board.o
11obj-$(CONFIG_SMP) += platsmp.o headsmp.o platsmp-a9.o headsmp-a9.o 13obj-$(CONFIG_SMP) += platsmp.o headsmp.o platsmp-a9.o headsmp-a9.o
12endif 14endif
13 15
14obj-$(CONFIG_MACH_DOVE) += dove.o 16obj-$(CONFIG_MACH_DOVE) += dove.o
15obj-$(CONFIG_MACH_KIRKWOOD) += kirkwood.o kirkwood-pm.o 17
18ifeq ($(CONFIG_MACH_KIRKWOOD),y)
19obj-y += kirkwood.o
20obj-$(CONFIG_PM) += kirkwood-pm.o
21endif
diff --git a/arch/arm/mach-mvebu/coherency.c b/arch/arm/mach-mvebu/coherency.c
index 7e989d61159c..e80f0dde2189 100644
--- a/arch/arm/mach-mvebu/coherency.c
+++ b/arch/arm/mach-mvebu/coherency.c
@@ -162,22 +162,16 @@ exit:
162} 162}
163 163
164/* 164/*
165 * This ioremap hook is used on Armada 375/38x to ensure that PCIe 165 * This ioremap hook is used on Armada 375/38x to ensure that all MMIO
166 * memory areas are mapped as MT_UNCACHED instead of MT_DEVICE. This 166 * areas are mapped as MT_UNCACHED instead of MT_DEVICE. This is
167 * is needed as a workaround for a deadlock issue between the PCIe 167 * needed for the HW I/O coherency mechanism to work properly without
168 * interface and the cache controller. 168 * deadlock.
169 */ 169 */
170static void __iomem * 170static void __iomem *
171armada_pcie_wa_ioremap_caller(phys_addr_t phys_addr, size_t size, 171armada_wa_ioremap_caller(phys_addr_t phys_addr, size_t size,
172 unsigned int mtype, void *caller) 172 unsigned int mtype, void *caller)
173{ 173{
174 struct resource pcie_mem; 174 mtype = MT_UNCACHED;
175
176 mvebu_mbus_get_pcie_mem_aperture(&pcie_mem);
177
178 if (pcie_mem.start <= phys_addr && (phys_addr + size) <= pcie_mem.end)
179 mtype = MT_UNCACHED;
180
181 return __arm_ioremap_caller(phys_addr, size, mtype, caller); 175 return __arm_ioremap_caller(phys_addr, size, mtype, caller);
182} 176}
183 177
@@ -186,7 +180,8 @@ static void __init armada_375_380_coherency_init(struct device_node *np)
186 struct device_node *cache_dn; 180 struct device_node *cache_dn;
187 181
188 coherency_cpu_base = of_iomap(np, 0); 182 coherency_cpu_base = of_iomap(np, 0);
189 arch_ioremap_caller = armada_pcie_wa_ioremap_caller; 183 arch_ioremap_caller = armada_wa_ioremap_caller;
184 pci_ioremap_set_mem_type(MT_UNCACHED);
190 185
191 /* 186 /*
192 * We should switch the PL310 to I/O coherency mode only if 187 * We should switch the PL310 to I/O coherency mode only if