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authorDave Airlie <airlied@redhat.com>2018-03-21 00:07:03 -0400
committerDave Airlie <airlied@redhat.com>2018-03-21 00:07:03 -0400
commit78230c46ec0a91dd4256c9e54934b3c7095a7ee3 (patch)
treef812daca099880181fb666a3d98298bf5f249d57
parentb65bd40311565a58b12f400e95e8aa0a1e3a8878 (diff)
parent037f03155b7d87e85168b4296516bfda5c9f6380 (diff)
Merge tag 'omapdrm-4.17' of git://git.kernel.org/pub/scm/linux/kernel/git/tomba/linux into drm-next
omapdrm patches for v4.17 * Fix sparse warnings from omapdrm * HPD support for DVI connector * Big cleanup to remove static variables * tag 'omapdrm-4.17' of git://git.kernel.org/pub/scm/linux/kernel/git/tomba/linux: (69 commits) drm/omap: fix compile error when DPI is disabled drm/omap: fix compile error when debugfs is disabled drm: omapdrm: displays: panel-dsi-cm: Fix field access before set drm/omap: cleanup color space conversion drm/omap: Allow HDMI audio setup even if we do not have video configured drm/omap: fix maximum sizes drm/omap: add writeback funcs to dispc_ops drm/omap: fix scaling limits for WB drm/omap: fix WB height with interlace drm/omap: fix WBDELAYCOUNT with interlace drm/omap: fix WBDELAYCOUNT for HDMI drm/omap: set WB channel-in in wb_setup() drm/omap: Add pclk setting case when channel is DSS_WB drm/omap: dispc: disp_wb_setup to check return code drm/omap: remove leftover enums dt-bindings: display: add HPD gpio to DVI connector drm/omap: add HPD support to connector-dvi drm/omap: Init fbdev emulation only when we have displays drm/omap: cleanup fbdev init/free drm/omap: fix omap_fbdev_free() when omap_fbdev_create() wasn't called ...
Diffstat
-rw-r--r--Documentation/devicetree/bindings/display/connector/dvi-connector.txt1
-rw-r--r--drivers/gpu/drm/omapdrm/displays/connector-analog-tv.c50
-rw-r--r--drivers/gpu/drm/omapdrm/displays/connector-dvi.c146
-rw-r--r--drivers/gpu/drm/omapdrm/displays/connector-hdmi.c40
-rw-r--r--drivers/gpu/drm/omapdrm/displays/encoder-opa362.c40
-rw-r--r--drivers/gpu/drm/omapdrm/displays/encoder-tfp410.c39
-rw-r--r--drivers/gpu/drm/omapdrm/displays/encoder-tpd12s015.c69
-rw-r--r--drivers/gpu/drm/omapdrm/displays/panel-dpi.c37
-rw-r--r--drivers/gpu/drm/omapdrm/displays/panel-dsi-cm.c44
-rw-r--r--drivers/gpu/drm/omapdrm/displays/panel-lgphilips-lb035q02.c38
-rw-r--r--drivers/gpu/drm/omapdrm/displays/panel-nec-nl8048hl11.c42
-rw-r--r--drivers/gpu/drm/omapdrm/displays/panel-sharp-ls037v7dw01.c38
-rw-r--r--drivers/gpu/drm/omapdrm/displays/panel-sony-acx565akm.c41
-rw-r--r--drivers/gpu/drm/omapdrm/displays/panel-tpo-td028ttec1.c49
-rw-r--r--drivers/gpu/drm/omapdrm/displays/panel-tpo-td043mtea1.c32
-rw-r--r--drivers/gpu/drm/omapdrm/dss/base.c27
-rw-r--r--drivers/gpu/drm/omapdrm/dss/dispc.c2346
-rw-r--r--drivers/gpu/drm/omapdrm/dss/display.c5
-rw-r--r--drivers/gpu/drm/omapdrm/dss/dpi.c91
-rw-r--r--drivers/gpu/drm/omapdrm/dss/dsi.c1553
-rw-r--r--drivers/gpu/drm/omapdrm/dss/dss-of.c2
-rw-r--r--drivers/gpu/drm/omapdrm/dss/dss.c823
-rw-r--r--drivers/gpu/drm/omapdrm/dss/dss.h245
-rw-r--r--drivers/gpu/drm/omapdrm/dss/hdmi.h11
-rw-r--r--drivers/gpu/drm/omapdrm/dss/hdmi4.c406
-rw-r--r--drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c4
-rw-r--r--drivers/gpu/drm/omapdrm/dss/hdmi4_core.h4
-rw-r--r--drivers/gpu/drm/omapdrm/dss/hdmi5.c418
-rw-r--r--drivers/gpu/drm/omapdrm/dss/hdmi5_core.c24
-rw-r--r--drivers/gpu/drm/omapdrm/dss/hdmi_phy.c2
-rw-r--r--drivers/gpu/drm/omapdrm/dss/hdmi_pll.c15
-rw-r--r--drivers/gpu/drm/omapdrm/dss/hdmi_wp.c2
-rw-r--r--drivers/gpu/drm/omapdrm/dss/omapdss.h213
-rw-r--r--drivers/gpu/drm/omapdrm/dss/output.c53
-rw-r--r--drivers/gpu/drm/omapdrm/dss/pll.c44
-rw-r--r--drivers/gpu/drm/omapdrm/dss/sdi.c162
-rw-r--r--drivers/gpu/drm/omapdrm/dss/venc.c453
-rw-r--r--drivers/gpu/drm/omapdrm/dss/video-pll.c19
-rw-r--r--drivers/gpu/drm/omapdrm/omap_crtc.c74
-rw-r--r--drivers/gpu/drm/omapdrm/omap_crtc.h4
-rw-r--r--drivers/gpu/drm/omapdrm/omap_dmm_priv.h10
-rw-r--r--drivers/gpu/drm/omapdrm/omap_dmm_tiler.c46
-rw-r--r--drivers/gpu/drm/omapdrm/omap_dmm_tiler.h22
-rw-r--r--drivers/gpu/drm/omapdrm/omap_drv.c122
-rw-r--r--drivers/gpu/drm/omapdrm/omap_drv.h8
-rw-r--r--drivers/gpu/drm/omapdrm/omap_fb.c18
-rw-r--r--drivers/gpu/drm/omapdrm/omap_fbdev.c38
-rw-r--r--drivers/gpu/drm/omapdrm/omap_fbdev.h9
-rw-r--r--drivers/gpu/drm/omapdrm/omap_gem.c41
-rw-r--r--drivers/gpu/drm/omapdrm/omap_gem.h16
-rw-r--r--drivers/gpu/drm/omapdrm/omap_irq.c38
-rw-r--r--drivers/gpu/drm/omapdrm/omap_irq.h2
-rw-r--r--drivers/gpu/drm/omapdrm/omap_plane.c16
-rw-r--r--drivers/gpu/drm/omapdrm/tcm-sita.c12
-rw-r--r--drivers/gpu/drm/omapdrm/tcm.h4
55 files changed, 4277 insertions, 3831 deletions
diff --git a/Documentation/devicetree/bindings/display/connector/dvi-connector.txt b/Documentation/devicetree/bindings/display/connector/dvi-connector.txt
index fc53f7c60bc6..207e42e9eba0 100644
--- a/Documentation/devicetree/bindings/display/connector/dvi-connector.txt
+++ b/Documentation/devicetree/bindings/display/connector/dvi-connector.txt
@@ -10,6 +10,7 @@ Optional properties:
10- analog: the connector has DVI analog pins 10- analog: the connector has DVI analog pins
11- digital: the connector has DVI digital pins 11- digital: the connector has DVI digital pins
12- dual-link: the connector has pins for DVI dual-link 12- dual-link: the connector has pins for DVI dual-link
13- hpd-gpios: HPD GPIO number
13 14
14Required nodes: 15Required nodes:
15- Video port for DVI input 16- Video port for DVI input
diff --git a/drivers/gpu/drm/omapdrm/displays/connector-analog-tv.c b/drivers/gpu/drm/omapdrm/displays/connector-analog-tv.c
index 95ea6abae914..9eabd7201a12 100644
--- a/drivers/gpu/drm/omapdrm/displays/connector-analog-tv.c
+++ b/drivers/gpu/drm/omapdrm/displays/connector-analog-tv.c
@@ -40,14 +40,12 @@ static const struct videomode tvc_pal_vm = {
40 DISPLAY_FLAGS_VSYNC_LOW, 40 DISPLAY_FLAGS_VSYNC_LOW,
41}; 41};
42 42
43static const struct of_device_id tvc_of_match[];
44
45#define to_panel_data(x) container_of(x, struct panel_drv_data, dssdev) 43#define to_panel_data(x) container_of(x, struct panel_drv_data, dssdev)
46 44
47static int tvc_connect(struct omap_dss_device *dssdev) 45static int tvc_connect(struct omap_dss_device *dssdev)
48{ 46{
49 struct panel_drv_data *ddata = to_panel_data(dssdev); 47 struct panel_drv_data *ddata = to_panel_data(dssdev);
50 struct omap_dss_device *in = ddata->in; 48 struct omap_dss_device *in;
51 int r; 49 int r;
52 50
53 dev_dbg(ddata->dev, "connect\n"); 51 dev_dbg(ddata->dev, "connect\n");
@@ -55,10 +53,19 @@ static int tvc_connect(struct omap_dss_device *dssdev)
55 if (omapdss_device_is_connected(dssdev)) 53 if (omapdss_device_is_connected(dssdev))
56 return 0; 54 return 0;
57 55
56 in = omapdss_of_find_source_for_first_ep(ddata->dev->of_node);
57 if (IS_ERR(in)) {
58 dev_err(ddata->dev, "failed to find video source\n");
59 return PTR_ERR(in);
60 }
61
58 r = in->ops.atv->connect(in, dssdev); 62 r = in->ops.atv->connect(in, dssdev);
59 if (r) 63 if (r) {
64 omap_dss_put_device(in);
60 return r; 65 return r;
66 }
61 67
68 ddata->in = in;
62 return 0; 69 return 0;
63} 70}
64 71
@@ -73,6 +80,9 @@ static void tvc_disconnect(struct omap_dss_device *dssdev)
73 return; 80 return;
74 81
75 in->ops.atv->disconnect(in, dssdev); 82 in->ops.atv->disconnect(in, dssdev);
83
84 omap_dss_put_device(in);
85 ddata->in = NULL;
76} 86}
77 87
78static int tvc_enable(struct omap_dss_device *dssdev) 88static int tvc_enable(struct omap_dss_device *dssdev)
@@ -175,32 +185,12 @@ static struct omap_dss_driver tvc_driver = {
175 .set_wss = tvc_set_wss, 185 .set_wss = tvc_set_wss,
176}; 186};
177 187
178static int tvc_probe_of(struct platform_device *pdev)
179{
180 struct panel_drv_data *ddata = platform_get_drvdata(pdev);
181 struct device_node *node = pdev->dev.of_node;
182 struct omap_dss_device *in;
183
184 in = omapdss_of_find_source_for_first_ep(node);
185 if (IS_ERR(in)) {
186 dev_err(&pdev->dev, "failed to find video source\n");
187 return PTR_ERR(in);
188 }
189
190 ddata->in = in;
191
192 return 0;
193}
194
195static int tvc_probe(struct platform_device *pdev) 188static int tvc_probe(struct platform_device *pdev)
196{ 189{
197 struct panel_drv_data *ddata; 190 struct panel_drv_data *ddata;
198 struct omap_dss_device *dssdev; 191 struct omap_dss_device *dssdev;
199 int r; 192 int r;
200 193
201 if (!pdev->dev.of_node)
202 return -ENODEV;
203
204 ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL); 194 ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL);
205 if (!ddata) 195 if (!ddata)
206 return -ENOMEM; 196 return -ENOMEM;
@@ -208,10 +198,6 @@ static int tvc_probe(struct platform_device *pdev)
208 platform_set_drvdata(pdev, ddata); 198 platform_set_drvdata(pdev, ddata);
209 ddata->dev = &pdev->dev; 199 ddata->dev = &pdev->dev;
210 200
211 r = tvc_probe_of(pdev);
212 if (r)
213 return r;
214
215 ddata->vm = tvc_pal_vm; 201 ddata->vm = tvc_pal_vm;
216 202
217 dssdev = &ddata->dssdev; 203 dssdev = &ddata->dssdev;
@@ -224,28 +210,22 @@ static int tvc_probe(struct platform_device *pdev)
224 r = omapdss_register_display(dssdev); 210 r = omapdss_register_display(dssdev);
225 if (r) { 211 if (r) {
226 dev_err(&pdev->dev, "Failed to register panel\n"); 212 dev_err(&pdev->dev, "Failed to register panel\n");
227 goto err_reg; 213 return r;
228 } 214 }
229 215
230 return 0; 216 return 0;
231err_reg:
232 omap_dss_put_device(ddata->in);
233 return r;
234} 217}
235 218
236static int __exit tvc_remove(struct platform_device *pdev) 219static int __exit tvc_remove(struct platform_device *pdev)
237{ 220{
238 struct panel_drv_data *ddata = platform_get_drvdata(pdev); 221 struct panel_drv_data *ddata = platform_get_drvdata(pdev);
239 struct omap_dss_device *dssdev = &ddata->dssdev; 222 struct omap_dss_device *dssdev = &ddata->dssdev;
240 struct omap_dss_device *in = ddata->in;
241 223
242 omapdss_unregister_display(&ddata->dssdev); 224 omapdss_unregister_display(&ddata->dssdev);
243 225
244 tvc_disable(dssdev); 226 tvc_disable(dssdev);
245 tvc_disconnect(dssdev); 227 tvc_disconnect(dssdev);
246 228
247 omap_dss_put_device(in);
248
249 return 0; 229 return 0;
250} 230}
251 231
diff --git a/drivers/gpu/drm/omapdrm/displays/connector-dvi.c b/drivers/gpu/drm/omapdrm/displays/connector-dvi.c
index 10b4b97d3595..6d8cbd9e2110 100644
--- a/drivers/gpu/drm/omapdrm/displays/connector-dvi.c
+++ b/drivers/gpu/drm/omapdrm/displays/connector-dvi.c
@@ -9,6 +9,7 @@
9 * the Free Software Foundation. 9 * the Free Software Foundation.
10 */ 10 */
11 11
12#include <linux/gpio/consumer.h>
12#include <linux/i2c.h> 13#include <linux/i2c.h>
13#include <linux/module.h> 14#include <linux/module.h>
14#include <linux/platform_device.h> 15#include <linux/platform_device.h>
@@ -44,6 +45,14 @@ struct panel_drv_data {
44 struct videomode vm; 45 struct videomode vm;
45 46
46 struct i2c_adapter *i2c_adapter; 47 struct i2c_adapter *i2c_adapter;
48
49 struct gpio_desc *hpd_gpio;
50
51 void (*hpd_cb)(void *cb_data, enum drm_connector_status status);
52 void *hpd_cb_data;
53 bool hpd_enabled;
54 /* mutex for hpd fields above */
55 struct mutex hpd_lock;
47}; 56};
48 57
49#define to_panel_data(x) container_of(x, struct panel_drv_data, dssdev) 58#define to_panel_data(x) container_of(x, struct panel_drv_data, dssdev)
@@ -51,16 +60,25 @@ struct panel_drv_data {
51static int dvic_connect(struct omap_dss_device *dssdev) 60static int dvic_connect(struct omap_dss_device *dssdev)
52{ 61{
53 struct panel_drv_data *ddata = to_panel_data(dssdev); 62 struct panel_drv_data *ddata = to_panel_data(dssdev);
54 struct omap_dss_device *in = ddata->in; 63 struct omap_dss_device *in;
55 int r; 64 int r;
56 65
57 if (omapdss_device_is_connected(dssdev)) 66 if (omapdss_device_is_connected(dssdev))
58 return 0; 67 return 0;
59 68
69 in = omapdss_of_find_source_for_first_ep(dssdev->dev->of_node);
70 if (IS_ERR(in)) {
71 dev_err(dssdev->dev, "failed to find video source\n");
72 return PTR_ERR(in);
73 }
74
60 r = in->ops.dvi->connect(in, dssdev); 75 r = in->ops.dvi->connect(in, dssdev);
61 if (r) 76 if (r) {
77 omap_dss_put_device(in);
62 return r; 78 return r;
79 }
63 80
81 ddata->in = in;
64 return 0; 82 return 0;
65} 83}
66 84
@@ -73,6 +91,9 @@ static void dvic_disconnect(struct omap_dss_device *dssdev)
73 return; 91 return;
74 92
75 in->ops.dvi->disconnect(in, dssdev); 93 in->ops.dvi->disconnect(in, dssdev);
94
95 omap_dss_put_device(in);
96 ddata->in = NULL;
76} 97}
77 98
78static int dvic_enable(struct omap_dss_device *dssdev) 99static int dvic_enable(struct omap_dss_device *dssdev)
@@ -177,6 +198,9 @@ static int dvic_read_edid(struct omap_dss_device *dssdev,
177 struct panel_drv_data *ddata = to_panel_data(dssdev); 198 struct panel_drv_data *ddata = to_panel_data(dssdev);
178 int r, l, bytes_read; 199 int r, l, bytes_read;
179 200
201 if (ddata->hpd_gpio && !gpiod_get_value_cansleep(ddata->hpd_gpio))
202 return -ENODEV;
203
180 if (!ddata->i2c_adapter) 204 if (!ddata->i2c_adapter)
181 return -ENODEV; 205 return -ENODEV;
182 206
@@ -208,6 +232,9 @@ static bool dvic_detect(struct omap_dss_device *dssdev)
208 unsigned char out; 232 unsigned char out;
209 int r; 233 int r;
210 234
235 if (ddata->hpd_gpio)
236 return gpiod_get_value_cansleep(ddata->hpd_gpio);
237
211 if (!ddata->i2c_adapter) 238 if (!ddata->i2c_adapter)
212 return true; 239 return true;
213 240
@@ -216,6 +243,60 @@ static bool dvic_detect(struct omap_dss_device *dssdev)
216 return r == 0; 243 return r == 0;
217} 244}
218 245
246static int dvic_register_hpd_cb(struct omap_dss_device *dssdev,
247 void (*cb)(void *cb_data,
248 enum drm_connector_status status),
249 void *cb_data)
250{
251 struct panel_drv_data *ddata = to_panel_data(dssdev);
252
253 if (!ddata->hpd_gpio)
254 return -ENOTSUPP;
255
256 mutex_lock(&ddata->hpd_lock);
257 ddata->hpd_cb = cb;
258 ddata->hpd_cb_data = cb_data;
259 mutex_unlock(&ddata->hpd_lock);
260 return 0;
261}
262
263static void dvic_unregister_hpd_cb(struct omap_dss_device *dssdev)
264{
265 struct panel_drv_data *ddata = to_panel_data(dssdev);
266
267 if (!ddata->hpd_gpio)
268 return;
269
270 mutex_lock(&ddata->hpd_lock);
271 ddata->hpd_cb = NULL;
272 ddata->hpd_cb_data = NULL;
273 mutex_unlock(&ddata->hpd_lock);
274}
275
276static void dvic_enable_hpd(struct omap_dss_device *dssdev)
277{
278 struct panel_drv_data *ddata = to_panel_data(dssdev);
279
280 if (!ddata->hpd_gpio)
281 return;
282
283 mutex_lock(&ddata->hpd_lock);
284 ddata->hpd_enabled = true;
285 mutex_unlock(&ddata->hpd_lock);
286}
287
288static void dvic_disable_hpd(struct omap_dss_device *dssdev)
289{
290 struct panel_drv_data *ddata = to_panel_data(dssdev);
291
292 if (!ddata->hpd_gpio)
293 return;
294
295 mutex_lock(&ddata->hpd_lock);
296 ddata->hpd_enabled = false;
297 mutex_unlock(&ddata->hpd_lock);
298}
299
219static struct omap_dss_driver dvic_driver = { 300static struct omap_dss_driver dvic_driver = {
220 .connect = dvic_connect, 301 .connect = dvic_connect,
221 .disconnect = dvic_disconnect, 302 .disconnect = dvic_disconnect,
@@ -229,23 +310,60 @@ static struct omap_dss_driver dvic_driver = {
229 310
230 .read_edid = dvic_read_edid, 311 .read_edid = dvic_read_edid,
231 .detect = dvic_detect, 312 .detect = dvic_detect,
313
314 .register_hpd_cb = dvic_register_hpd_cb,
315 .unregister_hpd_cb = dvic_unregister_hpd_cb,
316 .enable_hpd = dvic_enable_hpd,
317 .disable_hpd = dvic_disable_hpd,
232}; 318};
233 319
320static irqreturn_t dvic_hpd_isr(int irq, void *data)
321{
322 struct panel_drv_data *ddata = data;
323
324 mutex_lock(&ddata->hpd_lock);
325 if (ddata->hpd_enabled && ddata->hpd_cb) {
326 enum drm_connector_status status;
327
328 if (dvic_detect(&ddata->dssdev))
329 status = connector_status_connected;
330 else
331 status = connector_status_disconnected;
332
333 ddata->hpd_cb(ddata->hpd_cb_data, status);
334 }
335 mutex_unlock(&ddata->hpd_lock);
336
337 return IRQ_HANDLED;
338}
339
234static int dvic_probe_of(struct platform_device *pdev) 340static int dvic_probe_of(struct platform_device *pdev)
235{ 341{
236 struct panel_drv_data *ddata = platform_get_drvdata(pdev); 342 struct panel_drv_data *ddata = platform_get_drvdata(pdev);
237 struct device_node *node = pdev->dev.of_node; 343 struct device_node *node = pdev->dev.of_node;
238 struct omap_dss_device *in;
239 struct device_node *adapter_node; 344 struct device_node *adapter_node;
240 struct i2c_adapter *adapter; 345 struct i2c_adapter *adapter;
346 struct gpio_desc *gpio;
347 int r;
241 348
242 in = omapdss_of_find_source_for_first_ep(node); 349 gpio = devm_gpiod_get_optional(&pdev->dev, "hpd", GPIOD_IN);
243 if (IS_ERR(in)) { 350 if (IS_ERR(gpio)) {
244 dev_err(&pdev->dev, "failed to find video source\n"); 351 dev_err(&pdev->dev, "failed to parse HPD gpio\n");
245 return PTR_ERR(in); 352 return PTR_ERR(gpio);
246 } 353 }
247 354
248 ddata->in = in; 355 ddata->hpd_gpio = gpio;
356
357 mutex_init(&ddata->hpd_lock);
358
359 if (ddata->hpd_gpio) {
360 r = devm_request_threaded_irq(&pdev->dev,
361 gpiod_to_irq(ddata->hpd_gpio), NULL, dvic_hpd_isr,
362 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
363 "DVI HPD", ddata);
364 if (r)
365 return r;
366 }
249 367
250 adapter_node = of_parse_phandle(node, "ddc-i2c-bus", 0); 368 adapter_node = of_parse_phandle(node, "ddc-i2c-bus", 0);
251 if (adapter_node) { 369 if (adapter_node) {
@@ -253,7 +371,6 @@ static int dvic_probe_of(struct platform_device *pdev)
253 of_node_put(adapter_node); 371 of_node_put(adapter_node);
254 if (adapter == NULL) { 372 if (adapter == NULL) {
255 dev_err(&pdev->dev, "failed to parse ddc-i2c-bus\n"); 373 dev_err(&pdev->dev, "failed to parse ddc-i2c-bus\n");
256 omap_dss_put_device(ddata->in);
257 return -EPROBE_DEFER; 374 return -EPROBE_DEFER;
258 } 375 }
259 376
@@ -275,9 +392,6 @@ static int dvic_probe(struct platform_device *pdev)
275 392
276 platform_set_drvdata(pdev, ddata); 393 platform_set_drvdata(pdev, ddata);
277 394
278 if (!pdev->dev.of_node)
279 return -ENODEV;
280
281 r = dvic_probe_of(pdev); 395 r = dvic_probe_of(pdev);
282 if (r) 396 if (r)
283 return r; 397 return r;
@@ -300,9 +414,8 @@ static int dvic_probe(struct platform_device *pdev)
300 return 0; 414 return 0;
301 415
302err_reg: 416err_reg:
303 omap_dss_put_device(ddata->in);
304
305 i2c_put_adapter(ddata->i2c_adapter); 417 i2c_put_adapter(ddata->i2c_adapter);
418 mutex_destroy(&ddata->hpd_lock);
306 419
307 return r; 420 return r;
308} 421}
@@ -311,17 +424,16 @@ static int __exit dvic_remove(struct platform_device *pdev)
311{ 424{
312 struct panel_drv_data *ddata = platform_get_drvdata(pdev); 425 struct panel_drv_data *ddata = platform_get_drvdata(pdev);
313 struct omap_dss_device *dssdev = &ddata->dssdev; 426 struct omap_dss_device *dssdev = &ddata->dssdev;
314 struct omap_dss_device *in = ddata->in;
315 427
316 omapdss_unregister_display(&ddata->dssdev); 428 omapdss_unregister_display(&ddata->dssdev);
317 429
318 dvic_disable(dssdev); 430 dvic_disable(dssdev);
319 dvic_disconnect(dssdev); 431 dvic_disconnect(dssdev);
320 432
321 omap_dss_put_device(in);
322
323 i2c_put_adapter(ddata->i2c_adapter); 433 i2c_put_adapter(ddata->i2c_adapter);
324 434
435 mutex_destroy(&ddata->hpd_lock);
436
325 return 0; 437 return 0;
326} 438}
327 439
diff --git a/drivers/gpu/drm/omapdrm/displays/connector-hdmi.c b/drivers/gpu/drm/omapdrm/displays/connector-hdmi.c
index 2867476419dc..ca30ed9da7eb 100644
--- a/drivers/gpu/drm/omapdrm/displays/connector-hdmi.c
+++ b/drivers/gpu/drm/omapdrm/displays/connector-hdmi.c
@@ -55,7 +55,7 @@ struct panel_drv_data {
55static int hdmic_connect(struct omap_dss_device *dssdev) 55static int hdmic_connect(struct omap_dss_device *dssdev)
56{ 56{
57 struct panel_drv_data *ddata = to_panel_data(dssdev); 57 struct panel_drv_data *ddata = to_panel_data(dssdev);
58 struct omap_dss_device *in = ddata->in; 58 struct omap_dss_device *in;
59 int r; 59 int r;
60 60
61 dev_dbg(ddata->dev, "connect\n"); 61 dev_dbg(ddata->dev, "connect\n");
@@ -63,10 +63,19 @@ static int hdmic_connect(struct omap_dss_device *dssdev)
63 if (omapdss_device_is_connected(dssdev)) 63 if (omapdss_device_is_connected(dssdev))
64 return 0; 64 return 0;
65 65
66 in = omapdss_of_find_source_for_first_ep(ddata->dev->of_node);
67 if (IS_ERR(in)) {
68 dev_err(ddata->dev, "failed to find video source\n");
69 return PTR_ERR(in);
70 }
71
66 r = in->ops.hdmi->connect(in, dssdev); 72 r = in->ops.hdmi->connect(in, dssdev);
67 if (r) 73 if (r) {
74 omap_dss_put_device(in);
68 return r; 75 return r;
76 }
69 77
78 ddata->in = in;
70 return 0; 79 return 0;
71} 80}
72 81
@@ -81,6 +90,9 @@ static void hdmic_disconnect(struct omap_dss_device *dssdev)
81 return; 90 return;
82 91
83 in->ops.hdmi->disconnect(in, dssdev); 92 in->ops.hdmi->disconnect(in, dssdev);
93
94 omap_dss_put_device(in);
95 ddata->in = NULL;
84} 96}
85 97
86static int hdmic_enable(struct omap_dss_device *dssdev) 98static int hdmic_enable(struct omap_dss_device *dssdev)
@@ -302,7 +314,6 @@ static int hdmic_probe_of(struct platform_device *pdev)
302{ 314{
303 struct panel_drv_data *ddata = platform_get_drvdata(pdev); 315 struct panel_drv_data *ddata = platform_get_drvdata(pdev);
304 struct device_node *node = pdev->dev.of_node; 316 struct device_node *node = pdev->dev.of_node;
305 struct omap_dss_device *in;
306 int gpio; 317 int gpio;
307 318
308 /* HPD GPIO */ 319 /* HPD GPIO */
@@ -312,14 +323,6 @@ static int hdmic_probe_of(struct platform_device *pdev)
312 else 323 else
313 ddata->hpd_gpio = -ENODEV; 324 ddata->hpd_gpio = -ENODEV;
314 325
315 in = omapdss_of_find_source_for_first_ep(node);
316 if (IS_ERR(in)) {
317 dev_err(&pdev->dev, "failed to find video source\n");
318 return PTR_ERR(in);
319 }
320
321 ddata->in = in;
322
323 return 0; 326 return 0;
324} 327}
325 328
@@ -336,9 +339,6 @@ static int hdmic_probe(struct platform_device *pdev)
336 platform_set_drvdata(pdev, ddata); 339 platform_set_drvdata(pdev, ddata);
337 ddata->dev = &pdev->dev; 340 ddata->dev = &pdev->dev;
338 341
339 if (!pdev->dev.of_node)
340 return -ENODEV;
341
342 r = hdmic_probe_of(pdev); 342 r = hdmic_probe_of(pdev);
343 if (r) 343 if (r)
344 return r; 344 return r;
@@ -349,7 +349,7 @@ static int hdmic_probe(struct platform_device *pdev)
349 r = devm_gpio_request_one(&pdev->dev, ddata->hpd_gpio, 349 r = devm_gpio_request_one(&pdev->dev, ddata->hpd_gpio,
350 GPIOF_DIR_IN, "hdmi_hpd"); 350 GPIOF_DIR_IN, "hdmi_hpd");
351 if (r) 351 if (r)
352 goto err_reg; 352 return r;
353 353
354 r = devm_request_threaded_irq(&pdev->dev, 354 r = devm_request_threaded_irq(&pdev->dev,
355 gpio_to_irq(ddata->hpd_gpio), 355 gpio_to_irq(ddata->hpd_gpio),
@@ -358,7 +358,7 @@ static int hdmic_probe(struct platform_device *pdev)
358 IRQF_ONESHOT, 358 IRQF_ONESHOT,
359 "hdmic hpd", ddata); 359 "hdmic hpd", ddata);
360 if (r) 360 if (r)
361 goto err_reg; 361 return r;
362 } 362 }
363 363
364 ddata->vm = hdmic_default_vm; 364 ddata->vm = hdmic_default_vm;
@@ -373,28 +373,22 @@ static int hdmic_probe(struct platform_device *pdev)
373 r = omapdss_register_display(dssdev); 373 r = omapdss_register_display(dssdev);
374 if (r) { 374 if (r) {
375 dev_err(&pdev->dev, "Failed to register panel\n"); 375 dev_err(&pdev->dev, "Failed to register panel\n");
376 goto err_reg; 376 return r;
377 } 377 }
378 378
379 return 0; 379 return 0;
380err_reg:
381 omap_dss_put_device(ddata->in);
382 return r;
383} 380}
384 381
385static int __exit hdmic_remove(struct platform_device *pdev) 382static int __exit hdmic_remove(struct platform_device *pdev)
386{ 383{
387 struct panel_drv_data *ddata = platform_get_drvdata(pdev); 384 struct panel_drv_data *ddata = platform_get_drvdata(pdev);
388 struct omap_dss_device *dssdev = &ddata->dssdev; 385 struct omap_dss_device *dssdev = &ddata->dssdev;
389 struct omap_dss_device *in = ddata->in;
390 386
391 omapdss_unregister_display(&ddata->dssdev); 387 omapdss_unregister_display(&ddata->dssdev);
392 388
393 hdmic_disable(dssdev); 389 hdmic_disable(dssdev);
394 hdmic_disconnect(dssdev); 390 hdmic_disconnect(dssdev);
395 391
396 omap_dss_put_device(in);
397
398 return 0; 392 return 0;
399} 393}
400 394
diff --git a/drivers/gpu/drm/omapdrm/displays/encoder-opa362.c b/drivers/gpu/drm/omapdrm/displays/encoder-opa362.c
index d523c67a3ae3..afee1b8b457a 100644
--- a/drivers/gpu/drm/omapdrm/displays/encoder-opa362.c
+++ b/drivers/gpu/drm/omapdrm/displays/encoder-opa362.c
@@ -36,7 +36,7 @@ static int opa362_connect(struct omap_dss_device *dssdev,
36 struct omap_dss_device *dst) 36 struct omap_dss_device *dst)
37{ 37{
38 struct panel_drv_data *ddata = to_panel_data(dssdev); 38 struct panel_drv_data *ddata = to_panel_data(dssdev);
39 struct omap_dss_device *in = ddata->in; 39 struct omap_dss_device *in;
40 int r; 40 int r;
41 41
42 dev_dbg(dssdev->dev, "connect\n"); 42 dev_dbg(dssdev->dev, "connect\n");
@@ -44,13 +44,22 @@ static int opa362_connect(struct omap_dss_device *dssdev,
44 if (omapdss_device_is_connected(dssdev)) 44 if (omapdss_device_is_connected(dssdev))
45 return -EBUSY; 45 return -EBUSY;
46 46
47 in = omapdss_of_find_source_for_first_ep(dssdev->dev->of_node);
48 if (IS_ERR(in)) {
49 dev_err(dssdev->dev, "failed to find video source\n");
50 return PTR_ERR(in);
51 }
52
47 r = in->ops.atv->connect(in, dssdev); 53 r = in->ops.atv->connect(in, dssdev);
48 if (r) 54 if (r) {
55 omap_dss_put_device(in);
49 return r; 56 return r;
57 }
50 58
51 dst->src = dssdev; 59 dst->src = dssdev;
52 dssdev->dst = dst; 60 dssdev->dst = dst;
53 61
62 ddata->in = in;
54 return 0; 63 return 0;
55} 64}
56 65
@@ -74,6 +83,9 @@ static void opa362_disconnect(struct omap_dss_device *dssdev,
74 dssdev->dst = NULL; 83 dssdev->dst = NULL;
75 84
76 in->ops.atv->disconnect(in, &ddata->dssdev); 85 in->ops.atv->disconnect(in, &ddata->dssdev);
86
87 omap_dss_put_device(in);
88 ddata->in = NULL;
77} 89}
78 90
79static int opa362_enable(struct omap_dss_device *dssdev) 91static int opa362_enable(struct omap_dss_device *dssdev)
@@ -171,19 +183,13 @@ static const struct omapdss_atv_ops opa362_atv_ops = {
171 183
172static int opa362_probe(struct platform_device *pdev) 184static int opa362_probe(struct platform_device *pdev)
173{ 185{
174 struct device_node *node = pdev->dev.of_node;
175 struct panel_drv_data *ddata; 186 struct panel_drv_data *ddata;
176 struct omap_dss_device *dssdev, *in; 187 struct omap_dss_device *dssdev;
177 struct gpio_desc *gpio; 188 struct gpio_desc *gpio;
178 int r; 189 int r;
179 190
180 dev_dbg(&pdev->dev, "probe\n"); 191 dev_dbg(&pdev->dev, "probe\n");
181 192
182 if (node == NULL) {
183 dev_err(&pdev->dev, "Unable to find device tree\n");
184 return -EINVAL;
185 }
186
187 ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL); 193 ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL);
188 if (!ddata) 194 if (!ddata)
189 return -ENOMEM; 195 return -ENOMEM;
@@ -196,14 +202,6 @@ static int opa362_probe(struct platform_device *pdev)
196 202
197 ddata->enable_gpio = gpio; 203 ddata->enable_gpio = gpio;
198 204
199 in = omapdss_of_find_source_for_first_ep(node);
200 if (IS_ERR(in)) {
201 dev_err(&pdev->dev, "failed to find video source\n");
202 return PTR_ERR(in);
203 }
204
205 ddata->in = in;
206
207 dssdev = &ddata->dssdev; 205 dssdev = &ddata->dssdev;
208 dssdev->ops.atv = &opa362_atv_ops; 206 dssdev->ops.atv = &opa362_atv_ops;
209 dssdev->dev = &pdev->dev; 207 dssdev->dev = &pdev->dev;
@@ -214,20 +212,16 @@ static int opa362_probe(struct platform_device *pdev)
214 r = omapdss_register_output(dssdev); 212 r = omapdss_register_output(dssdev);
215 if (r) { 213 if (r) {
216 dev_err(&pdev->dev, "Failed to register output\n"); 214 dev_err(&pdev->dev, "Failed to register output\n");
217 goto err_reg; 215 return r;
218 } 216 }
219 217
220 return 0; 218 return 0;
221err_reg:
222 omap_dss_put_device(ddata->in);
223 return r;
224} 219}
225 220
226static int __exit opa362_remove(struct platform_device *pdev) 221static int __exit opa362_remove(struct platform_device *pdev)
227{ 222{
228 struct panel_drv_data *ddata = platform_get_drvdata(pdev); 223 struct panel_drv_data *ddata = platform_get_drvdata(pdev);
229 struct omap_dss_device *dssdev = &ddata->dssdev; 224 struct omap_dss_device *dssdev = &ddata->dssdev;
230 struct omap_dss_device *in = ddata->in;
231 225
232 omapdss_unregister_output(&ddata->dssdev); 226 omapdss_unregister_output(&ddata->dssdev);
233 227
@@ -239,8 +233,6 @@ static int __exit opa362_remove(struct platform_device *pdev)
239 if (omapdss_device_is_connected(dssdev)) 233 if (omapdss_device_is_connected(dssdev))
240 opa362_disconnect(dssdev, dssdev->dst); 234 opa362_disconnect(dssdev, dssdev->dst);
241 235
242 omap_dss_put_device(in);
243
244 return 0; 236 return 0;
245} 237}
246 238
diff --git a/drivers/gpu/drm/omapdrm/displays/encoder-tfp410.c b/drivers/gpu/drm/omapdrm/displays/encoder-tfp410.c
index e01ab3db6d86..ed7ae384c3ed 100644
--- a/drivers/gpu/drm/omapdrm/displays/encoder-tfp410.c
+++ b/drivers/gpu/drm/omapdrm/displays/encoder-tfp410.c
@@ -32,19 +32,28 @@ static int tfp410_connect(struct omap_dss_device *dssdev,
32 struct omap_dss_device *dst) 32 struct omap_dss_device *dst)
33{ 33{
34 struct panel_drv_data *ddata = to_panel_data(dssdev); 34 struct panel_drv_data *ddata = to_panel_data(dssdev);
35 struct omap_dss_device *in = ddata->in; 35 struct omap_dss_device *in;
36 int r; 36 int r;
37 37
38 if (omapdss_device_is_connected(dssdev)) 38 if (omapdss_device_is_connected(dssdev))
39 return -EBUSY; 39 return -EBUSY;
40 40
41 in = omapdss_of_find_source_for_first_ep(dssdev->dev->of_node);
42 if (IS_ERR(in)) {
43 dev_err(dssdev->dev, "failed to find video source\n");
44 return PTR_ERR(in);
45 }
46
41 r = in->ops.dpi->connect(in, dssdev); 47 r = in->ops.dpi->connect(in, dssdev);
42 if (r) 48 if (r) {
49 omap_dss_put_device(in);
43 return r; 50 return r;
51 }
44 52
45 dst->src = dssdev; 53 dst->src = dssdev;
46 dssdev->dst = dst; 54 dssdev->dst = dst;
47 55
56 ddata->in = in;
48 return 0; 57 return 0;
49} 58}
50 59
@@ -66,6 +75,9 @@ static void tfp410_disconnect(struct omap_dss_device *dssdev,
66 dssdev->dst = NULL; 75 dssdev->dst = NULL;
67 76
68 in->ops.dpi->disconnect(in, &ddata->dssdev); 77 in->ops.dpi->disconnect(in, &ddata->dssdev);
78
79 omap_dss_put_device(in);
80 ddata->in = NULL;
69} 81}
70 82
71static int tfp410_enable(struct omap_dss_device *dssdev) 83static int tfp410_enable(struct omap_dss_device *dssdev)
@@ -165,7 +177,6 @@ static int tfp410_probe_of(struct platform_device *pdev)
165{ 177{
166 struct panel_drv_data *ddata = platform_get_drvdata(pdev); 178 struct panel_drv_data *ddata = platform_get_drvdata(pdev);
167 struct device_node *node = pdev->dev.of_node; 179 struct device_node *node = pdev->dev.of_node;
168 struct omap_dss_device *in;
169 int gpio; 180 int gpio;
170 181
171 gpio = of_get_named_gpio(node, "powerdown-gpios", 0); 182 gpio = of_get_named_gpio(node, "powerdown-gpios", 0);
@@ -178,14 +189,6 @@ static int tfp410_probe_of(struct platform_device *pdev)
178 return gpio; 189 return gpio;
179 } 190 }
180 191
181 in = omapdss_of_find_source_for_first_ep(node);
182 if (IS_ERR(in)) {
183 dev_err(&pdev->dev, "failed to find video source\n");
184 return PTR_ERR(in);
185 }
186
187 ddata->in = in;
188
189 return 0; 192 return 0;
190} 193}
191 194
@@ -201,9 +204,6 @@ static int tfp410_probe(struct platform_device *pdev)
201 204
202 platform_set_drvdata(pdev, ddata); 205 platform_set_drvdata(pdev, ddata);
203 206
204 if (!pdev->dev.of_node)
205 return -ENODEV;
206
207 r = tfp410_probe_of(pdev); 207 r = tfp410_probe_of(pdev);
208 if (r) 208 if (r)
209 return r; 209 return r;
@@ -214,7 +214,7 @@ static int tfp410_probe(struct platform_device *pdev)
214 if (r) { 214 if (r) {
215 dev_err(&pdev->dev, "Failed to request PD GPIO %d\n", 215 dev_err(&pdev->dev, "Failed to request PD GPIO %d\n",
216 ddata->pd_gpio); 216 ddata->pd_gpio);
217 goto err_gpio; 217 return r;
218 } 218 }
219 } 219 }
220 220
@@ -229,21 +229,16 @@ static int tfp410_probe(struct platform_device *pdev)
229 r = omapdss_register_output(dssdev); 229 r = omapdss_register_output(dssdev);
230 if (r) { 230 if (r) {
231 dev_err(&pdev->dev, "Failed to register output\n"); 231 dev_err(&pdev->dev, "Failed to register output\n");
232 goto err_reg; 232 return r;
233 } 233 }
234 234
235 return 0; 235 return 0;
236err_reg:
237err_gpio:
238 omap_dss_put_device(ddata->in);
239 return r;
240} 236}
241 237
242static int __exit tfp410_remove(struct platform_device *pdev) 238static int __exit tfp410_remove(struct platform_device *pdev)
243{ 239{
244 struct panel_drv_data *ddata = platform_get_drvdata(pdev); 240 struct panel_drv_data *ddata = platform_get_drvdata(pdev);
245 struct omap_dss_device *dssdev = &ddata->dssdev; 241 struct omap_dss_device *dssdev = &ddata->dssdev;
246 struct omap_dss_device *in = ddata->in;
247 242
248 omapdss_unregister_output(&ddata->dssdev); 243 omapdss_unregister_output(&ddata->dssdev);
249 244
@@ -255,8 +250,6 @@ static int __exit tfp410_remove(struct platform_device *pdev)
255 if (omapdss_device_is_connected(dssdev)) 250 if (omapdss_device_is_connected(dssdev))
256 tfp410_disconnect(dssdev, dssdev->dst); 251 tfp410_disconnect(dssdev, dssdev->dst);
257 252
258 omap_dss_put_device(in);
259
260 return 0; 253 return 0;
261} 254}
262 255
diff --git a/drivers/gpu/drm/omapdrm/displays/encoder-tpd12s015.c b/drivers/gpu/drm/omapdrm/displays/encoder-tpd12s015.c
index 1fd493e5fa3d..d275bf152da5 100644
--- a/drivers/gpu/drm/omapdrm/displays/encoder-tpd12s015.c
+++ b/drivers/gpu/drm/omapdrm/displays/encoder-tpd12s015.c
@@ -40,12 +40,20 @@ static int tpd_connect(struct omap_dss_device *dssdev,
40 struct omap_dss_device *dst) 40 struct omap_dss_device *dst)
41{ 41{
42 struct panel_drv_data *ddata = to_panel_data(dssdev); 42 struct panel_drv_data *ddata = to_panel_data(dssdev);
43 struct omap_dss_device *in = ddata->in; 43 struct omap_dss_device *in;
44 int r; 44 int r;
45 45
46 in = omapdss_of_find_source_for_first_ep(dssdev->dev->of_node);
47 if (IS_ERR(in)) {
48 dev_err(dssdev->dev, "failed to find video source\n");
49 return PTR_ERR(in);
50 }
51
46 r = in->ops.hdmi->connect(in, dssdev); 52 r = in->ops.hdmi->connect(in, dssdev);
47 if (r) 53 if (r) {
54 omap_dss_put_device(in);
48 return r; 55 return r;
56 }
49 57
50 dst->src = dssdev; 58 dst->src = dssdev;
51 dssdev->dst = dst; 59 dssdev->dst = dst;
@@ -56,6 +64,7 @@ static int tpd_connect(struct omap_dss_device *dssdev,
56 /* DC-DC converter needs at max 300us to get to 90% of 5V */ 64 /* DC-DC converter needs at max 300us to get to 90% of 5V */
57 udelay(300); 65 udelay(300);
58 66
67 ddata->in = in;
59 return 0; 68 return 0;
60} 69}
61 70
@@ -77,6 +86,9 @@ static void tpd_disconnect(struct omap_dss_device *dssdev,
77 dssdev->dst = NULL; 86 dssdev->dst = NULL;
78 87
79 in->ops.hdmi->disconnect(in, &ddata->dssdev); 88 in->ops.hdmi->disconnect(in, &ddata->dssdev);
89
90 omap_dss_put_device(in);
91 ddata->in = NULL;
80} 92}
81 93
82static int tpd_enable(struct omap_dss_device *dssdev) 94static int tpd_enable(struct omap_dss_device *dssdev)
@@ -269,23 +281,6 @@ static irqreturn_t tpd_hpd_isr(int irq, void *data)
269 return IRQ_HANDLED; 281 return IRQ_HANDLED;
270} 282}
271 283
272static int tpd_probe_of(struct platform_device *pdev)
273{
274 struct panel_drv_data *ddata = platform_get_drvdata(pdev);
275 struct device_node *node = pdev->dev.of_node;
276 struct omap_dss_device *in;
277
278 in = omapdss_of_find_source_for_first_ep(node);
279 if (IS_ERR(in)) {
280 dev_err(&pdev->dev, "failed to find video source\n");
281 return PTR_ERR(in);
282 }
283
284 ddata->in = in;
285
286 return 0;
287}
288
289static int tpd_probe(struct platform_device *pdev) 284static int tpd_probe(struct platform_device *pdev)
290{ 285{
291 struct omap_dss_device *in, *dssdev; 286 struct omap_dss_device *in, *dssdev;
@@ -299,37 +294,24 @@ static int tpd_probe(struct platform_device *pdev)
299 294
300 platform_set_drvdata(pdev, ddata); 295 platform_set_drvdata(pdev, ddata);
301 296
302 if (!pdev->dev.of_node)
303 return -ENODEV;
304
305 r = tpd_probe_of(pdev);
306 if (r)
307 return r;
308
309 gpio = devm_gpiod_get_index_optional(&pdev->dev, NULL, 0, 297 gpio = devm_gpiod_get_index_optional(&pdev->dev, NULL, 0,
310 GPIOD_OUT_LOW); 298 GPIOD_OUT_LOW);
311 if (IS_ERR(gpio)) { 299 if (IS_ERR(gpio))
312 r = PTR_ERR(gpio); 300 return PTR_ERR(gpio);
313 goto err_gpio;
314 }
315 301
316 ddata->ct_cp_hpd_gpio = gpio; 302 ddata->ct_cp_hpd_gpio = gpio;
317 303
318 gpio = devm_gpiod_get_index_optional(&pdev->dev, NULL, 1, 304 gpio = devm_gpiod_get_index_optional(&pdev->dev, NULL, 1,
319 GPIOD_OUT_LOW); 305 GPIOD_OUT_LOW);
320 if (IS_ERR(gpio)) { 306 if (IS_ERR(gpio))
321 r = PTR_ERR(gpio); 307 return PTR_ERR(gpio);
322 goto err_gpio;
323 }
324 308
325 ddata->ls_oe_gpio = gpio; 309 ddata->ls_oe_gpio = gpio;
326 310
327 gpio = devm_gpiod_get_index(&pdev->dev, NULL, 2, 311 gpio = devm_gpiod_get_index(&pdev->dev, NULL, 2,
328 GPIOD_IN); 312 GPIOD_IN);
329 if (IS_ERR(gpio)) { 313 if (IS_ERR(gpio))
330 r = PTR_ERR(gpio); 314 return PTR_ERR(gpio);
331 goto err_gpio;
332 }
333 315
334 ddata->hpd_gpio = gpio; 316 ddata->hpd_gpio = gpio;
335 317
@@ -340,7 +322,7 @@ static int tpd_probe(struct platform_device *pdev)
340 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 322 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
341 "tpd12s015 hpd", ddata); 323 "tpd12s015 hpd", ddata);
342 if (r) 324 if (r)
343 goto err_gpio; 325 return r;
344 326
345 dssdev = &ddata->dssdev; 327 dssdev = &ddata->dssdev;
346 dssdev->ops.hdmi = &tpd_hdmi_ops; 328 dssdev->ops.hdmi = &tpd_hdmi_ops;
@@ -355,21 +337,16 @@ static int tpd_probe(struct platform_device *pdev)
355 r = omapdss_register_output(dssdev); 337 r = omapdss_register_output(dssdev);
356 if (r) { 338 if (r) {
357 dev_err(&pdev->dev, "Failed to register output\n"); 339 dev_err(&pdev->dev, "Failed to register output\n");
358 goto err_reg; 340 return r;
359 } 341 }
360 342
361 return 0; 343 return 0;
362err_reg:
363err_gpio:
364 omap_dss_put_device(ddata->in);
365 return r;
366} 344}
367 345
368static int __exit tpd_remove(struct platform_device *pdev) 346static int __exit tpd_remove(struct platform_device *pdev)
369{ 347{
370 struct panel_drv_data *ddata = platform_get_drvdata(pdev); 348 struct panel_drv_data *ddata = platform_get_drvdata(pdev);
371 struct omap_dss_device *dssdev = &ddata->dssdev; 349 struct omap_dss_device *dssdev = &ddata->dssdev;
372 struct omap_dss_device *in = ddata->in;
373 350
374 omapdss_unregister_output(&ddata->dssdev); 351 omapdss_unregister_output(&ddata->dssdev);
375 352
@@ -381,8 +358,6 @@ static int __exit tpd_remove(struct platform_device *pdev)
381 if (omapdss_device_is_connected(dssdev)) 358 if (omapdss_device_is_connected(dssdev))
382 tpd_disconnect(dssdev, dssdev->dst); 359 tpd_disconnect(dssdev, dssdev->dst);
383 360
384 omap_dss_put_device(in);
385
386 return 0; 361 return 0;
387} 362}
388 363
diff --git a/drivers/gpu/drm/omapdrm/displays/panel-dpi.c b/drivers/gpu/drm/omapdrm/displays/panel-dpi.c
index 48a03f55610a..6cbf570d6727 100644
--- a/drivers/gpu/drm/omapdrm/displays/panel-dpi.c
+++ b/drivers/gpu/drm/omapdrm/displays/panel-dpi.c
@@ -38,16 +38,25 @@ struct panel_drv_data {
38static int panel_dpi_connect(struct omap_dss_device *dssdev) 38static int panel_dpi_connect(struct omap_dss_device *dssdev)
39{ 39{
40 struct panel_drv_data *ddata = to_panel_data(dssdev); 40 struct panel_drv_data *ddata = to_panel_data(dssdev);
41 struct omap_dss_device *in = ddata->in; 41 struct omap_dss_device *in;
42 int r; 42 int r;
43 43
44 if (omapdss_device_is_connected(dssdev)) 44 if (omapdss_device_is_connected(dssdev))
45 return 0; 45 return 0;
46 46
47 in = omapdss_of_find_source_for_first_ep(dssdev->dev->of_node);
48 if (IS_ERR(in)) {
49 dev_err(dssdev->dev, "failed to find video source\n");
50 return PTR_ERR(in);
51 }
52
47 r = in->ops.dpi->connect(in, dssdev); 53 r = in->ops.dpi->connect(in, dssdev);
48 if (r) 54 if (r) {
55 omap_dss_put_device(in);
49 return r; 56 return r;
57 }
50 58
59 ddata->in = in;
51 return 0; 60 return 0;
52} 61}
53 62
@@ -60,6 +69,9 @@ static void panel_dpi_disconnect(struct omap_dss_device *dssdev)
60 return; 69 return;
61 70
62 in->ops.dpi->disconnect(in, dssdev); 71 in->ops.dpi->disconnect(in, dssdev);
72
73 omap_dss_put_device(in);
74 ddata->in = NULL;
63} 75}
64 76
65static int panel_dpi_enable(struct omap_dss_device *dssdev) 77static int panel_dpi_enable(struct omap_dss_device *dssdev)
@@ -157,7 +169,6 @@ static int panel_dpi_probe_of(struct platform_device *pdev)
157{ 169{
158 struct panel_drv_data *ddata = platform_get_drvdata(pdev); 170 struct panel_drv_data *ddata = platform_get_drvdata(pdev);
159 struct device_node *node = pdev->dev.of_node; 171 struct device_node *node = pdev->dev.of_node;
160 struct omap_dss_device *in;
161 int r; 172 int r;
162 struct display_timing timing; 173 struct display_timing timing;
163 struct gpio_desc *gpio; 174 struct gpio_desc *gpio;
@@ -195,14 +206,6 @@ static int panel_dpi_probe_of(struct platform_device *pdev)
195 206
196 videomode_from_timing(&timing, &ddata->vm); 207 videomode_from_timing(&timing, &ddata->vm);
197 208
198 in = omapdss_of_find_source_for_first_ep(node);
199 if (IS_ERR(in)) {
200 dev_err(&pdev->dev, "failed to find video source\n");
201 return PTR_ERR(in);
202 }
203
204 ddata->in = in;
205
206 return 0; 209 return 0;
207} 210}
208 211
@@ -212,9 +215,6 @@ static int panel_dpi_probe(struct platform_device *pdev)
212 struct omap_dss_device *dssdev; 215 struct omap_dss_device *dssdev;
213 int r; 216 int r;
214 217
215 if (!pdev->dev.of_node)
216 return -ENODEV;
217
218 ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL); 218 ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL);
219 if (ddata == NULL) 219 if (ddata == NULL)
220 return -ENOMEM; 220 return -ENOMEM;
@@ -235,29 +235,22 @@ static int panel_dpi_probe(struct platform_device *pdev)
235 r = omapdss_register_display(dssdev); 235 r = omapdss_register_display(dssdev);
236 if (r) { 236 if (r) {
237 dev_err(&pdev->dev, "Failed to register panel\n"); 237 dev_err(&pdev->dev, "Failed to register panel\n");
238 goto err_reg; 238 return r;
239 } 239 }
240 240
241 return 0; 241 return 0;
242
243err_reg:
244 omap_dss_put_device(ddata->in);
245 return r;
246} 242}
247 243
248static int __exit panel_dpi_remove(struct platform_device *pdev) 244static int __exit panel_dpi_remove(struct platform_device *pdev)
249{ 245{
250 struct panel_drv_data *ddata = platform_get_drvdata(pdev); 246 struct panel_drv_data *ddata = platform_get_drvdata(pdev);
251 struct omap_dss_device *dssdev = &ddata->dssdev; 247 struct omap_dss_device *dssdev = &ddata->dssdev;
252 struct omap_dss_device *in = ddata->in;
253 248
254 omapdss_unregister_display(dssdev); 249 omapdss_unregister_display(dssdev);
255 250
256 panel_dpi_disable(dssdev); 251 panel_dpi_disable(dssdev);
257 panel_dpi_disconnect(dssdev); 252 panel_dpi_disconnect(dssdev);
258 253
259 omap_dss_put_device(in);
260
261 return 0; 254 return 0;
262} 255}
263 256
diff --git a/drivers/gpu/drm/omapdrm/displays/panel-dsi-cm.c b/drivers/gpu/drm/omapdrm/displays/panel-dsi-cm.c
index 15399a1a666b..428de90fced1 100644
--- a/drivers/gpu/drm/omapdrm/displays/panel-dsi-cm.c
+++ b/drivers/gpu/drm/omapdrm/displays/panel-dsi-cm.c
@@ -86,7 +86,7 @@ struct panel_drv_data {
86 struct workqueue_struct *workqueue; 86 struct workqueue_struct *workqueue;
87 87
88 bool ulps_enabled; 88 bool ulps_enabled;
89 unsigned ulps_timeout; 89 unsigned int ulps_timeout;
90 struct delayed_work ulps_work; 90 struct delayed_work ulps_work;
91}; 91};
92 92
@@ -513,7 +513,7 @@ static ssize_t dsicm_show_ulps(struct device *dev,
513{ 513{
514 struct platform_device *pdev = to_platform_device(dev); 514 struct platform_device *pdev = to_platform_device(dev);
515 struct panel_drv_data *ddata = platform_get_drvdata(pdev); 515 struct panel_drv_data *ddata = platform_get_drvdata(pdev);
516 unsigned t; 516 unsigned int t;
517 517
518 mutex_lock(&ddata->lock); 518 mutex_lock(&ddata->lock);
519 t = ddata->ulps_enabled; 519 t = ddata->ulps_enabled;
@@ -560,7 +560,7 @@ static ssize_t dsicm_show_ulps_timeout(struct device *dev,
560{ 560{
561 struct platform_device *pdev = to_platform_device(dev); 561 struct platform_device *pdev = to_platform_device(dev);
562 struct panel_drv_data *ddata = platform_get_drvdata(pdev); 562 struct panel_drv_data *ddata = platform_get_drvdata(pdev);
563 unsigned t; 563 unsigned int t;
564 564
565 mutex_lock(&ddata->lock); 565 mutex_lock(&ddata->lock);
566 t = ddata->ulps_timeout; 566 t = ddata->ulps_timeout;
@@ -759,37 +759,46 @@ static int dsicm_panel_reset(struct panel_drv_data *ddata)
759static int dsicm_connect(struct omap_dss_device *dssdev) 759static int dsicm_connect(struct omap_dss_device *dssdev)
760{ 760{
761 struct panel_drv_data *ddata = to_panel_data(dssdev); 761 struct panel_drv_data *ddata = to_panel_data(dssdev);
762 struct omap_dss_device *in = ddata->in;
763 struct device *dev = &ddata->pdev->dev; 762 struct device *dev = &ddata->pdev->dev;
763 struct omap_dss_device *in;
764 int r; 764 int r;
765 765
766 if (omapdss_device_is_connected(dssdev)) 766 if (omapdss_device_is_connected(dssdev))
767 return 0; 767 return 0;
768 768
769 in = omapdss_of_find_source_for_first_ep(dssdev->dev->of_node);
770 if (IS_ERR(in)) {
771 dev_err(dssdev->dev, "failed to find video source\n");
772 return PTR_ERR(in);
773 }
774
769 r = in->ops.dsi->connect(in, dssdev); 775 r = in->ops.dsi->connect(in, dssdev);
770 if (r) { 776 if (r) {
771 dev_err(dev, "Failed to connect to video source\n"); 777 dev_err(dev, "Failed to connect to video source\n");
772 return r; 778 goto err_connect;
773 } 779 }
774 780
775 r = in->ops.dsi->request_vc(ddata->in, &ddata->channel); 781 r = in->ops.dsi->request_vc(in, &ddata->channel);
776 if (r) { 782 if (r) {
777 dev_err(dev, "failed to get virtual channel\n"); 783 dev_err(dev, "failed to get virtual channel\n");
778 goto err_req_vc; 784 goto err_req_vc;
779 } 785 }
780 786
781 r = in->ops.dsi->set_vc_id(ddata->in, ddata->channel, TCH); 787 r = in->ops.dsi->set_vc_id(in, ddata->channel, TCH);
782 if (r) { 788 if (r) {
783 dev_err(dev, "failed to set VC_ID\n"); 789 dev_err(dev, "failed to set VC_ID\n");
784 goto err_vc_id; 790 goto err_vc_id;
785 } 791 }
786 792
793 ddata->in = in;
787 return 0; 794 return 0;
788 795
789err_vc_id: 796err_vc_id:
790 in->ops.dsi->release_vc(ddata->in, ddata->channel); 797 in->ops.dsi->release_vc(in, ddata->channel);
791err_req_vc: 798err_req_vc:
792 in->ops.dsi->disconnect(in, dssdev); 799 in->ops.dsi->disconnect(in, dssdev);
800err_connect:
801 omap_dss_put_device(in);
793 return r; 802 return r;
794} 803}
795 804
@@ -803,6 +812,9 @@ static void dsicm_disconnect(struct omap_dss_device *dssdev)
803 812
804 in->ops.dsi->release_vc(in, ddata->channel); 813 in->ops.dsi->release_vc(in, ddata->channel);
805 in->ops.dsi->disconnect(in, dssdev); 814 in->ops.dsi->disconnect(in, dssdev);
815
816 omap_dss_put_device(in);
817 ddata->in = NULL;
806} 818}
807 819
808static int dsicm_enable(struct omap_dss_device *dssdev) 820static int dsicm_enable(struct omap_dss_device *dssdev)
@@ -1064,7 +1076,7 @@ static int dsicm_memory_read(struct omap_dss_device *dssdev,
1064 int r; 1076 int r;
1065 int first = 1; 1077 int first = 1;
1066 int plen; 1078 int plen;
1067 unsigned buf_used = 0; 1079 unsigned int buf_used = 0;
1068 1080
1069 if (size < w * h * 3) 1081 if (size < w * h * 3)
1070 return -ENOMEM; 1082 return -ENOMEM;
@@ -1223,7 +1235,6 @@ static int dsicm_probe_of(struct platform_device *pdev)
1223 struct device_node *node = pdev->dev.of_node; 1235 struct device_node *node = pdev->dev.of_node;
1224 struct device_node *backlight; 1236 struct device_node *backlight;
1225 struct panel_drv_data *ddata = platform_get_drvdata(pdev); 1237 struct panel_drv_data *ddata = platform_get_drvdata(pdev);
1226 struct omap_dss_device *in;
1227 struct display_timing timing; 1238 struct display_timing timing;
1228 int err; 1239 int err;
1229 1240
@@ -1259,12 +1270,6 @@ static int dsicm_probe_of(struct platform_device *pdev)
1259 ddata->height_mm = 0; 1270 ddata->height_mm = 0;
1260 of_property_read_u32(node, "height-mm", &ddata->height_mm); 1271 of_property_read_u32(node, "height-mm", &ddata->height_mm);
1261 1272
1262 in = omapdss_of_find_source_for_first_ep(node);
1263 if (IS_ERR(in)) {
1264 dev_err(&pdev->dev, "failed to find video source\n");
1265 return PTR_ERR(in);
1266 }
1267
1268 ddata->vpnl = devm_regulator_get_optional(&pdev->dev, "vpnl"); 1273 ddata->vpnl = devm_regulator_get_optional(&pdev->dev, "vpnl");
1269 if (IS_ERR(ddata->vpnl)) { 1274 if (IS_ERR(ddata->vpnl)) {
1270 err = PTR_ERR(ddata->vpnl); 1275 err = PTR_ERR(ddata->vpnl);
@@ -1281,8 +1286,6 @@ static int dsicm_probe_of(struct platform_device *pdev)
1281 ddata->vddi = NULL; 1286 ddata->vddi = NULL;
1282 } 1287 }
1283 1288
1284 ddata->in = in;
1285
1286 backlight = of_parse_phandle(node, "backlight", 0); 1289 backlight = of_parse_phandle(node, "backlight", 0);
1287 if (backlight) { 1290 if (backlight) {
1288 ddata->extbldev = of_find_backlight_by_node(backlight); 1291 ddata->extbldev = of_find_backlight_by_node(backlight);
@@ -1317,9 +1320,6 @@ static int dsicm_probe(struct platform_device *pdev)
1317 platform_set_drvdata(pdev, ddata); 1320 platform_set_drvdata(pdev, ddata);
1318 ddata->pdev = pdev; 1321 ddata->pdev = pdev;
1319 1322
1320 if (!pdev->dev.of_node)
1321 return -ENODEV;
1322
1323 ddata->vm.hactive = 864; 1323 ddata->vm.hactive = 864;
1324 ddata->vm.vactive = 480; 1324 ddata->vm.vactive = 480;
1325 ddata->vm.pixelclock = 864 * 480 * 60; 1325 ddata->vm.pixelclock = 864 * 480 * 60;
@@ -1424,8 +1424,6 @@ static int __exit dsicm_remove(struct platform_device *pdev)
1424 if (ddata->extbldev) 1424 if (ddata->extbldev)
1425 put_device(&ddata->extbldev->dev); 1425 put_device(&ddata->extbldev->dev);
1426 1426
1427 omap_dss_put_device(ddata->in);
1428
1429 dsicm_cancel_ulps_work(ddata); 1427 dsicm_cancel_ulps_work(ddata);
1430 destroy_workqueue(ddata->workqueue); 1428 destroy_workqueue(ddata->workqueue);
1431 1429
diff --git a/drivers/gpu/drm/omapdrm/displays/panel-lgphilips-lb035q02.c b/drivers/gpu/drm/omapdrm/displays/panel-lgphilips-lb035q02.c
index 57af22ce87c5..754197099440 100644
--- a/drivers/gpu/drm/omapdrm/displays/panel-lgphilips-lb035q02.c
+++ b/drivers/gpu/drm/omapdrm/displays/panel-lgphilips-lb035q02.c
@@ -119,18 +119,27 @@ static void init_lb035q02_panel(struct spi_device *spi)
119static int lb035q02_connect(struct omap_dss_device *dssdev) 119static int lb035q02_connect(struct omap_dss_device *dssdev)
120{ 120{
121 struct panel_drv_data *ddata = to_panel_data(dssdev); 121 struct panel_drv_data *ddata = to_panel_data(dssdev);
122 struct omap_dss_device *in = ddata->in; 122 struct omap_dss_device *in;
123 int r; 123 int r;
124 124
125 if (omapdss_device_is_connected(dssdev)) 125 if (omapdss_device_is_connected(dssdev))
126 return 0; 126 return 0;
127 127
128 in = omapdss_of_find_source_for_first_ep(dssdev->dev->of_node);
129 if (IS_ERR(in)) {
130 dev_err(dssdev->dev, "failed to find video source\n");
131 return PTR_ERR(in);
132 }
133
128 r = in->ops.dpi->connect(in, dssdev); 134 r = in->ops.dpi->connect(in, dssdev);
129 if (r) 135 if (r) {
136 omap_dss_put_device(in);
130 return r; 137 return r;
138 }
131 139
132 init_lb035q02_panel(ddata->spi); 140 init_lb035q02_panel(ddata->spi);
133 141
142 ddata->in = in;
134 return 0; 143 return 0;
135} 144}
136 145
@@ -143,6 +152,9 @@ static void lb035q02_disconnect(struct omap_dss_device *dssdev)
143 return; 152 return;
144 153
145 in->ops.dpi->disconnect(in, dssdev); 154 in->ops.dpi->disconnect(in, dssdev);
155
156 omap_dss_put_device(in);
157 ddata->in = NULL;
146} 158}
147 159
148static int lb035q02_enable(struct omap_dss_device *dssdev) 160static int lb035q02_enable(struct omap_dss_device *dssdev)
@@ -230,9 +242,7 @@ static struct omap_dss_driver lb035q02_ops = {
230 242
231static int lb035q02_probe_of(struct spi_device *spi) 243static int lb035q02_probe_of(struct spi_device *spi)
232{ 244{
233 struct device_node *node = spi->dev.of_node;
234 struct panel_drv_data *ddata = dev_get_drvdata(&spi->dev); 245 struct panel_drv_data *ddata = dev_get_drvdata(&spi->dev);
235 struct omap_dss_device *in;
236 struct gpio_desc *gpio; 246 struct gpio_desc *gpio;
237 247
238 gpio = devm_gpiod_get(&spi->dev, "enable", GPIOD_OUT_LOW); 248 gpio = devm_gpiod_get(&spi->dev, "enable", GPIOD_OUT_LOW);
@@ -243,14 +253,6 @@ static int lb035q02_probe_of(struct spi_device *spi)
243 253
244 ddata->enable_gpio = gpio; 254 ddata->enable_gpio = gpio;
245 255
246 in = omapdss_of_find_source_for_first_ep(node);
247 if (IS_ERR(in)) {
248 dev_err(&spi->dev, "failed to find video source\n");
249 return PTR_ERR(in);
250 }
251
252 ddata->in = in;
253
254 return 0; 256 return 0;
255} 257}
256 258
@@ -268,9 +270,6 @@ static int lb035q02_panel_spi_probe(struct spi_device *spi)
268 270
269 ddata->spi = spi; 271 ddata->spi = spi;
270 272
271 if (!spi->dev.of_node)
272 return -ENODEV;
273
274 r = lb035q02_probe_of(spi); 273 r = lb035q02_probe_of(spi);
275 if (r) 274 if (r)
276 return r; 275 return r;
@@ -287,29 +286,22 @@ static int lb035q02_panel_spi_probe(struct spi_device *spi)
287 r = omapdss_register_display(dssdev); 286 r = omapdss_register_display(dssdev);
288 if (r) { 287 if (r) {
289 dev_err(&spi->dev, "Failed to register panel\n"); 288 dev_err(&spi->dev, "Failed to register panel\n");
290 goto err_reg; 289 return r;
291 } 290 }
292 291
293 return 0; 292 return 0;
294
295err_reg:
296 omap_dss_put_device(ddata->in);
297 return r;
298} 293}
299 294
300static int lb035q02_panel_spi_remove(struct spi_device *spi) 295static int lb035q02_panel_spi_remove(struct spi_device *spi)
301{ 296{
302 struct panel_drv_data *ddata = dev_get_drvdata(&spi->dev); 297 struct panel_drv_data *ddata = dev_get_drvdata(&spi->dev);
303 struct omap_dss_device *dssdev = &ddata->dssdev; 298 struct omap_dss_device *dssdev = &ddata->dssdev;
304 struct omap_dss_device *in = ddata->in;
305 299
306 omapdss_unregister_display(dssdev); 300 omapdss_unregister_display(dssdev);
307 301
308 lb035q02_disable(dssdev); 302 lb035q02_disable(dssdev);
309 lb035q02_disconnect(dssdev); 303 lb035q02_disconnect(dssdev);
310 304
311 omap_dss_put_device(in);
312
313 return 0; 305 return 0;
314} 306}
315 307
diff --git a/drivers/gpu/drm/omapdrm/displays/panel-nec-nl8048hl11.c b/drivers/gpu/drm/omapdrm/displays/panel-nec-nl8048hl11.c
index bf53676263ad..9a3b27fa5cb5 100644
--- a/drivers/gpu/drm/omapdrm/displays/panel-nec-nl8048hl11.c
+++ b/drivers/gpu/drm/omapdrm/displays/panel-nec-nl8048hl11.c
@@ -115,16 +115,25 @@ static int init_nec_8048_wvga_lcd(struct spi_device *spi)
115static int nec_8048_connect(struct omap_dss_device *dssdev) 115static int nec_8048_connect(struct omap_dss_device *dssdev)
116{ 116{
117 struct panel_drv_data *ddata = to_panel_data(dssdev); 117 struct panel_drv_data *ddata = to_panel_data(dssdev);
118 struct omap_dss_device *in = ddata->in; 118 struct omap_dss_device *in;
119 int r; 119 int r;
120 120
121 if (omapdss_device_is_connected(dssdev)) 121 if (omapdss_device_is_connected(dssdev))
122 return 0; 122 return 0;
123 123
124 in = omapdss_of_find_source_for_first_ep(dssdev->dev->of_node);
125 if (IS_ERR(in)) {
126 dev_err(dssdev->dev, "failed to find video source\n");
127 return PTR_ERR(in);
128 }
129
124 r = in->ops.dpi->connect(in, dssdev); 130 r = in->ops.dpi->connect(in, dssdev);
125 if (r) 131 if (r) {
132 omap_dss_put_device(in);
126 return r; 133 return r;
134 }
127 135
136 ddata->in = in;
128 return 0; 137 return 0;
129} 138}
130 139
@@ -137,6 +146,9 @@ static void nec_8048_disconnect(struct omap_dss_device *dssdev)
137 return; 146 return;
138 147
139 in->ops.dpi->disconnect(in, dssdev); 148 in->ops.dpi->disconnect(in, dssdev);
149
150 omap_dss_put_device(in);
151 ddata->in = NULL;
140} 152}
141 153
142static int nec_8048_enable(struct omap_dss_device *dssdev) 154static int nec_8048_enable(struct omap_dss_device *dssdev)
@@ -226,7 +238,6 @@ static int nec_8048_probe_of(struct spi_device *spi)
226{ 238{
227 struct device_node *node = spi->dev.of_node; 239 struct device_node *node = spi->dev.of_node;
228 struct panel_drv_data *ddata = dev_get_drvdata(&spi->dev); 240 struct panel_drv_data *ddata = dev_get_drvdata(&spi->dev);
229 struct omap_dss_device *in;
230 int gpio; 241 int gpio;
231 242
232 gpio = of_get_named_gpio(node, "reset-gpios", 0); 243 gpio = of_get_named_gpio(node, "reset-gpios", 0);
@@ -239,14 +250,6 @@ static int nec_8048_probe_of(struct spi_device *spi)
239 /* XXX the panel spec doesn't mention any QVGA pin?? */ 250 /* XXX the panel spec doesn't mention any QVGA pin?? */
240 ddata->qvga_gpio = -ENOENT; 251 ddata->qvga_gpio = -ENOENT;
241 252
242 in = omapdss_of_find_source_for_first_ep(node);
243 if (IS_ERR(in)) {
244 dev_err(&spi->dev, "failed to find video source\n");
245 return PTR_ERR(in);
246 }
247
248 ddata->in = in;
249
250 return 0; 253 return 0;
251} 254}
252 255
@@ -277,9 +280,6 @@ static int nec_8048_probe(struct spi_device *spi)
277 280
278 ddata->spi = spi; 281 ddata->spi = spi;
279 282
280 if (!spi->dev.of_node)
281 return -ENODEV;
282
283 r = nec_8048_probe_of(spi); 283 r = nec_8048_probe_of(spi);
284 if (r) 284 if (r)
285 return r; 285 return r;
@@ -288,14 +288,14 @@ static int nec_8048_probe(struct spi_device *spi)
288 r = devm_gpio_request_one(&spi->dev, ddata->qvga_gpio, 288 r = devm_gpio_request_one(&spi->dev, ddata->qvga_gpio,
289 GPIOF_OUT_INIT_HIGH, "lcd QVGA"); 289 GPIOF_OUT_INIT_HIGH, "lcd QVGA");
290 if (r) 290 if (r)
291 goto err_gpio; 291 return r;
292 } 292 }
293 293
294 if (gpio_is_valid(ddata->res_gpio)) { 294 if (gpio_is_valid(ddata->res_gpio)) {
295 r = devm_gpio_request_one(&spi->dev, ddata->res_gpio, 295 r = devm_gpio_request_one(&spi->dev, ddata->res_gpio,
296 GPIOF_OUT_INIT_LOW, "lcd RES"); 296 GPIOF_OUT_INIT_LOW, "lcd RES");
297 if (r) 297 if (r)
298 goto err_gpio; 298 return r;
299 } 299 }
300 300
301 ddata->vm = nec_8048_panel_vm; 301 ddata->vm = nec_8048_panel_vm;
@@ -310,22 +310,16 @@ static int nec_8048_probe(struct spi_device *spi)
310 r = omapdss_register_display(dssdev); 310 r = omapdss_register_display(dssdev);
311 if (r) { 311 if (r) {
312 dev_err(&spi->dev, "Failed to register panel\n"); 312 dev_err(&spi->dev, "Failed to register panel\n");
313 goto err_reg; 313 return r;
314 } 314 }
315 315
316 return 0; 316 return 0;
317
318err_reg:
319err_gpio:
320 omap_dss_put_device(ddata->in);
321 return r;
322} 317}
323 318
324static int nec_8048_remove(struct spi_device *spi) 319static int nec_8048_remove(struct spi_device *spi)
325{ 320{
326 struct panel_drv_data *ddata = dev_get_drvdata(&spi->dev); 321 struct panel_drv_data *ddata = dev_get_drvdata(&spi->dev);
327 struct omap_dss_device *dssdev = &ddata->dssdev; 322 struct omap_dss_device *dssdev = &ddata->dssdev;
328 struct omap_dss_device *in = ddata->in;
329 323
330 dev_dbg(&ddata->spi->dev, "%s\n", __func__); 324 dev_dbg(&ddata->spi->dev, "%s\n", __func__);
331 325
@@ -334,8 +328,6 @@ static int nec_8048_remove(struct spi_device *spi)
334 nec_8048_disable(dssdev); 328 nec_8048_disable(dssdev);
335 nec_8048_disconnect(dssdev); 329 nec_8048_disconnect(dssdev);
336 330
337 omap_dss_put_device(in);
338
339 return 0; 331 return 0;
340} 332}
341 333
diff --git a/drivers/gpu/drm/omapdrm/displays/panel-sharp-ls037v7dw01.c b/drivers/gpu/drm/omapdrm/displays/panel-sharp-ls037v7dw01.c
index 34555801fa4c..bb5b680cabfe 100644
--- a/drivers/gpu/drm/omapdrm/displays/panel-sharp-ls037v7dw01.c
+++ b/drivers/gpu/drm/omapdrm/displays/panel-sharp-ls037v7dw01.c
@@ -61,16 +61,25 @@ static const struct videomode sharp_ls_vm = {
61static int sharp_ls_connect(struct omap_dss_device *dssdev) 61static int sharp_ls_connect(struct omap_dss_device *dssdev)
62{ 62{
63 struct panel_drv_data *ddata = to_panel_data(dssdev); 63 struct panel_drv_data *ddata = to_panel_data(dssdev);
64 struct omap_dss_device *in = ddata->in; 64 struct omap_dss_device *in;
65 int r; 65 int r;
66 66
67 if (omapdss_device_is_connected(dssdev)) 67 if (omapdss_device_is_connected(dssdev))
68 return 0; 68 return 0;
69 69
70 in = omapdss_of_find_source_for_first_ep(dssdev->dev->of_node);
71 if (IS_ERR(in)) {
72 dev_err(dssdev->dev, "failed to find video source\n");
73 return PTR_ERR(in);
74 }
75
70 r = in->ops.dpi->connect(in, dssdev); 76 r = in->ops.dpi->connect(in, dssdev);
71 if (r) 77 if (r) {
78 omap_dss_put_device(in);
72 return r; 79 return r;
80 }
73 81
82 ddata->in = in;
74 return 0; 83 return 0;
75} 84}
76 85
@@ -83,6 +92,9 @@ static void sharp_ls_disconnect(struct omap_dss_device *dssdev)
83 return; 92 return;
84 93
85 in->ops.dpi->disconnect(in, dssdev); 94 in->ops.dpi->disconnect(in, dssdev);
95
96 omap_dss_put_device(in);
97 ddata->in = NULL;
86} 98}
87 99
88static int sharp_ls_enable(struct omap_dss_device *dssdev) 100static int sharp_ls_enable(struct omap_dss_device *dssdev)
@@ -210,8 +222,6 @@ static int sharp_ls_get_gpio_of(struct device *dev, int index, int val,
210static int sharp_ls_probe_of(struct platform_device *pdev) 222static int sharp_ls_probe_of(struct platform_device *pdev)
211{ 223{
212 struct panel_drv_data *ddata = platform_get_drvdata(pdev); 224 struct panel_drv_data *ddata = platform_get_drvdata(pdev);
213 struct device_node *node = pdev->dev.of_node;
214 struct omap_dss_device *in;
215 int r; 225 int r;
216 226
217 ddata->vcc = devm_regulator_get(&pdev->dev, "envdd"); 227 ddata->vcc = devm_regulator_get(&pdev->dev, "envdd");
@@ -245,14 +255,6 @@ static int sharp_ls_probe_of(struct platform_device *pdev)
245 if (r) 255 if (r)
246 return r; 256 return r;
247 257
248 in = omapdss_of_find_source_for_first_ep(node);
249 if (IS_ERR(in)) {
250 dev_err(&pdev->dev, "failed to find video source\n");
251 return PTR_ERR(in);
252 }
253
254 ddata->in = in;
255
256 return 0; 258 return 0;
257} 259}
258 260
@@ -268,9 +270,6 @@ static int sharp_ls_probe(struct platform_device *pdev)
268 270
269 platform_set_drvdata(pdev, ddata); 271 platform_set_drvdata(pdev, ddata);
270 272
271 if (!pdev->dev.of_node)
272 return -ENODEV;
273
274 r = sharp_ls_probe_of(pdev); 273 r = sharp_ls_probe_of(pdev);
275 if (r) 274 if (r)
276 return r; 275 return r;
@@ -287,29 +286,22 @@ static int sharp_ls_probe(struct platform_device *pdev)
287 r = omapdss_register_display(dssdev); 286 r = omapdss_register_display(dssdev);
288 if (r) { 287 if (r) {
289 dev_err(&pdev->dev, "Failed to register panel\n"); 288 dev_err(&pdev->dev, "Failed to register panel\n");
290 goto err_reg; 289 return r;
291 } 290 }
292 291
293 return 0; 292 return 0;
294
295err_reg:
296 omap_dss_put_device(ddata->in);
297 return r;
298} 293}
299 294
300static int __exit sharp_ls_remove(struct platform_device *pdev) 295static int __exit sharp_ls_remove(struct platform_device *pdev)
301{ 296{
302 struct panel_drv_data *ddata = platform_get_drvdata(pdev); 297 struct panel_drv_data *ddata = platform_get_drvdata(pdev);
303 struct omap_dss_device *dssdev = &ddata->dssdev; 298 struct omap_dss_device *dssdev = &ddata->dssdev;
304 struct omap_dss_device *in = ddata->in;
305 299
306 omapdss_unregister_display(dssdev); 300 omapdss_unregister_display(dssdev);
307 301
308 sharp_ls_disable(dssdev); 302 sharp_ls_disable(dssdev);
309 sharp_ls_disconnect(dssdev); 303 sharp_ls_disconnect(dssdev);
310 304
311 omap_dss_put_device(in);
312
313 return 0; 305 return 0;
314} 306}
315 307
diff --git a/drivers/gpu/drm/omapdrm/displays/panel-sony-acx565akm.c b/drivers/gpu/drm/omapdrm/displays/panel-sony-acx565akm.c
index 8e5bff4e5226..92fe125ce22e 100644
--- a/drivers/gpu/drm/omapdrm/displays/panel-sony-acx565akm.c
+++ b/drivers/gpu/drm/omapdrm/displays/panel-sony-acx565akm.c
@@ -216,12 +216,12 @@ static void set_display_state(struct panel_drv_data *ddata, int enabled)
216 216
217static int panel_enabled(struct panel_drv_data *ddata) 217static int panel_enabled(struct panel_drv_data *ddata)
218{ 218{
219 __be32 v;
219 u32 disp_status; 220 u32 disp_status;
220 int enabled; 221 int enabled;
221 222
222 acx565akm_read(ddata, MIPID_CMD_READ_DISP_STATUS, 223 acx565akm_read(ddata, MIPID_CMD_READ_DISP_STATUS, (u8 *)&v, 4);
223 (u8 *)&disp_status, 4); 224 disp_status = __be32_to_cpu(v);
224 disp_status = __be32_to_cpu(disp_status);
225 enabled = (disp_status & (1 << 17)) && (disp_status & (1 << 10)); 225 enabled = (disp_status & (1 << 17)) && (disp_status & (1 << 10));
226 dev_dbg(&ddata->spi->dev, 226 dev_dbg(&ddata->spi->dev,
227 "LCD panel %senabled by bootloader (status 0x%04x)\n", 227 "LCD panel %senabled by bootloader (status 0x%04x)\n",
@@ -289,7 +289,7 @@ static void enable_backlight_ctrl(struct panel_drv_data *ddata, int enable)
289 acx565akm_write(ddata, MIPID_CMD_WRITE_CTRL_DISP, (u8 *)&ctrl, 2); 289 acx565akm_write(ddata, MIPID_CMD_WRITE_CTRL_DISP, (u8 *)&ctrl, 2);
290} 290}
291 291
292static void set_cabc_mode(struct panel_drv_data *ddata, unsigned mode) 292static void set_cabc_mode(struct panel_drv_data *ddata, unsigned int mode)
293{ 293{
294 u16 cabc_ctrl; 294 u16 cabc_ctrl;
295 295
@@ -303,12 +303,12 @@ static void set_cabc_mode(struct panel_drv_data *ddata, unsigned mode)
303 acx565akm_write(ddata, MIPID_CMD_WRITE_CABC, (u8 *)&cabc_ctrl, 2); 303 acx565akm_write(ddata, MIPID_CMD_WRITE_CABC, (u8 *)&cabc_ctrl, 2);
304} 304}
305 305
306static unsigned get_cabc_mode(struct panel_drv_data *ddata) 306static unsigned int get_cabc_mode(struct panel_drv_data *ddata)
307{ 307{
308 return ddata->cabc_mode; 308 return ddata->cabc_mode;
309} 309}
310 310
311static unsigned get_hw_cabc_mode(struct panel_drv_data *ddata) 311static unsigned int get_hw_cabc_mode(struct panel_drv_data *ddata)
312{ 312{
313 u8 cabc_ctrl; 313 u8 cabc_ctrl;
314 314
@@ -510,16 +510,25 @@ static const struct attribute_group bldev_attr_group = {
510static int acx565akm_connect(struct omap_dss_device *dssdev) 510static int acx565akm_connect(struct omap_dss_device *dssdev)
511{ 511{
512 struct panel_drv_data *ddata = to_panel_data(dssdev); 512 struct panel_drv_data *ddata = to_panel_data(dssdev);
513 struct omap_dss_device *in = ddata->in; 513 struct omap_dss_device *in;
514 int r; 514 int r;
515 515
516 if (omapdss_device_is_connected(dssdev)) 516 if (omapdss_device_is_connected(dssdev))
517 return 0; 517 return 0;
518 518
519 in = omapdss_of_find_source_for_first_ep(dssdev->dev->of_node);
520 if (IS_ERR(in)) {
521 dev_err(dssdev->dev, "failed to find video source\n");
522 return PTR_ERR(in);
523 }
524
519 r = in->ops.sdi->connect(in, dssdev); 525 r = in->ops.sdi->connect(in, dssdev);
520 if (r) 526 if (r) {
527 omap_dss_put_device(in);
521 return r; 528 return r;
529 }
522 530
531 ddata->in = in;
523 return 0; 532 return 0;
524} 533}
525 534
@@ -532,6 +541,9 @@ static void acx565akm_disconnect(struct omap_dss_device *dssdev)
532 return; 541 return;
533 542
534 in->ops.sdi->disconnect(in, dssdev); 543 in->ops.sdi->disconnect(in, dssdev);
544
545 omap_dss_put_device(in);
546 ddata->in = NULL;
535} 547}
536 548
537static int acx565akm_panel_power_on(struct omap_dss_device *dssdev) 549static int acx565akm_panel_power_on(struct omap_dss_device *dssdev)
@@ -700,12 +712,6 @@ static int acx565akm_probe_of(struct spi_device *spi)
700 712
701 ddata->reset_gpio = of_get_named_gpio(np, "reset-gpios", 0); 713 ddata->reset_gpio = of_get_named_gpio(np, "reset-gpios", 0);
702 714
703 ddata->in = omapdss_of_find_source_for_first_ep(np);
704 if (IS_ERR(ddata->in)) {
705 dev_err(&spi->dev, "failed to find video source\n");
706 return PTR_ERR(ddata->in);
707 }
708
709 return 0; 715 return 0;
710} 716}
711 717
@@ -720,9 +726,6 @@ static int acx565akm_probe(struct spi_device *spi)
720 726
721 dev_dbg(&spi->dev, "%s\n", __func__); 727 dev_dbg(&spi->dev, "%s\n", __func__);
722 728
723 if (!spi->dev.of_node)
724 return -ENODEV;
725
726 spi->mode = SPI_MODE_3; 729 spi->mode = SPI_MODE_3;
727 730
728 ddata = devm_kzalloc(&spi->dev, sizeof(*ddata), GFP_KERNEL); 731 ddata = devm_kzalloc(&spi->dev, sizeof(*ddata), GFP_KERNEL);
@@ -826,7 +829,6 @@ err_sysfs:
826err_reg_bl: 829err_reg_bl:
827err_detect: 830err_detect:
828err_gpio: 831err_gpio:
829 omap_dss_put_device(ddata->in);
830 return r; 832 return r;
831} 833}
832 834
@@ -834,7 +836,6 @@ static int acx565akm_remove(struct spi_device *spi)
834{ 836{
835 struct panel_drv_data *ddata = dev_get_drvdata(&spi->dev); 837 struct panel_drv_data *ddata = dev_get_drvdata(&spi->dev);
836 struct omap_dss_device *dssdev = &ddata->dssdev; 838 struct omap_dss_device *dssdev = &ddata->dssdev;
837 struct omap_dss_device *in = ddata->in;
838 839
839 dev_dbg(&ddata->spi->dev, "%s\n", __func__); 840 dev_dbg(&ddata->spi->dev, "%s\n", __func__);
840 841
@@ -846,8 +847,6 @@ static int acx565akm_remove(struct spi_device *spi)
846 acx565akm_disable(dssdev); 847 acx565akm_disable(dssdev);
847 acx565akm_disconnect(dssdev); 848 acx565akm_disconnect(dssdev);
848 849
849 omap_dss_put_device(in);
850
851 return 0; 850 return 0;
852} 851}
853 852
diff --git a/drivers/gpu/drm/omapdrm/displays/panel-tpo-td028ttec1.c b/drivers/gpu/drm/omapdrm/displays/panel-tpo-td028ttec1.c
index 2721a86ac5e7..b5d8a00df811 100644
--- a/drivers/gpu/drm/omapdrm/displays/panel-tpo-td028ttec1.c
+++ b/drivers/gpu/drm/omapdrm/displays/panel-tpo-td028ttec1.c
@@ -169,16 +169,25 @@ enum jbt_register {
169static int td028ttec1_panel_connect(struct omap_dss_device *dssdev) 169static int td028ttec1_panel_connect(struct omap_dss_device *dssdev)
170{ 170{
171 struct panel_drv_data *ddata = to_panel_data(dssdev); 171 struct panel_drv_data *ddata = to_panel_data(dssdev);
172 struct omap_dss_device *in = ddata->in; 172 struct omap_dss_device *in;
173 int r; 173 int r;
174 174
175 if (omapdss_device_is_connected(dssdev)) 175 if (omapdss_device_is_connected(dssdev))
176 return 0; 176 return 0;
177 177
178 in = omapdss_of_find_source_for_first_ep(dssdev->dev->of_node);
179 if (IS_ERR(in)) {
180 dev_err(dssdev->dev, "failed to find video source\n");
181 return PTR_ERR(in);
182 }
183
178 r = in->ops.dpi->connect(in, dssdev); 184 r = in->ops.dpi->connect(in, dssdev);
179 if (r) 185 if (r) {
186 omap_dss_put_device(in);
180 return r; 187 return r;
188 }
181 189
190 ddata->in = in;
182 return 0; 191 return 0;
183} 192}
184 193
@@ -191,6 +200,9 @@ static void td028ttec1_panel_disconnect(struct omap_dss_device *dssdev)
191 return; 200 return;
192 201
193 in->ops.dpi->disconnect(in, dssdev); 202 in->ops.dpi->disconnect(in, dssdev);
203
204 omap_dss_put_device(in);
205 ddata->in = NULL;
194} 206}
195 207
196static int td028ttec1_panel_enable(struct omap_dss_device *dssdev) 208static int td028ttec1_panel_enable(struct omap_dss_device *dssdev)
@@ -362,23 +374,6 @@ static struct omap_dss_driver td028ttec1_ops = {
362 .check_timings = td028ttec1_panel_check_timings, 374 .check_timings = td028ttec1_panel_check_timings,
363}; 375};
364 376
365static int td028ttec1_probe_of(struct spi_device *spi)
366{
367 struct device_node *node = spi->dev.of_node;
368 struct panel_drv_data *ddata = dev_get_drvdata(&spi->dev);
369 struct omap_dss_device *in;
370
371 in = omapdss_of_find_source_for_first_ep(node);
372 if (IS_ERR(in)) {
373 dev_err(&spi->dev, "failed to find video source\n");
374 return PTR_ERR(in);
375 }
376
377 ddata->in = in;
378
379 return 0;
380}
381
382static int td028ttec1_panel_probe(struct spi_device *spi) 377static int td028ttec1_panel_probe(struct spi_device *spi)
383{ 378{
384 struct panel_drv_data *ddata; 379 struct panel_drv_data *ddata;
@@ -404,13 +399,6 @@ static int td028ttec1_panel_probe(struct spi_device *spi)
404 399
405 ddata->spi_dev = spi; 400 ddata->spi_dev = spi;
406 401
407 if (!spi->dev.of_node)
408 return -ENODEV;
409
410 r = td028ttec1_probe_of(spi);
411 if (r)
412 return r;
413
414 ddata->vm = td028ttec1_panel_vm; 402 ddata->vm = td028ttec1_panel_vm;
415 403
416 dssdev = &ddata->dssdev; 404 dssdev = &ddata->dssdev;
@@ -423,21 +411,16 @@ static int td028ttec1_panel_probe(struct spi_device *spi)
423 r = omapdss_register_display(dssdev); 411 r = omapdss_register_display(dssdev);
424 if (r) { 412 if (r) {
425 dev_err(&spi->dev, "Failed to register panel\n"); 413 dev_err(&spi->dev, "Failed to register panel\n");
426 goto err_reg; 414 return r;
427 } 415 }
428 416
429 return 0; 417 return 0;
430
431err_reg:
432 omap_dss_put_device(ddata->in);
433 return r;
434} 418}
435 419
436static int td028ttec1_panel_remove(struct spi_device *spi) 420static int td028ttec1_panel_remove(struct spi_device *spi)
437{ 421{
438 struct panel_drv_data *ddata = dev_get_drvdata(&spi->dev); 422 struct panel_drv_data *ddata = dev_get_drvdata(&spi->dev);
439 struct omap_dss_device *dssdev = &ddata->dssdev; 423 struct omap_dss_device *dssdev = &ddata->dssdev;
440 struct omap_dss_device *in = ddata->in;
441 424
442 dev_dbg(&ddata->spi_dev->dev, "%s\n", __func__); 425 dev_dbg(&ddata->spi_dev->dev, "%s\n", __func__);
443 426
@@ -446,8 +429,6 @@ static int td028ttec1_panel_remove(struct spi_device *spi)
446 td028ttec1_panel_disable(dssdev); 429 td028ttec1_panel_disable(dssdev);
447 td028ttec1_panel_disconnect(dssdev); 430 td028ttec1_panel_disconnect(dssdev);
448 431
449 omap_dss_put_device(in);
450
451 return 0; 432 return 0;
452} 433}
453 434
diff --git a/drivers/gpu/drm/omapdrm/displays/panel-tpo-td043mtea1.c b/drivers/gpu/drm/omapdrm/displays/panel-tpo-td043mtea1.c
index ac4a6d4d134c..c08e22b43447 100644
--- a/drivers/gpu/drm/omapdrm/displays/panel-tpo-td043mtea1.c
+++ b/drivers/gpu/drm/omapdrm/displays/panel-tpo-td043mtea1.c
@@ -340,16 +340,25 @@ static void tpo_td043_power_off(struct panel_drv_data *ddata)
340static int tpo_td043_connect(struct omap_dss_device *dssdev) 340static int tpo_td043_connect(struct omap_dss_device *dssdev)
341{ 341{
342 struct panel_drv_data *ddata = to_panel_data(dssdev); 342 struct panel_drv_data *ddata = to_panel_data(dssdev);
343 struct omap_dss_device *in = ddata->in; 343 struct omap_dss_device *in;
344 int r; 344 int r;
345 345
346 if (omapdss_device_is_connected(dssdev)) 346 if (omapdss_device_is_connected(dssdev))
347 return 0; 347 return 0;
348 348
349 in = omapdss_of_find_source_for_first_ep(dssdev->dev->of_node);
350 if (IS_ERR(in)) {
351 dev_err(dssdev->dev, "failed to find video source\n");
352 return PTR_ERR(in);
353 }
354
349 r = in->ops.dpi->connect(in, dssdev); 355 r = in->ops.dpi->connect(in, dssdev);
350 if (r) 356 if (r) {
357 omap_dss_put_device(in);
351 return r; 358 return r;
359 }
352 360
361 ddata->in = in;
353 return 0; 362 return 0;
354} 363}
355 364
@@ -362,6 +371,9 @@ static void tpo_td043_disconnect(struct omap_dss_device *dssdev)
362 return; 371 return;
363 372
364 in->ops.dpi->disconnect(in, dssdev); 373 in->ops.dpi->disconnect(in, dssdev);
374
375 omap_dss_put_device(in);
376 ddata->in = NULL;
365} 377}
366 378
367static int tpo_td043_enable(struct omap_dss_device *dssdev) 379static int tpo_td043_enable(struct omap_dss_device *dssdev)
@@ -463,7 +475,6 @@ static int tpo_td043_probe_of(struct spi_device *spi)
463{ 475{
464 struct device_node *node = spi->dev.of_node; 476 struct device_node *node = spi->dev.of_node;
465 struct panel_drv_data *ddata = dev_get_drvdata(&spi->dev); 477 struct panel_drv_data *ddata = dev_get_drvdata(&spi->dev);
466 struct omap_dss_device *in;
467 int gpio; 478 int gpio;
468 479
469 gpio = of_get_named_gpio(node, "reset-gpios", 0); 480 gpio = of_get_named_gpio(node, "reset-gpios", 0);
@@ -473,14 +484,6 @@ static int tpo_td043_probe_of(struct spi_device *spi)
473 } 484 }
474 ddata->nreset_gpio = gpio; 485 ddata->nreset_gpio = gpio;
475 486
476 in = omapdss_of_find_source_for_first_ep(node);
477 if (IS_ERR(in)) {
478 dev_err(&spi->dev, "failed to find video source\n");
479 return PTR_ERR(in);
480 }
481
482 ddata->in = in;
483
484 return 0; 487 return 0;
485} 488}
486 489
@@ -509,9 +512,6 @@ static int tpo_td043_probe(struct spi_device *spi)
509 512
510 ddata->spi = spi; 513 ddata->spi = spi;
511 514
512 if (!spi->dev.of_node)
513 return -ENODEV;
514
515 r = tpo_td043_probe_of(spi); 515 r = tpo_td043_probe_of(spi);
516 if (r) 516 if (r)
517 return r; 517 return r;
@@ -564,7 +564,6 @@ err_reg:
564err_sysfs: 564err_sysfs:
565err_gpio_req: 565err_gpio_req:
566err_regulator: 566err_regulator:
567 omap_dss_put_device(ddata->in);
568 return r; 567 return r;
569} 568}
570 569
@@ -572,7 +571,6 @@ static int tpo_td043_remove(struct spi_device *spi)
572{ 571{
573 struct panel_drv_data *ddata = dev_get_drvdata(&spi->dev); 572 struct panel_drv_data *ddata = dev_get_drvdata(&spi->dev);
574 struct omap_dss_device *dssdev = &ddata->dssdev; 573 struct omap_dss_device *dssdev = &ddata->dssdev;
575 struct omap_dss_device *in = ddata->in;
576 574
577 dev_dbg(&ddata->spi->dev, "%s\n", __func__); 575 dev_dbg(&ddata->spi->dev, "%s\n", __func__);
578 576
@@ -581,8 +579,6 @@ static int tpo_td043_remove(struct spi_device *spi)
581 tpo_td043_disable(dssdev); 579 tpo_td043_disable(dssdev);
582 tpo_td043_disconnect(dssdev); 580 tpo_td043_disconnect(dssdev);
583 581
584 omap_dss_put_device(in);
585
586 sysfs_remove_group(&spi->dev.kobj, &tpo_td043_attr_group); 582 sysfs_remove_group(&spi->dev.kobj, &tpo_td043_attr_group);
587 583
588 return 0; 584 return 0;
diff --git a/drivers/gpu/drm/omapdrm/dss/base.c b/drivers/gpu/drm/omapdrm/dss/base.c
index 67cc87a4f1f6..99e8cb8dc65b 100644
--- a/drivers/gpu/drm/omapdrm/dss/base.c
+++ b/drivers/gpu/drm/omapdrm/dss/base.c
@@ -18,10 +18,11 @@
18#include <linux/of.h> 18#include <linux/of.h>
19#include <linux/of_graph.h> 19#include <linux/of_graph.h>
20#include <linux/list.h> 20#include <linux/list.h>
21
22#include "dss.h"
21#include "omapdss.h" 23#include "omapdss.h"
22 24
23static bool dss_initialized; 25static struct dss_device *dss_device;
24static const struct dispc_ops *ops;
25 26
26static struct list_head omapdss_comp_list; 27static struct list_head omapdss_comp_list;
27 28
@@ -31,27 +32,27 @@ struct omapdss_comp_node {
31 bool dss_core_component; 32 bool dss_core_component;
32}; 33};
33 34
34void omapdss_set_is_initialized(bool set) 35struct dss_device *omapdss_get_dss(void)
35{ 36{
36 dss_initialized = set; 37 return dss_device;
37} 38}
38EXPORT_SYMBOL(omapdss_set_is_initialized); 39EXPORT_SYMBOL(omapdss_get_dss);
39 40
40bool omapdss_is_initialized(void) 41void omapdss_set_dss(struct dss_device *dss)
41{ 42{
42 return dss_initialized; 43 dss_device = dss;
43} 44}
44EXPORT_SYMBOL(omapdss_is_initialized); 45EXPORT_SYMBOL(omapdss_set_dss);
45 46
46void dispc_set_ops(const struct dispc_ops *o) 47struct dispc_device *dispc_get_dispc(struct dss_device *dss)
47{ 48{
48 ops = o; 49 return dss->dispc;
49} 50}
50EXPORT_SYMBOL(dispc_set_ops); 51EXPORT_SYMBOL(dispc_get_dispc);
51 52
52const struct dispc_ops *dispc_get_ops(void) 53const struct dispc_ops *dispc_get_ops(struct dss_device *dss)
53{ 54{
54 return ops; 55 return dss->dispc_ops;
55} 56}
56EXPORT_SYMBOL(dispc_get_ops); 57EXPORT_SYMBOL(dispc_get_ops);
57 58
diff --git a/drivers/gpu/drm/omapdrm/dss/dispc.c b/drivers/gpu/drm/omapdrm/dss/dispc.c
index 4e8f68efd169..5e2e65e88847 100644
--- a/drivers/gpu/drm/omapdrm/dss/dispc.c
+++ b/drivers/gpu/drm/omapdrm/dss/dispc.c
@@ -47,6 +47,8 @@
47#include "dss.h" 47#include "dss.h"
48#include "dispc.h" 48#include "dispc.h"
49 49
50struct dispc_device;
51
50/* DISPC */ 52/* DISPC */
51#define DISPC_SZ_REGS SZ_4K 53#define DISPC_SZ_REGS SZ_4K
52 54
@@ -56,11 +58,12 @@ enum omap_burst_size {
56 BURST_SIZE_X8 = 2, 58 BURST_SIZE_X8 = 2,
57}; 59};
58 60
59#define REG_GET(idx, start, end) \ 61#define REG_GET(dispc, idx, start, end) \
60 FLD_GET(dispc_read_reg(idx), start, end) 62 FLD_GET(dispc_read_reg(dispc, idx), start, end)
61 63
62#define REG_FLD_MOD(idx, val, start, end) \ 64#define REG_FLD_MOD(dispc, idx, val, start, end) \
63 dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end)) 65 dispc_write_reg(dispc, idx, \
66 FLD_MOD(dispc_read_reg(dispc, idx), val, start, end))
64 67
65/* DISPC has feature id */ 68/* DISPC has feature id */
66enum dispc_feature_id { 69enum dispc_feature_id {
@@ -105,7 +108,8 @@ struct dispc_features {
105 unsigned int max_downscale; 108 unsigned int max_downscale;
106 unsigned int max_line_width; 109 unsigned int max_line_width;
107 unsigned int min_pcd; 110 unsigned int min_pcd;
108 int (*calc_scaling) (unsigned long pclk, unsigned long lclk, 111 int (*calc_scaling)(struct dispc_device *dispc,
112 unsigned long pclk, unsigned long lclk,
109 const struct videomode *vm, 113 const struct videomode *vm,
110 u16 width, u16 height, u16 out_width, u16 out_height, 114 u16 width, u16 height, u16 out_width, u16 out_height,
111 u32 fourcc, bool *five_taps, 115 u32 fourcc, bool *five_taps,
@@ -162,9 +166,12 @@ struct dispc_features {
162#define DISPC_MAX_NR_FIFOS 5 166#define DISPC_MAX_NR_FIFOS 5
163#define DISPC_MAX_CHANNEL_GAMMA 4 167#define DISPC_MAX_CHANNEL_GAMMA 4
164 168
165static struct { 169struct dispc_device {
166 struct platform_device *pdev; 170 struct platform_device *pdev;
167 void __iomem *base; 171 void __iomem *base;
172 struct dss_device *dss;
173
174 struct dss_debugfs_entry *debugfs;
168 175
169 int irq; 176 int irq;
170 irq_handler_t user_handler; 177 irq_handler_t user_handler;
@@ -191,7 +198,7 @@ static struct {
191 198
192 /* DISPC_CONTROL & DISPC_CONFIG lock*/ 199 /* DISPC_CONTROL & DISPC_CONFIG lock*/
193 spinlock_t control_lock; 200 spinlock_t control_lock;
194} dispc; 201};
195 202
196enum omap_color_component { 203enum omap_color_component {
197 /* used for all color formats for OMAP3 and earlier 204 /* used for all color formats for OMAP3 and earlier
@@ -345,313 +352,315 @@ static const struct {
345 }, 352 },
346}; 353};
347 354
348struct color_conv_coef { 355static unsigned long dispc_fclk_rate(struct dispc_device *dispc);
349 int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb; 356static unsigned long dispc_core_clk_rate(struct dispc_device *dispc);
350 int full_range; 357static unsigned long dispc_mgr_lclk_rate(struct dispc_device *dispc,
351}; 358 enum omap_channel channel);
352 359static unsigned long dispc_mgr_pclk_rate(struct dispc_device *dispc,
353static unsigned long dispc_fclk_rate(void); 360 enum omap_channel channel);
354static unsigned long dispc_core_clk_rate(void);
355static unsigned long dispc_mgr_lclk_rate(enum omap_channel channel);
356static unsigned long dispc_mgr_pclk_rate(enum omap_channel channel);
357 361
358static unsigned long dispc_plane_pclk_rate(enum omap_plane_id plane); 362static unsigned long dispc_plane_pclk_rate(struct dispc_device *dispc,
359static unsigned long dispc_plane_lclk_rate(enum omap_plane_id plane); 363 enum omap_plane_id plane);
364static unsigned long dispc_plane_lclk_rate(struct dispc_device *dispc,
365 enum omap_plane_id plane);
360 366
361static void dispc_clear_irqstatus(u32 mask); 367static void dispc_clear_irqstatus(struct dispc_device *dispc, u32 mask);
362static bool dispc_mgr_is_enabled(enum omap_channel channel);
363static void dispc_clear_irqstatus(u32 mask);
364 368
365static inline void dispc_write_reg(const u16 idx, u32 val) 369static inline void dispc_write_reg(struct dispc_device *dispc, u16 idx, u32 val)
366{ 370{
367 __raw_writel(val, dispc.base + idx); 371 __raw_writel(val, dispc->base + idx);
368} 372}
369 373
370static inline u32 dispc_read_reg(const u16 idx) 374static inline u32 dispc_read_reg(struct dispc_device *dispc, u16 idx)
371{ 375{
372 return __raw_readl(dispc.base + idx); 376 return __raw_readl(dispc->base + idx);
373} 377}
374 378
375static u32 mgr_fld_read(enum omap_channel channel, enum mgr_reg_fields regfld) 379static u32 mgr_fld_read(struct dispc_device *dispc, enum omap_channel channel,
380 enum mgr_reg_fields regfld)
376{ 381{
377 const struct dispc_reg_field rfld = mgr_desc[channel].reg_desc[regfld]; 382 const struct dispc_reg_field rfld = mgr_desc[channel].reg_desc[regfld];
378 return REG_GET(rfld.reg, rfld.high, rfld.low); 383
384 return REG_GET(dispc, rfld.reg, rfld.high, rfld.low);
379} 385}
380 386
381static void mgr_fld_write(enum omap_channel channel, 387static void mgr_fld_write(struct dispc_device *dispc, enum omap_channel channel,
382 enum mgr_reg_fields regfld, int val) { 388 enum mgr_reg_fields regfld, int val)
389{
383 const struct dispc_reg_field rfld = mgr_desc[channel].reg_desc[regfld]; 390 const struct dispc_reg_field rfld = mgr_desc[channel].reg_desc[regfld];
384 const bool need_lock = rfld.reg == DISPC_CONTROL || rfld.reg == DISPC_CONFIG; 391 const bool need_lock = rfld.reg == DISPC_CONTROL || rfld.reg == DISPC_CONFIG;
385 unsigned long flags; 392 unsigned long flags;
386 393
387 if (need_lock) 394 if (need_lock) {
388 spin_lock_irqsave(&dispc.control_lock, flags); 395 spin_lock_irqsave(&dispc->control_lock, flags);
389 396 REG_FLD_MOD(dispc, rfld.reg, val, rfld.high, rfld.low);
390 REG_FLD_MOD(rfld.reg, val, rfld.high, rfld.low); 397 spin_unlock_irqrestore(&dispc->control_lock, flags);
391 398 } else {
392 if (need_lock) 399 REG_FLD_MOD(dispc, rfld.reg, val, rfld.high, rfld.low);
393 spin_unlock_irqrestore(&dispc.control_lock, flags); 400 }
394} 401}
395 402
396static int dispc_get_num_ovls(void) 403static int dispc_get_num_ovls(struct dispc_device *dispc)
397{ 404{
398 return dispc.feat->num_ovls; 405 return dispc->feat->num_ovls;
399} 406}
400 407
401static int dispc_get_num_mgrs(void) 408static int dispc_get_num_mgrs(struct dispc_device *dispc)
402{ 409{
403 return dispc.feat->num_mgrs; 410 return dispc->feat->num_mgrs;
404} 411}
405 412
406static void dispc_get_reg_field(enum dispc_feat_reg_field id, 413static void dispc_get_reg_field(struct dispc_device *dispc,
414 enum dispc_feat_reg_field id,
407 u8 *start, u8 *end) 415 u8 *start, u8 *end)
408{ 416{
409 if (id >= dispc.feat->num_reg_fields) 417 if (id >= dispc->feat->num_reg_fields)
410 BUG(); 418 BUG();
411 419
412 *start = dispc.feat->reg_fields[id].start; 420 *start = dispc->feat->reg_fields[id].start;
413 *end = dispc.feat->reg_fields[id].end; 421 *end = dispc->feat->reg_fields[id].end;
414} 422}
415 423
416static bool dispc_has_feature(enum dispc_feature_id id) 424static bool dispc_has_feature(struct dispc_device *dispc,
425 enum dispc_feature_id id)
417{ 426{
418 unsigned int i; 427 unsigned int i;
419 428
420 for (i = 0; i < dispc.feat->num_features; i++) { 429 for (i = 0; i < dispc->feat->num_features; i++) {
421 if (dispc.feat->features[i] == id) 430 if (dispc->feat->features[i] == id)
422 return true; 431 return true;
423 } 432 }
424 433
425 return false; 434 return false;
426} 435}
427 436
428#define SR(reg) \ 437#define SR(dispc, reg) \
429 dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg) 438 dispc->ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(dispc, DISPC_##reg)
430#define RR(reg) \ 439#define RR(dispc, reg) \
431 dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)]) 440 dispc_write_reg(dispc, DISPC_##reg, dispc->ctx[DISPC_##reg / sizeof(u32)])
432 441
433static void dispc_save_context(void) 442static void dispc_save_context(struct dispc_device *dispc)
434{ 443{
435 int i, j; 444 int i, j;
436 445
437 DSSDBG("dispc_save_context\n"); 446 DSSDBG("dispc_save_context\n");
438 447
439 SR(IRQENABLE); 448 SR(dispc, IRQENABLE);
440 SR(CONTROL); 449 SR(dispc, CONTROL);
441 SR(CONFIG); 450 SR(dispc, CONFIG);
442 SR(LINE_NUMBER); 451 SR(dispc, LINE_NUMBER);
443 if (dispc_has_feature(FEAT_ALPHA_FIXED_ZORDER) || 452 if (dispc_has_feature(dispc, FEAT_ALPHA_FIXED_ZORDER) ||
444 dispc_has_feature(FEAT_ALPHA_FREE_ZORDER)) 453 dispc_has_feature(dispc, FEAT_ALPHA_FREE_ZORDER))
445 SR(GLOBAL_ALPHA); 454 SR(dispc, GLOBAL_ALPHA);
446 if (dispc_has_feature(FEAT_MGR_LCD2)) { 455 if (dispc_has_feature(dispc, FEAT_MGR_LCD2)) {
447 SR(CONTROL2); 456 SR(dispc, CONTROL2);
448 SR(CONFIG2); 457 SR(dispc, CONFIG2);
449 } 458 }
450 if (dispc_has_feature(FEAT_MGR_LCD3)) { 459 if (dispc_has_feature(dispc, FEAT_MGR_LCD3)) {
451 SR(CONTROL3); 460 SR(dispc, CONTROL3);
452 SR(CONFIG3); 461 SR(dispc, CONFIG3);
453 } 462 }
454 463
455 for (i = 0; i < dispc_get_num_mgrs(); i++) { 464 for (i = 0; i < dispc_get_num_mgrs(dispc); i++) {
456 SR(DEFAULT_COLOR(i)); 465 SR(dispc, DEFAULT_COLOR(i));
457 SR(TRANS_COLOR(i)); 466 SR(dispc, TRANS_COLOR(i));
458 SR(SIZE_MGR(i)); 467 SR(dispc, SIZE_MGR(i));
459 if (i == OMAP_DSS_CHANNEL_DIGIT) 468 if (i == OMAP_DSS_CHANNEL_DIGIT)
460 continue; 469 continue;
461 SR(TIMING_H(i)); 470 SR(dispc, TIMING_H(i));
462 SR(TIMING_V(i)); 471 SR(dispc, TIMING_V(i));
463 SR(POL_FREQ(i)); 472 SR(dispc, POL_FREQ(i));
464 SR(DIVISORo(i)); 473 SR(dispc, DIVISORo(i));
465 474
466 SR(DATA_CYCLE1(i)); 475 SR(dispc, DATA_CYCLE1(i));
467 SR(DATA_CYCLE2(i)); 476 SR(dispc, DATA_CYCLE2(i));
468 SR(DATA_CYCLE3(i)); 477 SR(dispc, DATA_CYCLE3(i));
469 478
470 if (dispc_has_feature(FEAT_CPR)) { 479 if (dispc_has_feature(dispc, FEAT_CPR)) {
471 SR(CPR_COEF_R(i)); 480 SR(dispc, CPR_COEF_R(i));
472 SR(CPR_COEF_G(i)); 481 SR(dispc, CPR_COEF_G(i));
473 SR(CPR_COEF_B(i)); 482 SR(dispc, CPR_COEF_B(i));
474 } 483 }
475 } 484 }
476 485
477 for (i = 0; i < dispc_get_num_ovls(); i++) { 486 for (i = 0; i < dispc_get_num_ovls(dispc); i++) {
478 SR(OVL_BA0(i)); 487 SR(dispc, OVL_BA0(i));
479 SR(OVL_BA1(i)); 488 SR(dispc, OVL_BA1(i));
480 SR(OVL_POSITION(i)); 489 SR(dispc, OVL_POSITION(i));
481 SR(OVL_SIZE(i)); 490 SR(dispc, OVL_SIZE(i));
482 SR(OVL_ATTRIBUTES(i)); 491 SR(dispc, OVL_ATTRIBUTES(i));
483 SR(OVL_FIFO_THRESHOLD(i)); 492 SR(dispc, OVL_FIFO_THRESHOLD(i));
484 SR(OVL_ROW_INC(i)); 493 SR(dispc, OVL_ROW_INC(i));
485 SR(OVL_PIXEL_INC(i)); 494 SR(dispc, OVL_PIXEL_INC(i));
486 if (dispc_has_feature(FEAT_PRELOAD)) 495 if (dispc_has_feature(dispc, FEAT_PRELOAD))
487 SR(OVL_PRELOAD(i)); 496 SR(dispc, OVL_PRELOAD(i));
488 if (i == OMAP_DSS_GFX) { 497 if (i == OMAP_DSS_GFX) {
489 SR(OVL_WINDOW_SKIP(i)); 498 SR(dispc, OVL_WINDOW_SKIP(i));
490 SR(OVL_TABLE_BA(i)); 499 SR(dispc, OVL_TABLE_BA(i));
491 continue; 500 continue;
492 } 501 }
493 SR(OVL_FIR(i)); 502 SR(dispc, OVL_FIR(i));
494 SR(OVL_PICTURE_SIZE(i)); 503 SR(dispc, OVL_PICTURE_SIZE(i));
495 SR(OVL_ACCU0(i)); 504 SR(dispc, OVL_ACCU0(i));
496 SR(OVL_ACCU1(i)); 505 SR(dispc, OVL_ACCU1(i));
497 506
498 for (j = 0; j < 8; j++) 507 for (j = 0; j < 8; j++)
499 SR(OVL_FIR_COEF_H(i, j)); 508 SR(dispc, OVL_FIR_COEF_H(i, j));
500 509
501 for (j = 0; j < 8; j++) 510 for (j = 0; j < 8; j++)
502 SR(OVL_FIR_COEF_HV(i, j)); 511 SR(dispc, OVL_FIR_COEF_HV(i, j));
503 512
504 for (j = 0; j < 5; j++) 513 for (j = 0; j < 5; j++)
505 SR(OVL_CONV_COEF(i, j)); 514 SR(dispc, OVL_CONV_COEF(i, j));
506 515
507 if (dispc_has_feature(FEAT_FIR_COEF_V)) { 516 if (dispc_has_feature(dispc, FEAT_FIR_COEF_V)) {
508 for (j = 0; j < 8; j++) 517 for (j = 0; j < 8; j++)
509 SR(OVL_FIR_COEF_V(i, j)); 518 SR(dispc, OVL_FIR_COEF_V(i, j));
510 } 519 }
511 520
512 if (dispc_has_feature(FEAT_HANDLE_UV_SEPARATE)) { 521 if (dispc_has_feature(dispc, FEAT_HANDLE_UV_SEPARATE)) {
513 SR(OVL_BA0_UV(i)); 522 SR(dispc, OVL_BA0_UV(i));
514 SR(OVL_BA1_UV(i)); 523 SR(dispc, OVL_BA1_UV(i));
515 SR(OVL_FIR2(i)); 524 SR(dispc, OVL_FIR2(i));
516 SR(OVL_ACCU2_0(i)); 525 SR(dispc, OVL_ACCU2_0(i));
517 SR(OVL_ACCU2_1(i)); 526 SR(dispc, OVL_ACCU2_1(i));
518 527
519 for (j = 0; j < 8; j++) 528 for (j = 0; j < 8; j++)
520 SR(OVL_FIR_COEF_H2(i, j)); 529 SR(dispc, OVL_FIR_COEF_H2(i, j));
521 530
522 for (j = 0; j < 8; j++) 531 for (j = 0; j < 8; j++)
523 SR(OVL_FIR_COEF_HV2(i, j)); 532 SR(dispc, OVL_FIR_COEF_HV2(i, j));
524 533
525 for (j = 0; j < 8; j++) 534 for (j = 0; j < 8; j++)
526 SR(OVL_FIR_COEF_V2(i, j)); 535 SR(dispc, OVL_FIR_COEF_V2(i, j));
527 } 536 }
528 if (dispc_has_feature(FEAT_ATTR2)) 537 if (dispc_has_feature(dispc, FEAT_ATTR2))
529 SR(OVL_ATTRIBUTES2(i)); 538 SR(dispc, OVL_ATTRIBUTES2(i));
530 } 539 }
531 540
532 if (dispc_has_feature(FEAT_CORE_CLK_DIV)) 541 if (dispc_has_feature(dispc, FEAT_CORE_CLK_DIV))
533 SR(DIVISOR); 542 SR(dispc, DIVISOR);
534 543
535 dispc.ctx_valid = true; 544 dispc->ctx_valid = true;
536 545
537 DSSDBG("context saved\n"); 546 DSSDBG("context saved\n");
538} 547}
539 548
540static void dispc_restore_context(void) 549static void dispc_restore_context(struct dispc_device *dispc)
541{ 550{
542 int i, j; 551 int i, j;
543 552
544 DSSDBG("dispc_restore_context\n"); 553 DSSDBG("dispc_restore_context\n");
545 554
546 if (!dispc.ctx_valid) 555 if (!dispc->ctx_valid)
547 return; 556 return;
548 557
549 /*RR(IRQENABLE);*/ 558 /*RR(dispc, IRQENABLE);*/
550 /*RR(CONTROL);*/ 559 /*RR(dispc, CONTROL);*/
551 RR(CONFIG); 560 RR(dispc, CONFIG);
552 RR(LINE_NUMBER); 561 RR(dispc, LINE_NUMBER);
553 if (dispc_has_feature(FEAT_ALPHA_FIXED_ZORDER) || 562 if (dispc_has_feature(dispc, FEAT_ALPHA_FIXED_ZORDER) ||
554 dispc_has_feature(FEAT_ALPHA_FREE_ZORDER)) 563 dispc_has_feature(dispc, FEAT_ALPHA_FREE_ZORDER))
555 RR(GLOBAL_ALPHA); 564 RR(dispc, GLOBAL_ALPHA);
556 if (dispc_has_feature(FEAT_MGR_LCD2)) 565 if (dispc_has_feature(dispc, FEAT_MGR_LCD2))
557 RR(CONFIG2); 566 RR(dispc, CONFIG2);
558 if (dispc_has_feature(FEAT_MGR_LCD3)) 567 if (dispc_has_feature(dispc, FEAT_MGR_LCD3))
559 RR(CONFIG3); 568 RR(dispc, CONFIG3);
560 569
561 for (i = 0; i < dispc_get_num_mgrs(); i++) { 570 for (i = 0; i < dispc_get_num_mgrs(dispc); i++) {
562 RR(DEFAULT_COLOR(i)); 571 RR(dispc, DEFAULT_COLOR(i));
563 RR(TRANS_COLOR(i)); 572 RR(dispc, TRANS_COLOR(i));
564 RR(SIZE_MGR(i)); 573 RR(dispc, SIZE_MGR(i));
565 if (i == OMAP_DSS_CHANNEL_DIGIT) 574 if (i == OMAP_DSS_CHANNEL_DIGIT)
566 continue; 575 continue;
567 RR(TIMING_H(i)); 576 RR(dispc, TIMING_H(i));
568 RR(TIMING_V(i)); 577 RR(dispc, TIMING_V(i));
569 RR(POL_FREQ(i)); 578 RR(dispc, POL_FREQ(i));
570 RR(DIVISORo(i)); 579 RR(dispc, DIVISORo(i));
571 580
572 RR(DATA_CYCLE1(i)); 581 RR(dispc, DATA_CYCLE1(i));
573 RR(DATA_CYCLE2(i)); 582 RR(dispc, DATA_CYCLE2(i));
574 RR(DATA_CYCLE3(i)); 583 RR(dispc, DATA_CYCLE3(i));
575 584
576 if (dispc_has_feature(FEAT_CPR)) { 585 if (dispc_has_feature(dispc, FEAT_CPR)) {
577 RR(CPR_COEF_R(i)); 586 RR(dispc, CPR_COEF_R(i));
578 RR(CPR_COEF_G(i)); 587 RR(dispc, CPR_COEF_G(i));
579 RR(CPR_COEF_B(i)); 588 RR(dispc, CPR_COEF_B(i));
580 } 589 }
581 } 590 }
582 591
583 for (i = 0; i < dispc_get_num_ovls(); i++) { 592 for (i = 0; i < dispc_get_num_ovls(dispc); i++) {
584 RR(OVL_BA0(i)); 593 RR(dispc, OVL_BA0(i));
585 RR(OVL_BA1(i)); 594 RR(dispc, OVL_BA1(i));
586 RR(OVL_POSITION(i)); 595 RR(dispc, OVL_POSITION(i));
587 RR(OVL_SIZE(i)); 596 RR(dispc, OVL_SIZE(i));
588 RR(OVL_ATTRIBUTES(i)); 597 RR(dispc, OVL_ATTRIBUTES(i));
589 RR(OVL_FIFO_THRESHOLD(i)); 598 RR(dispc, OVL_FIFO_THRESHOLD(i));
590 RR(OVL_ROW_INC(i)); 599 RR(dispc, OVL_ROW_INC(i));
591 RR(OVL_PIXEL_INC(i)); 600 RR(dispc, OVL_PIXEL_INC(i));
592 if (dispc_has_feature(FEAT_PRELOAD)) 601 if (dispc_has_feature(dispc, FEAT_PRELOAD))
593 RR(OVL_PRELOAD(i)); 602 RR(dispc, OVL_PRELOAD(i));
594 if (i == OMAP_DSS_GFX) { 603 if (i == OMAP_DSS_GFX) {
595 RR(OVL_WINDOW_SKIP(i)); 604 RR(dispc, OVL_WINDOW_SKIP(i));
596 RR(OVL_TABLE_BA(i)); 605 RR(dispc, OVL_TABLE_BA(i));
597 continue; 606 continue;
598 } 607 }
599 RR(OVL_FIR(i)); 608 RR(dispc, OVL_FIR(i));
600 RR(OVL_PICTURE_SIZE(i)); 609 RR(dispc, OVL_PICTURE_SIZE(i));
601 RR(OVL_ACCU0(i)); 610 RR(dispc, OVL_ACCU0(i));
602 RR(OVL_ACCU1(i)); 611 RR(dispc, OVL_ACCU1(i));
603 612
604 for (j = 0; j < 8; j++) 613 for (j = 0; j < 8; j++)
605 RR(OVL_FIR_COEF_H(i, j)); 614 RR(dispc, OVL_FIR_COEF_H(i, j));
606 615
607 for (j = 0; j < 8; j++) 616 for (j = 0; j < 8; j++)
608 RR(OVL_FIR_COEF_HV(i, j)); 617 RR(dispc, OVL_FIR_COEF_HV(i, j));
609 618
610 for (j = 0; j < 5; j++) 619 for (j = 0; j < 5; j++)
611 RR(OVL_CONV_COEF(i, j)); 620 RR(dispc, OVL_CONV_COEF(i, j));
612 621
613 if (dispc_has_feature(FEAT_FIR_COEF_V)) { 622 if (dispc_has_feature(dispc, FEAT_FIR_COEF_V)) {
614 for (j = 0; j < 8; j++) 623 for (j = 0; j < 8; j++)
615 RR(OVL_FIR_COEF_V(i, j)); 624 RR(dispc, OVL_FIR_COEF_V(i, j));
616 } 625 }
617 626
618 if (dispc_has_feature(FEAT_HANDLE_UV_SEPARATE)) { 627 if (dispc_has_feature(dispc, FEAT_HANDLE_UV_SEPARATE)) {
619 RR(OVL_BA0_UV(i)); 628 RR(dispc, OVL_BA0_UV(i));
620 RR(OVL_BA1_UV(i)); 629 RR(dispc, OVL_BA1_UV(i));
621 RR(OVL_FIR2(i)); 630 RR(dispc, OVL_FIR2(i));
622 RR(OVL_ACCU2_0(i)); 631 RR(dispc, OVL_ACCU2_0(i));
623 RR(OVL_ACCU2_1(i)); 632 RR(dispc, OVL_ACCU2_1(i));
624 633
625 for (j = 0; j < 8; j++) 634 for (j = 0; j < 8; j++)
626 RR(OVL_FIR_COEF_H2(i, j)); 635 RR(dispc, OVL_FIR_COEF_H2(i, j));
627 636
628 for (j = 0; j < 8; j++) 637 for (j = 0; j < 8; j++)
629 RR(OVL_FIR_COEF_HV2(i, j)); 638 RR(dispc, OVL_FIR_COEF_HV2(i, j));
630 639
631 for (j = 0; j < 8; j++) 640 for (j = 0; j < 8; j++)
632 RR(OVL_FIR_COEF_V2(i, j)); 641 RR(dispc, OVL_FIR_COEF_V2(i, j));
633 } 642 }
634 if (dispc_has_feature(FEAT_ATTR2)) 643 if (dispc_has_feature(dispc, FEAT_ATTR2))
635 RR(OVL_ATTRIBUTES2(i)); 644 RR(dispc, OVL_ATTRIBUTES2(i));
636 } 645 }
637 646
638 if (dispc_has_feature(FEAT_CORE_CLK_DIV)) 647 if (dispc_has_feature(dispc, FEAT_CORE_CLK_DIV))
639 RR(DIVISOR); 648 RR(dispc, DIVISOR);
640 649
641 /* enable last, because LCD & DIGIT enable are here */ 650 /* enable last, because LCD & DIGIT enable are here */
642 RR(CONTROL); 651 RR(dispc, CONTROL);
643 if (dispc_has_feature(FEAT_MGR_LCD2)) 652 if (dispc_has_feature(dispc, FEAT_MGR_LCD2))
644 RR(CONTROL2); 653 RR(dispc, CONTROL2);
645 if (dispc_has_feature(FEAT_MGR_LCD3)) 654 if (dispc_has_feature(dispc, FEAT_MGR_LCD3))
646 RR(CONTROL3); 655 RR(dispc, CONTROL3);
647 /* clear spurious SYNC_LOST_DIGIT interrupts */ 656 /* clear spurious SYNC_LOST_DIGIT interrupts */
648 dispc_clear_irqstatus(DISPC_IRQ_SYNC_LOST_DIGIT); 657 dispc_clear_irqstatus(dispc, DISPC_IRQ_SYNC_LOST_DIGIT);
649 658
650 /* 659 /*
651 * enable last so IRQs won't trigger before 660 * enable last so IRQs won't trigger before
652 * the context is fully restored 661 * the context is fully restored
653 */ 662 */
654 RR(IRQENABLE); 663 RR(dispc, IRQENABLE);
655 664
656 DSSDBG("context restored\n"); 665 DSSDBG("context restored\n");
657} 666}
@@ -659,146 +668,159 @@ static void dispc_restore_context(void)
659#undef SR 668#undef SR
660#undef RR 669#undef RR
661 670
662int dispc_runtime_get(void) 671int dispc_runtime_get(struct dispc_device *dispc)
663{ 672{
664 int r; 673 int r;
665 674
666 DSSDBG("dispc_runtime_get\n"); 675 DSSDBG("dispc_runtime_get\n");
667 676
668 r = pm_runtime_get_sync(&dispc.pdev->dev); 677 r = pm_runtime_get_sync(&dispc->pdev->dev);
669 WARN_ON(r < 0); 678 WARN_ON(r < 0);
670 return r < 0 ? r : 0; 679 return r < 0 ? r : 0;
671} 680}
672 681
673void dispc_runtime_put(void) 682void dispc_runtime_put(struct dispc_device *dispc)
674{ 683{
675 int r; 684 int r;
676 685
677 DSSDBG("dispc_runtime_put\n"); 686 DSSDBG("dispc_runtime_put\n");
678 687
679 r = pm_runtime_put_sync(&dispc.pdev->dev); 688 r = pm_runtime_put_sync(&dispc->pdev->dev);
680 WARN_ON(r < 0 && r != -ENOSYS); 689 WARN_ON(r < 0 && r != -ENOSYS);
681} 690}
682 691
683static u32 dispc_mgr_get_vsync_irq(enum omap_channel channel) 692static u32 dispc_mgr_get_vsync_irq(struct dispc_device *dispc,
693 enum omap_channel channel)
684{ 694{
685 return mgr_desc[channel].vsync_irq; 695 return mgr_desc[channel].vsync_irq;
686} 696}
687 697
688static u32 dispc_mgr_get_framedone_irq(enum omap_channel channel) 698static u32 dispc_mgr_get_framedone_irq(struct dispc_device *dispc,
699 enum omap_channel channel)
689{ 700{
690 if (channel == OMAP_DSS_CHANNEL_DIGIT && dispc.feat->no_framedone_tv) 701 if (channel == OMAP_DSS_CHANNEL_DIGIT && dispc->feat->no_framedone_tv)
691 return 0; 702 return 0;
692 703
693 return mgr_desc[channel].framedone_irq; 704 return mgr_desc[channel].framedone_irq;
694} 705}
695 706
696static u32 dispc_mgr_get_sync_lost_irq(enum omap_channel channel) 707static u32 dispc_mgr_get_sync_lost_irq(struct dispc_device *dispc,
708 enum omap_channel channel)
697{ 709{
698 return mgr_desc[channel].sync_lost_irq; 710 return mgr_desc[channel].sync_lost_irq;
699} 711}
700 712
701u32 dispc_wb_get_framedone_irq(void) 713static u32 dispc_wb_get_framedone_irq(struct dispc_device *dispc)
702{ 714{
703 return DISPC_IRQ_FRAMEDONEWB; 715 return DISPC_IRQ_FRAMEDONEWB;
704} 716}
705 717
706static void dispc_mgr_enable(enum omap_channel channel, bool enable) 718static void dispc_mgr_enable(struct dispc_device *dispc,
719 enum omap_channel channel, bool enable)
707{ 720{
708 mgr_fld_write(channel, DISPC_MGR_FLD_ENABLE, enable); 721 mgr_fld_write(dispc, channel, DISPC_MGR_FLD_ENABLE, enable);
709 /* flush posted write */ 722 /* flush posted write */
710 mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE); 723 mgr_fld_read(dispc, channel, DISPC_MGR_FLD_ENABLE);
711} 724}
712 725
713static bool dispc_mgr_is_enabled(enum omap_channel channel) 726static bool dispc_mgr_is_enabled(struct dispc_device *dispc,
727 enum omap_channel channel)
714{ 728{
715 return !!mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE); 729 return !!mgr_fld_read(dispc, channel, DISPC_MGR_FLD_ENABLE);
716} 730}
717 731
718static bool dispc_mgr_go_busy(enum omap_channel channel) 732static bool dispc_mgr_go_busy(struct dispc_device *dispc,
733 enum omap_channel channel)
719{ 734{
720 return mgr_fld_read(channel, DISPC_MGR_FLD_GO) == 1; 735 return mgr_fld_read(dispc, channel, DISPC_MGR_FLD_GO) == 1;
721} 736}
722 737
723static void dispc_mgr_go(enum omap_channel channel) 738static void dispc_mgr_go(struct dispc_device *dispc, enum omap_channel channel)
724{ 739{
725 WARN_ON(!dispc_mgr_is_enabled(channel)); 740 WARN_ON(!dispc_mgr_is_enabled(dispc, channel));
726 WARN_ON(dispc_mgr_go_busy(channel)); 741 WARN_ON(dispc_mgr_go_busy(dispc, channel));
727 742
728 DSSDBG("GO %s\n", mgr_desc[channel].name); 743 DSSDBG("GO %s\n", mgr_desc[channel].name);
729 744
730 mgr_fld_write(channel, DISPC_MGR_FLD_GO, 1); 745 mgr_fld_write(dispc, channel, DISPC_MGR_FLD_GO, 1);
731} 746}
732 747
733bool dispc_wb_go_busy(void) 748static bool dispc_wb_go_busy(struct dispc_device *dispc)
734{ 749{
735 return REG_GET(DISPC_CONTROL2, 6, 6) == 1; 750 return REG_GET(dispc, DISPC_CONTROL2, 6, 6) == 1;
736} 751}
737 752
738void dispc_wb_go(void) 753static void dispc_wb_go(struct dispc_device *dispc)
739{ 754{
740 enum omap_plane_id plane = OMAP_DSS_WB; 755 enum omap_plane_id plane = OMAP_DSS_WB;
741 bool enable, go; 756 bool enable, go;
742 757
743 enable = REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0) == 1; 758 enable = REG_GET(dispc, DISPC_OVL_ATTRIBUTES(plane), 0, 0) == 1;
744 759
745 if (!enable) 760 if (!enable)
746 return; 761 return;
747 762
748 go = REG_GET(DISPC_CONTROL2, 6, 6) == 1; 763 go = REG_GET(dispc, DISPC_CONTROL2, 6, 6) == 1;
749 if (go) { 764 if (go) {
750 DSSERR("GO bit not down for WB\n"); 765 DSSERR("GO bit not down for WB\n");
751 return; 766 return;
752 } 767 }
753 768
754 REG_FLD_MOD(DISPC_CONTROL2, 1, 6, 6); 769 REG_FLD_MOD(dispc, DISPC_CONTROL2, 1, 6, 6);
755} 770}
756 771
757static void dispc_ovl_write_firh_reg(enum omap_plane_id plane, int reg, 772static void dispc_ovl_write_firh_reg(struct dispc_device *dispc,
773 enum omap_plane_id plane, int reg,
758 u32 value) 774 u32 value)
759{ 775{
760 dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value); 776 dispc_write_reg(dispc, DISPC_OVL_FIR_COEF_H(plane, reg), value);
761} 777}
762 778
763static void dispc_ovl_write_firhv_reg(enum omap_plane_id plane, int reg, 779static void dispc_ovl_write_firhv_reg(struct dispc_device *dispc,
780 enum omap_plane_id plane, int reg,
764 u32 value) 781 u32 value)
765{ 782{
766 dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value); 783 dispc_write_reg(dispc, DISPC_OVL_FIR_COEF_HV(plane, reg), value);
767} 784}
768 785
769static void dispc_ovl_write_firv_reg(enum omap_plane_id plane, int reg, 786static void dispc_ovl_write_firv_reg(struct dispc_device *dispc,
787 enum omap_plane_id plane, int reg,
770 u32 value) 788 u32 value)
771{ 789{
772 dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value); 790 dispc_write_reg(dispc, DISPC_OVL_FIR_COEF_V(plane, reg), value);
773} 791}
774 792
775static void dispc_ovl_write_firh2_reg(enum omap_plane_id plane, int reg, 793static void dispc_ovl_write_firh2_reg(struct dispc_device *dispc,
794 enum omap_plane_id plane, int reg,
776 u32 value) 795 u32 value)
777{ 796{
778 BUG_ON(plane == OMAP_DSS_GFX); 797 BUG_ON(plane == OMAP_DSS_GFX);
779 798
780 dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value); 799 dispc_write_reg(dispc, DISPC_OVL_FIR_COEF_H2(plane, reg), value);
781} 800}
782 801
783static void dispc_ovl_write_firhv2_reg(enum omap_plane_id plane, int reg, 802static void dispc_ovl_write_firhv2_reg(struct dispc_device *dispc,
784 u32 value) 803 enum omap_plane_id plane, int reg,
804 u32 value)
785{ 805{
786 BUG_ON(plane == OMAP_DSS_GFX); 806 BUG_ON(plane == OMAP_DSS_GFX);
787 807
788 dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value); 808 dispc_write_reg(dispc, DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
789} 809}
790 810
791static void dispc_ovl_write_firv2_reg(enum omap_plane_id plane, int reg, 811static void dispc_ovl_write_firv2_reg(struct dispc_device *dispc,
812 enum omap_plane_id plane, int reg,
792 u32 value) 813 u32 value)
793{ 814{
794 BUG_ON(plane == OMAP_DSS_GFX); 815 BUG_ON(plane == OMAP_DSS_GFX);
795 816
796 dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value); 817 dispc_write_reg(dispc, DISPC_OVL_FIR_COEF_V2(plane, reg), value);
797} 818}
798 819
799static void dispc_ovl_set_scale_coef(enum omap_plane_id plane, int fir_hinc, 820static void dispc_ovl_set_scale_coef(struct dispc_device *dispc,
800 int fir_vinc, int five_taps, 821 enum omap_plane_id plane, int fir_hinc,
801 enum omap_color_component color_comp) 822 int fir_vinc, int five_taps,
823 enum omap_color_component color_comp)
802{ 824{
803 const struct dispc_coef *h_coef, *v_coef; 825 const struct dispc_coef *h_coef, *v_coef;
804 int i; 826 int i;
@@ -819,11 +841,11 @@ static void dispc_ovl_set_scale_coef(enum omap_plane_id plane, int fir_hinc,
819 | FLD_VAL(v_coef[i].hc3_vc2, 31, 24); 841 | FLD_VAL(v_coef[i].hc3_vc2, 31, 24);
820 842
821 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) { 843 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
822 dispc_ovl_write_firh_reg(plane, i, h); 844 dispc_ovl_write_firh_reg(dispc, plane, i, h);
823 dispc_ovl_write_firhv_reg(plane, i, hv); 845 dispc_ovl_write_firhv_reg(dispc, plane, i, hv);
824 } else { 846 } else {
825 dispc_ovl_write_firh2_reg(plane, i, h); 847 dispc_ovl_write_firh2_reg(dispc, plane, i, h);
826 dispc_ovl_write_firhv2_reg(plane, i, hv); 848 dispc_ovl_write_firhv2_reg(dispc, plane, i, hv);
827 } 849 }
828 850
829 } 851 }
@@ -834,72 +856,113 @@ static void dispc_ovl_set_scale_coef(enum omap_plane_id plane, int fir_hinc,
834 v = FLD_VAL(v_coef[i].hc0_vc00, 7, 0) 856 v = FLD_VAL(v_coef[i].hc0_vc00, 7, 0)
835 | FLD_VAL(v_coef[i].hc4_vc22, 15, 8); 857 | FLD_VAL(v_coef[i].hc4_vc22, 15, 8);
836 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) 858 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y)
837 dispc_ovl_write_firv_reg(plane, i, v); 859 dispc_ovl_write_firv_reg(dispc, plane, i, v);
838 else 860 else
839 dispc_ovl_write_firv2_reg(plane, i, v); 861 dispc_ovl_write_firv2_reg(dispc, plane, i, v);
840 } 862 }
841 } 863 }
842} 864}
843 865
866struct csc_coef_yuv2rgb {
867 int ry, rcb, rcr, gy, gcb, gcr, by, bcb, bcr;
868 bool full_range;
869};
870
871struct csc_coef_rgb2yuv {
872 int yr, yg, yb, cbr, cbg, cbb, crr, crg, crb;
873 bool full_range;
874};
875
876static void dispc_ovl_write_color_conv_coef(struct dispc_device *dispc,
877 enum omap_plane_id plane,
878 const struct csc_coef_yuv2rgb *ct)
879{
880#define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
881
882 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 0), CVAL(ct->rcr, ct->ry));
883 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 1), CVAL(ct->gy, ct->rcb));
884 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 2), CVAL(ct->gcb, ct->gcr));
885 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->bcr, ct->by));
886 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 4), CVAL(0, ct->bcb));
844 887
845static void dispc_ovl_write_color_conv_coef(enum omap_plane_id plane, 888 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11);
846 const struct color_conv_coef *ct) 889
890#undef CVAL
891}
892
893static void dispc_wb_write_color_conv_coef(struct dispc_device *dispc,
894 const struct csc_coef_rgb2yuv *ct)
847{ 895{
896 const enum omap_plane_id plane = OMAP_DSS_WB;
897
848#define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0)) 898#define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
849 899
850 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 0), CVAL(ct->rcr, ct->ry)); 900 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 0), CVAL(ct->yg, ct->yr));
851 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 1), CVAL(ct->gy, ct->rcb)); 901 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 1), CVAL(ct->crr, ct->yb));
852 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 2), CVAL(ct->gcb, ct->gcr)); 902 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 2), CVAL(ct->crb, ct->crg));
853 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->bcr, ct->by)); 903 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->cbg, ct->cbr));
854 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 4), CVAL(0, ct->bcb)); 904 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 4), CVAL(0, ct->cbb));
855 905
856 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11); 906 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11);
857 907
858#undef CVAL 908#undef CVAL
859} 909}
860 910
861static void dispc_setup_color_conv_coef(void) 911static void dispc_setup_color_conv_coef(struct dispc_device *dispc)
862{ 912{
863 int i; 913 int i;
864 int num_ovl = dispc_get_num_ovls(); 914 int num_ovl = dispc_get_num_ovls(dispc);
865 const struct color_conv_coef ctbl_bt601_5_ovl = { 915
866 /* YUV -> RGB */ 916 /* YUV -> RGB, ITU-R BT.601, limited range */
867 298, 409, 0, 298, -208, -100, 298, 0, 517, 0, 917 const struct csc_coef_yuv2rgb coefs_yuv2rgb_bt601_lim = {
918 298, 0, 409, /* ry, rcb, rcr */
919 298, -100, -208, /* gy, gcb, gcr */
920 298, 516, 0, /* by, bcb, bcr */
921 false, /* limited range */
868 }; 922 };
869 const struct color_conv_coef ctbl_bt601_5_wb = { 923
870 /* RGB -> YUV */ 924 /* RGB -> YUV, ITU-R BT.601, limited range */
871 66, 129, 25, 112, -94, -18, -38, -74, 112, 0, 925 const struct csc_coef_rgb2yuv coefs_rgb2yuv_bt601_lim = {
926 66, 129, 25, /* yr, yg, yb */
927 -38, -74, 112, /* cbr, cbg, cbb */
928 112, -94, -18, /* crr, crg, crb */
929 false, /* limited range */
872 }; 930 };
873 931
874 for (i = 1; i < num_ovl; i++) 932 for (i = 1; i < num_ovl; i++)
875 dispc_ovl_write_color_conv_coef(i, &ctbl_bt601_5_ovl); 933 dispc_ovl_write_color_conv_coef(dispc, i, &coefs_yuv2rgb_bt601_lim);
876 934
877 if (dispc.feat->has_writeback) 935 if (dispc->feat->has_writeback)
878 dispc_ovl_write_color_conv_coef(OMAP_DSS_WB, &ctbl_bt601_5_wb); 936 dispc_wb_write_color_conv_coef(dispc, &coefs_rgb2yuv_bt601_lim);
879} 937}
880 938
881static void dispc_ovl_set_ba0(enum omap_plane_id plane, u32 paddr) 939static void dispc_ovl_set_ba0(struct dispc_device *dispc,
940 enum omap_plane_id plane, u32 paddr)
882{ 941{
883 dispc_write_reg(DISPC_OVL_BA0(plane), paddr); 942 dispc_write_reg(dispc, DISPC_OVL_BA0(plane), paddr);
884} 943}
885 944
886static void dispc_ovl_set_ba1(enum omap_plane_id plane, u32 paddr) 945static void dispc_ovl_set_ba1(struct dispc_device *dispc,
946 enum omap_plane_id plane, u32 paddr)
887{ 947{
888 dispc_write_reg(DISPC_OVL_BA1(plane), paddr); 948 dispc_write_reg(dispc, DISPC_OVL_BA1(plane), paddr);
889} 949}
890 950
891static void dispc_ovl_set_ba0_uv(enum omap_plane_id plane, u32 paddr) 951static void dispc_ovl_set_ba0_uv(struct dispc_device *dispc,
952 enum omap_plane_id plane, u32 paddr)
892{ 953{
893 dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr); 954 dispc_write_reg(dispc, DISPC_OVL_BA0_UV(plane), paddr);
894} 955}
895 956
896static void dispc_ovl_set_ba1_uv(enum omap_plane_id plane, u32 paddr) 957static void dispc_ovl_set_ba1_uv(struct dispc_device *dispc,
958 enum omap_plane_id plane, u32 paddr)
897{ 959{
898 dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr); 960 dispc_write_reg(dispc, DISPC_OVL_BA1_UV(plane), paddr);
899} 961}
900 962
901static void dispc_ovl_set_pos(enum omap_plane_id plane, 963static void dispc_ovl_set_pos(struct dispc_device *dispc,
902 enum omap_overlay_caps caps, int x, int y) 964 enum omap_plane_id plane,
965 enum omap_overlay_caps caps, int x, int y)
903{ 966{
904 u32 val; 967 u32 val;
905 968
@@ -908,22 +971,24 @@ static void dispc_ovl_set_pos(enum omap_plane_id plane,
908 971
909 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0); 972 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
910 973
911 dispc_write_reg(DISPC_OVL_POSITION(plane), val); 974 dispc_write_reg(dispc, DISPC_OVL_POSITION(plane), val);
912} 975}
913 976
914static void dispc_ovl_set_input_size(enum omap_plane_id plane, int width, 977static void dispc_ovl_set_input_size(struct dispc_device *dispc,
915 int height) 978 enum omap_plane_id plane, int width,
979 int height)
916{ 980{
917 u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0); 981 u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
918 982
919 if (plane == OMAP_DSS_GFX || plane == OMAP_DSS_WB) 983 if (plane == OMAP_DSS_GFX || plane == OMAP_DSS_WB)
920 dispc_write_reg(DISPC_OVL_SIZE(plane), val); 984 dispc_write_reg(dispc, DISPC_OVL_SIZE(plane), val);
921 else 985 else
922 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val); 986 dispc_write_reg(dispc, DISPC_OVL_PICTURE_SIZE(plane), val);
923} 987}
924 988
925static void dispc_ovl_set_output_size(enum omap_plane_id plane, int width, 989static void dispc_ovl_set_output_size(struct dispc_device *dispc,
926 int height) 990 enum omap_plane_id plane, int width,
991 int height)
927{ 992{
928 u32 val; 993 u32 val;
929 994
@@ -932,64 +997,72 @@ static void dispc_ovl_set_output_size(enum omap_plane_id plane, int width,
932 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0); 997 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
933 998
934 if (plane == OMAP_DSS_WB) 999 if (plane == OMAP_DSS_WB)
935 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val); 1000 dispc_write_reg(dispc, DISPC_OVL_PICTURE_SIZE(plane), val);
936 else 1001 else
937 dispc_write_reg(DISPC_OVL_SIZE(plane), val); 1002 dispc_write_reg(dispc, DISPC_OVL_SIZE(plane), val);
938} 1003}
939 1004
940static void dispc_ovl_set_zorder(enum omap_plane_id plane, 1005static void dispc_ovl_set_zorder(struct dispc_device *dispc,
941 enum omap_overlay_caps caps, u8 zorder) 1006 enum omap_plane_id plane,
1007 enum omap_overlay_caps caps, u8 zorder)
942{ 1008{
943 if ((caps & OMAP_DSS_OVL_CAP_ZORDER) == 0) 1009 if ((caps & OMAP_DSS_OVL_CAP_ZORDER) == 0)
944 return; 1010 return;
945 1011
946 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26); 1012 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26);
947} 1013}
948 1014
949static void dispc_ovl_enable_zorder_planes(void) 1015static void dispc_ovl_enable_zorder_planes(struct dispc_device *dispc)
950{ 1016{
951 int i; 1017 int i;
952 1018
953 if (!dispc_has_feature(FEAT_ALPHA_FREE_ZORDER)) 1019 if (!dispc_has_feature(dispc, FEAT_ALPHA_FREE_ZORDER))
954 return; 1020 return;
955 1021
956 for (i = 0; i < dispc_get_num_ovls(); i++) 1022 for (i = 0; i < dispc_get_num_ovls(dispc); i++)
957 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25); 1023 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(i), 1, 25, 25);
958} 1024}
959 1025
960static void dispc_ovl_set_pre_mult_alpha(enum omap_plane_id plane, 1026static void dispc_ovl_set_pre_mult_alpha(struct dispc_device *dispc,
961 enum omap_overlay_caps caps, bool enable) 1027 enum omap_plane_id plane,
1028 enum omap_overlay_caps caps,
1029 bool enable)
962{ 1030{
963 if ((caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0) 1031 if ((caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0)
964 return; 1032 return;
965 1033
966 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28); 1034 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
967} 1035}
968 1036
969static void dispc_ovl_setup_global_alpha(enum omap_plane_id plane, 1037static void dispc_ovl_setup_global_alpha(struct dispc_device *dispc,
970 enum omap_overlay_caps caps, u8 global_alpha) 1038 enum omap_plane_id plane,
1039 enum omap_overlay_caps caps,
1040 u8 global_alpha)
971{ 1041{
972 static const unsigned shifts[] = { 0, 8, 16, 24, }; 1042 static const unsigned int shifts[] = { 0, 8, 16, 24, };
973 int shift; 1043 int shift;
974 1044
975 if ((caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0) 1045 if ((caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0)
976 return; 1046 return;
977 1047
978 shift = shifts[plane]; 1048 shift = shifts[plane];
979 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift); 1049 REG_FLD_MOD(dispc, DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift);
980} 1050}
981 1051
982static void dispc_ovl_set_pix_inc(enum omap_plane_id plane, s32 inc) 1052static void dispc_ovl_set_pix_inc(struct dispc_device *dispc,
1053 enum omap_plane_id plane, s32 inc)
983{ 1054{
984 dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc); 1055 dispc_write_reg(dispc, DISPC_OVL_PIXEL_INC(plane), inc);
985} 1056}
986 1057
987static void dispc_ovl_set_row_inc(enum omap_plane_id plane, s32 inc) 1058static void dispc_ovl_set_row_inc(struct dispc_device *dispc,
1059 enum omap_plane_id plane, s32 inc)
988{ 1060{
989 dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc); 1061 dispc_write_reg(dispc, DISPC_OVL_ROW_INC(plane), inc);
990} 1062}
991 1063
992static void dispc_ovl_set_color_mode(enum omap_plane_id plane, u32 fourcc) 1064static void dispc_ovl_set_color_mode(struct dispc_device *dispc,
1065 enum omap_plane_id plane, u32 fourcc)
993{ 1066{
994 u32 m = 0; 1067 u32 m = 0;
995 if (plane != OMAP_DSS_GFX) { 1068 if (plane != OMAP_DSS_GFX) {
@@ -1058,7 +1131,7 @@ static void dispc_ovl_set_color_mode(enum omap_plane_id plane, u32 fourcc)
1058 } 1131 }
1059 } 1132 }
1060 1133
1061 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1); 1134 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
1062} 1135}
1063 1136
1064static bool format_is_yuv(u32 fourcc) 1137static bool format_is_yuv(u32 fourcc)
@@ -1073,19 +1146,21 @@ static bool format_is_yuv(u32 fourcc)
1073 } 1146 }
1074} 1147}
1075 1148
1076static void dispc_ovl_configure_burst_type(enum omap_plane_id plane, 1149static void dispc_ovl_configure_burst_type(struct dispc_device *dispc,
1077 enum omap_dss_rotation_type rotation_type) 1150 enum omap_plane_id plane,
1151 enum omap_dss_rotation_type rotation)
1078{ 1152{
1079 if (dispc_has_feature(FEAT_BURST_2D) == 0) 1153 if (dispc_has_feature(dispc, FEAT_BURST_2D) == 0)
1080 return; 1154 return;
1081 1155
1082 if (rotation_type == OMAP_DSS_ROT_TILER) 1156 if (rotation == OMAP_DSS_ROT_TILER)
1083 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 1, 29, 29); 1157 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), 1, 29, 29);
1084 else 1158 else
1085 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 0, 29, 29); 1159 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), 0, 29, 29);
1086} 1160}
1087 1161
1088static void dispc_ovl_set_channel_out(enum omap_plane_id plane, 1162static void dispc_ovl_set_channel_out(struct dispc_device *dispc,
1163 enum omap_plane_id plane,
1089 enum omap_channel channel) 1164 enum omap_channel channel)
1090{ 1165{
1091 int shift; 1166 int shift;
@@ -1106,8 +1181,8 @@ static void dispc_ovl_set_channel_out(enum omap_plane_id plane,
1106 return; 1181 return;
1107 } 1182 }
1108 1183
1109 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane)); 1184 val = dispc_read_reg(dispc, DISPC_OVL_ATTRIBUTES(plane));
1110 if (dispc_has_feature(FEAT_MGR_LCD2)) { 1185 if (dispc_has_feature(dispc, FEAT_MGR_LCD2)) {
1111 switch (channel) { 1186 switch (channel) {
1112 case OMAP_DSS_CHANNEL_LCD: 1187 case OMAP_DSS_CHANNEL_LCD:
1113 chan = 0; 1188 chan = 0;
@@ -1122,7 +1197,7 @@ static void dispc_ovl_set_channel_out(enum omap_plane_id plane,
1122 chan2 = 1; 1197 chan2 = 1;
1123 break; 1198 break;
1124 case OMAP_DSS_CHANNEL_LCD3: 1199 case OMAP_DSS_CHANNEL_LCD3:
1125 if (dispc_has_feature(FEAT_MGR_LCD3)) { 1200 if (dispc_has_feature(dispc, FEAT_MGR_LCD3)) {
1126 chan = 0; 1201 chan = 0;
1127 chan2 = 2; 1202 chan2 = 2;
1128 } else { 1203 } else {
@@ -1144,10 +1219,11 @@ static void dispc_ovl_set_channel_out(enum omap_plane_id plane,
1144 } else { 1219 } else {
1145 val = FLD_MOD(val, channel, shift, shift); 1220 val = FLD_MOD(val, channel, shift, shift);
1146 } 1221 }
1147 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val); 1222 dispc_write_reg(dispc, DISPC_OVL_ATTRIBUTES(plane), val);
1148} 1223}
1149 1224
1150static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane_id plane) 1225static enum omap_channel dispc_ovl_get_channel_out(struct dispc_device *dispc,
1226 enum omap_plane_id plane)
1151{ 1227{
1152 int shift; 1228 int shift;
1153 u32 val; 1229 u32 val;
@@ -1166,12 +1242,12 @@ static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane_id plane)
1166 return 0; 1242 return 0;
1167 } 1243 }
1168 1244
1169 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane)); 1245 val = dispc_read_reg(dispc, DISPC_OVL_ATTRIBUTES(plane));
1170 1246
1171 if (FLD_GET(val, shift, shift) == 1) 1247 if (FLD_GET(val, shift, shift) == 1)
1172 return OMAP_DSS_CHANNEL_DIGIT; 1248 return OMAP_DSS_CHANNEL_DIGIT;
1173 1249
1174 if (!dispc_has_feature(FEAT_MGR_LCD2)) 1250 if (!dispc_has_feature(dispc, FEAT_MGR_LCD2))
1175 return OMAP_DSS_CHANNEL_LCD; 1251 return OMAP_DSS_CHANNEL_LCD;
1176 1252
1177 switch (FLD_GET(val, 31, 30)) { 1253 switch (FLD_GET(val, 31, 30)) {
@@ -1187,47 +1263,44 @@ static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane_id plane)
1187 } 1263 }
1188} 1264}
1189 1265
1190void dispc_wb_set_channel_in(enum dss_writeback_channel channel) 1266static void dispc_ovl_set_burst_size(struct dispc_device *dispc,
1191{ 1267 enum omap_plane_id plane,
1192 enum omap_plane_id plane = OMAP_DSS_WB; 1268 enum omap_burst_size burst_size)
1193
1194 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), channel, 18, 16);
1195}
1196
1197static void dispc_ovl_set_burst_size(enum omap_plane_id plane,
1198 enum omap_burst_size burst_size)
1199{ 1269{
1200 static const unsigned shifts[] = { 6, 14, 14, 14, 14, }; 1270 static const unsigned int shifts[] = { 6, 14, 14, 14, 14, };
1201 int shift; 1271 int shift;
1202 1272
1203 shift = shifts[plane]; 1273 shift = shifts[plane];
1204 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift); 1274 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), burst_size,
1275 shift + 1, shift);
1205} 1276}
1206 1277
1207static void dispc_configure_burst_sizes(void) 1278static void dispc_configure_burst_sizes(struct dispc_device *dispc)
1208{ 1279{
1209 int i; 1280 int i;
1210 const int burst_size = BURST_SIZE_X8; 1281 const int burst_size = BURST_SIZE_X8;
1211 1282
1212 /* Configure burst size always to maximum size */ 1283 /* Configure burst size always to maximum size */
1213 for (i = 0; i < dispc_get_num_ovls(); ++i) 1284 for (i = 0; i < dispc_get_num_ovls(dispc); ++i)
1214 dispc_ovl_set_burst_size(i, burst_size); 1285 dispc_ovl_set_burst_size(dispc, i, burst_size);
1215 if (dispc.feat->has_writeback) 1286 if (dispc->feat->has_writeback)
1216 dispc_ovl_set_burst_size(OMAP_DSS_WB, burst_size); 1287 dispc_ovl_set_burst_size(dispc, OMAP_DSS_WB, burst_size);
1217} 1288}
1218 1289
1219static u32 dispc_ovl_get_burst_size(enum omap_plane_id plane) 1290static u32 dispc_ovl_get_burst_size(struct dispc_device *dispc,
1291 enum omap_plane_id plane)
1220{ 1292{
1221 /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */ 1293 /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */
1222 return dispc.feat->burst_size_unit * 8; 1294 return dispc->feat->burst_size_unit * 8;
1223} 1295}
1224 1296
1225static bool dispc_ovl_color_mode_supported(enum omap_plane_id plane, u32 fourcc) 1297static bool dispc_ovl_color_mode_supported(struct dispc_device *dispc,
1298 enum omap_plane_id plane, u32 fourcc)
1226{ 1299{
1227 const u32 *modes; 1300 const u32 *modes;
1228 unsigned int i; 1301 unsigned int i;
1229 1302
1230 modes = dispc.feat->supported_color_modes[plane]; 1303 modes = dispc->feat->supported_color_modes[plane];
1231 1304
1232 for (i = 0; modes[i]; ++i) { 1305 for (i = 0; modes[i]; ++i) {
1233 if (modes[i] == fourcc) 1306 if (modes[i] == fourcc)
@@ -1237,21 +1310,24 @@ static bool dispc_ovl_color_mode_supported(enum omap_plane_id plane, u32 fourcc)
1237 return false; 1310 return false;
1238} 1311}
1239 1312
1240static const u32 *dispc_ovl_get_color_modes(enum omap_plane_id plane) 1313static const u32 *dispc_ovl_get_color_modes(struct dispc_device *dispc,
1314 enum omap_plane_id plane)
1241{ 1315{
1242 return dispc.feat->supported_color_modes[plane]; 1316 return dispc->feat->supported_color_modes[plane];
1243} 1317}
1244 1318
1245static void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable) 1319static void dispc_mgr_enable_cpr(struct dispc_device *dispc,
1320 enum omap_channel channel, bool enable)
1246{ 1321{
1247 if (channel == OMAP_DSS_CHANNEL_DIGIT) 1322 if (channel == OMAP_DSS_CHANNEL_DIGIT)
1248 return; 1323 return;
1249 1324
1250 mgr_fld_write(channel, DISPC_MGR_FLD_CPR, enable); 1325 mgr_fld_write(dispc, channel, DISPC_MGR_FLD_CPR, enable);
1251} 1326}
1252 1327
1253static void dispc_mgr_set_cpr_coef(enum omap_channel channel, 1328static void dispc_mgr_set_cpr_coef(struct dispc_device *dispc,
1254 const struct omap_dss_cpr_coefs *coefs) 1329 enum omap_channel channel,
1330 const struct omap_dss_cpr_coefs *coefs)
1255{ 1331{
1256 u32 coef_r, coef_g, coef_b; 1332 u32 coef_r, coef_g, coef_b;
1257 1333
@@ -1265,48 +1341,50 @@ static void dispc_mgr_set_cpr_coef(enum omap_channel channel,
1265 coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) | 1341 coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) |
1266 FLD_VAL(coefs->bb, 9, 0); 1342 FLD_VAL(coefs->bb, 9, 0);
1267 1343
1268 dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r); 1344 dispc_write_reg(dispc, DISPC_CPR_COEF_R(channel), coef_r);
1269 dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g); 1345 dispc_write_reg(dispc, DISPC_CPR_COEF_G(channel), coef_g);
1270 dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b); 1346 dispc_write_reg(dispc, DISPC_CPR_COEF_B(channel), coef_b);
1271} 1347}
1272 1348
1273static void dispc_ovl_set_vid_color_conv(enum omap_plane_id plane, 1349static void dispc_ovl_set_vid_color_conv(struct dispc_device *dispc,
1274 bool enable) 1350 enum omap_plane_id plane, bool enable)
1275{ 1351{
1276 u32 val; 1352 u32 val;
1277 1353
1278 BUG_ON(plane == OMAP_DSS_GFX); 1354 BUG_ON(plane == OMAP_DSS_GFX);
1279 1355
1280 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane)); 1356 val = dispc_read_reg(dispc, DISPC_OVL_ATTRIBUTES(plane));
1281 val = FLD_MOD(val, enable, 9, 9); 1357 val = FLD_MOD(val, enable, 9, 9);
1282 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val); 1358 dispc_write_reg(dispc, DISPC_OVL_ATTRIBUTES(plane), val);
1283} 1359}
1284 1360
1285static void dispc_ovl_enable_replication(enum omap_plane_id plane, 1361static void dispc_ovl_enable_replication(struct dispc_device *dispc,
1286 enum omap_overlay_caps caps, bool enable) 1362 enum omap_plane_id plane,
1363 enum omap_overlay_caps caps,
1364 bool enable)
1287{ 1365{
1288 static const unsigned shifts[] = { 5, 10, 10, 10 }; 1366 static const unsigned int shifts[] = { 5, 10, 10, 10 };
1289 int shift; 1367 int shift;
1290 1368
1291 if ((caps & OMAP_DSS_OVL_CAP_REPLICATION) == 0) 1369 if ((caps & OMAP_DSS_OVL_CAP_REPLICATION) == 0)
1292 return; 1370 return;
1293 1371
1294 shift = shifts[plane]; 1372 shift = shifts[plane];
1295 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift); 1373 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift);
1296} 1374}
1297 1375
1298static void dispc_mgr_set_size(enum omap_channel channel, u16 width, 1376static void dispc_mgr_set_size(struct dispc_device *dispc,
1299 u16 height) 1377 enum omap_channel channel, u16 width, u16 height)
1300{ 1378{
1301 u32 val; 1379 u32 val;
1302 1380
1303 val = FLD_VAL(height - 1, dispc.feat->mgr_height_start, 16) | 1381 val = FLD_VAL(height - 1, dispc->feat->mgr_height_start, 16) |
1304 FLD_VAL(width - 1, dispc.feat->mgr_width_start, 0); 1382 FLD_VAL(width - 1, dispc->feat->mgr_width_start, 0);
1305 1383
1306 dispc_write_reg(DISPC_SIZE_MGR(channel), val); 1384 dispc_write_reg(dispc, DISPC_SIZE_MGR(channel), val);
1307} 1385}
1308 1386
1309static void dispc_init_fifos(void) 1387static void dispc_init_fifos(struct dispc_device *dispc)
1310{ 1388{
1311 u32 size; 1389 u32 size;
1312 int fifo; 1390 int fifo;
@@ -1314,20 +1392,21 @@ static void dispc_init_fifos(void)
1314 u32 unit; 1392 u32 unit;
1315 int i; 1393 int i;
1316 1394
1317 unit = dispc.feat->buffer_size_unit; 1395 unit = dispc->feat->buffer_size_unit;
1318 1396
1319 dispc_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end); 1397 dispc_get_reg_field(dispc, FEAT_REG_FIFOSIZE, &start, &end);
1320 1398
1321 for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) { 1399 for (fifo = 0; fifo < dispc->feat->num_fifos; ++fifo) {
1322 size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(fifo), start, end); 1400 size = REG_GET(dispc, DISPC_OVL_FIFO_SIZE_STATUS(fifo),
1401 start, end);
1323 size *= unit; 1402 size *= unit;
1324 dispc.fifo_size[fifo] = size; 1403 dispc->fifo_size[fifo] = size;
1325 1404
1326 /* 1405 /*
1327 * By default fifos are mapped directly to overlays, fifo 0 to 1406 * By default fifos are mapped directly to overlays, fifo 0 to
1328 * ovl 0, fifo 1 to ovl 1, etc. 1407 * ovl 0, fifo 1 to ovl 1, etc.
1329 */ 1408 */
1330 dispc.fifo_assignment[fifo] = fifo; 1409 dispc->fifo_assignment[fifo] = fifo;
1331 } 1410 }
1332 1411
1333 /* 1412 /*
@@ -1337,68 +1416,71 @@ static void dispc_init_fifos(void)
1337 * giving GFX plane a larger fifo. WB but should work fine with a 1416 * giving GFX plane a larger fifo. WB but should work fine with a
1338 * smaller fifo. 1417 * smaller fifo.
1339 */ 1418 */
1340 if (dispc.feat->gfx_fifo_workaround) { 1419 if (dispc->feat->gfx_fifo_workaround) {
1341 u32 v; 1420 u32 v;
1342 1421
1343 v = dispc_read_reg(DISPC_GLOBAL_BUFFER); 1422 v = dispc_read_reg(dispc, DISPC_GLOBAL_BUFFER);
1344 1423
1345 v = FLD_MOD(v, 4, 2, 0); /* GFX BUF top to WB */ 1424 v = FLD_MOD(v, 4, 2, 0); /* GFX BUF top to WB */
1346 v = FLD_MOD(v, 4, 5, 3); /* GFX BUF bottom to WB */ 1425 v = FLD_MOD(v, 4, 5, 3); /* GFX BUF bottom to WB */
1347 v = FLD_MOD(v, 0, 26, 24); /* WB BUF top to GFX */ 1426 v = FLD_MOD(v, 0, 26, 24); /* WB BUF top to GFX */
1348 v = FLD_MOD(v, 0, 29, 27); /* WB BUF bottom to GFX */ 1427 v = FLD_MOD(v, 0, 29, 27); /* WB BUF bottom to GFX */
1349 1428
1350 dispc_write_reg(DISPC_GLOBAL_BUFFER, v); 1429 dispc_write_reg(dispc, DISPC_GLOBAL_BUFFER, v);
1351 1430
1352 dispc.fifo_assignment[OMAP_DSS_GFX] = OMAP_DSS_WB; 1431 dispc->fifo_assignment[OMAP_DSS_GFX] = OMAP_DSS_WB;
1353 dispc.fifo_assignment[OMAP_DSS_WB] = OMAP_DSS_GFX; 1432 dispc->fifo_assignment[OMAP_DSS_WB] = OMAP_DSS_GFX;
1354 } 1433 }
1355 1434
1356 /* 1435 /*
1357 * Setup default fifo thresholds. 1436 * Setup default fifo thresholds.
1358 */ 1437 */
1359 for (i = 0; i < dispc_get_num_ovls(); ++i) { 1438 for (i = 0; i < dispc_get_num_ovls(dispc); ++i) {
1360 u32 low, high; 1439 u32 low, high;
1361 const bool use_fifomerge = false; 1440 const bool use_fifomerge = false;
1362 const bool manual_update = false; 1441 const bool manual_update = false;
1363 1442
1364 dispc_ovl_compute_fifo_thresholds(i, &low, &high, 1443 dispc_ovl_compute_fifo_thresholds(dispc, i, &low, &high,
1365 use_fifomerge, manual_update); 1444 use_fifomerge, manual_update);
1366 1445
1367 dispc_ovl_set_fifo_threshold(i, low, high); 1446 dispc_ovl_set_fifo_threshold(dispc, i, low, high);
1368 } 1447 }
1369 1448
1370 if (dispc.feat->has_writeback) { 1449 if (dispc->feat->has_writeback) {
1371 u32 low, high; 1450 u32 low, high;
1372 const bool use_fifomerge = false; 1451 const bool use_fifomerge = false;
1373 const bool manual_update = false; 1452 const bool manual_update = false;
1374 1453
1375 dispc_ovl_compute_fifo_thresholds(OMAP_DSS_WB, &low, &high, 1454 dispc_ovl_compute_fifo_thresholds(dispc, OMAP_DSS_WB,
1376 use_fifomerge, manual_update); 1455 &low, &high, use_fifomerge,
1456 manual_update);
1377 1457
1378 dispc_ovl_set_fifo_threshold(OMAP_DSS_WB, low, high); 1458 dispc_ovl_set_fifo_threshold(dispc, OMAP_DSS_WB, low, high);
1379 } 1459 }
1380} 1460}
1381 1461
1382static u32 dispc_ovl_get_fifo_size(enum omap_plane_id plane) 1462static u32 dispc_ovl_get_fifo_size(struct dispc_device *dispc,
1463 enum omap_plane_id plane)
1383{ 1464{
1384 int fifo; 1465 int fifo;
1385 u32 size = 0; 1466 u32 size = 0;
1386 1467
1387 for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) { 1468 for (fifo = 0; fifo < dispc->feat->num_fifos; ++fifo) {
1388 if (dispc.fifo_assignment[fifo] == plane) 1469 if (dispc->fifo_assignment[fifo] == plane)
1389 size += dispc.fifo_size[fifo]; 1470 size += dispc->fifo_size[fifo];
1390 } 1471 }
1391 1472
1392 return size; 1473 return size;
1393} 1474}
1394 1475
1395void dispc_ovl_set_fifo_threshold(enum omap_plane_id plane, u32 low, 1476void dispc_ovl_set_fifo_threshold(struct dispc_device *dispc,
1396 u32 high) 1477 enum omap_plane_id plane,
1478 u32 low, u32 high)
1397{ 1479{
1398 u8 hi_start, hi_end, lo_start, lo_end; 1480 u8 hi_start, hi_end, lo_start, lo_end;
1399 u32 unit; 1481 u32 unit;
1400 1482
1401 unit = dispc.feat->buffer_size_unit; 1483 unit = dispc->feat->buffer_size_unit;
1402 1484
1403 WARN_ON(low % unit != 0); 1485 WARN_ON(low % unit != 0);
1404 WARN_ON(high % unit != 0); 1486 WARN_ON(high % unit != 0);
@@ -1406,18 +1488,20 @@ void dispc_ovl_set_fifo_threshold(enum omap_plane_id plane, u32 low,
1406 low /= unit; 1488 low /= unit;
1407 high /= unit; 1489 high /= unit;
1408 1490
1409 dispc_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end); 1491 dispc_get_reg_field(dispc, FEAT_REG_FIFOHIGHTHRESHOLD,
1410 dispc_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end); 1492 &hi_start, &hi_end);
1493 dispc_get_reg_field(dispc, FEAT_REG_FIFOLOWTHRESHOLD,
1494 &lo_start, &lo_end);
1411 1495
1412 DSSDBG("fifo(%d) threshold (bytes), old %u/%u, new %u/%u\n", 1496 DSSDBG("fifo(%d) threshold (bytes), old %u/%u, new %u/%u\n",
1413 plane, 1497 plane,
1414 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane), 1498 REG_GET(dispc, DISPC_OVL_FIFO_THRESHOLD(plane),
1415 lo_start, lo_end) * unit, 1499 lo_start, lo_end) * unit,
1416 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane), 1500 REG_GET(dispc, DISPC_OVL_FIFO_THRESHOLD(plane),
1417 hi_start, hi_end) * unit, 1501 hi_start, hi_end) * unit,
1418 low * unit, high * unit); 1502 low * unit, high * unit);
1419 1503
1420 dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane), 1504 dispc_write_reg(dispc, DISPC_OVL_FIFO_THRESHOLD(plane),
1421 FLD_VAL(high, hi_start, hi_end) | 1505 FLD_VAL(high, hi_start, hi_end) |
1422 FLD_VAL(low, lo_start, lo_end)); 1506 FLD_VAL(low, lo_start, lo_end));
1423 1507
@@ -1426,42 +1510,43 @@ void dispc_ovl_set_fifo_threshold(enum omap_plane_id plane, u32 low,
1426 * large for the preload field, set the threshold to the maximum value 1510 * large for the preload field, set the threshold to the maximum value
1427 * that can be held by the preload register 1511 * that can be held by the preload register
1428 */ 1512 */
1429 if (dispc_has_feature(FEAT_PRELOAD) && dispc.feat->set_max_preload && 1513 if (dispc_has_feature(dispc, FEAT_PRELOAD) &&
1430 plane != OMAP_DSS_WB) 1514 dispc->feat->set_max_preload && plane != OMAP_DSS_WB)
1431 dispc_write_reg(DISPC_OVL_PRELOAD(plane), min(high, 0xfffu)); 1515 dispc_write_reg(dispc, DISPC_OVL_PRELOAD(plane),
1516 min(high, 0xfffu));
1432} 1517}
1433 1518
1434void dispc_enable_fifomerge(bool enable) 1519void dispc_enable_fifomerge(struct dispc_device *dispc, bool enable)
1435{ 1520{
1436 if (!dispc_has_feature(FEAT_FIFO_MERGE)) { 1521 if (!dispc_has_feature(dispc, FEAT_FIFO_MERGE)) {
1437 WARN_ON(enable); 1522 WARN_ON(enable);
1438 return; 1523 return;
1439 } 1524 }
1440 1525
1441 DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled"); 1526 DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1442 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14); 1527 REG_FLD_MOD(dispc, DISPC_CONFIG, enable ? 1 : 0, 14, 14);
1443} 1528}
1444 1529
1445void dispc_ovl_compute_fifo_thresholds(enum omap_plane_id plane, 1530void dispc_ovl_compute_fifo_thresholds(struct dispc_device *dispc,
1446 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge, 1531 enum omap_plane_id plane,
1447 bool manual_update) 1532 u32 *fifo_low, u32 *fifo_high,
1533 bool use_fifomerge, bool manual_update)
1448{ 1534{
1449 /* 1535 /*
1450 * All sizes are in bytes. Both the buffer and burst are made of 1536 * All sizes are in bytes. Both the buffer and burst are made of
1451 * buffer_units, and the fifo thresholds must be buffer_unit aligned. 1537 * buffer_units, and the fifo thresholds must be buffer_unit aligned.
1452 */ 1538 */
1453 1539 unsigned int buf_unit = dispc->feat->buffer_size_unit;
1454 unsigned buf_unit = dispc.feat->buffer_size_unit; 1540 unsigned int ovl_fifo_size, total_fifo_size, burst_size;
1455 unsigned ovl_fifo_size, total_fifo_size, burst_size;
1456 int i; 1541 int i;
1457 1542
1458 burst_size = dispc_ovl_get_burst_size(plane); 1543 burst_size = dispc_ovl_get_burst_size(dispc, plane);
1459 ovl_fifo_size = dispc_ovl_get_fifo_size(plane); 1544 ovl_fifo_size = dispc_ovl_get_fifo_size(dispc, plane);
1460 1545
1461 if (use_fifomerge) { 1546 if (use_fifomerge) {
1462 total_fifo_size = 0; 1547 total_fifo_size = 0;
1463 for (i = 0; i < dispc_get_num_ovls(); ++i) 1548 for (i = 0; i < dispc_get_num_ovls(dispc); ++i)
1464 total_fifo_size += dispc_ovl_get_fifo_size(i); 1549 total_fifo_size += dispc_ovl_get_fifo_size(dispc, i);
1465 } else { 1550 } else {
1466 total_fifo_size = ovl_fifo_size; 1551 total_fifo_size = ovl_fifo_size;
1467 } 1552 }
@@ -1472,7 +1557,7 @@ void dispc_ovl_compute_fifo_thresholds(enum omap_plane_id plane,
1472 * combined fifo size 1557 * combined fifo size
1473 */ 1558 */
1474 1559
1475 if (manual_update && dispc_has_feature(FEAT_OMAP3_DSI_FIFO_BUG)) { 1560 if (manual_update && dispc_has_feature(dispc, FEAT_OMAP3_DSI_FIFO_BUG)) {
1476 *fifo_low = ovl_fifo_size - burst_size * 2; 1561 *fifo_low = ovl_fifo_size - burst_size * 2;
1477 *fifo_high = total_fifo_size - burst_size; 1562 *fifo_high = total_fifo_size - burst_size;
1478 } else if (plane == OMAP_DSS_WB) { 1563 } else if (plane == OMAP_DSS_WB) {
@@ -1489,7 +1574,8 @@ void dispc_ovl_compute_fifo_thresholds(enum omap_plane_id plane,
1489 } 1574 }
1490} 1575}
1491 1576
1492static void dispc_ovl_set_mflag(enum omap_plane_id plane, bool enable) 1577static void dispc_ovl_set_mflag(struct dispc_device *dispc,
1578 enum omap_plane_id plane, bool enable)
1493{ 1579{
1494 int bit; 1580 int bit;
1495 1581
@@ -1498,17 +1584,18 @@ static void dispc_ovl_set_mflag(enum omap_plane_id plane, bool enable)
1498 else 1584 else
1499 bit = 23; 1585 bit = 23;
1500 1586
1501 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, bit, bit); 1587 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), enable, bit, bit);
1502} 1588}
1503 1589
1504static void dispc_ovl_set_mflag_threshold(enum omap_plane_id plane, 1590static void dispc_ovl_set_mflag_threshold(struct dispc_device *dispc,
1505 int low, int high) 1591 enum omap_plane_id plane,
1592 int low, int high)
1506{ 1593{
1507 dispc_write_reg(DISPC_OVL_MFLAG_THRESHOLD(plane), 1594 dispc_write_reg(dispc, DISPC_OVL_MFLAG_THRESHOLD(plane),
1508 FLD_VAL(high, 31, 16) | FLD_VAL(low, 15, 0)); 1595 FLD_VAL(high, 31, 16) | FLD_VAL(low, 15, 0));
1509} 1596}
1510 1597
1511static void dispc_init_mflag(void) 1598static void dispc_init_mflag(struct dispc_device *dispc)
1512{ 1599{
1513 int i; 1600 int i;
1514 1601
@@ -1522,16 +1609,16 @@ static void dispc_init_mflag(void)
1522 * 1609 *
1523 * As a work-around, set force MFLAG to always on. 1610 * As a work-around, set force MFLAG to always on.
1524 */ 1611 */
1525 dispc_write_reg(DISPC_GLOBAL_MFLAG_ATTRIBUTE, 1612 dispc_write_reg(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE,
1526 (1 << 0) | /* MFLAG_CTRL = force always on */ 1613 (1 << 0) | /* MFLAG_CTRL = force always on */
1527 (0 << 2)); /* MFLAG_START = disable */ 1614 (0 << 2)); /* MFLAG_START = disable */
1528 1615
1529 for (i = 0; i < dispc_get_num_ovls(); ++i) { 1616 for (i = 0; i < dispc_get_num_ovls(dispc); ++i) {
1530 u32 size = dispc_ovl_get_fifo_size(i); 1617 u32 size = dispc_ovl_get_fifo_size(dispc, i);
1531 u32 unit = dispc.feat->buffer_size_unit; 1618 u32 unit = dispc->feat->buffer_size_unit;
1532 u32 low, high; 1619 u32 low, high;
1533 1620
1534 dispc_ovl_set_mflag(i, true); 1621 dispc_ovl_set_mflag(dispc, i, true);
1535 1622
1536 /* 1623 /*
1537 * Simulation team suggests below thesholds: 1624 * Simulation team suggests below thesholds:
@@ -1542,15 +1629,15 @@ static void dispc_init_mflag(void)
1542 low = size * 4 / 8 / unit; 1629 low = size * 4 / 8 / unit;
1543 high = size * 5 / 8 / unit; 1630 high = size * 5 / 8 / unit;
1544 1631
1545 dispc_ovl_set_mflag_threshold(i, low, high); 1632 dispc_ovl_set_mflag_threshold(dispc, i, low, high);
1546 } 1633 }
1547 1634
1548 if (dispc.feat->has_writeback) { 1635 if (dispc->feat->has_writeback) {
1549 u32 size = dispc_ovl_get_fifo_size(OMAP_DSS_WB); 1636 u32 size = dispc_ovl_get_fifo_size(dispc, OMAP_DSS_WB);
1550 u32 unit = dispc.feat->buffer_size_unit; 1637 u32 unit = dispc->feat->buffer_size_unit;
1551 u32 low, high; 1638 u32 low, high;
1552 1639
1553 dispc_ovl_set_mflag(OMAP_DSS_WB, true); 1640 dispc_ovl_set_mflag(dispc, OMAP_DSS_WB, true);
1554 1641
1555 /* 1642 /*
1556 * Simulation team suggests below thesholds: 1643 * Simulation team suggests below thesholds:
@@ -1561,98 +1648,112 @@ static void dispc_init_mflag(void)
1561 low = size * 4 / 8 / unit; 1648 low = size * 4 / 8 / unit;
1562 high = size * 5 / 8 / unit; 1649 high = size * 5 / 8 / unit;
1563 1650
1564 dispc_ovl_set_mflag_threshold(OMAP_DSS_WB, low, high); 1651 dispc_ovl_set_mflag_threshold(dispc, OMAP_DSS_WB, low, high);
1565 } 1652 }
1566} 1653}
1567 1654
1568static void dispc_ovl_set_fir(enum omap_plane_id plane, 1655static void dispc_ovl_set_fir(struct dispc_device *dispc,
1569 int hinc, int vinc, 1656 enum omap_plane_id plane,
1570 enum omap_color_component color_comp) 1657 int hinc, int vinc,
1658 enum omap_color_component color_comp)
1571{ 1659{
1572 u32 val; 1660 u32 val;
1573 1661
1574 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) { 1662 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
1575 u8 hinc_start, hinc_end, vinc_start, vinc_end; 1663 u8 hinc_start, hinc_end, vinc_start, vinc_end;
1576 1664
1577 dispc_get_reg_field(FEAT_REG_FIRHINC, &hinc_start, &hinc_end); 1665 dispc_get_reg_field(dispc, FEAT_REG_FIRHINC,
1578 dispc_get_reg_field(FEAT_REG_FIRVINC, &vinc_start, &vinc_end); 1666 &hinc_start, &hinc_end);
1667 dispc_get_reg_field(dispc, FEAT_REG_FIRVINC,
1668 &vinc_start, &vinc_end);
1579 val = FLD_VAL(vinc, vinc_start, vinc_end) | 1669 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1580 FLD_VAL(hinc, hinc_start, hinc_end); 1670 FLD_VAL(hinc, hinc_start, hinc_end);
1581 1671
1582 dispc_write_reg(DISPC_OVL_FIR(plane), val); 1672 dispc_write_reg(dispc, DISPC_OVL_FIR(plane), val);
1583 } else { 1673 } else {
1584 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0); 1674 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1585 dispc_write_reg(DISPC_OVL_FIR2(plane), val); 1675 dispc_write_reg(dispc, DISPC_OVL_FIR2(plane), val);
1586 } 1676 }
1587} 1677}
1588 1678
1589static void dispc_ovl_set_vid_accu0(enum omap_plane_id plane, int haccu, 1679static void dispc_ovl_set_vid_accu0(struct dispc_device *dispc,
1680 enum omap_plane_id plane, int haccu,
1590 int vaccu) 1681 int vaccu)
1591{ 1682{
1592 u32 val; 1683 u32 val;
1593 u8 hor_start, hor_end, vert_start, vert_end; 1684 u8 hor_start, hor_end, vert_start, vert_end;
1594 1685
1595 dispc_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end); 1686 dispc_get_reg_field(dispc, FEAT_REG_HORIZONTALACCU,
1596 dispc_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end); 1687 &hor_start, &hor_end);
1688 dispc_get_reg_field(dispc, FEAT_REG_VERTICALACCU,
1689 &vert_start, &vert_end);
1597 1690
1598 val = FLD_VAL(vaccu, vert_start, vert_end) | 1691 val = FLD_VAL(vaccu, vert_start, vert_end) |
1599 FLD_VAL(haccu, hor_start, hor_end); 1692 FLD_VAL(haccu, hor_start, hor_end);
1600 1693
1601 dispc_write_reg(DISPC_OVL_ACCU0(plane), val); 1694 dispc_write_reg(dispc, DISPC_OVL_ACCU0(plane), val);
1602} 1695}
1603 1696
1604static void dispc_ovl_set_vid_accu1(enum omap_plane_id plane, int haccu, 1697static void dispc_ovl_set_vid_accu1(struct dispc_device *dispc,
1698 enum omap_plane_id plane, int haccu,
1605 int vaccu) 1699 int vaccu)
1606{ 1700{
1607 u32 val; 1701 u32 val;
1608 u8 hor_start, hor_end, vert_start, vert_end; 1702 u8 hor_start, hor_end, vert_start, vert_end;
1609 1703
1610 dispc_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end); 1704 dispc_get_reg_field(dispc, FEAT_REG_HORIZONTALACCU,
1611 dispc_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end); 1705 &hor_start, &hor_end);
1706 dispc_get_reg_field(dispc, FEAT_REG_VERTICALACCU,
1707 &vert_start, &vert_end);
1612 1708
1613 val = FLD_VAL(vaccu, vert_start, vert_end) | 1709 val = FLD_VAL(vaccu, vert_start, vert_end) |
1614 FLD_VAL(haccu, hor_start, hor_end); 1710 FLD_VAL(haccu, hor_start, hor_end);
1615 1711
1616 dispc_write_reg(DISPC_OVL_ACCU1(plane), val); 1712 dispc_write_reg(dispc, DISPC_OVL_ACCU1(plane), val);
1617} 1713}
1618 1714
1619static void dispc_ovl_set_vid_accu2_0(enum omap_plane_id plane, int haccu, 1715static void dispc_ovl_set_vid_accu2_0(struct dispc_device *dispc,
1620 int vaccu) 1716 enum omap_plane_id plane, int haccu,
1717 int vaccu)
1621{ 1718{
1622 u32 val; 1719 u32 val;
1623 1720
1624 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0); 1721 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1625 dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val); 1722 dispc_write_reg(dispc, DISPC_OVL_ACCU2_0(plane), val);
1626} 1723}
1627 1724
1628static void dispc_ovl_set_vid_accu2_1(enum omap_plane_id plane, int haccu, 1725static void dispc_ovl_set_vid_accu2_1(struct dispc_device *dispc,
1629 int vaccu) 1726 enum omap_plane_id plane, int haccu,
1727 int vaccu)
1630{ 1728{
1631 u32 val; 1729 u32 val;
1632 1730
1633 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0); 1731 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1634 dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val); 1732 dispc_write_reg(dispc, DISPC_OVL_ACCU2_1(plane), val);
1635} 1733}
1636 1734
1637static void dispc_ovl_set_scale_param(enum omap_plane_id plane, 1735static void dispc_ovl_set_scale_param(struct dispc_device *dispc,
1638 u16 orig_width, u16 orig_height, 1736 enum omap_plane_id plane,
1639 u16 out_width, u16 out_height, 1737 u16 orig_width, u16 orig_height,
1640 bool five_taps, u8 rotation, 1738 u16 out_width, u16 out_height,
1641 enum omap_color_component color_comp) 1739 bool five_taps, u8 rotation,
1740 enum omap_color_component color_comp)
1642{ 1741{
1643 int fir_hinc, fir_vinc; 1742 int fir_hinc, fir_vinc;
1644 1743
1645 fir_hinc = 1024 * orig_width / out_width; 1744 fir_hinc = 1024 * orig_width / out_width;
1646 fir_vinc = 1024 * orig_height / out_height; 1745 fir_vinc = 1024 * orig_height / out_height;
1647 1746
1648 dispc_ovl_set_scale_coef(plane, fir_hinc, fir_vinc, five_taps, 1747 dispc_ovl_set_scale_coef(dispc, plane, fir_hinc, fir_vinc, five_taps,
1649 color_comp); 1748 color_comp);
1650 dispc_ovl_set_fir(plane, fir_hinc, fir_vinc, color_comp); 1749 dispc_ovl_set_fir(dispc, plane, fir_hinc, fir_vinc, color_comp);
1651} 1750}
1652 1751
1653static void dispc_ovl_set_accu_uv(enum omap_plane_id plane, 1752static void dispc_ovl_set_accu_uv(struct dispc_device *dispc,
1654 u16 orig_width, u16 orig_height, u16 out_width, u16 out_height, 1753 enum omap_plane_id plane,
1655 bool ilace, u32 fourcc, u8 rotation) 1754 u16 orig_width, u16 orig_height,
1755 u16 out_width, u16 out_height,
1756 bool ilace, u32 fourcc, u8 rotation)
1656{ 1757{
1657 int h_accu2_0, h_accu2_1; 1758 int h_accu2_0, h_accu2_1;
1658 int v_accu2_0, v_accu2_1; 1759 int v_accu2_0, v_accu2_1;
@@ -1733,25 +1834,26 @@ static void dispc_ovl_set_accu_uv(enum omap_plane_id plane,
1733 v_accu2_0 = (accu_val->v0_m * chroma_vinc / accu_val->v0_n) % 1024; 1834 v_accu2_0 = (accu_val->v0_m * chroma_vinc / accu_val->v0_n) % 1024;
1734 v_accu2_1 = (accu_val->v1_m * chroma_vinc / accu_val->v1_n) % 1024; 1835 v_accu2_1 = (accu_val->v1_m * chroma_vinc / accu_val->v1_n) % 1024;
1735 1836
1736 dispc_ovl_set_vid_accu2_0(plane, h_accu2_0, v_accu2_0); 1837 dispc_ovl_set_vid_accu2_0(dispc, plane, h_accu2_0, v_accu2_0);
1737 dispc_ovl_set_vid_accu2_1(plane, h_accu2_1, v_accu2_1); 1838 dispc_ovl_set_vid_accu2_1(dispc, plane, h_accu2_1, v_accu2_1);
1738} 1839}
1739 1840
1740static void dispc_ovl_set_scaling_common(enum omap_plane_id plane, 1841static void dispc_ovl_set_scaling_common(struct dispc_device *dispc,
1741 u16 orig_width, u16 orig_height, 1842 enum omap_plane_id plane,
1742 u16 out_width, u16 out_height, 1843 u16 orig_width, u16 orig_height,
1743 bool ilace, bool five_taps, 1844 u16 out_width, u16 out_height,
1744 bool fieldmode, u32 fourcc, 1845 bool ilace, bool five_taps,
1745 u8 rotation) 1846 bool fieldmode, u32 fourcc,
1847 u8 rotation)
1746{ 1848{
1747 int accu0 = 0; 1849 int accu0 = 0;
1748 int accu1 = 0; 1850 int accu1 = 0;
1749 u32 l; 1851 u32 l;
1750 1852
1751 dispc_ovl_set_scale_param(plane, orig_width, orig_height, 1853 dispc_ovl_set_scale_param(dispc, plane, orig_width, orig_height,
1752 out_width, out_height, five_taps, 1854 out_width, out_height, five_taps,
1753 rotation, DISPC_COLOR_COMPONENT_RGB_Y); 1855 rotation, DISPC_COLOR_COMPONENT_RGB_Y);
1754 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane)); 1856 l = dispc_read_reg(dispc, DISPC_OVL_ATTRIBUTES(plane));
1755 1857
1756 /* RESIZEENABLE and VERTICALTAPS */ 1858 /* RESIZEENABLE and VERTICALTAPS */
1757 l &= ~((0x3 << 5) | (0x1 << 21)); 1859 l &= ~((0x3 << 5) | (0x1 << 21));
@@ -1760,19 +1862,19 @@ static void dispc_ovl_set_scaling_common(enum omap_plane_id plane,
1760 l |= five_taps ? (1 << 21) : 0; 1862 l |= five_taps ? (1 << 21) : 0;
1761 1863
1762 /* VRESIZECONF and HRESIZECONF */ 1864 /* VRESIZECONF and HRESIZECONF */
1763 if (dispc_has_feature(FEAT_RESIZECONF)) { 1865 if (dispc_has_feature(dispc, FEAT_RESIZECONF)) {
1764 l &= ~(0x3 << 7); 1866 l &= ~(0x3 << 7);
1765 l |= (orig_width <= out_width) ? 0 : (1 << 7); 1867 l |= (orig_width <= out_width) ? 0 : (1 << 7);
1766 l |= (orig_height <= out_height) ? 0 : (1 << 8); 1868 l |= (orig_height <= out_height) ? 0 : (1 << 8);
1767 } 1869 }
1768 1870
1769 /* LINEBUFFERSPLIT */ 1871 /* LINEBUFFERSPLIT */
1770 if (dispc_has_feature(FEAT_LINEBUFFERSPLIT)) { 1872 if (dispc_has_feature(dispc, FEAT_LINEBUFFERSPLIT)) {
1771 l &= ~(0x1 << 22); 1873 l &= ~(0x1 << 22);
1772 l |= five_taps ? (1 << 22) : 0; 1874 l |= five_taps ? (1 << 22) : 0;
1773 } 1875 }
1774 1876
1775 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l); 1877 dispc_write_reg(dispc, DISPC_OVL_ATTRIBUTES(plane), l);
1776 1878
1777 /* 1879 /*
1778 * field 0 = even field = bottom field 1880 * field 0 = even field = bottom field
@@ -1787,33 +1889,35 @@ static void dispc_ovl_set_scaling_common(enum omap_plane_id plane,
1787 } 1889 }
1788 } 1890 }
1789 1891
1790 dispc_ovl_set_vid_accu0(plane, 0, accu0); 1892 dispc_ovl_set_vid_accu0(dispc, plane, 0, accu0);
1791 dispc_ovl_set_vid_accu1(plane, 0, accu1); 1893 dispc_ovl_set_vid_accu1(dispc, plane, 0, accu1);
1792} 1894}
1793 1895
1794static void dispc_ovl_set_scaling_uv(enum omap_plane_id plane, 1896static void dispc_ovl_set_scaling_uv(struct dispc_device *dispc,
1795 u16 orig_width, u16 orig_height, 1897 enum omap_plane_id plane,
1796 u16 out_width, u16 out_height, 1898 u16 orig_width, u16 orig_height,
1797 bool ilace, bool five_taps, 1899 u16 out_width, u16 out_height,
1798 bool fieldmode, u32 fourcc, 1900 bool ilace, bool five_taps,
1799 u8 rotation) 1901 bool fieldmode, u32 fourcc,
1902 u8 rotation)
1800{ 1903{
1801 int scale_x = out_width != orig_width; 1904 int scale_x = out_width != orig_width;
1802 int scale_y = out_height != orig_height; 1905 int scale_y = out_height != orig_height;
1803 bool chroma_upscale = plane != OMAP_DSS_WB; 1906 bool chroma_upscale = plane != OMAP_DSS_WB;
1804 1907
1805 if (!dispc_has_feature(FEAT_HANDLE_UV_SEPARATE)) 1908 if (!dispc_has_feature(dispc, FEAT_HANDLE_UV_SEPARATE))
1806 return; 1909 return;
1807 1910
1808 if (!format_is_yuv(fourcc)) { 1911 if (!format_is_yuv(fourcc)) {
1809 /* reset chroma resampling for RGB formats */ 1912 /* reset chroma resampling for RGB formats */
1810 if (plane != OMAP_DSS_WB) 1913 if (plane != OMAP_DSS_WB)
1811 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8); 1914 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES2(plane),
1915 0, 8, 8);
1812 return; 1916 return;
1813 } 1917 }
1814 1918
1815 dispc_ovl_set_accu_uv(plane, orig_width, orig_height, out_width, 1919 dispc_ovl_set_accu_uv(dispc, plane, orig_width, orig_height, out_width,
1816 out_height, ilace, fourcc, rotation); 1920 out_height, ilace, fourcc, rotation);
1817 1921
1818 switch (fourcc) { 1922 switch (fourcc) {
1819 case DRM_FORMAT_NV12: 1923 case DRM_FORMAT_NV12:
@@ -1855,46 +1959,43 @@ static void dispc_ovl_set_scaling_uv(enum omap_plane_id plane,
1855 if (out_height != orig_height) 1959 if (out_height != orig_height)
1856 scale_y = true; 1960 scale_y = true;
1857 1961
1858 dispc_ovl_set_scale_param(plane, orig_width, orig_height, 1962 dispc_ovl_set_scale_param(dispc, plane, orig_width, orig_height,
1859 out_width, out_height, five_taps, 1963 out_width, out_height, five_taps,
1860 rotation, DISPC_COLOR_COMPONENT_UV); 1964 rotation, DISPC_COLOR_COMPONENT_UV);
1861 1965
1862 if (plane != OMAP_DSS_WB) 1966 if (plane != OMAP_DSS_WB)
1863 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 1967 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES2(plane),
1864 (scale_x || scale_y) ? 1 : 0, 8, 8); 1968 (scale_x || scale_y) ? 1 : 0, 8, 8);
1865 1969
1866 /* set H scaling */ 1970 /* set H scaling */
1867 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5); 1971 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);
1868 /* set V scaling */ 1972 /* set V scaling */
1869 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6); 1973 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
1870} 1974}
1871 1975
1872static void dispc_ovl_set_scaling(enum omap_plane_id plane, 1976static void dispc_ovl_set_scaling(struct dispc_device *dispc,
1873 u16 orig_width, u16 orig_height, 1977 enum omap_plane_id plane,
1874 u16 out_width, u16 out_height, 1978 u16 orig_width, u16 orig_height,
1875 bool ilace, bool five_taps, 1979 u16 out_width, u16 out_height,
1876 bool fieldmode, u32 fourcc, 1980 bool ilace, bool five_taps,
1877 u8 rotation) 1981 bool fieldmode, u32 fourcc,
1982 u8 rotation)
1878{ 1983{
1879 BUG_ON(plane == OMAP_DSS_GFX); 1984 BUG_ON(plane == OMAP_DSS_GFX);
1880 1985
1881 dispc_ovl_set_scaling_common(plane, 1986 dispc_ovl_set_scaling_common(dispc, plane, orig_width, orig_height,
1882 orig_width, orig_height, 1987 out_width, out_height, ilace, five_taps,
1883 out_width, out_height, 1988 fieldmode, fourcc, rotation);
1884 ilace, five_taps,
1885 fieldmode, fourcc,
1886 rotation);
1887 1989
1888 dispc_ovl_set_scaling_uv(plane, 1990 dispc_ovl_set_scaling_uv(dispc, plane, orig_width, orig_height,
1889 orig_width, orig_height, 1991 out_width, out_height, ilace, five_taps,
1890 out_width, out_height, 1992 fieldmode, fourcc, rotation);
1891 ilace, five_taps,
1892 fieldmode, fourcc,
1893 rotation);
1894} 1993}
1895 1994
1896static void dispc_ovl_set_rotation_attrs(enum omap_plane_id plane, u8 rotation, 1995static void dispc_ovl_set_rotation_attrs(struct dispc_device *dispc,
1897 enum omap_dss_rotation_type rotation_type, u32 fourcc) 1996 enum omap_plane_id plane, u8 rotation,
1997 enum omap_dss_rotation_type rotation_type,
1998 u32 fourcc)
1898{ 1999{
1899 bool row_repeat = false; 2000 bool row_repeat = false;
1900 int vidrot = 0; 2001 int vidrot = 0;
@@ -1948,19 +2049,20 @@ static void dispc_ovl_set_rotation_attrs(enum omap_plane_id plane, u8 rotation,
1948 if (fourcc == DRM_FORMAT_NV12 && rotation_type != OMAP_DSS_ROT_TILER) 2049 if (fourcc == DRM_FORMAT_NV12 && rotation_type != OMAP_DSS_ROT_TILER)
1949 vidrot = 1; 2050 vidrot = 1;
1950 2051
1951 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12); 2052 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
1952 if (dispc_has_feature(FEAT_ROWREPEATENABLE)) 2053 if (dispc_has_feature(dispc, FEAT_ROWREPEATENABLE))
1953 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 2054 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane),
1954 row_repeat ? 1 : 0, 18, 18); 2055 row_repeat ? 1 : 0, 18, 18);
1955 2056
1956 if (dispc_ovl_color_mode_supported(plane, DRM_FORMAT_NV12)) { 2057 if (dispc_ovl_color_mode_supported(dispc, plane, DRM_FORMAT_NV12)) {
1957 bool doublestride = 2058 bool doublestride =
1958 fourcc == DRM_FORMAT_NV12 && 2059 fourcc == DRM_FORMAT_NV12 &&
1959 rotation_type == OMAP_DSS_ROT_TILER && 2060 rotation_type == OMAP_DSS_ROT_TILER &&
1960 !drm_rotation_90_or_270(rotation); 2061 !drm_rotation_90_or_270(rotation);
1961 2062
1962 /* DOUBLESTRIDE */ 2063 /* DOUBLESTRIDE */
1963 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), doublestride, 22, 22); 2064 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane),
2065 doublestride, 22, 22);
1964 } 2066 }
1965} 2067}
1966 2068
@@ -2006,8 +2108,8 @@ static s32 pixinc(int pixels, u8 ps)
2006} 2108}
2007 2109
2008static void calc_offset(u16 screen_width, u16 width, 2110static void calc_offset(u16 screen_width, u16 width,
2009 u32 fourcc, bool fieldmode, 2111 u32 fourcc, bool fieldmode, unsigned int field_offset,
2010 unsigned int field_offset, unsigned *offset0, unsigned *offset1, 2112 unsigned int *offset0, unsigned int *offset1,
2011 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim, 2113 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim,
2012 enum omap_dss_rotation_type rotation_type, u8 rotation) 2114 enum omap_dss_rotation_type rotation_type, u8 rotation)
2013{ 2115{
@@ -2197,27 +2299,31 @@ static unsigned long calc_core_clk_44xx(unsigned long pclk, u16 width,
2197 return pclk; 2299 return pclk;
2198} 2300}
2199 2301
2200static int dispc_ovl_calc_scaling_24xx(unsigned long pclk, unsigned long lclk, 2302static int dispc_ovl_calc_scaling_24xx(struct dispc_device *dispc,
2201 const struct videomode *vm, 2303 unsigned long pclk, unsigned long lclk,
2202 u16 width, u16 height, u16 out_width, u16 out_height, 2304 const struct videomode *vm,
2203 u32 fourcc, bool *five_taps, 2305 u16 width, u16 height,
2204 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y, 2306 u16 out_width, u16 out_height,
2205 u16 pos_x, unsigned long *core_clk, bool mem_to_mem) 2307 u32 fourcc, bool *five_taps,
2308 int *x_predecim, int *y_predecim,
2309 int *decim_x, int *decim_y,
2310 u16 pos_x, unsigned long *core_clk,
2311 bool mem_to_mem)
2206{ 2312{
2207 int error; 2313 int error;
2208 u16 in_width, in_height; 2314 u16 in_width, in_height;
2209 int min_factor = min(*decim_x, *decim_y); 2315 int min_factor = min(*decim_x, *decim_y);
2210 const int maxsinglelinewidth = dispc.feat->max_line_width; 2316 const int maxsinglelinewidth = dispc->feat->max_line_width;
2211 2317
2212 *five_taps = false; 2318 *five_taps = false;
2213 2319
2214 do { 2320 do {
2215 in_height = height / *decim_y; 2321 in_height = height / *decim_y;
2216 in_width = width / *decim_x; 2322 in_width = width / *decim_x;
2217 *core_clk = dispc.feat->calc_core_clk(pclk, in_width, 2323 *core_clk = dispc->feat->calc_core_clk(pclk, in_width,
2218 in_height, out_width, out_height, mem_to_mem); 2324 in_height, out_width, out_height, mem_to_mem);
2219 error = (in_width > maxsinglelinewidth || !*core_clk || 2325 error = (in_width > maxsinglelinewidth || !*core_clk ||
2220 *core_clk > dispc_core_clk_rate()); 2326 *core_clk > dispc_core_clk_rate(dispc));
2221 if (error) { 2327 if (error) {
2222 if (*decim_x == *decim_y) { 2328 if (*decim_x == *decim_y) {
2223 *decim_x = min_factor; 2329 *decim_x = min_factor;
@@ -2242,16 +2348,20 @@ static int dispc_ovl_calc_scaling_24xx(unsigned long pclk, unsigned long lclk,
2242 return 0; 2348 return 0;
2243} 2349}
2244 2350
2245static int dispc_ovl_calc_scaling_34xx(unsigned long pclk, unsigned long lclk, 2351static int dispc_ovl_calc_scaling_34xx(struct dispc_device *dispc,
2246 const struct videomode *vm, 2352 unsigned long pclk, unsigned long lclk,
2247 u16 width, u16 height, u16 out_width, u16 out_height, 2353 const struct videomode *vm,
2248 u32 fourcc, bool *five_taps, 2354 u16 width, u16 height,
2249 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y, 2355 u16 out_width, u16 out_height,
2250 u16 pos_x, unsigned long *core_clk, bool mem_to_mem) 2356 u32 fourcc, bool *five_taps,
2357 int *x_predecim, int *y_predecim,
2358 int *decim_x, int *decim_y,
2359 u16 pos_x, unsigned long *core_clk,
2360 bool mem_to_mem)
2251{ 2361{
2252 int error; 2362 int error;
2253 u16 in_width, in_height; 2363 u16 in_width, in_height;
2254 const int maxsinglelinewidth = dispc.feat->max_line_width; 2364 const int maxsinglelinewidth = dispc->feat->max_line_width;
2255 2365
2256 do { 2366 do {
2257 in_height = height / *decim_y; 2367 in_height = height / *decim_y;
@@ -2268,7 +2378,7 @@ again:
2268 in_width, in_height, out_width, 2378 in_width, in_height, out_width,
2269 out_height, fourcc); 2379 out_height, fourcc);
2270 else 2380 else
2271 *core_clk = dispc.feat->calc_core_clk(pclk, in_width, 2381 *core_clk = dispc->feat->calc_core_clk(pclk, in_width,
2272 in_height, out_width, out_height, 2382 in_height, out_width, out_height,
2273 mem_to_mem); 2383 mem_to_mem);
2274 2384
@@ -2282,7 +2392,7 @@ again:
2282 2392
2283 error = (error || in_width > maxsinglelinewidth * 2 || 2393 error = (error || in_width > maxsinglelinewidth * 2 ||
2284 (in_width > maxsinglelinewidth && *five_taps) || 2394 (in_width > maxsinglelinewidth && *five_taps) ||
2285 !*core_clk || *core_clk > dispc_core_clk_rate()); 2395 !*core_clk || *core_clk > dispc_core_clk_rate(dispc));
2286 2396
2287 if (!error) { 2397 if (!error) {
2288 /* verify that we're inside the limits of scaler */ 2398 /* verify that we're inside the limits of scaler */
@@ -2326,24 +2436,28 @@ again:
2326 return 0; 2436 return 0;
2327} 2437}
2328 2438
2329static int dispc_ovl_calc_scaling_44xx(unsigned long pclk, unsigned long lclk, 2439static int dispc_ovl_calc_scaling_44xx(struct dispc_device *dispc,
2330 const struct videomode *vm, 2440 unsigned long pclk, unsigned long lclk,
2331 u16 width, u16 height, u16 out_width, u16 out_height, 2441 const struct videomode *vm,
2332 u32 fourcc, bool *five_taps, 2442 u16 width, u16 height,
2333 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y, 2443 u16 out_width, u16 out_height,
2334 u16 pos_x, unsigned long *core_clk, bool mem_to_mem) 2444 u32 fourcc, bool *five_taps,
2445 int *x_predecim, int *y_predecim,
2446 int *decim_x, int *decim_y,
2447 u16 pos_x, unsigned long *core_clk,
2448 bool mem_to_mem)
2335{ 2449{
2336 u16 in_width, in_width_max; 2450 u16 in_width, in_width_max;
2337 int decim_x_min = *decim_x; 2451 int decim_x_min = *decim_x;
2338 u16 in_height = height / *decim_y; 2452 u16 in_height = height / *decim_y;
2339 const int maxsinglelinewidth = dispc.feat->max_line_width; 2453 const int maxsinglelinewidth = dispc->feat->max_line_width;
2340 const int maxdownscale = dispc.feat->max_downscale; 2454 const int maxdownscale = dispc->feat->max_downscale;
2341 2455
2342 if (mem_to_mem) { 2456 if (mem_to_mem) {
2343 in_width_max = out_width * maxdownscale; 2457 in_width_max = out_width * maxdownscale;
2344 } else { 2458 } else {
2345 in_width_max = dispc_core_clk_rate() / 2459 in_width_max = dispc_core_clk_rate(dispc)
2346 DIV_ROUND_UP(pclk, out_width); 2460 / DIV_ROUND_UP(pclk, out_width);
2347 } 2461 }
2348 2462
2349 *decim_x = DIV_ROUND_UP(width, in_width_max); 2463 *decim_x = DIV_ROUND_UP(width, in_width_max);
@@ -2381,7 +2495,7 @@ static int dispc_ovl_calc_scaling_44xx(unsigned long pclk, unsigned long lclk,
2381 return -EINVAL; 2495 return -EINVAL;
2382 } 2496 }
2383 2497
2384 *core_clk = dispc.feat->calc_core_clk(pclk, in_width, in_height, 2498 *core_clk = dispc->feat->calc_core_clk(pclk, in_width, in_height,
2385 out_width, out_height, mem_to_mem); 2499 out_width, out_height, mem_to_mem);
2386 return 0; 2500 return 0;
2387} 2501}
@@ -2389,15 +2503,20 @@ static int dispc_ovl_calc_scaling_44xx(unsigned long pclk, unsigned long lclk,
2389#define DIV_FRAC(dividend, divisor) \ 2503#define DIV_FRAC(dividend, divisor) \
2390 ((dividend) * 100 / (divisor) - ((dividend) / (divisor) * 100)) 2504 ((dividend) * 100 / (divisor) - ((dividend) / (divisor) * 100))
2391 2505
2392static int dispc_ovl_calc_scaling(unsigned long pclk, unsigned long lclk, 2506static int dispc_ovl_calc_scaling(struct dispc_device *dispc,
2393 enum omap_overlay_caps caps, 2507 enum omap_plane_id plane,
2394 const struct videomode *vm, 2508 unsigned long pclk, unsigned long lclk,
2395 u16 width, u16 height, u16 out_width, u16 out_height, 2509 enum omap_overlay_caps caps,
2396 u32 fourcc, bool *five_taps, 2510 const struct videomode *vm,
2397 int *x_predecim, int *y_predecim, u16 pos_x, 2511 u16 width, u16 height,
2398 enum omap_dss_rotation_type rotation_type, bool mem_to_mem) 2512 u16 out_width, u16 out_height,
2399{ 2513 u32 fourcc, bool *five_taps,
2400 const int maxdownscale = dispc.feat->max_downscale; 2514 int *x_predecim, int *y_predecim, u16 pos_x,
2515 enum omap_dss_rotation_type rotation_type,
2516 bool mem_to_mem)
2517{
2518 int maxhdownscale = dispc->feat->max_downscale;
2519 int maxvdownscale = dispc->feat->max_downscale;
2401 const int max_decim_limit = 16; 2520 const int max_decim_limit = 16;
2402 unsigned long core_clk = 0; 2521 unsigned long core_clk = 0;
2403 int decim_x, decim_y, ret; 2522 int decim_x, decim_y, ret;
@@ -2405,6 +2524,20 @@ static int dispc_ovl_calc_scaling(unsigned long pclk, unsigned long lclk,
2405 if (width == out_width && height == out_height) 2524 if (width == out_width && height == out_height)
2406 return 0; 2525 return 0;
2407 2526
2527 if (plane == OMAP_DSS_WB) {
2528 switch (fourcc) {
2529 case DRM_FORMAT_NV12:
2530 maxhdownscale = maxvdownscale = 2;
2531 break;
2532 case DRM_FORMAT_YUYV:
2533 case DRM_FORMAT_UYVY:
2534 maxhdownscale = 2;
2535 maxvdownscale = 4;
2536 break;
2537 default:
2538 break;
2539 }
2540 }
2408 if (!mem_to_mem && (pclk == 0 || vm->pixelclock == 0)) { 2541 if (!mem_to_mem && (pclk == 0 || vm->pixelclock == 0)) {
2409 DSSERR("cannot calculate scaling settings: pclk is zero\n"); 2542 DSSERR("cannot calculate scaling settings: pclk is zero\n");
2410 return -EINVAL; 2543 return -EINVAL;
@@ -2418,12 +2551,12 @@ static int dispc_ovl_calc_scaling(unsigned long pclk, unsigned long lclk,
2418 } else { 2551 } else {
2419 *x_predecim = max_decim_limit; 2552 *x_predecim = max_decim_limit;
2420 *y_predecim = (rotation_type == OMAP_DSS_ROT_TILER && 2553 *y_predecim = (rotation_type == OMAP_DSS_ROT_TILER &&
2421 dispc_has_feature(FEAT_BURST_2D)) ? 2554 dispc_has_feature(dispc, FEAT_BURST_2D)) ?
2422 2 : max_decim_limit; 2555 2 : max_decim_limit;
2423 } 2556 }
2424 2557
2425 decim_x = DIV_ROUND_UP(DIV_ROUND_UP(width, out_width), maxdownscale); 2558 decim_x = DIV_ROUND_UP(DIV_ROUND_UP(width, out_width), maxhdownscale);
2426 decim_y = DIV_ROUND_UP(DIV_ROUND_UP(height, out_height), maxdownscale); 2559 decim_y = DIV_ROUND_UP(DIV_ROUND_UP(height, out_height), maxvdownscale);
2427 2560
2428 if (decim_x > *x_predecim || out_width > width * 8) 2561 if (decim_x > *x_predecim || out_width > width * 8)
2429 return -EINVAL; 2562 return -EINVAL;
@@ -2431,10 +2564,11 @@ static int dispc_ovl_calc_scaling(unsigned long pclk, unsigned long lclk,
2431 if (decim_y > *y_predecim || out_height > height * 8) 2564 if (decim_y > *y_predecim || out_height > height * 8)
2432 return -EINVAL; 2565 return -EINVAL;
2433 2566
2434 ret = dispc.feat->calc_scaling(pclk, lclk, vm, width, height, 2567 ret = dispc->feat->calc_scaling(dispc, pclk, lclk, vm, width, height,
2435 out_width, out_height, fourcc, five_taps, 2568 out_width, out_height, fourcc,
2436 x_predecim, y_predecim, &decim_x, &decim_y, pos_x, &core_clk, 2569 five_taps, x_predecim, y_predecim,
2437 mem_to_mem); 2570 &decim_x, &decim_y, pos_x, &core_clk,
2571 mem_to_mem);
2438 if (ret) 2572 if (ret)
2439 return ret; 2573 return ret;
2440 2574
@@ -2450,13 +2584,13 @@ static int dispc_ovl_calc_scaling(unsigned long pclk, unsigned long lclk,
2450 out_height / (height / decim_y), DIV_FRAC(out_height, height / decim_y), 2584 out_height / (height / decim_y), DIV_FRAC(out_height, height / decim_y),
2451 2585
2452 *five_taps ? 5 : 3, 2586 *five_taps ? 5 : 3,
2453 core_clk, dispc_core_clk_rate()); 2587 core_clk, dispc_core_clk_rate(dispc));
2454 2588
2455 if (!core_clk || core_clk > dispc_core_clk_rate()) { 2589 if (!core_clk || core_clk > dispc_core_clk_rate(dispc)) {
2456 DSSERR("failed to set up scaling, " 2590 DSSERR("failed to set up scaling, "
2457 "required core clk rate = %lu Hz, " 2591 "required core clk rate = %lu Hz, "
2458 "current core clk rate = %lu Hz\n", 2592 "current core clk rate = %lu Hz\n",
2459 core_clk, dispc_core_clk_rate()); 2593 core_clk, dispc_core_clk_rate(dispc));
2460 return -EINVAL; 2594 return -EINVAL;
2461 } 2595 }
2462 2596
@@ -2465,19 +2599,23 @@ static int dispc_ovl_calc_scaling(unsigned long pclk, unsigned long lclk,
2465 return 0; 2599 return 0;
2466} 2600}
2467 2601
2468static int dispc_ovl_setup_common(enum omap_plane_id plane, 2602static int dispc_ovl_setup_common(struct dispc_device *dispc,
2469 enum omap_overlay_caps caps, u32 paddr, u32 p_uv_addr, 2603 enum omap_plane_id plane,
2470 u16 screen_width, int pos_x, int pos_y, u16 width, u16 height, 2604 enum omap_overlay_caps caps,
2471 u16 out_width, u16 out_height, u32 fourcc, 2605 u32 paddr, u32 p_uv_addr,
2472 u8 rotation, u8 zorder, u8 pre_mult_alpha, 2606 u16 screen_width, int pos_x, int pos_y,
2473 u8 global_alpha, enum omap_dss_rotation_type rotation_type, 2607 u16 width, u16 height,
2474 bool replication, const struct videomode *vm, 2608 u16 out_width, u16 out_height,
2475 bool mem_to_mem) 2609 u32 fourcc, u8 rotation, u8 zorder,
2610 u8 pre_mult_alpha, u8 global_alpha,
2611 enum omap_dss_rotation_type rotation_type,
2612 bool replication, const struct videomode *vm,
2613 bool mem_to_mem)
2476{ 2614{
2477 bool five_taps = true; 2615 bool five_taps = true;
2478 bool fieldmode = false; 2616 bool fieldmode = false;
2479 int r, cconv = 0; 2617 int r, cconv = 0;
2480 unsigned offset0, offset1; 2618 unsigned int offset0, offset1;
2481 s32 row_inc; 2619 s32 row_inc;
2482 s32 pix_inc; 2620 s32 pix_inc;
2483 u16 frame_width, frame_height; 2621 u16 frame_width, frame_height;
@@ -2486,8 +2624,12 @@ static int dispc_ovl_setup_common(enum omap_plane_id plane,
2486 u16 in_width = width; 2624 u16 in_width = width;
2487 int x_predecim = 1, y_predecim = 1; 2625 int x_predecim = 1, y_predecim = 1;
2488 bool ilace = !!(vm->flags & DISPLAY_FLAGS_INTERLACED); 2626 bool ilace = !!(vm->flags & DISPLAY_FLAGS_INTERLACED);
2489 unsigned long pclk = dispc_plane_pclk_rate(plane); 2627 unsigned long pclk = dispc_plane_pclk_rate(dispc, plane);
2490 unsigned long lclk = dispc_plane_lclk_rate(plane); 2628 unsigned long lclk = dispc_plane_lclk_rate(dispc, plane);
2629
2630 /* when setting up WB, dispc_plane_pclk_rate() returns 0 */
2631 if (plane == OMAP_DSS_WB)
2632 pclk = vm->pixelclock;
2491 2633
2492 if (paddr == 0 && rotation_type != OMAP_DSS_ROT_TILER) 2634 if (paddr == 0 && rotation_type != OMAP_DSS_ROT_TILER)
2493 return -EINVAL; 2635 return -EINVAL;
@@ -2500,27 +2642,28 @@ static int dispc_ovl_setup_common(enum omap_plane_id plane,
2500 out_width = out_width == 0 ? width : out_width; 2642 out_width = out_width == 0 ? width : out_width;
2501 out_height = out_height == 0 ? height : out_height; 2643 out_height = out_height == 0 ? height : out_height;
2502 2644
2503 if (ilace && height == out_height) 2645 if (plane != OMAP_DSS_WB) {
2504 fieldmode = true; 2646 if (ilace && height == out_height)
2647 fieldmode = true;
2505 2648
2506 if (ilace) { 2649 if (ilace) {
2507 if (fieldmode) 2650 if (fieldmode)
2508 in_height /= 2; 2651 in_height /= 2;
2509 pos_y /= 2; 2652 pos_y /= 2;
2510 out_height /= 2; 2653 out_height /= 2;
2511 2654
2512 DSSDBG("adjusting for ilace: height %d, pos_y %d, " 2655 DSSDBG("adjusting for ilace: height %d, pos_y %d, out_height %d\n",
2513 "out_height %d\n", in_height, pos_y, 2656 in_height, pos_y, out_height);
2514 out_height); 2657 }
2515 } 2658 }
2516 2659
2517 if (!dispc_ovl_color_mode_supported(plane, fourcc)) 2660 if (!dispc_ovl_color_mode_supported(dispc, plane, fourcc))
2518 return -EINVAL; 2661 return -EINVAL;
2519 2662
2520 r = dispc_ovl_calc_scaling(pclk, lclk, caps, vm, in_width, 2663 r = dispc_ovl_calc_scaling(dispc, plane, pclk, lclk, caps, vm, in_width,
2521 in_height, out_width, out_height, fourcc, 2664 in_height, out_width, out_height, fourcc,
2522 &five_taps, &x_predecim, &y_predecim, pos_x, 2665 &five_taps, &x_predecim, &y_predecim, pos_x,
2523 rotation_type, mem_to_mem); 2666 rotation_type, mem_to_mem);
2524 if (r) 2667 if (r)
2525 return r; 2668 return r;
2526 2669
@@ -2582,60 +2725,62 @@ static int dispc_ovl_setup_common(enum omap_plane_id plane,
2582 DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n", 2725 DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
2583 offset0, offset1, row_inc, pix_inc); 2726 offset0, offset1, row_inc, pix_inc);
2584 2727
2585 dispc_ovl_set_color_mode(plane, fourcc); 2728 dispc_ovl_set_color_mode(dispc, plane, fourcc);
2586 2729
2587 dispc_ovl_configure_burst_type(plane, rotation_type); 2730 dispc_ovl_configure_burst_type(dispc, plane, rotation_type);
2588 2731
2589 if (dispc.feat->reverse_ilace_field_order) 2732 if (dispc->feat->reverse_ilace_field_order)
2590 swap(offset0, offset1); 2733 swap(offset0, offset1);
2591 2734
2592 dispc_ovl_set_ba0(plane, paddr + offset0); 2735 dispc_ovl_set_ba0(dispc, plane, paddr + offset0);
2593 dispc_ovl_set_ba1(plane, paddr + offset1); 2736 dispc_ovl_set_ba1(dispc, plane, paddr + offset1);
2594 2737
2595 if (fourcc == DRM_FORMAT_NV12) { 2738 if (fourcc == DRM_FORMAT_NV12) {
2596 dispc_ovl_set_ba0_uv(plane, p_uv_addr + offset0); 2739 dispc_ovl_set_ba0_uv(dispc, plane, p_uv_addr + offset0);
2597 dispc_ovl_set_ba1_uv(plane, p_uv_addr + offset1); 2740 dispc_ovl_set_ba1_uv(dispc, plane, p_uv_addr + offset1);
2598 } 2741 }
2599 2742
2600 if (dispc.feat->last_pixel_inc_missing) 2743 if (dispc->feat->last_pixel_inc_missing)
2601 row_inc += pix_inc - 1; 2744 row_inc += pix_inc - 1;
2602 2745
2603 dispc_ovl_set_row_inc(plane, row_inc); 2746 dispc_ovl_set_row_inc(dispc, plane, row_inc);
2604 dispc_ovl_set_pix_inc(plane, pix_inc); 2747 dispc_ovl_set_pix_inc(dispc, plane, pix_inc);
2605 2748
2606 DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, in_width, 2749 DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, in_width,
2607 in_height, out_width, out_height); 2750 in_height, out_width, out_height);
2608 2751
2609 dispc_ovl_set_pos(plane, caps, pos_x, pos_y); 2752 dispc_ovl_set_pos(dispc, plane, caps, pos_x, pos_y);
2610 2753
2611 dispc_ovl_set_input_size(plane, in_width, in_height); 2754 dispc_ovl_set_input_size(dispc, plane, in_width, in_height);
2612 2755
2613 if (caps & OMAP_DSS_OVL_CAP_SCALE) { 2756 if (caps & OMAP_DSS_OVL_CAP_SCALE) {
2614 dispc_ovl_set_scaling(plane, in_width, in_height, out_width, 2757 dispc_ovl_set_scaling(dispc, plane, in_width, in_height,
2615 out_height, ilace, five_taps, fieldmode, 2758 out_width, out_height, ilace, five_taps,
2616 fourcc, rotation); 2759 fieldmode, fourcc, rotation);
2617 dispc_ovl_set_output_size(plane, out_width, out_height); 2760 dispc_ovl_set_output_size(dispc, plane, out_width, out_height);
2618 dispc_ovl_set_vid_color_conv(plane, cconv); 2761 dispc_ovl_set_vid_color_conv(dispc, plane, cconv);
2619 } 2762 }
2620 2763
2621 dispc_ovl_set_rotation_attrs(plane, rotation, rotation_type, fourcc); 2764 dispc_ovl_set_rotation_attrs(dispc, plane, rotation, rotation_type,
2765 fourcc);
2622 2766
2623 dispc_ovl_set_zorder(plane, caps, zorder); 2767 dispc_ovl_set_zorder(dispc, plane, caps, zorder);
2624 dispc_ovl_set_pre_mult_alpha(plane, caps, pre_mult_alpha); 2768 dispc_ovl_set_pre_mult_alpha(dispc, plane, caps, pre_mult_alpha);
2625 dispc_ovl_setup_global_alpha(plane, caps, global_alpha); 2769 dispc_ovl_setup_global_alpha(dispc, plane, caps, global_alpha);
2626 2770
2627 dispc_ovl_enable_replication(plane, caps, replication); 2771 dispc_ovl_enable_replication(dispc, plane, caps, replication);
2628 2772
2629 return 0; 2773 return 0;
2630} 2774}
2631 2775
2632static int dispc_ovl_setup(enum omap_plane_id plane, 2776static int dispc_ovl_setup(struct dispc_device *dispc,
2633 const struct omap_overlay_info *oi, 2777 enum omap_plane_id plane,
2634 const struct videomode *vm, bool mem_to_mem, 2778 const struct omap_overlay_info *oi,
2635 enum omap_channel channel) 2779 const struct videomode *vm, bool mem_to_mem,
2780 enum omap_channel channel)
2636{ 2781{
2637 int r; 2782 int r;
2638 enum omap_overlay_caps caps = dispc.feat->overlay_caps[plane]; 2783 enum omap_overlay_caps caps = dispc->feat->overlay_caps[plane];
2639 const bool replication = true; 2784 const bool replication = true;
2640 2785
2641 DSSDBG("dispc_ovl_setup %d, pa %pad, pa_uv %pad, sw %d, %d,%d, %dx%d ->" 2786 DSSDBG("dispc_ovl_setup %d, pa %pad, pa_uv %pad, sw %d, %d,%d, %dx%d ->"
@@ -2644,9 +2789,9 @@ static int dispc_ovl_setup(enum omap_plane_id plane,
2644 oi->pos_y, oi->width, oi->height, oi->out_width, oi->out_height, 2789 oi->pos_y, oi->width, oi->height, oi->out_width, oi->out_height,
2645 oi->fourcc, oi->rotation, channel, replication); 2790 oi->fourcc, oi->rotation, channel, replication);
2646 2791
2647 dispc_ovl_set_channel_out(plane, channel); 2792 dispc_ovl_set_channel_out(dispc, plane, channel);
2648 2793
2649 r = dispc_ovl_setup_common(plane, caps, oi->paddr, oi->p_uv_addr, 2794 r = dispc_ovl_setup_common(dispc, plane, caps, oi->paddr, oi->p_uv_addr,
2650 oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height, 2795 oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height,
2651 oi->out_width, oi->out_height, oi->fourcc, oi->rotation, 2796 oi->out_width, oi->out_height, oi->fourcc, oi->rotation,
2652 oi->zorder, oi->pre_mult_alpha, oi->global_alpha, 2797 oi->zorder, oi->pre_mult_alpha, oi->global_alpha,
@@ -2655,8 +2800,10 @@ static int dispc_ovl_setup(enum omap_plane_id plane,
2655 return r; 2800 return r;
2656} 2801}
2657 2802
2658int dispc_wb_setup(const struct omap_dss_writeback_info *wi, 2803static int dispc_wb_setup(struct dispc_device *dispc,
2659 bool mem_to_mem, const struct videomode *vm) 2804 const struct omap_dss_writeback_info *wi,
2805 bool mem_to_mem, const struct videomode *vm,
2806 enum dss_writeback_channel channel_in)
2660{ 2807{
2661 int r; 2808 int r;
2662 u32 l; 2809 u32 l;
@@ -2670,15 +2817,20 @@ int dispc_wb_setup(const struct omap_dss_writeback_info *wi,
2670 enum omap_overlay_caps caps = 2817 enum omap_overlay_caps caps =
2671 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA; 2818 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA;
2672 2819
2820 if (vm->flags & DISPLAY_FLAGS_INTERLACED)
2821 in_height /= 2;
2822
2673 DSSDBG("dispc_wb_setup, pa %x, pa_uv %x, %d,%d -> %dx%d, cmode %x, " 2823 DSSDBG("dispc_wb_setup, pa %x, pa_uv %x, %d,%d -> %dx%d, cmode %x, "
2674 "rot %d\n", wi->paddr, wi->p_uv_addr, in_width, 2824 "rot %d\n", wi->paddr, wi->p_uv_addr, in_width,
2675 in_height, wi->width, wi->height, wi->fourcc, wi->rotation); 2825 in_height, wi->width, wi->height, wi->fourcc, wi->rotation);
2676 2826
2677 r = dispc_ovl_setup_common(plane, caps, wi->paddr, wi->p_uv_addr, 2827 r = dispc_ovl_setup_common(dispc, plane, caps, wi->paddr, wi->p_uv_addr,
2678 wi->buf_width, pos_x, pos_y, in_width, in_height, wi->width, 2828 wi->buf_width, pos_x, pos_y, in_width, in_height, wi->width,
2679 wi->height, wi->fourcc, wi->rotation, zorder, 2829 wi->height, wi->fourcc, wi->rotation, zorder,
2680 wi->pre_mult_alpha, global_alpha, wi->rotation_type, 2830 wi->pre_mult_alpha, global_alpha, wi->rotation_type,
2681 replication, vm, mem_to_mem); 2831 replication, vm, mem_to_mem);
2832 if (r)
2833 return r;
2682 2834
2683 switch (wi->fourcc) { 2835 switch (wi->fourcc) {
2684 case DRM_FORMAT_RGB565: 2836 case DRM_FORMAT_RGB565:
@@ -2697,132 +2849,162 @@ int dispc_wb_setup(const struct omap_dss_writeback_info *wi,
2697 } 2849 }
2698 2850
2699 /* setup extra DISPC_WB_ATTRIBUTES */ 2851 /* setup extra DISPC_WB_ATTRIBUTES */
2700 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane)); 2852 l = dispc_read_reg(dispc, DISPC_OVL_ATTRIBUTES(plane));
2701 l = FLD_MOD(l, truncation, 10, 10); /* TRUNCATIONENABLE */ 2853 l = FLD_MOD(l, truncation, 10, 10); /* TRUNCATIONENABLE */
2854 l = FLD_MOD(l, channel_in, 18, 16); /* CHANNELIN */
2702 l = FLD_MOD(l, mem_to_mem, 19, 19); /* WRITEBACKMODE */ 2855 l = FLD_MOD(l, mem_to_mem, 19, 19); /* WRITEBACKMODE */
2703 if (mem_to_mem) 2856 if (mem_to_mem)
2704 l = FLD_MOD(l, 1, 26, 24); /* CAPTUREMODE */ 2857 l = FLD_MOD(l, 1, 26, 24); /* CAPTUREMODE */
2705 else 2858 else
2706 l = FLD_MOD(l, 0, 26, 24); /* CAPTUREMODE */ 2859 l = FLD_MOD(l, 0, 26, 24); /* CAPTUREMODE */
2707 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l); 2860 dispc_write_reg(dispc, DISPC_OVL_ATTRIBUTES(plane), l);
2708 2861
2709 if (mem_to_mem) { 2862 if (mem_to_mem) {
2710 /* WBDELAYCOUNT */ 2863 /* WBDELAYCOUNT */
2711 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 7, 0); 2864 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES2(plane), 0, 7, 0);
2712 } else { 2865 } else {
2713 int wbdelay; 2866 u32 wbdelay;
2867
2868 if (channel_in == DSS_WB_TV_MGR)
2869 wbdelay = vm->vsync_len + vm->vback_porch;
2870 else
2871 wbdelay = vm->vfront_porch + vm->vsync_len +
2872 vm->vback_porch;
2873
2874 if (vm->flags & DISPLAY_FLAGS_INTERLACED)
2875 wbdelay /= 2;
2714 2876
2715 wbdelay = min(vm->vfront_porch + 2877 wbdelay = min(wbdelay, 255u);
2716 vm->vsync_len + vm->vback_porch, (u32)255);
2717 2878
2718 /* WBDELAYCOUNT */ 2879 /* WBDELAYCOUNT */
2719 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), wbdelay, 7, 0); 2880 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES2(plane), wbdelay, 7, 0);
2720 } 2881 }
2721 2882
2722 return r; 2883 return 0;
2884}
2885
2886static bool dispc_has_writeback(struct dispc_device *dispc)
2887{
2888 return dispc->feat->has_writeback;
2723} 2889}
2724 2890
2725static int dispc_ovl_enable(enum omap_plane_id plane, bool enable) 2891static int dispc_ovl_enable(struct dispc_device *dispc,
2892 enum omap_plane_id plane, bool enable)
2726{ 2893{
2727 DSSDBG("dispc_enable_plane %d, %d\n", plane, enable); 2894 DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
2728 2895
2729 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0); 2896 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
2730 2897
2731 return 0; 2898 return 0;
2732} 2899}
2733 2900
2734static enum omap_dss_output_id dispc_mgr_get_supported_outputs(enum omap_channel channel) 2901static enum omap_dss_output_id
2902dispc_mgr_get_supported_outputs(struct dispc_device *dispc,
2903 enum omap_channel channel)
2735{ 2904{
2736 return dss_get_supported_outputs(channel); 2905 return dss_get_supported_outputs(dispc->dss, channel);
2737} 2906}
2738 2907
2739static void dispc_lcd_enable_signal_polarity(bool act_high) 2908static void dispc_lcd_enable_signal_polarity(struct dispc_device *dispc,
2909 bool act_high)
2740{ 2910{
2741 if (!dispc_has_feature(FEAT_LCDENABLEPOL)) 2911 if (!dispc_has_feature(dispc, FEAT_LCDENABLEPOL))
2742 return; 2912 return;
2743 2913
2744 REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29); 2914 REG_FLD_MOD(dispc, DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
2745} 2915}
2746 2916
2747void dispc_lcd_enable_signal(bool enable) 2917void dispc_lcd_enable_signal(struct dispc_device *dispc, bool enable)
2748{ 2918{
2749 if (!dispc_has_feature(FEAT_LCDENABLESIGNAL)) 2919 if (!dispc_has_feature(dispc, FEAT_LCDENABLESIGNAL))
2750 return; 2920 return;
2751 2921
2752 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28); 2922 REG_FLD_MOD(dispc, DISPC_CONTROL, enable ? 1 : 0, 28, 28);
2753} 2923}
2754 2924
2755void dispc_pck_free_enable(bool enable) 2925void dispc_pck_free_enable(struct dispc_device *dispc, bool enable)
2756{ 2926{
2757 if (!dispc_has_feature(FEAT_PCKFREEENABLE)) 2927 if (!dispc_has_feature(dispc, FEAT_PCKFREEENABLE))
2758 return; 2928 return;
2759 2929
2760 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27); 2930 REG_FLD_MOD(dispc, DISPC_CONTROL, enable ? 1 : 0, 27, 27);
2761} 2931}
2762 2932
2763static void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable) 2933static void dispc_mgr_enable_fifohandcheck(struct dispc_device *dispc,
2934 enum omap_channel channel,
2935 bool enable)
2764{ 2936{
2765 mgr_fld_write(channel, DISPC_MGR_FLD_FIFOHANDCHECK, enable); 2937 mgr_fld_write(dispc, channel, DISPC_MGR_FLD_FIFOHANDCHECK, enable);
2766} 2938}
2767 2939
2768 2940
2769static void dispc_mgr_set_lcd_type_tft(enum omap_channel channel) 2941static void dispc_mgr_set_lcd_type_tft(struct dispc_device *dispc,
2942 enum omap_channel channel)
2770{ 2943{
2771 mgr_fld_write(channel, DISPC_MGR_FLD_STNTFT, 1); 2944 mgr_fld_write(dispc, channel, DISPC_MGR_FLD_STNTFT, 1);
2772} 2945}
2773 2946
2774static void dispc_set_loadmode(enum omap_dss_load_mode mode) 2947static void dispc_set_loadmode(struct dispc_device *dispc,
2948 enum omap_dss_load_mode mode)
2775{ 2949{
2776 REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1); 2950 REG_FLD_MOD(dispc, DISPC_CONFIG, mode, 2, 1);
2777} 2951}
2778 2952
2779 2953
2780static void dispc_mgr_set_default_color(enum omap_channel channel, u32 color) 2954static void dispc_mgr_set_default_color(struct dispc_device *dispc,
2955 enum omap_channel channel, u32 color)
2781{ 2956{
2782 dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color); 2957 dispc_write_reg(dispc, DISPC_DEFAULT_COLOR(channel), color);
2783} 2958}
2784 2959
2785static void dispc_mgr_set_trans_key(enum omap_channel ch, 2960static void dispc_mgr_set_trans_key(struct dispc_device *dispc,
2786 enum omap_dss_trans_key_type type, 2961 enum omap_channel ch,
2787 u32 trans_key) 2962 enum omap_dss_trans_key_type type,
2963 u32 trans_key)
2788{ 2964{
2789 mgr_fld_write(ch, DISPC_MGR_FLD_TCKSELECTION, type); 2965 mgr_fld_write(dispc, ch, DISPC_MGR_FLD_TCKSELECTION, type);
2790 2966
2791 dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key); 2967 dispc_write_reg(dispc, DISPC_TRANS_COLOR(ch), trans_key);
2792} 2968}
2793 2969
2794static void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable) 2970static void dispc_mgr_enable_trans_key(struct dispc_device *dispc,
2971 enum omap_channel ch, bool enable)
2795{ 2972{
2796 mgr_fld_write(ch, DISPC_MGR_FLD_TCKENABLE, enable); 2973 mgr_fld_write(dispc, ch, DISPC_MGR_FLD_TCKENABLE, enable);
2797} 2974}
2798 2975
2799static void dispc_mgr_enable_alpha_fixed_zorder(enum omap_channel ch, 2976static void dispc_mgr_enable_alpha_fixed_zorder(struct dispc_device *dispc,
2800 bool enable) 2977 enum omap_channel ch,
2978 bool enable)
2801{ 2979{
2802 if (!dispc_has_feature(FEAT_ALPHA_FIXED_ZORDER)) 2980 if (!dispc_has_feature(dispc, FEAT_ALPHA_FIXED_ZORDER))
2803 return; 2981 return;
2804 2982
2805 if (ch == OMAP_DSS_CHANNEL_LCD) 2983 if (ch == OMAP_DSS_CHANNEL_LCD)
2806 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18); 2984 REG_FLD_MOD(dispc, DISPC_CONFIG, enable, 18, 18);
2807 else if (ch == OMAP_DSS_CHANNEL_DIGIT) 2985 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2808 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19); 2986 REG_FLD_MOD(dispc, DISPC_CONFIG, enable, 19, 19);
2809} 2987}
2810 2988
2811static void dispc_mgr_setup(enum omap_channel channel, 2989static void dispc_mgr_setup(struct dispc_device *dispc,
2812 const struct omap_overlay_manager_info *info) 2990 enum omap_channel channel,
2991 const struct omap_overlay_manager_info *info)
2813{ 2992{
2814 dispc_mgr_set_default_color(channel, info->default_color); 2993 dispc_mgr_set_default_color(dispc, channel, info->default_color);
2815 dispc_mgr_set_trans_key(channel, info->trans_key_type, info->trans_key); 2994 dispc_mgr_set_trans_key(dispc, channel, info->trans_key_type,
2816 dispc_mgr_enable_trans_key(channel, info->trans_enabled); 2995 info->trans_key);
2817 dispc_mgr_enable_alpha_fixed_zorder(channel, 2996 dispc_mgr_enable_trans_key(dispc, channel, info->trans_enabled);
2997 dispc_mgr_enable_alpha_fixed_zorder(dispc, channel,
2818 info->partial_alpha_enabled); 2998 info->partial_alpha_enabled);
2819 if (dispc_has_feature(FEAT_CPR)) { 2999 if (dispc_has_feature(dispc, FEAT_CPR)) {
2820 dispc_mgr_enable_cpr(channel, info->cpr_enable); 3000 dispc_mgr_enable_cpr(dispc, channel, info->cpr_enable);
2821 dispc_mgr_set_cpr_coef(channel, &info->cpr_coefs); 3001 dispc_mgr_set_cpr_coef(dispc, channel, &info->cpr_coefs);
2822 } 3002 }
2823} 3003}
2824 3004
2825static void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines) 3005static void dispc_mgr_set_tft_data_lines(struct dispc_device *dispc,
3006 enum omap_channel channel,
3007 u8 data_lines)
2826{ 3008{
2827 int code; 3009 int code;
2828 3010
@@ -2844,10 +3026,11 @@ static void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_line
2844 return; 3026 return;
2845 } 3027 }
2846 3028
2847 mgr_fld_write(channel, DISPC_MGR_FLD_TFTDATALINES, code); 3029 mgr_fld_write(dispc, channel, DISPC_MGR_FLD_TFTDATALINES, code);
2848} 3030}
2849 3031
2850static void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode) 3032static void dispc_mgr_set_io_pad_mode(struct dispc_device *dispc,
3033 enum dss_io_pad_mode mode)
2851{ 3034{
2852 u32 l; 3035 u32 l;
2853 int gpout0, gpout1; 3036 int gpout0, gpout1;
@@ -2870,68 +3053,74 @@ static void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode)
2870 return; 3053 return;
2871 } 3054 }
2872 3055
2873 l = dispc_read_reg(DISPC_CONTROL); 3056 l = dispc_read_reg(dispc, DISPC_CONTROL);
2874 l = FLD_MOD(l, gpout0, 15, 15); 3057 l = FLD_MOD(l, gpout0, 15, 15);
2875 l = FLD_MOD(l, gpout1, 16, 16); 3058 l = FLD_MOD(l, gpout1, 16, 16);
2876 dispc_write_reg(DISPC_CONTROL, l); 3059 dispc_write_reg(dispc, DISPC_CONTROL, l);
2877} 3060}
2878 3061
2879static void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable) 3062static void dispc_mgr_enable_stallmode(struct dispc_device *dispc,
3063 enum omap_channel channel, bool enable)
2880{ 3064{
2881 mgr_fld_write(channel, DISPC_MGR_FLD_STALLMODE, enable); 3065 mgr_fld_write(dispc, channel, DISPC_MGR_FLD_STALLMODE, enable);
2882} 3066}
2883 3067
2884static void dispc_mgr_set_lcd_config(enum omap_channel channel, 3068static void dispc_mgr_set_lcd_config(struct dispc_device *dispc,
2885 const struct dss_lcd_mgr_config *config) 3069 enum omap_channel channel,
3070 const struct dss_lcd_mgr_config *config)
2886{ 3071{
2887 dispc_mgr_set_io_pad_mode(config->io_pad_mode); 3072 dispc_mgr_set_io_pad_mode(dispc, config->io_pad_mode);
2888 3073
2889 dispc_mgr_enable_stallmode(channel, config->stallmode); 3074 dispc_mgr_enable_stallmode(dispc, channel, config->stallmode);
2890 dispc_mgr_enable_fifohandcheck(channel, config->fifohandcheck); 3075 dispc_mgr_enable_fifohandcheck(dispc, channel, config->fifohandcheck);
2891 3076
2892 dispc_mgr_set_clock_div(channel, &config->clock_info); 3077 dispc_mgr_set_clock_div(dispc, channel, &config->clock_info);
2893 3078
2894 dispc_mgr_set_tft_data_lines(channel, config->video_port_width); 3079 dispc_mgr_set_tft_data_lines(dispc, channel, config->video_port_width);
2895 3080
2896 dispc_lcd_enable_signal_polarity(config->lcden_sig_polarity); 3081 dispc_lcd_enable_signal_polarity(dispc, config->lcden_sig_polarity);
2897 3082
2898 dispc_mgr_set_lcd_type_tft(channel); 3083 dispc_mgr_set_lcd_type_tft(dispc, channel);
2899} 3084}
2900 3085
2901static bool _dispc_mgr_size_ok(u16 width, u16 height) 3086static bool _dispc_mgr_size_ok(struct dispc_device *dispc,
3087 u16 width, u16 height)
2902{ 3088{
2903 return width <= dispc.feat->mgr_width_max && 3089 return width <= dispc->feat->mgr_width_max &&
2904 height <= dispc.feat->mgr_height_max; 3090 height <= dispc->feat->mgr_height_max;
2905} 3091}
2906 3092
2907static bool _dispc_lcd_timings_ok(int hsync_len, int hfp, int hbp, 3093static bool _dispc_lcd_timings_ok(struct dispc_device *dispc,
2908 int vsw, int vfp, int vbp) 3094 int hsync_len, int hfp, int hbp,
3095 int vsw, int vfp, int vbp)
2909{ 3096{
2910 if (hsync_len < 1 || hsync_len > dispc.feat->sw_max || 3097 if (hsync_len < 1 || hsync_len > dispc->feat->sw_max ||
2911 hfp < 1 || hfp > dispc.feat->hp_max || 3098 hfp < 1 || hfp > dispc->feat->hp_max ||
2912 hbp < 1 || hbp > dispc.feat->hp_max || 3099 hbp < 1 || hbp > dispc->feat->hp_max ||
2913 vsw < 1 || vsw > dispc.feat->sw_max || 3100 vsw < 1 || vsw > dispc->feat->sw_max ||
2914 vfp < 0 || vfp > dispc.feat->vp_max || 3101 vfp < 0 || vfp > dispc->feat->vp_max ||
2915 vbp < 0 || vbp > dispc.feat->vp_max) 3102 vbp < 0 || vbp > dispc->feat->vp_max)
2916 return false; 3103 return false;
2917 return true; 3104 return true;
2918} 3105}
2919 3106
2920static bool _dispc_mgr_pclk_ok(enum omap_channel channel, 3107static bool _dispc_mgr_pclk_ok(struct dispc_device *dispc,
2921 unsigned long pclk) 3108 enum omap_channel channel,
3109 unsigned long pclk)
2922{ 3110{
2923 if (dss_mgr_is_lcd(channel)) 3111 if (dss_mgr_is_lcd(channel))
2924 return pclk <= dispc.feat->max_lcd_pclk; 3112 return pclk <= dispc->feat->max_lcd_pclk;
2925 else 3113 else
2926 return pclk <= dispc.feat->max_tv_pclk; 3114 return pclk <= dispc->feat->max_tv_pclk;
2927} 3115}
2928 3116
2929bool dispc_mgr_timings_ok(enum omap_channel channel, const struct videomode *vm) 3117bool dispc_mgr_timings_ok(struct dispc_device *dispc, enum omap_channel channel,
3118 const struct videomode *vm)
2930{ 3119{
2931 if (!_dispc_mgr_size_ok(vm->hactive, vm->vactive)) 3120 if (!_dispc_mgr_size_ok(dispc, vm->hactive, vm->vactive))
2932 return false; 3121 return false;
2933 3122
2934 if (!_dispc_mgr_pclk_ok(channel, vm->pixelclock)) 3123 if (!_dispc_mgr_pclk_ok(dispc, channel, vm->pixelclock))
2935 return false; 3124 return false;
2936 3125
2937 if (dss_mgr_is_lcd(channel)) { 3126 if (dss_mgr_is_lcd(channel)) {
@@ -2939,7 +3128,7 @@ bool dispc_mgr_timings_ok(enum omap_channel channel, const struct videomode *vm)
2939 if (vm->flags & DISPLAY_FLAGS_INTERLACED) 3128 if (vm->flags & DISPLAY_FLAGS_INTERLACED)
2940 return false; 3129 return false;
2941 3130
2942 if (!_dispc_lcd_timings_ok(vm->hsync_len, 3131 if (!_dispc_lcd_timings_ok(dispc, vm->hsync_len,
2943 vm->hfront_porch, vm->hback_porch, 3132 vm->hfront_porch, vm->hback_porch,
2944 vm->vsync_len, vm->vfront_porch, 3133 vm->vsync_len, vm->vfront_porch,
2945 vm->vback_porch)) 3134 vm->vback_porch))
@@ -2949,21 +3138,22 @@ bool dispc_mgr_timings_ok(enum omap_channel channel, const struct videomode *vm)
2949 return true; 3138 return true;
2950} 3139}
2951 3140
2952static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, 3141static void _dispc_mgr_set_lcd_timings(struct dispc_device *dispc,
3142 enum omap_channel channel,
2953 const struct videomode *vm) 3143 const struct videomode *vm)
2954{ 3144{
2955 u32 timing_h, timing_v, l; 3145 u32 timing_h, timing_v, l;
2956 bool onoff, rf, ipc, vs, hs, de; 3146 bool onoff, rf, ipc, vs, hs, de;
2957 3147
2958 timing_h = FLD_VAL(vm->hsync_len - 1, dispc.feat->sw_start, 0) | 3148 timing_h = FLD_VAL(vm->hsync_len - 1, dispc->feat->sw_start, 0) |
2959 FLD_VAL(vm->hfront_porch - 1, dispc.feat->fp_start, 8) | 3149 FLD_VAL(vm->hfront_porch - 1, dispc->feat->fp_start, 8) |
2960 FLD_VAL(vm->hback_porch - 1, dispc.feat->bp_start, 20); 3150 FLD_VAL(vm->hback_porch - 1, dispc->feat->bp_start, 20);
2961 timing_v = FLD_VAL(vm->vsync_len - 1, dispc.feat->sw_start, 0) | 3151 timing_v = FLD_VAL(vm->vsync_len - 1, dispc->feat->sw_start, 0) |
2962 FLD_VAL(vm->vfront_porch, dispc.feat->fp_start, 8) | 3152 FLD_VAL(vm->vfront_porch, dispc->feat->fp_start, 8) |
2963 FLD_VAL(vm->vback_porch, dispc.feat->bp_start, 20); 3153 FLD_VAL(vm->vback_porch, dispc->feat->bp_start, 20);
2964 3154
2965 dispc_write_reg(DISPC_TIMING_H(channel), timing_h); 3155 dispc_write_reg(dispc, DISPC_TIMING_H(channel), timing_h);
2966 dispc_write_reg(DISPC_TIMING_V(channel), timing_v); 3156 dispc_write_reg(dispc, DISPC_TIMING_V(channel), timing_v);
2967 3157
2968 if (vm->flags & DISPLAY_FLAGS_VSYNC_HIGH) 3158 if (vm->flags & DISPLAY_FLAGS_VSYNC_HIGH)
2969 vs = false; 3159 vs = false;
@@ -3001,12 +3191,12 @@ static void _dispc_mgr_set_lcd_timings(enum omap_channel channel,
3001 FLD_VAL(vs, 12, 12); 3191 FLD_VAL(vs, 12, 12);
3002 3192
3003 /* always set ALIGN bit when available */ 3193 /* always set ALIGN bit when available */
3004 if (dispc.feat->supports_sync_align) 3194 if (dispc->feat->supports_sync_align)
3005 l |= (1 << 18); 3195 l |= (1 << 18);
3006 3196
3007 dispc_write_reg(DISPC_POL_FREQ(channel), l); 3197 dispc_write_reg(dispc, DISPC_POL_FREQ(channel), l);
3008 3198
3009 if (dispc.syscon_pol) { 3199 if (dispc->syscon_pol) {
3010 const int shifts[] = { 3200 const int shifts[] = {
3011 [OMAP_DSS_CHANNEL_LCD] = 0, 3201 [OMAP_DSS_CHANNEL_LCD] = 0,
3012 [OMAP_DSS_CHANNEL_LCD2] = 1, 3202 [OMAP_DSS_CHANNEL_LCD2] = 1,
@@ -3021,8 +3211,8 @@ static void _dispc_mgr_set_lcd_timings(enum omap_channel channel,
3021 mask <<= 16 + shifts[channel]; 3211 mask <<= 16 + shifts[channel];
3022 val <<= 16 + shifts[channel]; 3212 val <<= 16 + shifts[channel];
3023 3213
3024 regmap_update_bits(dispc.syscon_pol, dispc.syscon_pol_offset, 3214 regmap_update_bits(dispc->syscon_pol, dispc->syscon_pol_offset,
3025 mask, val); 3215 mask, val);
3026 } 3216 }
3027} 3217}
3028 3218
@@ -3037,22 +3227,23 @@ static int vm_flag_to_int(enum display_flags flags, enum display_flags high,
3037} 3227}
3038 3228
3039/* change name to mode? */ 3229/* change name to mode? */
3040static void dispc_mgr_set_timings(enum omap_channel channel, 3230static void dispc_mgr_set_timings(struct dispc_device *dispc,
3041 const struct videomode *vm) 3231 enum omap_channel channel,
3232 const struct videomode *vm)
3042{ 3233{
3043 unsigned xtot, ytot; 3234 unsigned int xtot, ytot;
3044 unsigned long ht, vt; 3235 unsigned long ht, vt;
3045 struct videomode t = *vm; 3236 struct videomode t = *vm;
3046 3237
3047 DSSDBG("channel %d xres %u yres %u\n", channel, t.hactive, t.vactive); 3238 DSSDBG("channel %d xres %u yres %u\n", channel, t.hactive, t.vactive);
3048 3239
3049 if (!dispc_mgr_timings_ok(channel, &t)) { 3240 if (!dispc_mgr_timings_ok(dispc, channel, &t)) {
3050 BUG(); 3241 BUG();
3051 return; 3242 return;
3052 } 3243 }
3053 3244
3054 if (dss_mgr_is_lcd(channel)) { 3245 if (dss_mgr_is_lcd(channel)) {
3055 _dispc_mgr_set_lcd_timings(channel, &t); 3246 _dispc_mgr_set_lcd_timings(dispc, channel, &t);
3056 3247
3057 xtot = t.hactive + t.hfront_porch + t.hsync_len + t.hback_porch; 3248 xtot = t.hactive + t.hfront_porch + t.hsync_len + t.hback_porch;
3058 ytot = t.vactive + t.vfront_porch + t.vsync_len + t.vback_porch; 3249 ytot = t.vactive + t.vfront_porch + t.vsync_len + t.vback_porch;
@@ -3076,52 +3267,54 @@ static void dispc_mgr_set_timings(enum omap_channel channel,
3076 if (t.flags & DISPLAY_FLAGS_INTERLACED) 3267 if (t.flags & DISPLAY_FLAGS_INTERLACED)
3077 t.vactive /= 2; 3268 t.vactive /= 2;
3078 3269
3079 if (dispc.feat->supports_double_pixel) 3270 if (dispc->feat->supports_double_pixel)
3080 REG_FLD_MOD(DISPC_CONTROL, 3271 REG_FLD_MOD(dispc, DISPC_CONTROL,
3081 !!(t.flags & DISPLAY_FLAGS_DOUBLECLK), 3272 !!(t.flags & DISPLAY_FLAGS_DOUBLECLK),
3082 19, 17); 3273 19, 17);
3083 } 3274 }
3084 3275
3085 dispc_mgr_set_size(channel, t.hactive, t.vactive); 3276 dispc_mgr_set_size(dispc, channel, t.hactive, t.vactive);
3086} 3277}
3087 3278
3088static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div, 3279static void dispc_mgr_set_lcd_divisor(struct dispc_device *dispc,
3089 u16 pck_div) 3280 enum omap_channel channel, u16 lck_div,
3281 u16 pck_div)
3090{ 3282{
3091 BUG_ON(lck_div < 1); 3283 BUG_ON(lck_div < 1);
3092 BUG_ON(pck_div < 1); 3284 BUG_ON(pck_div < 1);
3093 3285
3094 dispc_write_reg(DISPC_DIVISORo(channel), 3286 dispc_write_reg(dispc, DISPC_DIVISORo(channel),
3095 FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0)); 3287 FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
3096 3288
3097 if (!dispc_has_feature(FEAT_CORE_CLK_DIV) && 3289 if (!dispc_has_feature(dispc, FEAT_CORE_CLK_DIV) &&
3098 channel == OMAP_DSS_CHANNEL_LCD) 3290 channel == OMAP_DSS_CHANNEL_LCD)
3099 dispc.core_clk_rate = dispc_fclk_rate() / lck_div; 3291 dispc->core_clk_rate = dispc_fclk_rate(dispc) / lck_div;
3100} 3292}
3101 3293
3102static void dispc_mgr_get_lcd_divisor(enum omap_channel channel, int *lck_div, 3294static void dispc_mgr_get_lcd_divisor(struct dispc_device *dispc,
3103 int *pck_div) 3295 enum omap_channel channel, int *lck_div,
3296 int *pck_div)
3104{ 3297{
3105 u32 l; 3298 u32 l;
3106 l = dispc_read_reg(DISPC_DIVISORo(channel)); 3299 l = dispc_read_reg(dispc, DISPC_DIVISORo(channel));
3107 *lck_div = FLD_GET(l, 23, 16); 3300 *lck_div = FLD_GET(l, 23, 16);
3108 *pck_div = FLD_GET(l, 7, 0); 3301 *pck_div = FLD_GET(l, 7, 0);
3109} 3302}
3110 3303
3111static unsigned long dispc_fclk_rate(void) 3304static unsigned long dispc_fclk_rate(struct dispc_device *dispc)
3112{ 3305{
3113 unsigned long r; 3306 unsigned long r;
3114 enum dss_clk_source src; 3307 enum dss_clk_source src;
3115 3308
3116 src = dss_get_dispc_clk_source(); 3309 src = dss_get_dispc_clk_source(dispc->dss);
3117 3310
3118 if (src == DSS_CLK_SRC_FCK) { 3311 if (src == DSS_CLK_SRC_FCK) {
3119 r = dss_get_dispc_clk_rate(); 3312 r = dss_get_dispc_clk_rate(dispc->dss);
3120 } else { 3313 } else {
3121 struct dss_pll *pll; 3314 struct dss_pll *pll;
3122 unsigned clkout_idx; 3315 unsigned int clkout_idx;
3123 3316
3124 pll = dss_pll_find_by_src(src); 3317 pll = dss_pll_find_by_src(dispc->dss, src);
3125 clkout_idx = dss_pll_get_clkout_idx_for_src(src); 3318 clkout_idx = dss_pll_get_clkout_idx_for_src(src);
3126 3319
3127 r = pll->cinfo.clkout[clkout_idx]; 3320 r = pll->cinfo.clkout[clkout_idx];
@@ -3130,7 +3323,8 @@ static unsigned long dispc_fclk_rate(void)
3130 return r; 3323 return r;
3131} 3324}
3132 3325
3133static unsigned long dispc_mgr_lclk_rate(enum omap_channel channel) 3326static unsigned long dispc_mgr_lclk_rate(struct dispc_device *dispc,
3327 enum omap_channel channel)
3134{ 3328{
3135 int lcd; 3329 int lcd;
3136 unsigned long r; 3330 unsigned long r;
@@ -3138,28 +3332,29 @@ static unsigned long dispc_mgr_lclk_rate(enum omap_channel channel)
3138 3332
3139 /* for TV, LCLK rate is the FCLK rate */ 3333 /* for TV, LCLK rate is the FCLK rate */
3140 if (!dss_mgr_is_lcd(channel)) 3334 if (!dss_mgr_is_lcd(channel))
3141 return dispc_fclk_rate(); 3335 return dispc_fclk_rate(dispc);
3142 3336
3143 src = dss_get_lcd_clk_source(channel); 3337 src = dss_get_lcd_clk_source(dispc->dss, channel);
3144 3338
3145 if (src == DSS_CLK_SRC_FCK) { 3339 if (src == DSS_CLK_SRC_FCK) {
3146 r = dss_get_dispc_clk_rate(); 3340 r = dss_get_dispc_clk_rate(dispc->dss);
3147 } else { 3341 } else {
3148 struct dss_pll *pll; 3342 struct dss_pll *pll;
3149 unsigned clkout_idx; 3343 unsigned int clkout_idx;
3150 3344
3151 pll = dss_pll_find_by_src(src); 3345 pll = dss_pll_find_by_src(dispc->dss, src);
3152 clkout_idx = dss_pll_get_clkout_idx_for_src(src); 3346 clkout_idx = dss_pll_get_clkout_idx_for_src(src);
3153 3347
3154 r = pll->cinfo.clkout[clkout_idx]; 3348 r = pll->cinfo.clkout[clkout_idx];
3155 } 3349 }
3156 3350
3157 lcd = REG_GET(DISPC_DIVISORo(channel), 23, 16); 3351 lcd = REG_GET(dispc, DISPC_DIVISORo(channel), 23, 16);
3158 3352
3159 return r / lcd; 3353 return r / lcd;
3160} 3354}
3161 3355
3162static unsigned long dispc_mgr_pclk_rate(enum omap_channel channel) 3356static unsigned long dispc_mgr_pclk_rate(struct dispc_device *dispc,
3357 enum omap_channel channel)
3163{ 3358{
3164 unsigned long r; 3359 unsigned long r;
3165 3360
@@ -3167,109 +3362,115 @@ static unsigned long dispc_mgr_pclk_rate(enum omap_channel channel)
3167 int pcd; 3362 int pcd;
3168 u32 l; 3363 u32 l;
3169 3364
3170 l = dispc_read_reg(DISPC_DIVISORo(channel)); 3365 l = dispc_read_reg(dispc, DISPC_DIVISORo(channel));
3171 3366
3172 pcd = FLD_GET(l, 7, 0); 3367 pcd = FLD_GET(l, 7, 0);
3173 3368
3174 r = dispc_mgr_lclk_rate(channel); 3369 r = dispc_mgr_lclk_rate(dispc, channel);
3175 3370
3176 return r / pcd; 3371 return r / pcd;
3177 } else { 3372 } else {
3178 return dispc.tv_pclk_rate; 3373 return dispc->tv_pclk_rate;
3179 } 3374 }
3180} 3375}
3181 3376
3182void dispc_set_tv_pclk(unsigned long pclk) 3377void dispc_set_tv_pclk(struct dispc_device *dispc, unsigned long pclk)
3183{ 3378{
3184 dispc.tv_pclk_rate = pclk; 3379 dispc->tv_pclk_rate = pclk;
3185} 3380}
3186 3381
3187static unsigned long dispc_core_clk_rate(void) 3382static unsigned long dispc_core_clk_rate(struct dispc_device *dispc)
3188{ 3383{
3189 return dispc.core_clk_rate; 3384 return dispc->core_clk_rate;
3190} 3385}
3191 3386
3192static unsigned long dispc_plane_pclk_rate(enum omap_plane_id plane) 3387static unsigned long dispc_plane_pclk_rate(struct dispc_device *dispc,
3388 enum omap_plane_id plane)
3193{ 3389{
3194 enum omap_channel channel; 3390 enum omap_channel channel;
3195 3391
3196 if (plane == OMAP_DSS_WB) 3392 if (plane == OMAP_DSS_WB)
3197 return 0; 3393 return 0;
3198 3394
3199 channel = dispc_ovl_get_channel_out(plane); 3395 channel = dispc_ovl_get_channel_out(dispc, plane);
3200 3396
3201 return dispc_mgr_pclk_rate(channel); 3397 return dispc_mgr_pclk_rate(dispc, channel);
3202} 3398}
3203 3399
3204static unsigned long dispc_plane_lclk_rate(enum omap_plane_id plane) 3400static unsigned long dispc_plane_lclk_rate(struct dispc_device *dispc,
3401 enum omap_plane_id plane)
3205{ 3402{
3206 enum omap_channel channel; 3403 enum omap_channel channel;
3207 3404
3208 if (plane == OMAP_DSS_WB) 3405 if (plane == OMAP_DSS_WB)
3209 return 0; 3406 return 0;
3210 3407
3211 channel = dispc_ovl_get_channel_out(plane); 3408 channel = dispc_ovl_get_channel_out(dispc, plane);
3212 3409
3213 return dispc_mgr_lclk_rate(channel); 3410 return dispc_mgr_lclk_rate(dispc, channel);
3214} 3411}
3215 3412
3216static void dispc_dump_clocks_channel(struct seq_file *s, enum omap_channel channel) 3413static void dispc_dump_clocks_channel(struct dispc_device *dispc,
3414 struct seq_file *s,
3415 enum omap_channel channel)
3217{ 3416{
3218 int lcd, pcd; 3417 int lcd, pcd;
3219 enum dss_clk_source lcd_clk_src; 3418 enum dss_clk_source lcd_clk_src;
3220 3419
3221 seq_printf(s, "- %s -\n", mgr_desc[channel].name); 3420 seq_printf(s, "- %s -\n", mgr_desc[channel].name);
3222 3421
3223 lcd_clk_src = dss_get_lcd_clk_source(channel); 3422 lcd_clk_src = dss_get_lcd_clk_source(dispc->dss, channel);
3224 3423
3225 seq_printf(s, "%s clk source = %s\n", mgr_desc[channel].name, 3424 seq_printf(s, "%s clk source = %s\n", mgr_desc[channel].name,
3226 dss_get_clk_source_name(lcd_clk_src)); 3425 dss_get_clk_source_name(lcd_clk_src));
3227 3426
3228 dispc_mgr_get_lcd_divisor(channel, &lcd, &pcd); 3427 dispc_mgr_get_lcd_divisor(dispc, channel, &lcd, &pcd);
3229 3428
3230 seq_printf(s, "lck\t\t%-16lulck div\t%u\n", 3429 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
3231 dispc_mgr_lclk_rate(channel), lcd); 3430 dispc_mgr_lclk_rate(dispc, channel), lcd);
3232 seq_printf(s, "pck\t\t%-16lupck div\t%u\n", 3431 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
3233 dispc_mgr_pclk_rate(channel), pcd); 3432 dispc_mgr_pclk_rate(dispc, channel), pcd);
3234} 3433}
3235 3434
3236void dispc_dump_clocks(struct seq_file *s) 3435void dispc_dump_clocks(struct dispc_device *dispc, struct seq_file *s)
3237{ 3436{
3437 enum dss_clk_source dispc_clk_src;
3238 int lcd; 3438 int lcd;
3239 u32 l; 3439 u32 l;
3240 enum dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
3241 3440
3242 if (dispc_runtime_get()) 3441 if (dispc_runtime_get(dispc))
3243 return; 3442 return;
3244 3443
3245 seq_printf(s, "- DISPC -\n"); 3444 seq_printf(s, "- DISPC -\n");
3246 3445
3446 dispc_clk_src = dss_get_dispc_clk_source(dispc->dss);
3247 seq_printf(s, "dispc fclk source = %s\n", 3447 seq_printf(s, "dispc fclk source = %s\n",
3248 dss_get_clk_source_name(dispc_clk_src)); 3448 dss_get_clk_source_name(dispc_clk_src));
3249 3449
3250 seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate()); 3450 seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate(dispc));
3251 3451
3252 if (dispc_has_feature(FEAT_CORE_CLK_DIV)) { 3452 if (dispc_has_feature(dispc, FEAT_CORE_CLK_DIV)) {
3253 seq_printf(s, "- DISPC-CORE-CLK -\n"); 3453 seq_printf(s, "- DISPC-CORE-CLK -\n");
3254 l = dispc_read_reg(DISPC_DIVISOR); 3454 l = dispc_read_reg(dispc, DISPC_DIVISOR);
3255 lcd = FLD_GET(l, 23, 16); 3455 lcd = FLD_GET(l, 23, 16);
3256 3456
3257 seq_printf(s, "lck\t\t%-16lulck div\t%u\n", 3457 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
3258 (dispc_fclk_rate()/lcd), lcd); 3458 (dispc_fclk_rate(dispc)/lcd), lcd);
3259 } 3459 }
3260 3460
3261 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD); 3461 dispc_dump_clocks_channel(dispc, s, OMAP_DSS_CHANNEL_LCD);
3262 3462
3263 if (dispc_has_feature(FEAT_MGR_LCD2)) 3463 if (dispc_has_feature(dispc, FEAT_MGR_LCD2))
3264 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD2); 3464 dispc_dump_clocks_channel(dispc, s, OMAP_DSS_CHANNEL_LCD2);
3265 if (dispc_has_feature(FEAT_MGR_LCD3)) 3465 if (dispc_has_feature(dispc, FEAT_MGR_LCD3))
3266 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD3); 3466 dispc_dump_clocks_channel(dispc, s, OMAP_DSS_CHANNEL_LCD3);
3267 3467
3268 dispc_runtime_put(); 3468 dispc_runtime_put(dispc);
3269} 3469}
3270 3470
3271static void dispc_dump_regs(struct seq_file *s) 3471static int dispc_dump_regs(struct seq_file *s, void *p)
3272{ 3472{
3473 struct dispc_device *dispc = s->private;
3273 int i, j; 3474 int i, j;
3274 const char *mgr_names[] = { 3475 const char *mgr_names[] = {
3275 [OMAP_DSS_CHANNEL_LCD] = "LCD", 3476 [OMAP_DSS_CHANNEL_LCD] = "LCD",
@@ -3286,186 +3487,190 @@ static void dispc_dump_regs(struct seq_file *s)
3286 }; 3487 };
3287 const char **p_names; 3488 const char **p_names;
3288 3489
3289#define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r)) 3490#define DUMPREG(dispc, r) \
3491 seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(dispc, r))
3290 3492
3291 if (dispc_runtime_get()) 3493 if (dispc_runtime_get(dispc))
3292 return; 3494 return 0;
3293 3495
3294 /* DISPC common registers */ 3496 /* DISPC common registers */
3295 DUMPREG(DISPC_REVISION); 3497 DUMPREG(dispc, DISPC_REVISION);
3296 DUMPREG(DISPC_SYSCONFIG); 3498 DUMPREG(dispc, DISPC_SYSCONFIG);
3297 DUMPREG(DISPC_SYSSTATUS); 3499 DUMPREG(dispc, DISPC_SYSSTATUS);
3298 DUMPREG(DISPC_IRQSTATUS); 3500 DUMPREG(dispc, DISPC_IRQSTATUS);
3299 DUMPREG(DISPC_IRQENABLE); 3501 DUMPREG(dispc, DISPC_IRQENABLE);
3300 DUMPREG(DISPC_CONTROL); 3502 DUMPREG(dispc, DISPC_CONTROL);
3301 DUMPREG(DISPC_CONFIG); 3503 DUMPREG(dispc, DISPC_CONFIG);
3302 DUMPREG(DISPC_CAPABLE); 3504 DUMPREG(dispc, DISPC_CAPABLE);
3303 DUMPREG(DISPC_LINE_STATUS); 3505 DUMPREG(dispc, DISPC_LINE_STATUS);
3304 DUMPREG(DISPC_LINE_NUMBER); 3506 DUMPREG(dispc, DISPC_LINE_NUMBER);
3305 if (dispc_has_feature(FEAT_ALPHA_FIXED_ZORDER) || 3507 if (dispc_has_feature(dispc, FEAT_ALPHA_FIXED_ZORDER) ||
3306 dispc_has_feature(FEAT_ALPHA_FREE_ZORDER)) 3508 dispc_has_feature(dispc, FEAT_ALPHA_FREE_ZORDER))
3307 DUMPREG(DISPC_GLOBAL_ALPHA); 3509 DUMPREG(dispc, DISPC_GLOBAL_ALPHA);
3308 if (dispc_has_feature(FEAT_MGR_LCD2)) { 3510 if (dispc_has_feature(dispc, FEAT_MGR_LCD2)) {
3309 DUMPREG(DISPC_CONTROL2); 3511 DUMPREG(dispc, DISPC_CONTROL2);
3310 DUMPREG(DISPC_CONFIG2); 3512 DUMPREG(dispc, DISPC_CONFIG2);
3311 } 3513 }
3312 if (dispc_has_feature(FEAT_MGR_LCD3)) { 3514 if (dispc_has_feature(dispc, FEAT_MGR_LCD3)) {
3313 DUMPREG(DISPC_CONTROL3); 3515 DUMPREG(dispc, DISPC_CONTROL3);
3314 DUMPREG(DISPC_CONFIG3); 3516 DUMPREG(dispc, DISPC_CONFIG3);
3315 } 3517 }
3316 if (dispc_has_feature(FEAT_MFLAG)) 3518 if (dispc_has_feature(dispc, FEAT_MFLAG))
3317 DUMPREG(DISPC_GLOBAL_MFLAG_ATTRIBUTE); 3519 DUMPREG(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE);
3318 3520
3319#undef DUMPREG 3521#undef DUMPREG
3320 3522
3321#define DISPC_REG(i, name) name(i) 3523#define DISPC_REG(i, name) name(i)
3322#define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \ 3524#define DUMPREG(dispc, i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \
3323 (int)(48 - strlen(#r) - strlen(p_names[i])), " ", \ 3525 (int)(48 - strlen(#r) - strlen(p_names[i])), " ", \
3324 dispc_read_reg(DISPC_REG(i, r))) 3526 dispc_read_reg(dispc, DISPC_REG(i, r)))
3325 3527
3326 p_names = mgr_names; 3528 p_names = mgr_names;
3327 3529
3328 /* DISPC channel specific registers */ 3530 /* DISPC channel specific registers */
3329 for (i = 0; i < dispc_get_num_mgrs(); i++) { 3531 for (i = 0; i < dispc_get_num_mgrs(dispc); i++) {
3330 DUMPREG(i, DISPC_DEFAULT_COLOR); 3532 DUMPREG(dispc, i, DISPC_DEFAULT_COLOR);
3331 DUMPREG(i, DISPC_TRANS_COLOR); 3533 DUMPREG(dispc, i, DISPC_TRANS_COLOR);
3332 DUMPREG(i, DISPC_SIZE_MGR); 3534 DUMPREG(dispc, i, DISPC_SIZE_MGR);
3333 3535
3334 if (i == OMAP_DSS_CHANNEL_DIGIT) 3536 if (i == OMAP_DSS_CHANNEL_DIGIT)
3335 continue; 3537 continue;
3336 3538
3337 DUMPREG(i, DISPC_TIMING_H); 3539 DUMPREG(dispc, i, DISPC_TIMING_H);
3338 DUMPREG(i, DISPC_TIMING_V); 3540 DUMPREG(dispc, i, DISPC_TIMING_V);
3339 DUMPREG(i, DISPC_POL_FREQ); 3541 DUMPREG(dispc, i, DISPC_POL_FREQ);
3340 DUMPREG(i, DISPC_DIVISORo); 3542 DUMPREG(dispc, i, DISPC_DIVISORo);
3341 3543
3342 DUMPREG(i, DISPC_DATA_CYCLE1); 3544 DUMPREG(dispc, i, DISPC_DATA_CYCLE1);
3343 DUMPREG(i, DISPC_DATA_CYCLE2); 3545 DUMPREG(dispc, i, DISPC_DATA_CYCLE2);
3344 DUMPREG(i, DISPC_DATA_CYCLE3); 3546 DUMPREG(dispc, i, DISPC_DATA_CYCLE3);
3345 3547
3346 if (dispc_has_feature(FEAT_CPR)) { 3548 if (dispc_has_feature(dispc, FEAT_CPR)) {
3347 DUMPREG(i, DISPC_CPR_COEF_R); 3549 DUMPREG(dispc, i, DISPC_CPR_COEF_R);
3348 DUMPREG(i, DISPC_CPR_COEF_G); 3550 DUMPREG(dispc, i, DISPC_CPR_COEF_G);
3349 DUMPREG(i, DISPC_CPR_COEF_B); 3551 DUMPREG(dispc, i, DISPC_CPR_COEF_B);
3350 } 3552 }
3351 } 3553 }
3352 3554
3353 p_names = ovl_names; 3555 p_names = ovl_names;
3354 3556
3355 for (i = 0; i < dispc_get_num_ovls(); i++) { 3557 for (i = 0; i < dispc_get_num_ovls(dispc); i++) {
3356 DUMPREG(i, DISPC_OVL_BA0); 3558 DUMPREG(dispc, i, DISPC_OVL_BA0);
3357 DUMPREG(i, DISPC_OVL_BA1); 3559 DUMPREG(dispc, i, DISPC_OVL_BA1);
3358 DUMPREG(i, DISPC_OVL_POSITION); 3560 DUMPREG(dispc, i, DISPC_OVL_POSITION);
3359 DUMPREG(i, DISPC_OVL_SIZE); 3561 DUMPREG(dispc, i, DISPC_OVL_SIZE);
3360 DUMPREG(i, DISPC_OVL_ATTRIBUTES); 3562 DUMPREG(dispc, i, DISPC_OVL_ATTRIBUTES);
3361 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD); 3563 DUMPREG(dispc, i, DISPC_OVL_FIFO_THRESHOLD);
3362 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS); 3564 DUMPREG(dispc, i, DISPC_OVL_FIFO_SIZE_STATUS);
3363 DUMPREG(i, DISPC_OVL_ROW_INC); 3565 DUMPREG(dispc, i, DISPC_OVL_ROW_INC);
3364 DUMPREG(i, DISPC_OVL_PIXEL_INC); 3566 DUMPREG(dispc, i, DISPC_OVL_PIXEL_INC);
3365 3567
3366 if (dispc_has_feature(FEAT_PRELOAD)) 3568 if (dispc_has_feature(dispc, FEAT_PRELOAD))
3367 DUMPREG(i, DISPC_OVL_PRELOAD); 3569 DUMPREG(dispc, i, DISPC_OVL_PRELOAD);
3368 if (dispc_has_feature(FEAT_MFLAG)) 3570 if (dispc_has_feature(dispc, FEAT_MFLAG))
3369 DUMPREG(i, DISPC_OVL_MFLAG_THRESHOLD); 3571 DUMPREG(dispc, i, DISPC_OVL_MFLAG_THRESHOLD);
3370 3572
3371 if (i == OMAP_DSS_GFX) { 3573 if (i == OMAP_DSS_GFX) {
3372 DUMPREG(i, DISPC_OVL_WINDOW_SKIP); 3574 DUMPREG(dispc, i, DISPC_OVL_WINDOW_SKIP);
3373 DUMPREG(i, DISPC_OVL_TABLE_BA); 3575 DUMPREG(dispc, i, DISPC_OVL_TABLE_BA);
3374 continue; 3576 continue;
3375 } 3577 }
3376 3578
3377 DUMPREG(i, DISPC_OVL_FIR); 3579 DUMPREG(dispc, i, DISPC_OVL_FIR);
3378 DUMPREG(i, DISPC_OVL_PICTURE_SIZE); 3580 DUMPREG(dispc, i, DISPC_OVL_PICTURE_SIZE);
3379 DUMPREG(i, DISPC_OVL_ACCU0); 3581 DUMPREG(dispc, i, DISPC_OVL_ACCU0);
3380 DUMPREG(i, DISPC_OVL_ACCU1); 3582 DUMPREG(dispc, i, DISPC_OVL_ACCU1);
3381 if (dispc_has_feature(FEAT_HANDLE_UV_SEPARATE)) { 3583 if (dispc_has_feature(dispc, FEAT_HANDLE_UV_SEPARATE)) {
3382 DUMPREG(i, DISPC_OVL_BA0_UV); 3584 DUMPREG(dispc, i, DISPC_OVL_BA0_UV);
3383 DUMPREG(i, DISPC_OVL_BA1_UV); 3585 DUMPREG(dispc, i, DISPC_OVL_BA1_UV);
3384 DUMPREG(i, DISPC_OVL_FIR2); 3586 DUMPREG(dispc, i, DISPC_OVL_FIR2);
3385 DUMPREG(i, DISPC_OVL_ACCU2_0); 3587 DUMPREG(dispc, i, DISPC_OVL_ACCU2_0);
3386 DUMPREG(i, DISPC_OVL_ACCU2_1); 3588 DUMPREG(dispc, i, DISPC_OVL_ACCU2_1);
3387 } 3589 }
3388 if (dispc_has_feature(FEAT_ATTR2)) 3590 if (dispc_has_feature(dispc, FEAT_ATTR2))
3389 DUMPREG(i, DISPC_OVL_ATTRIBUTES2); 3591 DUMPREG(dispc, i, DISPC_OVL_ATTRIBUTES2);
3390 } 3592 }
3391 3593
3392 if (dispc.feat->has_writeback) { 3594 if (dispc->feat->has_writeback) {
3393 i = OMAP_DSS_WB; 3595 i = OMAP_DSS_WB;
3394 DUMPREG(i, DISPC_OVL_BA0); 3596 DUMPREG(dispc, i, DISPC_OVL_BA0);
3395 DUMPREG(i, DISPC_OVL_BA1); 3597 DUMPREG(dispc, i, DISPC_OVL_BA1);
3396 DUMPREG(i, DISPC_OVL_SIZE); 3598 DUMPREG(dispc, i, DISPC_OVL_SIZE);
3397 DUMPREG(i, DISPC_OVL_ATTRIBUTES); 3599 DUMPREG(dispc, i, DISPC_OVL_ATTRIBUTES);
3398 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD); 3600 DUMPREG(dispc, i, DISPC_OVL_FIFO_THRESHOLD);
3399 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS); 3601 DUMPREG(dispc, i, DISPC_OVL_FIFO_SIZE_STATUS);
3400 DUMPREG(i, DISPC_OVL_ROW_INC); 3602 DUMPREG(dispc, i, DISPC_OVL_ROW_INC);
3401 DUMPREG(i, DISPC_OVL_PIXEL_INC); 3603 DUMPREG(dispc, i, DISPC_OVL_PIXEL_INC);
3402 3604
3403 if (dispc_has_feature(FEAT_MFLAG)) 3605 if (dispc_has_feature(dispc, FEAT_MFLAG))
3404 DUMPREG(i, DISPC_OVL_MFLAG_THRESHOLD); 3606 DUMPREG(dispc, i, DISPC_OVL_MFLAG_THRESHOLD);
3405 3607
3406 DUMPREG(i, DISPC_OVL_FIR); 3608 DUMPREG(dispc, i, DISPC_OVL_FIR);
3407 DUMPREG(i, DISPC_OVL_PICTURE_SIZE); 3609 DUMPREG(dispc, i, DISPC_OVL_PICTURE_SIZE);
3408 DUMPREG(i, DISPC_OVL_ACCU0); 3610 DUMPREG(dispc, i, DISPC_OVL_ACCU0);
3409 DUMPREG(i, DISPC_OVL_ACCU1); 3611 DUMPREG(dispc, i, DISPC_OVL_ACCU1);
3410 if (dispc_has_feature(FEAT_HANDLE_UV_SEPARATE)) { 3612 if (dispc_has_feature(dispc, FEAT_HANDLE_UV_SEPARATE)) {
3411 DUMPREG(i, DISPC_OVL_BA0_UV); 3613 DUMPREG(dispc, i, DISPC_OVL_BA0_UV);
3412 DUMPREG(i, DISPC_OVL_BA1_UV); 3614 DUMPREG(dispc, i, DISPC_OVL_BA1_UV);
3413 DUMPREG(i, DISPC_OVL_FIR2); 3615 DUMPREG(dispc, i, DISPC_OVL_FIR2);
3414 DUMPREG(i, DISPC_OVL_ACCU2_0); 3616 DUMPREG(dispc, i, DISPC_OVL_ACCU2_0);
3415 DUMPREG(i, DISPC_OVL_ACCU2_1); 3617 DUMPREG(dispc, i, DISPC_OVL_ACCU2_1);
3416 } 3618 }
3417 if (dispc_has_feature(FEAT_ATTR2)) 3619 if (dispc_has_feature(dispc, FEAT_ATTR2))
3418 DUMPREG(i, DISPC_OVL_ATTRIBUTES2); 3620 DUMPREG(dispc, i, DISPC_OVL_ATTRIBUTES2);
3419 } 3621 }
3420 3622
3421#undef DISPC_REG 3623#undef DISPC_REG
3422#undef DUMPREG 3624#undef DUMPREG
3423 3625
3424#define DISPC_REG(plane, name, i) name(plane, i) 3626#define DISPC_REG(plane, name, i) name(plane, i)
3425#define DUMPREG(plane, name, i) \ 3627#define DUMPREG(dispc, plane, name, i) \
3426 seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \ 3628 seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \
3427 (int)(46 - strlen(#name) - strlen(p_names[plane])), " ", \ 3629 (int)(46 - strlen(#name) - strlen(p_names[plane])), " ", \
3428 dispc_read_reg(DISPC_REG(plane, name, i))) 3630 dispc_read_reg(dispc, DISPC_REG(plane, name, i)))
3429 3631
3430 /* Video pipeline coefficient registers */ 3632 /* Video pipeline coefficient registers */
3431 3633
3432 /* start from OMAP_DSS_VIDEO1 */ 3634 /* start from OMAP_DSS_VIDEO1 */
3433 for (i = 1; i < dispc_get_num_ovls(); i++) { 3635 for (i = 1; i < dispc_get_num_ovls(dispc); i++) {
3434 for (j = 0; j < 8; j++) 3636 for (j = 0; j < 8; j++)
3435 DUMPREG(i, DISPC_OVL_FIR_COEF_H, j); 3637 DUMPREG(dispc, i, DISPC_OVL_FIR_COEF_H, j);
3436 3638
3437 for (j = 0; j < 8; j++) 3639 for (j = 0; j < 8; j++)
3438 DUMPREG(i, DISPC_OVL_FIR_COEF_HV, j); 3640 DUMPREG(dispc, i, DISPC_OVL_FIR_COEF_HV, j);
3439 3641
3440 for (j = 0; j < 5; j++) 3642 for (j = 0; j < 5; j++)
3441 DUMPREG(i, DISPC_OVL_CONV_COEF, j); 3643 DUMPREG(dispc, i, DISPC_OVL_CONV_COEF, j);
3442 3644
3443 if (dispc_has_feature(FEAT_FIR_COEF_V)) { 3645 if (dispc_has_feature(dispc, FEAT_FIR_COEF_V)) {
3444 for (j = 0; j < 8; j++) 3646 for (j = 0; j < 8; j++)
3445 DUMPREG(i, DISPC_OVL_FIR_COEF_V, j); 3647 DUMPREG(dispc, i, DISPC_OVL_FIR_COEF_V, j);
3446 } 3648 }
3447 3649
3448 if (dispc_has_feature(FEAT_HANDLE_UV_SEPARATE)) { 3650 if (dispc_has_feature(dispc, FEAT_HANDLE_UV_SEPARATE)) {
3449 for (j = 0; j < 8; j++) 3651 for (j = 0; j < 8; j++)
3450 DUMPREG(i, DISPC_OVL_FIR_COEF_H2, j); 3652 DUMPREG(dispc, i, DISPC_OVL_FIR_COEF_H2, j);
3451 3653
3452 for (j = 0; j < 8; j++) 3654 for (j = 0; j < 8; j++)
3453 DUMPREG(i, DISPC_OVL_FIR_COEF_HV2, j); 3655 DUMPREG(dispc, i, DISPC_OVL_FIR_COEF_HV2, j);
3454 3656
3455 for (j = 0; j < 8; j++) 3657 for (j = 0; j < 8; j++)
3456 DUMPREG(i, DISPC_OVL_FIR_COEF_V2, j); 3658 DUMPREG(dispc, i, DISPC_OVL_FIR_COEF_V2, j);
3457 } 3659 }
3458 } 3660 }
3459 3661
3460 dispc_runtime_put(); 3662 dispc_runtime_put(dispc);
3461 3663
3462#undef DISPC_REG 3664#undef DISPC_REG
3463#undef DUMPREG 3665#undef DUMPREG
3666
3667 return 0;
3464} 3668}
3465 3669
3466/* calculate clock rates using dividers in cinfo */ 3670/* calculate clock rates using dividers in cinfo */
3467int dispc_calc_clock_rates(unsigned long dispc_fclk_rate, 3671int dispc_calc_clock_rates(struct dispc_device *dispc,
3468 struct dispc_clock_info *cinfo) 3672 unsigned long dispc_fclk_rate,
3673 struct dispc_clock_info *cinfo)
3469{ 3674{
3470 if (cinfo->lck_div > 255 || cinfo->lck_div == 0) 3675 if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
3471 return -EINVAL; 3676 return -EINVAL;
@@ -3478,16 +3683,16 @@ int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
3478 return 0; 3683 return 0;
3479} 3684}
3480 3685
3481bool dispc_div_calc(unsigned long dispc_freq, 3686bool dispc_div_calc(struct dispc_device *dispc, unsigned long dispc_freq,
3482 unsigned long pck_min, unsigned long pck_max, 3687 unsigned long pck_min, unsigned long pck_max,
3483 dispc_div_calc_func func, void *data) 3688 dispc_div_calc_func func, void *data)
3484{ 3689{
3485 int lckd, lckd_start, lckd_stop; 3690 int lckd, lckd_start, lckd_stop;
3486 int pckd, pckd_start, pckd_stop; 3691 int pckd, pckd_start, pckd_stop;
3487 unsigned long pck, lck; 3692 unsigned long pck, lck;
3488 unsigned long lck_max; 3693 unsigned long lck_max;
3489 unsigned long pckd_hw_min, pckd_hw_max; 3694 unsigned long pckd_hw_min, pckd_hw_max;
3490 unsigned min_fck_per_pck; 3695 unsigned int min_fck_per_pck;
3491 unsigned long fck; 3696 unsigned long fck;
3492 3697
3493#ifdef CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK 3698#ifdef CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK
@@ -3496,10 +3701,10 @@ bool dispc_div_calc(unsigned long dispc_freq,
3496 min_fck_per_pck = 0; 3701 min_fck_per_pck = 0;
3497#endif 3702#endif
3498 3703
3499 pckd_hw_min = dispc.feat->min_pcd; 3704 pckd_hw_min = dispc->feat->min_pcd;
3500 pckd_hw_max = 255; 3705 pckd_hw_max = 255;
3501 3706
3502 lck_max = dss_get_max_fck_rate(); 3707 lck_max = dss_get_max_fck_rate(dispc->dss);
3503 3708
3504 pck_min = pck_min ? pck_min : 1; 3709 pck_min = pck_min ? pck_min : 1;
3505 pck_max = pck_max ? pck_max : ULONG_MAX; 3710 pck_max = pck_max ? pck_max : ULONG_MAX;
@@ -3522,8 +3727,8 @@ bool dispc_div_calc(unsigned long dispc_freq,
3522 * also. Thus we need to use the calculated lck. For 3727 * also. Thus we need to use the calculated lck. For
3523 * OMAP4+ the DISPC fclk is a separate clock. 3728 * OMAP4+ the DISPC fclk is a separate clock.
3524 */ 3729 */
3525 if (dispc_has_feature(FEAT_CORE_CLK_DIV)) 3730 if (dispc_has_feature(dispc, FEAT_CORE_CLK_DIV))
3526 fck = dispc_core_clk_rate(); 3731 fck = dispc_core_clk_rate(dispc);
3527 else 3732 else
3528 fck = lck; 3733 fck = lck;
3529 3734
@@ -3538,24 +3743,27 @@ bool dispc_div_calc(unsigned long dispc_freq,
3538 return false; 3743 return false;
3539} 3744}
3540 3745
3541void dispc_mgr_set_clock_div(enum omap_channel channel, 3746void dispc_mgr_set_clock_div(struct dispc_device *dispc,
3542 const struct dispc_clock_info *cinfo) 3747 enum omap_channel channel,
3748 const struct dispc_clock_info *cinfo)
3543{ 3749{
3544 DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div); 3750 DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
3545 DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div); 3751 DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
3546 3752
3547 dispc_mgr_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div); 3753 dispc_mgr_set_lcd_divisor(dispc, channel, cinfo->lck_div,
3754 cinfo->pck_div);
3548} 3755}
3549 3756
3550int dispc_mgr_get_clock_div(enum omap_channel channel, 3757int dispc_mgr_get_clock_div(struct dispc_device *dispc,
3551 struct dispc_clock_info *cinfo) 3758 enum omap_channel channel,
3759 struct dispc_clock_info *cinfo)
3552{ 3760{
3553 unsigned long fck; 3761 unsigned long fck;
3554 3762
3555 fck = dispc_fclk_rate(); 3763 fck = dispc_fclk_rate(dispc);
3556 3764
3557 cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16); 3765 cinfo->lck_div = REG_GET(dispc, DISPC_DIVISORo(channel), 23, 16);
3558 cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0); 3766 cinfo->pck_div = REG_GET(dispc, DISPC_DIVISORo(channel), 7, 0);
3559 3767
3560 cinfo->lck = fck / cinfo->lck_div; 3768 cinfo->lck = fck / cinfo->lck_div;
3561 cinfo->pck = cinfo->lck / cinfo->pck_div; 3769 cinfo->pck = cinfo->lck / cinfo->pck_div;
@@ -3563,53 +3771,56 @@ int dispc_mgr_get_clock_div(enum omap_channel channel,
3563 return 0; 3771 return 0;
3564} 3772}
3565 3773
3566static u32 dispc_read_irqstatus(void) 3774static u32 dispc_read_irqstatus(struct dispc_device *dispc)
3567{ 3775{
3568 return dispc_read_reg(DISPC_IRQSTATUS); 3776 return dispc_read_reg(dispc, DISPC_IRQSTATUS);
3569} 3777}
3570 3778
3571static void dispc_clear_irqstatus(u32 mask) 3779static void dispc_clear_irqstatus(struct dispc_device *dispc, u32 mask)
3572{ 3780{
3573 dispc_write_reg(DISPC_IRQSTATUS, mask); 3781 dispc_write_reg(dispc, DISPC_IRQSTATUS, mask);
3574} 3782}
3575 3783
3576static void dispc_write_irqenable(u32 mask) 3784static void dispc_write_irqenable(struct dispc_device *dispc, u32 mask)
3577{ 3785{
3578 u32 old_mask = dispc_read_reg(DISPC_IRQENABLE); 3786 u32 old_mask = dispc_read_reg(dispc, DISPC_IRQENABLE);
3579 3787
3580 /* clear the irqstatus for newly enabled irqs */ 3788 /* clear the irqstatus for newly enabled irqs */
3581 dispc_clear_irqstatus((mask ^ old_mask) & mask); 3789 dispc_clear_irqstatus(dispc, (mask ^ old_mask) & mask);
3582 3790
3583 dispc_write_reg(DISPC_IRQENABLE, mask); 3791 dispc_write_reg(dispc, DISPC_IRQENABLE, mask);
3584 3792
3585 /* flush posted write */ 3793 /* flush posted write */
3586 dispc_read_reg(DISPC_IRQENABLE); 3794 dispc_read_reg(dispc, DISPC_IRQENABLE);
3587} 3795}
3588 3796
3589void dispc_enable_sidle(void) 3797void dispc_enable_sidle(struct dispc_device *dispc)
3590{ 3798{
3591 REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3); /* SIDLEMODE: smart idle */ 3799 /* SIDLEMODE: smart idle */
3800 REG_FLD_MOD(dispc, DISPC_SYSCONFIG, 2, 4, 3);
3592} 3801}
3593 3802
3594void dispc_disable_sidle(void) 3803void dispc_disable_sidle(struct dispc_device *dispc)
3595{ 3804{
3596 REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */ 3805 REG_FLD_MOD(dispc, DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */
3597} 3806}
3598 3807
3599static u32 dispc_mgr_gamma_size(enum omap_channel channel) 3808static u32 dispc_mgr_gamma_size(struct dispc_device *dispc,
3809 enum omap_channel channel)
3600{ 3810{
3601 const struct dispc_gamma_desc *gdesc = &mgr_desc[channel].gamma; 3811 const struct dispc_gamma_desc *gdesc = &mgr_desc[channel].gamma;
3602 3812
3603 if (!dispc.feat->has_gamma_table) 3813 if (!dispc->feat->has_gamma_table)
3604 return 0; 3814 return 0;
3605 3815
3606 return gdesc->len; 3816 return gdesc->len;
3607} 3817}
3608 3818
3609static void dispc_mgr_write_gamma_table(enum omap_channel channel) 3819static void dispc_mgr_write_gamma_table(struct dispc_device *dispc,
3820 enum omap_channel channel)
3610{ 3821{
3611 const struct dispc_gamma_desc *gdesc = &mgr_desc[channel].gamma; 3822 const struct dispc_gamma_desc *gdesc = &mgr_desc[channel].gamma;
3612 u32 *table = dispc.gamma_table[channel]; 3823 u32 *table = dispc->gamma_table[channel];
3613 unsigned int i; 3824 unsigned int i;
3614 3825
3615 DSSDBG("%s: channel %d\n", __func__, channel); 3826 DSSDBG("%s: channel %d\n", __func__, channel);
@@ -3622,26 +3833,26 @@ static void dispc_mgr_write_gamma_table(enum omap_channel channel)
3622 else if (i == 0) 3833 else if (i == 0)
3623 v |= 1 << 31; 3834 v |= 1 << 31;
3624 3835
3625 dispc_write_reg(gdesc->reg, v); 3836 dispc_write_reg(dispc, gdesc->reg, v);
3626 } 3837 }
3627} 3838}
3628 3839
3629static void dispc_restore_gamma_tables(void) 3840static void dispc_restore_gamma_tables(struct dispc_device *dispc)
3630{ 3841{
3631 DSSDBG("%s()\n", __func__); 3842 DSSDBG("%s()\n", __func__);
3632 3843
3633 if (!dispc.feat->has_gamma_table) 3844 if (!dispc->feat->has_gamma_table)
3634 return; 3845 return;
3635 3846
3636 dispc_mgr_write_gamma_table(OMAP_DSS_CHANNEL_LCD); 3847 dispc_mgr_write_gamma_table(dispc, OMAP_DSS_CHANNEL_LCD);
3637 3848
3638 dispc_mgr_write_gamma_table(OMAP_DSS_CHANNEL_DIGIT); 3849 dispc_mgr_write_gamma_table(dispc, OMAP_DSS_CHANNEL_DIGIT);
3639 3850
3640 if (dispc_has_feature(FEAT_MGR_LCD2)) 3851 if (dispc_has_feature(dispc, FEAT_MGR_LCD2))
3641 dispc_mgr_write_gamma_table(OMAP_DSS_CHANNEL_LCD2); 3852 dispc_mgr_write_gamma_table(dispc, OMAP_DSS_CHANNEL_LCD2);
3642 3853
3643 if (dispc_has_feature(FEAT_MGR_LCD3)) 3854 if (dispc_has_feature(dispc, FEAT_MGR_LCD3))
3644 dispc_mgr_write_gamma_table(OMAP_DSS_CHANNEL_LCD3); 3855 dispc_mgr_write_gamma_table(dispc, OMAP_DSS_CHANNEL_LCD3);
3645} 3856}
3646 3857
3647static const struct drm_color_lut dispc_mgr_gamma_default_lut[] = { 3858static const struct drm_color_lut dispc_mgr_gamma_default_lut[] = {
@@ -3649,18 +3860,19 @@ static const struct drm_color_lut dispc_mgr_gamma_default_lut[] = {
3649 { .red = U16_MAX, .green = U16_MAX, .blue = U16_MAX, }, 3860 { .red = U16_MAX, .green = U16_MAX, .blue = U16_MAX, },
3650}; 3861};
3651 3862
3652static void dispc_mgr_set_gamma(enum omap_channel channel, 3863static void dispc_mgr_set_gamma(struct dispc_device *dispc,
3653 const struct drm_color_lut *lut, 3864 enum omap_channel channel,
3654 unsigned int length) 3865 const struct drm_color_lut *lut,
3866 unsigned int length)
3655{ 3867{
3656 const struct dispc_gamma_desc *gdesc = &mgr_desc[channel].gamma; 3868 const struct dispc_gamma_desc *gdesc = &mgr_desc[channel].gamma;
3657 u32 *table = dispc.gamma_table[channel]; 3869 u32 *table = dispc->gamma_table[channel];
3658 uint i; 3870 uint i;
3659 3871
3660 DSSDBG("%s: channel %d, lut len %u, hw len %u\n", __func__, 3872 DSSDBG("%s: channel %d, lut len %u, hw len %u\n", __func__,
3661 channel, length, gdesc->len); 3873 channel, length, gdesc->len);
3662 3874
3663 if (!dispc.feat->has_gamma_table) 3875 if (!dispc->feat->has_gamma_table)
3664 return; 3876 return;
3665 3877
3666 if (lut == NULL || length < 2) { 3878 if (lut == NULL || length < 2) {
@@ -3692,82 +3904,83 @@ static void dispc_mgr_set_gamma(enum omap_channel channel,
3692 } 3904 }
3693 } 3905 }
3694 3906
3695 if (dispc.is_enabled) 3907 if (dispc->is_enabled)
3696 dispc_mgr_write_gamma_table(channel); 3908 dispc_mgr_write_gamma_table(dispc, channel);
3697} 3909}
3698 3910
3699static int dispc_init_gamma_tables(void) 3911static int dispc_init_gamma_tables(struct dispc_device *dispc)
3700{ 3912{
3701 int channel; 3913 int channel;
3702 3914
3703 if (!dispc.feat->has_gamma_table) 3915 if (!dispc->feat->has_gamma_table)
3704 return 0; 3916 return 0;
3705 3917
3706 for (channel = 0; channel < ARRAY_SIZE(dispc.gamma_table); channel++) { 3918 for (channel = 0; channel < ARRAY_SIZE(dispc->gamma_table); channel++) {
3707 const struct dispc_gamma_desc *gdesc = &mgr_desc[channel].gamma; 3919 const struct dispc_gamma_desc *gdesc = &mgr_desc[channel].gamma;
3708 u32 *gt; 3920 u32 *gt;
3709 3921
3710 if (channel == OMAP_DSS_CHANNEL_LCD2 && 3922 if (channel == OMAP_DSS_CHANNEL_LCD2 &&
3711 !dispc_has_feature(FEAT_MGR_LCD2)) 3923 !dispc_has_feature(dispc, FEAT_MGR_LCD2))
3712 continue; 3924 continue;
3713 3925
3714 if (channel == OMAP_DSS_CHANNEL_LCD3 && 3926 if (channel == OMAP_DSS_CHANNEL_LCD3 &&
3715 !dispc_has_feature(FEAT_MGR_LCD3)) 3927 !dispc_has_feature(dispc, FEAT_MGR_LCD3))
3716 continue; 3928 continue;
3717 3929
3718 gt = devm_kmalloc_array(&dispc.pdev->dev, gdesc->len, 3930 gt = devm_kmalloc_array(&dispc->pdev->dev, gdesc->len,
3719 sizeof(u32), GFP_KERNEL); 3931 sizeof(u32), GFP_KERNEL);
3720 if (!gt) 3932 if (!gt)
3721 return -ENOMEM; 3933 return -ENOMEM;
3722 3934
3723 dispc.gamma_table[channel] = gt; 3935 dispc->gamma_table[channel] = gt;
3724 3936
3725 dispc_mgr_set_gamma(channel, NULL, 0); 3937 dispc_mgr_set_gamma(dispc, channel, NULL, 0);
3726 } 3938 }
3727 return 0; 3939 return 0;
3728} 3940}
3729 3941
3730static void _omap_dispc_initial_config(void) 3942static void _omap_dispc_initial_config(struct dispc_device *dispc)
3731{ 3943{
3732 u32 l; 3944 u32 l;
3733 3945
3734 /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */ 3946 /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
3735 if (dispc_has_feature(FEAT_CORE_CLK_DIV)) { 3947 if (dispc_has_feature(dispc, FEAT_CORE_CLK_DIV)) {
3736 l = dispc_read_reg(DISPC_DIVISOR); 3948 l = dispc_read_reg(dispc, DISPC_DIVISOR);
3737 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */ 3949 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
3738 l = FLD_MOD(l, 1, 0, 0); 3950 l = FLD_MOD(l, 1, 0, 0);
3739 l = FLD_MOD(l, 1, 23, 16); 3951 l = FLD_MOD(l, 1, 23, 16);
3740 dispc_write_reg(DISPC_DIVISOR, l); 3952 dispc_write_reg(dispc, DISPC_DIVISOR, l);
3741 3953
3742 dispc.core_clk_rate = dispc_fclk_rate(); 3954 dispc->core_clk_rate = dispc_fclk_rate(dispc);
3743 } 3955 }
3744 3956
3745 /* Use gamma table mode, instead of palette mode */ 3957 /* Use gamma table mode, instead of palette mode */
3746 if (dispc.feat->has_gamma_table) 3958 if (dispc->feat->has_gamma_table)
3747 REG_FLD_MOD(DISPC_CONFIG, 1, 3, 3); 3959 REG_FLD_MOD(dispc, DISPC_CONFIG, 1, 3, 3);
3748 3960
3749 /* For older DSS versions (FEAT_FUNCGATED) this enables 3961 /* For older DSS versions (FEAT_FUNCGATED) this enables
3750 * func-clock auto-gating. For newer versions 3962 * func-clock auto-gating. For newer versions
3751 * (dispc.feat->has_gamma_table) this enables tv-out gamma tables. 3963 * (dispc->feat->has_gamma_table) this enables tv-out gamma tables.
3752 */ 3964 */
3753 if (dispc_has_feature(FEAT_FUNCGATED) || dispc.feat->has_gamma_table) 3965 if (dispc_has_feature(dispc, FEAT_FUNCGATED) ||
3754 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9); 3966 dispc->feat->has_gamma_table)
3967 REG_FLD_MOD(dispc, DISPC_CONFIG, 1, 9, 9);
3755 3968
3756 dispc_setup_color_conv_coef(); 3969 dispc_setup_color_conv_coef(dispc);
3757 3970
3758 dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY); 3971 dispc_set_loadmode(dispc, OMAP_DSS_LOAD_FRAME_ONLY);
3759 3972
3760 dispc_init_fifos(); 3973 dispc_init_fifos(dispc);
3761 3974
3762 dispc_configure_burst_sizes(); 3975 dispc_configure_burst_sizes(dispc);
3763 3976
3764 dispc_ovl_enable_zorder_planes(); 3977 dispc_ovl_enable_zorder_planes(dispc);
3765 3978
3766 if (dispc.feat->mstandby_workaround) 3979 if (dispc->feat->mstandby_workaround)
3767 REG_FLD_MOD(DISPC_MSTANDBY_CTRL, 1, 0, 0); 3980 REG_FLD_MOD(dispc, DISPC_MSTANDBY_CTRL, 1, 0, 0);
3768 3981
3769 if (dispc_has_feature(FEAT_MFLAG)) 3982 if (dispc_has_feature(dispc, FEAT_MFLAG))
3770 dispc_init_mflag(); 3983 dispc_init_mflag(dispc);
3771} 3984}
3772 3985
3773static const enum dispc_feature_id omap2_dispc_features_list[] = { 3986static const enum dispc_feature_id omap2_dispc_features_list[] = {
@@ -4286,49 +4499,52 @@ static const struct dispc_features omap54xx_dispc_feats = {
4286 4499
4287static irqreturn_t dispc_irq_handler(int irq, void *arg) 4500static irqreturn_t dispc_irq_handler(int irq, void *arg)
4288{ 4501{
4289 if (!dispc.is_enabled) 4502 struct dispc_device *dispc = arg;
4503
4504 if (!dispc->is_enabled)
4290 return IRQ_NONE; 4505 return IRQ_NONE;
4291 4506
4292 return dispc.user_handler(irq, dispc.user_data); 4507 return dispc->user_handler(irq, dispc->user_data);
4293} 4508}
4294 4509
4295static int dispc_request_irq(irq_handler_t handler, void *dev_id) 4510static int dispc_request_irq(struct dispc_device *dispc, irq_handler_t handler,
4511 void *dev_id)
4296{ 4512{
4297 int r; 4513 int r;
4298 4514
4299 if (dispc.user_handler != NULL) 4515 if (dispc->user_handler != NULL)
4300 return -EBUSY; 4516 return -EBUSY;
4301 4517
4302 dispc.user_handler = handler; 4518 dispc->user_handler = handler;
4303 dispc.user_data = dev_id; 4519 dispc->user_data = dev_id;
4304 4520
4305 /* ensure the dispc_irq_handler sees the values above */ 4521 /* ensure the dispc_irq_handler sees the values above */
4306 smp_wmb(); 4522 smp_wmb();
4307 4523
4308 r = devm_request_irq(&dispc.pdev->dev, dispc.irq, dispc_irq_handler, 4524 r = devm_request_irq(&dispc->pdev->dev, dispc->irq, dispc_irq_handler,
4309 IRQF_SHARED, "OMAP DISPC", &dispc); 4525 IRQF_SHARED, "OMAP DISPC", dispc);
4310 if (r) { 4526 if (r) {
4311 dispc.user_handler = NULL; 4527 dispc->user_handler = NULL;
4312 dispc.user_data = NULL; 4528 dispc->user_data = NULL;
4313 } 4529 }
4314 4530
4315 return r; 4531 return r;
4316} 4532}
4317 4533
4318static void dispc_free_irq(void *dev_id) 4534static void dispc_free_irq(struct dispc_device *dispc, void *dev_id)
4319{ 4535{
4320 devm_free_irq(&dispc.pdev->dev, dispc.irq, &dispc); 4536 devm_free_irq(&dispc->pdev->dev, dispc->irq, dispc);
4321 4537
4322 dispc.user_handler = NULL; 4538 dispc->user_handler = NULL;
4323 dispc.user_data = NULL; 4539 dispc->user_data = NULL;
4324} 4540}
4325 4541
4326static u32 dispc_get_memory_bandwidth_limit(void) 4542static u32 dispc_get_memory_bandwidth_limit(struct dispc_device *dispc)
4327{ 4543{
4328 u32 limit = 0; 4544 u32 limit = 0;
4329 4545
4330 /* Optional maximum memory bandwidth */ 4546 /* Optional maximum memory bandwidth */
4331 of_property_read_u32(dispc.pdev->dev.of_node, "max-memory-bandwidth", 4547 of_property_read_u32(dispc->pdev->dev.of_node, "max-memory-bandwidth",
4332 &limit); 4548 &limit);
4333 4549
4334 return limit; 4550 return limit;
@@ -4405,18 +4621,19 @@ static struct i734_buf {
4405 void *vaddr; 4621 void *vaddr;
4406} i734_buf; 4622} i734_buf;
4407 4623
4408static int dispc_errata_i734_wa_init(void) 4624static int dispc_errata_i734_wa_init(struct dispc_device *dispc)
4409{ 4625{
4410 if (!dispc.feat->has_gamma_i734_bug) 4626 if (!dispc->feat->has_gamma_i734_bug)
4411 return 0; 4627 return 0;
4412 4628
4413 i734_buf.size = i734.ovli.width * i734.ovli.height * 4629 i734_buf.size = i734.ovli.width * i734.ovli.height *
4414 color_mode_to_bpp(i734.ovli.fourcc) / 8; 4630 color_mode_to_bpp(i734.ovli.fourcc) / 8;
4415 4631
4416 i734_buf.vaddr = dma_alloc_writecombine(&dispc.pdev->dev, i734_buf.size, 4632 i734_buf.vaddr = dma_alloc_writecombine(&dispc->pdev->dev,
4417 &i734_buf.paddr, GFP_KERNEL); 4633 i734_buf.size, &i734_buf.paddr,
4634 GFP_KERNEL);
4418 if (!i734_buf.vaddr) { 4635 if (!i734_buf.vaddr) {
4419 dev_err(&dispc.pdev->dev, "%s: dma_alloc_writecombine failed", 4636 dev_err(&dispc->pdev->dev, "%s: dma_alloc_writecombine failed",
4420 __func__); 4637 __func__);
4421 return -ENOMEM; 4638 return -ENOMEM;
4422 } 4639 }
@@ -4424,72 +4641,73 @@ static int dispc_errata_i734_wa_init(void)
4424 return 0; 4641 return 0;
4425} 4642}
4426 4643
4427static void dispc_errata_i734_wa_fini(void) 4644static void dispc_errata_i734_wa_fini(struct dispc_device *dispc)
4428{ 4645{
4429 if (!dispc.feat->has_gamma_i734_bug) 4646 if (!dispc->feat->has_gamma_i734_bug)
4430 return; 4647 return;
4431 4648
4432 dma_free_writecombine(&dispc.pdev->dev, i734_buf.size, i734_buf.vaddr, 4649 dma_free_writecombine(&dispc->pdev->dev, i734_buf.size, i734_buf.vaddr,
4433 i734_buf.paddr); 4650 i734_buf.paddr);
4434} 4651}
4435 4652
4436static void dispc_errata_i734_wa(void) 4653static void dispc_errata_i734_wa(struct dispc_device *dispc)
4437{ 4654{
4438 u32 framedone_irq = dispc_mgr_get_framedone_irq(OMAP_DSS_CHANNEL_LCD); 4655 u32 framedone_irq = dispc_mgr_get_framedone_irq(dispc,
4656 OMAP_DSS_CHANNEL_LCD);
4439 struct omap_overlay_info ovli; 4657 struct omap_overlay_info ovli;
4440 struct dss_lcd_mgr_config lcd_conf; 4658 struct dss_lcd_mgr_config lcd_conf;
4441 u32 gatestate; 4659 u32 gatestate;
4442 unsigned int count; 4660 unsigned int count;
4443 4661
4444 if (!dispc.feat->has_gamma_i734_bug) 4662 if (!dispc->feat->has_gamma_i734_bug)
4445 return; 4663 return;
4446 4664
4447 gatestate = REG_GET(DISPC_CONFIG, 8, 4); 4665 gatestate = REG_GET(dispc, DISPC_CONFIG, 8, 4);
4448 4666
4449 ovli = i734.ovli; 4667 ovli = i734.ovli;
4450 ovli.paddr = i734_buf.paddr; 4668 ovli.paddr = i734_buf.paddr;
4451 lcd_conf = i734.lcd_conf; 4669 lcd_conf = i734.lcd_conf;
4452 4670
4453 /* Gate all LCD1 outputs */ 4671 /* Gate all LCD1 outputs */
4454 REG_FLD_MOD(DISPC_CONFIG, 0x1f, 8, 4); 4672 REG_FLD_MOD(dispc, DISPC_CONFIG, 0x1f, 8, 4);
4455 4673
4456 /* Setup and enable GFX plane */ 4674 /* Setup and enable GFX plane */
4457 dispc_ovl_setup(OMAP_DSS_GFX, &ovli, &i734.vm, false, 4675 dispc_ovl_setup(dispc, OMAP_DSS_GFX, &ovli, &i734.vm, false,
4458 OMAP_DSS_CHANNEL_LCD); 4676 OMAP_DSS_CHANNEL_LCD);
4459 dispc_ovl_enable(OMAP_DSS_GFX, true); 4677 dispc_ovl_enable(dispc, OMAP_DSS_GFX, true);
4460 4678
4461 /* Set up and enable display manager for LCD1 */ 4679 /* Set up and enable display manager for LCD1 */
4462 dispc_mgr_setup(OMAP_DSS_CHANNEL_LCD, &i734.mgri); 4680 dispc_mgr_setup(dispc, OMAP_DSS_CHANNEL_LCD, &i734.mgri);
4463 dispc_calc_clock_rates(dss_get_dispc_clk_rate(), 4681 dispc_calc_clock_rates(dispc, dss_get_dispc_clk_rate(dispc->dss),
4464 &lcd_conf.clock_info); 4682 &lcd_conf.clock_info);
4465 dispc_mgr_set_lcd_config(OMAP_DSS_CHANNEL_LCD, &lcd_conf); 4683 dispc_mgr_set_lcd_config(dispc, OMAP_DSS_CHANNEL_LCD, &lcd_conf);
4466 dispc_mgr_set_timings(OMAP_DSS_CHANNEL_LCD, &i734.vm); 4684 dispc_mgr_set_timings(dispc, OMAP_DSS_CHANNEL_LCD, &i734.vm);
4467 4685
4468 dispc_clear_irqstatus(framedone_irq); 4686 dispc_clear_irqstatus(dispc, framedone_irq);
4469 4687
4470 /* Enable and shut the channel to produce just one frame */ 4688 /* Enable and shut the channel to produce just one frame */
4471 dispc_mgr_enable(OMAP_DSS_CHANNEL_LCD, true); 4689 dispc_mgr_enable(dispc, OMAP_DSS_CHANNEL_LCD, true);
4472 dispc_mgr_enable(OMAP_DSS_CHANNEL_LCD, false); 4690 dispc_mgr_enable(dispc, OMAP_DSS_CHANNEL_LCD, false);
4473 4691
4474 /* Busy wait for framedone. We can't fiddle with irq handlers 4692 /* Busy wait for framedone. We can't fiddle with irq handlers
4475 * in PM resume. Typically the loop runs less than 5 times and 4693 * in PM resume. Typically the loop runs less than 5 times and
4476 * waits less than a micro second. 4694 * waits less than a micro second.
4477 */ 4695 */
4478 count = 0; 4696 count = 0;
4479 while (!(dispc_read_irqstatus() & framedone_irq)) { 4697 while (!(dispc_read_irqstatus(dispc) & framedone_irq)) {
4480 if (count++ > 10000) { 4698 if (count++ > 10000) {
4481 dev_err(&dispc.pdev->dev, "%s: framedone timeout\n", 4699 dev_err(&dispc->pdev->dev, "%s: framedone timeout\n",
4482 __func__); 4700 __func__);
4483 break; 4701 break;
4484 } 4702 }
4485 } 4703 }
4486 dispc_ovl_enable(OMAP_DSS_GFX, false); 4704 dispc_ovl_enable(dispc, OMAP_DSS_GFX, false);
4487 4705
4488 /* Clear all irq bits before continuing */ 4706 /* Clear all irq bits before continuing */
4489 dispc_clear_irqstatus(0xffffffff); 4707 dispc_clear_irqstatus(dispc, 0xffffffff);
4490 4708
4491 /* Restore the original state to LCD1 output gates */ 4709 /* Restore the original state to LCD1 output gates */
4492 REG_FLD_MOD(DISPC_CONFIG, gatestate, 8, 4); 4710 REG_FLD_MOD(dispc, DISPC_CONFIG, gatestate, 8, 4);
4493} 4711}
4494 4712
4495static const struct dispc_ops dispc_ops = { 4713static const struct dispc_ops dispc_ops = {
@@ -4525,6 +4743,12 @@ static const struct dispc_ops dispc_ops = {
4525 .ovl_enable = dispc_ovl_enable, 4743 .ovl_enable = dispc_ovl_enable,
4526 .ovl_setup = dispc_ovl_setup, 4744 .ovl_setup = dispc_ovl_setup,
4527 .ovl_get_color_modes = dispc_ovl_get_color_modes, 4745 .ovl_get_color_modes = dispc_ovl_get_color_modes,
4746
4747 .wb_get_framedone_irq = dispc_wb_get_framedone_irq,
4748 .wb_setup = dispc_wb_setup,
4749 .has_writeback = dispc_has_writeback,
4750 .wb_go_busy = dispc_wb_go_busy,
4751 .wb_go = dispc_wb_go,
4528}; 4752};
4529 4753
4530/* DISPC HW IP initialisation */ 4754/* DISPC HW IP initialisation */
@@ -4550,14 +4774,22 @@ static int dispc_bind(struct device *dev, struct device *master, void *data)
4550{ 4774{
4551 struct platform_device *pdev = to_platform_device(dev); 4775 struct platform_device *pdev = to_platform_device(dev);
4552 const struct soc_device_attribute *soc; 4776 const struct soc_device_attribute *soc;
4777 struct dss_device *dss = dss_get_device(master);
4778 struct dispc_device *dispc;
4553 u32 rev; 4779 u32 rev;
4554 int r = 0; 4780 int r = 0;
4555 struct resource *dispc_mem; 4781 struct resource *dispc_mem;
4556 struct device_node *np = pdev->dev.of_node; 4782 struct device_node *np = pdev->dev.of_node;
4557 4783
4558 dispc.pdev = pdev; 4784 dispc = kzalloc(sizeof(*dispc), GFP_KERNEL);
4785 if (!dispc)
4786 return -ENOMEM;
4787
4788 dispc->pdev = pdev;
4789 platform_set_drvdata(pdev, dispc);
4790 dispc->dss = dss;
4559 4791
4560 spin_lock_init(&dispc.control_lock); 4792 spin_lock_init(&dispc->control_lock);
4561 4793
4562 /* 4794 /*
4563 * The OMAP3-based models can't be told apart using the compatible 4795 * The OMAP3-based models can't be told apart using the compatible
@@ -4565,76 +4797,92 @@ static int dispc_bind(struct device *dev, struct device *master, void *data)
4565 */ 4797 */
4566 soc = soc_device_match(dispc_soc_devices); 4798 soc = soc_device_match(dispc_soc_devices);
4567 if (soc) 4799 if (soc)
4568 dispc.feat = soc->data; 4800 dispc->feat = soc->data;
4569 else 4801 else
4570 dispc.feat = of_match_device(dispc_of_match, &pdev->dev)->data; 4802 dispc->feat = of_match_device(dispc_of_match, &pdev->dev)->data;
4571 4803
4572 r = dispc_errata_i734_wa_init(); 4804 r = dispc_errata_i734_wa_init(dispc);
4573 if (r) 4805 if (r)
4574 return r; 4806 goto err_free;
4575 4807
4576 dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0); 4808 dispc_mem = platform_get_resource(dispc->pdev, IORESOURCE_MEM, 0);
4577 dispc.base = devm_ioremap_resource(&pdev->dev, dispc_mem); 4809 dispc->base = devm_ioremap_resource(&pdev->dev, dispc_mem);
4578 if (IS_ERR(dispc.base)) 4810 if (IS_ERR(dispc->base)) {
4579 return PTR_ERR(dispc.base); 4811 r = PTR_ERR(dispc->base);
4812 goto err_free;
4813 }
4580 4814
4581 dispc.irq = platform_get_irq(dispc.pdev, 0); 4815 dispc->irq = platform_get_irq(dispc->pdev, 0);
4582 if (dispc.irq < 0) { 4816 if (dispc->irq < 0) {
4583 DSSERR("platform_get_irq failed\n"); 4817 DSSERR("platform_get_irq failed\n");
4584 return -ENODEV; 4818 r = -ENODEV;
4819 goto err_free;
4585 } 4820 }
4586 4821
4587 if (np && of_property_read_bool(np, "syscon-pol")) { 4822 if (np && of_property_read_bool(np, "syscon-pol")) {
4588 dispc.syscon_pol = syscon_regmap_lookup_by_phandle(np, "syscon-pol"); 4823 dispc->syscon_pol = syscon_regmap_lookup_by_phandle(np, "syscon-pol");
4589 if (IS_ERR(dispc.syscon_pol)) { 4824 if (IS_ERR(dispc->syscon_pol)) {
4590 dev_err(&pdev->dev, "failed to get syscon-pol regmap\n"); 4825 dev_err(&pdev->dev, "failed to get syscon-pol regmap\n");
4591 return PTR_ERR(dispc.syscon_pol); 4826 r = PTR_ERR(dispc->syscon_pol);
4827 goto err_free;
4592 } 4828 }
4593 4829
4594 if (of_property_read_u32_index(np, "syscon-pol", 1, 4830 if (of_property_read_u32_index(np, "syscon-pol", 1,
4595 &dispc.syscon_pol_offset)) { 4831 &dispc->syscon_pol_offset)) {
4596 dev_err(&pdev->dev, "failed to get syscon-pol offset\n"); 4832 dev_err(&pdev->dev, "failed to get syscon-pol offset\n");
4597 return -EINVAL; 4833 r = -EINVAL;
4834 goto err_free;
4598 } 4835 }
4599 } 4836 }
4600 4837
4601 r = dispc_init_gamma_tables(); 4838 r = dispc_init_gamma_tables(dispc);
4602 if (r) 4839 if (r)
4603 return r; 4840 goto err_free;
4604 4841
4605 pm_runtime_enable(&pdev->dev); 4842 pm_runtime_enable(&pdev->dev);
4606 4843
4607 r = dispc_runtime_get(); 4844 r = dispc_runtime_get(dispc);
4608 if (r) 4845 if (r)
4609 goto err_runtime_get; 4846 goto err_runtime_get;
4610 4847
4611 _omap_dispc_initial_config(); 4848 _omap_dispc_initial_config(dispc);
4612 4849
4613 rev = dispc_read_reg(DISPC_REVISION); 4850 rev = dispc_read_reg(dispc, DISPC_REVISION);
4614 dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n", 4851 dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
4615 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); 4852 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
4616 4853
4617 dispc_runtime_put(); 4854 dispc_runtime_put(dispc);
4618 4855
4619 dispc_set_ops(&dispc_ops); 4856 dss->dispc = dispc;
4857 dss->dispc_ops = &dispc_ops;
4620 4858
4621 dss_debugfs_create_file("dispc", dispc_dump_regs); 4859 dispc->debugfs = dss_debugfs_create_file(dss, "dispc", dispc_dump_regs,
4860 dispc);
4622 4861
4623 return 0; 4862 return 0;
4624 4863
4625err_runtime_get: 4864err_runtime_get:
4626 pm_runtime_disable(&pdev->dev); 4865 pm_runtime_disable(&pdev->dev);
4866err_free:
4867 kfree(dispc);
4627 return r; 4868 return r;
4628} 4869}
4629 4870
4630static void dispc_unbind(struct device *dev, struct device *master, 4871static void dispc_unbind(struct device *dev, struct device *master, void *data)
4631 void *data)
4632{ 4872{
4633 dispc_set_ops(NULL); 4873 struct dispc_device *dispc = dev_get_drvdata(dev);
4874 struct dss_device *dss = dispc->dss;
4875
4876 dss_debugfs_remove_file(dispc->debugfs);
4877
4878 dss->dispc = NULL;
4879 dss->dispc_ops = NULL;
4634 4880
4635 pm_runtime_disable(dev); 4881 pm_runtime_disable(dev);
4636 4882
4637 dispc_errata_i734_wa_fini(); 4883 dispc_errata_i734_wa_fini(dispc);
4884
4885 kfree(dispc);
4638} 4886}
4639 4887
4640static const struct component_ops dispc_component_ops = { 4888static const struct component_ops dispc_component_ops = {
@@ -4655,36 +4903,40 @@ static int dispc_remove(struct platform_device *pdev)
4655 4903
4656static int dispc_runtime_suspend(struct device *dev) 4904static int dispc_runtime_suspend(struct device *dev)
4657{ 4905{
4658 dispc.is_enabled = false; 4906 struct dispc_device *dispc = dev_get_drvdata(dev);
4907
4908 dispc->is_enabled = false;
4659 /* ensure the dispc_irq_handler sees the is_enabled value */ 4909 /* ensure the dispc_irq_handler sees the is_enabled value */
4660 smp_wmb(); 4910 smp_wmb();
4661 /* wait for current handler to finish before turning the DISPC off */ 4911 /* wait for current handler to finish before turning the DISPC off */
4662 synchronize_irq(dispc.irq); 4912 synchronize_irq(dispc->irq);
4663 4913
4664 dispc_save_context(); 4914 dispc_save_context(dispc);
4665 4915
4666 return 0; 4916 return 0;
4667} 4917}
4668 4918
4669static int dispc_runtime_resume(struct device *dev) 4919static int dispc_runtime_resume(struct device *dev)
4670{ 4920{
4921 struct dispc_device *dispc = dev_get_drvdata(dev);
4922
4671 /* 4923 /*
4672 * The reset value for load mode is 0 (OMAP_DSS_LOAD_CLUT_AND_FRAME) 4924 * The reset value for load mode is 0 (OMAP_DSS_LOAD_CLUT_AND_FRAME)
4673 * but we always initialize it to 2 (OMAP_DSS_LOAD_FRAME_ONLY) in 4925 * but we always initialize it to 2 (OMAP_DSS_LOAD_FRAME_ONLY) in
4674 * _omap_dispc_initial_config(). We can thus use it to detect if 4926 * _omap_dispc_initial_config(). We can thus use it to detect if
4675 * we have lost register context. 4927 * we have lost register context.
4676 */ 4928 */
4677 if (REG_GET(DISPC_CONFIG, 2, 1) != OMAP_DSS_LOAD_FRAME_ONLY) { 4929 if (REG_GET(dispc, DISPC_CONFIG, 2, 1) != OMAP_DSS_LOAD_FRAME_ONLY) {
4678 _omap_dispc_initial_config(); 4930 _omap_dispc_initial_config(dispc);
4679 4931
4680 dispc_errata_i734_wa(); 4932 dispc_errata_i734_wa(dispc);
4681 4933
4682 dispc_restore_context(); 4934 dispc_restore_context(dispc);
4683 4935
4684 dispc_restore_gamma_tables(); 4936 dispc_restore_gamma_tables(dispc);
4685 } 4937 }
4686 4938
4687 dispc.is_enabled = true; 4939 dispc->is_enabled = true;
4688 /* ensure the dispc_irq_handler sees the is_enabled value */ 4940 /* ensure the dispc_irq_handler sees the is_enabled value */
4689 smp_wmb(); 4941 smp_wmb();
4690 4942
diff --git a/drivers/gpu/drm/omapdrm/dss/display.c b/drivers/gpu/drm/omapdrm/dss/display.c
index 0c9480ba85c0..424143128cd4 100644
--- a/drivers/gpu/drm/omapdrm/dss/display.c
+++ b/drivers/gpu/drm/omapdrm/dss/display.c
@@ -28,12 +28,11 @@
28 28
29#include "omapdss.h" 29#include "omapdss.h"
30 30
31void omapdss_default_get_timings(struct omap_dss_device *dssdev, 31static void omapdss_default_get_timings(struct omap_dss_device *dssdev,
32 struct videomode *vm) 32 struct videomode *vm)
33{ 33{
34 *vm = dssdev->panel.vm; 34 *vm = dssdev->panel.vm;
35} 35}
36EXPORT_SYMBOL(omapdss_default_get_timings);
37 36
38static LIST_HEAD(panel_list); 37static LIST_HEAD(panel_list);
39static DEFINE_MUTEX(panel_list_mutex); 38static DEFINE_MUTEX(panel_list_mutex);
diff --git a/drivers/gpu/drm/omapdrm/dss/dpi.c b/drivers/gpu/drm/omapdrm/dss/dpi.c
index ea44137ed08c..fb1c27f69e3a 100644
--- a/drivers/gpu/drm/omapdrm/dss/dpi.c
+++ b/drivers/gpu/drm/omapdrm/dss/dpi.c
@@ -38,6 +38,7 @@
38struct dpi_data { 38struct dpi_data {
39 struct platform_device *pdev; 39 struct platform_device *pdev;
40 enum dss_model dss_model; 40 enum dss_model dss_model;
41 struct dss_device *dss;
41 42
42 struct regulator *vdds_dsi_reg; 43 struct regulator *vdds_dsi_reg;
43 enum dss_clk_source clk_src; 44 enum dss_clk_source clk_src;
@@ -57,7 +58,8 @@ static struct dpi_data *dpi_get_data_from_dssdev(struct omap_dss_device *dssdev)
57 return container_of(dssdev, struct dpi_data, output); 58 return container_of(dssdev, struct dpi_data, output);
58} 59}
59 60
60static enum dss_clk_source dpi_get_clk_src_dra7xx(enum omap_channel channel) 61static enum dss_clk_source dpi_get_clk_src_dra7xx(struct dpi_data *dpi,
62 enum omap_channel channel)
61{ 63{
62 /* 64 /*
63 * Possible clock sources: 65 * Possible clock sources:
@@ -69,23 +71,23 @@ static enum dss_clk_source dpi_get_clk_src_dra7xx(enum omap_channel channel)
69 switch (channel) { 71 switch (channel) {
70 case OMAP_DSS_CHANNEL_LCD: 72 case OMAP_DSS_CHANNEL_LCD:
71 { 73 {
72 if (dss_pll_find_by_src(DSS_CLK_SRC_PLL1_1)) 74 if (dss_pll_find_by_src(dpi->dss, DSS_CLK_SRC_PLL1_1))
73 return DSS_CLK_SRC_PLL1_1; 75 return DSS_CLK_SRC_PLL1_1;
74 break; 76 break;
75 } 77 }
76 case OMAP_DSS_CHANNEL_LCD2: 78 case OMAP_DSS_CHANNEL_LCD2:
77 { 79 {
78 if (dss_pll_find_by_src(DSS_CLK_SRC_PLL1_3)) 80 if (dss_pll_find_by_src(dpi->dss, DSS_CLK_SRC_PLL1_3))
79 return DSS_CLK_SRC_PLL1_3; 81 return DSS_CLK_SRC_PLL1_3;
80 if (dss_pll_find_by_src(DSS_CLK_SRC_PLL2_3)) 82 if (dss_pll_find_by_src(dpi->dss, DSS_CLK_SRC_PLL2_3))
81 return DSS_CLK_SRC_PLL2_3; 83 return DSS_CLK_SRC_PLL2_3;
82 break; 84 break;
83 } 85 }
84 case OMAP_DSS_CHANNEL_LCD3: 86 case OMAP_DSS_CHANNEL_LCD3:
85 { 87 {
86 if (dss_pll_find_by_src(DSS_CLK_SRC_PLL2_1)) 88 if (dss_pll_find_by_src(dpi->dss, DSS_CLK_SRC_PLL2_1))
87 return DSS_CLK_SRC_PLL2_1; 89 return DSS_CLK_SRC_PLL2_1;
88 if (dss_pll_find_by_src(DSS_CLK_SRC_PLL1_3)) 90 if (dss_pll_find_by_src(dpi->dss, DSS_CLK_SRC_PLL1_3))
89 return DSS_CLK_SRC_PLL1_3; 91 return DSS_CLK_SRC_PLL1_3;
90 break; 92 break;
91 } 93 }
@@ -132,7 +134,7 @@ static enum dss_clk_source dpi_get_clk_src(struct dpi_data *dpi)
132 } 134 }
133 135
134 case DSS_MODEL_DRA7: 136 case DSS_MODEL_DRA7:
135 return dpi_get_clk_src_dra7xx(channel); 137 return dpi_get_clk_src_dra7xx(dpi, channel);
136 138
137 default: 139 default:
138 return DSS_CLK_SRC_FCK; 140 return DSS_CLK_SRC_FCK;
@@ -141,7 +143,7 @@ static enum dss_clk_source dpi_get_clk_src(struct dpi_data *dpi)
141 143
142struct dpi_clk_calc_ctx { 144struct dpi_clk_calc_ctx {
143 struct dss_pll *pll; 145 struct dss_pll *pll;
144 unsigned clkout_idx; 146 unsigned int clkout_idx;
145 147
146 /* inputs */ 148 /* inputs */
147 149
@@ -189,8 +191,9 @@ static bool dpi_calc_hsdiv_cb(int m_dispc, unsigned long dispc,
189 ctx->pll_cinfo.mX[ctx->clkout_idx] = m_dispc; 191 ctx->pll_cinfo.mX[ctx->clkout_idx] = m_dispc;
190 ctx->pll_cinfo.clkout[ctx->clkout_idx] = dispc; 192 ctx->pll_cinfo.clkout[ctx->clkout_idx] = dispc;
191 193
192 return dispc_div_calc(dispc, ctx->pck_min, ctx->pck_max, 194 return dispc_div_calc(ctx->pll->dss->dispc, dispc,
193 dpi_calc_dispc_cb, ctx); 195 ctx->pck_min, ctx->pck_max,
196 dpi_calc_dispc_cb, ctx);
194} 197}
195 198
196 199
@@ -206,7 +209,7 @@ static bool dpi_calc_pll_cb(int n, int m, unsigned long fint,
206 ctx->pll_cinfo.clkdco = clkdco; 209 ctx->pll_cinfo.clkdco = clkdco;
207 210
208 return dss_pll_hsdiv_calc_a(ctx->pll, clkdco, 211 return dss_pll_hsdiv_calc_a(ctx->pll, clkdco,
209 ctx->pck_min, dss_get_max_fck_rate(), 212 ctx->pck_min, dss_get_max_fck_rate(ctx->pll->dss),
210 dpi_calc_hsdiv_cb, ctx); 213 dpi_calc_hsdiv_cb, ctx);
211} 214}
212 215
@@ -216,8 +219,9 @@ static bool dpi_calc_dss_cb(unsigned long fck, void *data)
216 219
217 ctx->fck = fck; 220 ctx->fck = fck;
218 221
219 return dispc_div_calc(fck, ctx->pck_min, ctx->pck_max, 222 return dispc_div_calc(ctx->pll->dss->dispc, fck,
220 dpi_calc_dispc_cb, ctx); 223 ctx->pck_min, ctx->pck_max,
224 dpi_calc_dispc_cb, ctx);
221} 225}
222 226
223static bool dpi_pll_clk_calc(struct dpi_data *dpi, unsigned long pck, 227static bool dpi_pll_clk_calc(struct dpi_data *dpi, unsigned long pck,
@@ -255,7 +259,8 @@ static bool dpi_pll_clk_calc(struct dpi_data *dpi, unsigned long pck,
255 } 259 }
256} 260}
257 261
258static bool dpi_dss_clk_calc(unsigned long pck, struct dpi_clk_calc_ctx *ctx) 262static bool dpi_dss_clk_calc(struct dpi_data *dpi, unsigned long pck,
263 struct dpi_clk_calc_ctx *ctx)
259{ 264{
260 int i; 265 int i;
261 266
@@ -276,7 +281,8 @@ static bool dpi_dss_clk_calc(unsigned long pck, struct dpi_clk_calc_ctx *ctx)
276 ctx->pck_min = 0; 281 ctx->pck_min = 0;
277 ctx->pck_max = pck + 1000 * i * i * i; 282 ctx->pck_max = pck + 1000 * i * i * i;
278 283
279 ok = dss_div_calc(pck, ctx->pck_min, dpi_calc_dss_cb, ctx); 284 ok = dss_div_calc(dpi->dss, pck, ctx->pck_min,
285 dpi_calc_dss_cb, ctx);
280 if (ok) 286 if (ok)
281 return ok; 287 return ok;
282 } 288 }
@@ -302,7 +308,7 @@ static int dpi_set_pll_clk(struct dpi_data *dpi, enum omap_channel channel,
302 if (r) 308 if (r)
303 return r; 309 return r;
304 310
305 dss_select_lcd_clk_source(channel, dpi->clk_src); 311 dss_select_lcd_clk_source(dpi->dss, channel, dpi->clk_src);
306 312
307 dpi->mgr_config.clock_info = ctx.dispc_cinfo; 313 dpi->mgr_config.clock_info = ctx.dispc_cinfo;
308 314
@@ -320,11 +326,11 @@ static int dpi_set_dispc_clk(struct dpi_data *dpi, unsigned long pck_req,
320 int r; 326 int r;
321 bool ok; 327 bool ok;
322 328
323 ok = dpi_dss_clk_calc(pck_req, &ctx); 329 ok = dpi_dss_clk_calc(dpi, pck_req, &ctx);
324 if (!ok) 330 if (!ok)
325 return -EINVAL; 331 return -EINVAL;
326 332
327 r = dss_set_fck_rate(ctx.fck); 333 r = dss_set_fck_rate(dpi->dss, ctx.fck);
328 if (r) 334 if (r)
329 return r; 335 return r;
330 336
@@ -339,8 +345,6 @@ static int dpi_set_dispc_clk(struct dpi_data *dpi, unsigned long pck_req,
339 345
340static int dpi_set_mode(struct dpi_data *dpi) 346static int dpi_set_mode(struct dpi_data *dpi)
341{ 347{
342 struct omap_dss_device *out = &dpi->output;
343 enum omap_channel channel = out->dispc_channel;
344 struct videomode *vm = &dpi->vm; 348 struct videomode *vm = &dpi->vm;
345 int lck_div = 0, pck_div = 0; 349 int lck_div = 0, pck_div = 0;
346 unsigned long fck = 0; 350 unsigned long fck = 0;
@@ -348,8 +352,8 @@ static int dpi_set_mode(struct dpi_data *dpi)
348 int r = 0; 352 int r = 0;
349 353
350 if (dpi->pll) 354 if (dpi->pll)
351 r = dpi_set_pll_clk(dpi, channel, vm->pixelclock, &fck, 355 r = dpi_set_pll_clk(dpi, dpi->output.dispc_channel,
352 &lck_div, &pck_div); 356 vm->pixelclock, &fck, &lck_div, &pck_div);
353 else 357 else
354 r = dpi_set_dispc_clk(dpi, vm->pixelclock, &fck, 358 r = dpi_set_dispc_clk(dpi, vm->pixelclock, &fck,
355 &lck_div, &pck_div); 359 &lck_div, &pck_div);
@@ -365,16 +369,13 @@ static int dpi_set_mode(struct dpi_data *dpi)
365 vm->pixelclock = pck; 369 vm->pixelclock = pck;
366 } 370 }
367 371
368 dss_mgr_set_timings(channel, vm); 372 dss_mgr_set_timings(&dpi->output, vm);
369 373
370 return 0; 374 return 0;
371} 375}
372 376
373static void dpi_config_lcd_manager(struct dpi_data *dpi) 377static void dpi_config_lcd_manager(struct dpi_data *dpi)
374{ 378{
375 struct omap_dss_device *out = &dpi->output;
376 enum omap_channel channel = out->dispc_channel;
377
378 dpi->mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS; 379 dpi->mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS;
379 380
380 dpi->mgr_config.stallmode = false; 381 dpi->mgr_config.stallmode = false;
@@ -384,14 +385,13 @@ static void dpi_config_lcd_manager(struct dpi_data *dpi)
384 385
385 dpi->mgr_config.lcden_sig_polarity = 0; 386 dpi->mgr_config.lcden_sig_polarity = 0;
386 387
387 dss_mgr_set_lcd_config(channel, &dpi->mgr_config); 388 dss_mgr_set_lcd_config(&dpi->output, &dpi->mgr_config);
388} 389}
389 390
390static int dpi_display_enable(struct omap_dss_device *dssdev) 391static int dpi_display_enable(struct omap_dss_device *dssdev)
391{ 392{
392 struct dpi_data *dpi = dpi_get_data_from_dssdev(dssdev); 393 struct dpi_data *dpi = dpi_get_data_from_dssdev(dssdev);
393 struct omap_dss_device *out = &dpi->output; 394 struct omap_dss_device *out = &dpi->output;
394 enum omap_channel channel = out->dispc_channel;
395 int r; 395 int r;
396 396
397 mutex_lock(&dpi->lock); 397 mutex_lock(&dpi->lock);
@@ -408,11 +408,11 @@ static int dpi_display_enable(struct omap_dss_device *dssdev)
408 goto err_reg_enable; 408 goto err_reg_enable;
409 } 409 }
410 410
411 r = dispc_runtime_get(); 411 r = dispc_runtime_get(dpi->dss->dispc);
412 if (r) 412 if (r)
413 goto err_get_dispc; 413 goto err_get_dispc;
414 414
415 r = dss_dpi_select_source(out->port_num, channel); 415 r = dss_dpi_select_source(dpi->dss, out->port_num, out->dispc_channel);
416 if (r) 416 if (r)
417 goto err_src_sel; 417 goto err_src_sel;
418 418
@@ -430,7 +430,7 @@ static int dpi_display_enable(struct omap_dss_device *dssdev)
430 430
431 mdelay(2); 431 mdelay(2);
432 432
433 r = dss_mgr_enable(channel); 433 r = dss_mgr_enable(&dpi->output);
434 if (r) 434 if (r)
435 goto err_mgr_enable; 435 goto err_mgr_enable;
436 436
@@ -444,7 +444,7 @@ err_set_mode:
444 dss_pll_disable(dpi->pll); 444 dss_pll_disable(dpi->pll);
445err_pll_init: 445err_pll_init:
446err_src_sel: 446err_src_sel:
447 dispc_runtime_put(); 447 dispc_runtime_put(dpi->dss->dispc);
448err_get_dispc: 448err_get_dispc:
449 if (dpi->vdds_dsi_reg) 449 if (dpi->vdds_dsi_reg)
450 regulator_disable(dpi->vdds_dsi_reg); 450 regulator_disable(dpi->vdds_dsi_reg);
@@ -457,18 +457,18 @@ err_no_out_mgr:
457static void dpi_display_disable(struct omap_dss_device *dssdev) 457static void dpi_display_disable(struct omap_dss_device *dssdev)
458{ 458{
459 struct dpi_data *dpi = dpi_get_data_from_dssdev(dssdev); 459 struct dpi_data *dpi = dpi_get_data_from_dssdev(dssdev);
460 enum omap_channel channel = dpi->output.dispc_channel;
461 460
462 mutex_lock(&dpi->lock); 461 mutex_lock(&dpi->lock);
463 462
464 dss_mgr_disable(channel); 463 dss_mgr_disable(&dpi->output);
465 464
466 if (dpi->pll) { 465 if (dpi->pll) {
467 dss_select_lcd_clk_source(channel, DSS_CLK_SRC_FCK); 466 dss_select_lcd_clk_source(dpi->dss, dpi->output.dispc_channel,
467 DSS_CLK_SRC_FCK);
468 dss_pll_disable(dpi->pll); 468 dss_pll_disable(dpi->pll);
469 } 469 }
470 470
471 dispc_runtime_put(); 471 dispc_runtime_put(dpi->dss->dispc);
472 472
473 if (dpi->vdds_dsi_reg) 473 if (dpi->vdds_dsi_reg)
474 regulator_disable(dpi->vdds_dsi_reg); 474 regulator_disable(dpi->vdds_dsi_reg);
@@ -516,7 +516,7 @@ static int dpi_check_timings(struct omap_dss_device *dssdev,
516 if (vm->hactive % 8 != 0) 516 if (vm->hactive % 8 != 0)
517 return -EINVAL; 517 return -EINVAL;
518 518
519 if (!dispc_mgr_timings_ok(channel, vm)) 519 if (!dispc_mgr_timings_ok(dpi->dss->dispc, channel, vm))
520 return -EINVAL; 520 return -EINVAL;
521 521
522 if (vm->pixelclock == 0) 522 if (vm->pixelclock == 0)
@@ -529,7 +529,7 @@ static int dpi_check_timings(struct omap_dss_device *dssdev,
529 529
530 fck = ctx.pll_cinfo.clkout[ctx.clkout_idx]; 530 fck = ctx.pll_cinfo.clkout[ctx.clkout_idx];
531 } else { 531 } else {
532 ok = dpi_dss_clk_calc(vm->pixelclock, &ctx); 532 ok = dpi_dss_clk_calc(dpi, vm->pixelclock, &ctx);
533 if (!ok) 533 if (!ok)
534 return -EINVAL; 534 return -EINVAL;
535 535
@@ -602,7 +602,7 @@ static void dpi_init_pll(struct dpi_data *dpi)
602 602
603 dpi->clk_src = dpi_get_clk_src(dpi); 603 dpi->clk_src = dpi_get_clk_src(dpi);
604 604
605 pll = dss_pll_find_by_src(dpi->clk_src); 605 pll = dss_pll_find_by_src(dpi->dss, dpi->clk_src);
606 if (!pll) 606 if (!pll)
607 return; 607 return;
608 608
@@ -654,7 +654,6 @@ static int dpi_connect(struct omap_dss_device *dssdev,
654 struct omap_dss_device *dst) 654 struct omap_dss_device *dst)
655{ 655{
656 struct dpi_data *dpi = dpi_get_data_from_dssdev(dssdev); 656 struct dpi_data *dpi = dpi_get_data_from_dssdev(dssdev);
657 enum omap_channel channel = dpi->output.dispc_channel;
658 int r; 657 int r;
659 658
660 r = dpi_init_regulator(dpi); 659 r = dpi_init_regulator(dpi);
@@ -663,7 +662,7 @@ static int dpi_connect(struct omap_dss_device *dssdev,
663 662
664 dpi_init_pll(dpi); 663 dpi_init_pll(dpi);
665 664
666 r = dss_mgr_connect(channel, dssdev); 665 r = dss_mgr_connect(&dpi->output, dssdev);
667 if (r) 666 if (r)
668 return r; 667 return r;
669 668
@@ -671,7 +670,7 @@ static int dpi_connect(struct omap_dss_device *dssdev,
671 if (r) { 670 if (r) {
672 DSSERR("failed to connect output to new device: %s\n", 671 DSSERR("failed to connect output to new device: %s\n",
673 dst->name); 672 dst->name);
674 dss_mgr_disconnect(channel, dssdev); 673 dss_mgr_disconnect(&dpi->output, dssdev);
675 return r; 674 return r;
676 } 675 }
677 676
@@ -682,7 +681,6 @@ static void dpi_disconnect(struct omap_dss_device *dssdev,
682 struct omap_dss_device *dst) 681 struct omap_dss_device *dst)
683{ 682{
684 struct dpi_data *dpi = dpi_get_data_from_dssdev(dssdev); 683 struct dpi_data *dpi = dpi_get_data_from_dssdev(dssdev);
685 enum omap_channel channel = dpi->output.dispc_channel;
686 684
687 WARN_ON(dst != dssdev->dst); 685 WARN_ON(dst != dssdev->dst);
688 686
@@ -691,7 +689,7 @@ static void dpi_disconnect(struct omap_dss_device *dssdev,
691 689
692 omapdss_output_unset_device(dssdev); 690 omapdss_output_unset_device(dssdev);
693 691
694 dss_mgr_disconnect(channel, dssdev); 692 dss_mgr_disconnect(&dpi->output, dssdev);
695} 693}
696 694
697static const struct omapdss_dpi_ops dpi_ops = { 695static const struct omapdss_dpi_ops dpi_ops = {
@@ -748,8 +746,8 @@ static void dpi_uninit_output_port(struct device_node *port)
748 omapdss_unregister_output(out); 746 omapdss_unregister_output(out);
749} 747}
750 748
751int dpi_init_port(struct platform_device *pdev, struct device_node *port, 749int dpi_init_port(struct dss_device *dss, struct platform_device *pdev,
752 enum dss_model dss_model) 750 struct device_node *port, enum dss_model dss_model)
753{ 751{
754 struct dpi_data *dpi; 752 struct dpi_data *dpi;
755 struct device_node *ep; 753 struct device_node *ep;
@@ -776,6 +774,7 @@ int dpi_init_port(struct platform_device *pdev, struct device_node *port,
776 774
777 dpi->pdev = pdev; 775 dpi->pdev = pdev;
778 dpi->dss_model = dss_model; 776 dpi->dss_model = dss_model;
777 dpi->dss = dss;
779 port->data = dpi; 778 port->data = dpi;
780 779
781 mutex_init(&dpi->lock); 780 mutex_init(&dpi->lock);
diff --git a/drivers/gpu/drm/omapdrm/dss/dsi.c b/drivers/gpu/drm/omapdrm/dss/dsi.c
index 80f1f3679a3c..d4a680629825 100644
--- a/drivers/gpu/drm/omapdrm/dss/dsi.c
+++ b/drivers/gpu/drm/omapdrm/dss/dsi.c
@@ -119,11 +119,11 @@ struct dsi_reg { u16 module; u16 idx; };
119#define DSI_PLL_CONFIGURATION1 DSI_REG(DSI_PLL, 0x000C) 119#define DSI_PLL_CONFIGURATION1 DSI_REG(DSI_PLL, 0x000C)
120#define DSI_PLL_CONFIGURATION2 DSI_REG(DSI_PLL, 0x0010) 120#define DSI_PLL_CONFIGURATION2 DSI_REG(DSI_PLL, 0x0010)
121 121
122#define REG_GET(dsidev, idx, start, end) \ 122#define REG_GET(dsi, idx, start, end) \
123 FLD_GET(dsi_read_reg(dsidev, idx), start, end) 123 FLD_GET(dsi_read_reg(dsi, idx), start, end)
124 124
125#define REG_FLD_MOD(dsidev, idx, val, start, end) \ 125#define REG_FLD_MOD(dsi, idx, val, start, end) \
126 dsi_write_reg(dsidev, idx, FLD_MOD(dsi_read_reg(dsidev, idx), val, start, end)) 126 dsi_write_reg(dsi, idx, FLD_MOD(dsi_read_reg(dsi, idx), val, start, end))
127 127
128/* Global interrupts */ 128/* Global interrupts */
129#define DSI_IRQ_VC0 (1 << 0) 129#define DSI_IRQ_VC0 (1 << 0)
@@ -213,13 +213,12 @@ struct dsi_reg { u16 module; u16 idx; };
213 DSI_CIO_IRQ_ERRCONTENTIONLP0_5 | DSI_CIO_IRQ_ERRCONTENTIONLP1_5) 213 DSI_CIO_IRQ_ERRCONTENTIONLP0_5 | DSI_CIO_IRQ_ERRCONTENTIONLP1_5)
214 214
215typedef void (*omap_dsi_isr_t) (void *arg, u32 mask); 215typedef void (*omap_dsi_isr_t) (void *arg, u32 mask);
216struct dsi_data;
216 217
217static int dsi_display_init_dispc(struct platform_device *dsidev, 218static int dsi_display_init_dispc(struct dsi_data *dsi);
218 enum omap_channel channel); 219static void dsi_display_uninit_dispc(struct dsi_data *dsi);
219static void dsi_display_uninit_dispc(struct platform_device *dsidev,
220 enum omap_channel channel);
221 220
222static int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel); 221static int dsi_vc_send_null(struct dsi_data *dsi, int channel);
223 222
224/* DSI PLL HSDIV indices */ 223/* DSI PLL HSDIV indices */
225#define HSDIV_DISPC 0 224#define HSDIV_DISPC 0
@@ -269,10 +268,10 @@ enum dsi_vc_source {
269 268
270struct dsi_irq_stats { 269struct dsi_irq_stats {
271 unsigned long last_reset; 270 unsigned long last_reset;
272 unsigned irq_count; 271 unsigned int irq_count;
273 unsigned dsi_irqs[32]; 272 unsigned int dsi_irqs[32];
274 unsigned vc_irqs[4][32]; 273 unsigned int vc_irqs[4][32];
275 unsigned cio_irqs[32]; 274 unsigned int cio_irqs[32];
276}; 275};
277 276
278struct dsi_isr_tables { 277struct dsi_isr_tables {
@@ -282,7 +281,7 @@ struct dsi_isr_tables {
282}; 281};
283 282
284struct dsi_clk_calc_ctx { 283struct dsi_clk_calc_ctx {
285 struct platform_device *dsidev; 284 struct dsi_data *dsi;
286 struct dss_pll *pll; 285 struct dss_pll *pll;
287 286
288 /* inputs */ 287 /* inputs */
@@ -329,7 +328,7 @@ struct dsi_of_data {
329}; 328};
330 329
331struct dsi_data { 330struct dsi_data {
332 struct platform_device *pdev; 331 struct device *dev;
333 void __iomem *proto_base; 332 void __iomem *proto_base;
334 void __iomem *phy_base; 333 void __iomem *phy_base;
335 void __iomem *pll_base; 334 void __iomem *pll_base;
@@ -343,6 +342,7 @@ struct dsi_data {
343 342
344 struct clk *dss_clk; 343 struct clk *dss_clk;
345 struct regmap *syscon; 344 struct regmap *syscon;
345 struct dss_device *dss;
346 346
347 struct dispc_clock_info user_dispc_cinfo; 347 struct dispc_clock_info user_dispc_cinfo;
348 struct dss_pll_clock_info user_dsi_cinfo; 348 struct dss_pll_clock_info user_dsi_cinfo;
@@ -373,7 +373,7 @@ struct dsi_data {
373 373
374 int update_channel; 374 int update_channel;
375#ifdef DSI_PERF_MEASURE 375#ifdef DSI_PERF_MEASURE
376 unsigned update_bytes; 376 unsigned int update_bytes;
377#endif 377#endif
378 378
379 bool te_enabled; 379 bool te_enabled;
@@ -400,19 +400,23 @@ struct dsi_data {
400#endif 400#endif
401 int debug_read; 401 int debug_read;
402 int debug_write; 402 int debug_write;
403 struct {
404 struct dss_debugfs_entry *irqs;
405 struct dss_debugfs_entry *regs;
406 } debugfs;
403 407
404#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS 408#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
405 spinlock_t irq_stats_lock; 409 spinlock_t irq_stats_lock;
406 struct dsi_irq_stats irq_stats; 410 struct dsi_irq_stats irq_stats;
407#endif 411#endif
408 412
409 unsigned num_lanes_supported; 413 unsigned int num_lanes_supported;
410 unsigned line_buffer_size; 414 unsigned int line_buffer_size;
411 415
412 struct dsi_lane_config lanes[DSI_MAX_NR_LANES]; 416 struct dsi_lane_config lanes[DSI_MAX_NR_LANES];
413 unsigned num_lanes_used; 417 unsigned int num_lanes_used;
414 418
415 unsigned scp_clk_refcount; 419 unsigned int scp_clk_refcount;
416 420
417 struct dss_lcd_mgr_config mgr_config; 421 struct dss_lcd_mgr_config mgr_config;
418 struct videomode vm; 422 struct videomode vm;
@@ -424,7 +428,7 @@ struct dsi_data {
424}; 428};
425 429
426struct dsi_packet_sent_handler_data { 430struct dsi_packet_sent_handler_data {
427 struct platform_device *dsidev; 431 struct dsi_data *dsi;
428 struct completion *completion; 432 struct completion *completion;
429}; 433};
430 434
@@ -433,17 +437,12 @@ static bool dsi_perf;
433module_param(dsi_perf, bool, 0644); 437module_param(dsi_perf, bool, 0644);
434#endif 438#endif
435 439
436static inline struct dsi_data *dsi_get_dsidrv_data(struct platform_device *dsidev) 440static inline struct dsi_data *to_dsi_data(struct omap_dss_device *dssdev)
437{ 441{
438 return dev_get_drvdata(&dsidev->dev); 442 return dev_get_drvdata(dssdev->dev);
439} 443}
440 444
441static inline struct platform_device *dsi_get_dsidev_from_dssdev(struct omap_dss_device *dssdev) 445static struct dsi_data *dsi_get_dsi_from_id(int module)
442{
443 return to_platform_device(dssdev->dev);
444}
445
446static struct platform_device *dsi_get_dsidev_from_id(int module)
447{ 446{
448 struct omap_dss_device *out; 447 struct omap_dss_device *out;
449 enum omap_dss_output_id id; 448 enum omap_dss_output_id id;
@@ -461,13 +460,12 @@ static struct platform_device *dsi_get_dsidev_from_id(int module)
461 460
462 out = omap_dss_get_output(id); 461 out = omap_dss_get_output(id);
463 462
464 return out ? to_platform_device(out->dev) : NULL; 463 return out ? to_dsi_data(out) : NULL;
465} 464}
466 465
467static inline void dsi_write_reg(struct platform_device *dsidev, 466static inline void dsi_write_reg(struct dsi_data *dsi,
468 const struct dsi_reg idx, u32 val) 467 const struct dsi_reg idx, u32 val)
469{ 468{
470 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
471 void __iomem *base; 469 void __iomem *base;
472 470
473 switch(idx.module) { 471 switch(idx.module) {
@@ -480,10 +478,8 @@ static inline void dsi_write_reg(struct platform_device *dsidev,
480 __raw_writel(val, base + idx.idx); 478 __raw_writel(val, base + idx.idx);
481} 479}
482 480
483static inline u32 dsi_read_reg(struct platform_device *dsidev, 481static inline u32 dsi_read_reg(struct dsi_data *dsi, const struct dsi_reg idx)
484 const struct dsi_reg idx)
485{ 482{
486 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
487 void __iomem *base; 483 void __iomem *base;
488 484
489 switch(idx.module) { 485 switch(idx.module) {
@@ -498,24 +494,20 @@ static inline u32 dsi_read_reg(struct platform_device *dsidev,
498 494
499static void dsi_bus_lock(struct omap_dss_device *dssdev) 495static void dsi_bus_lock(struct omap_dss_device *dssdev)
500{ 496{
501 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 497 struct dsi_data *dsi = to_dsi_data(dssdev);
502 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
503 498
504 down(&dsi->bus_lock); 499 down(&dsi->bus_lock);
505} 500}
506 501
507static void dsi_bus_unlock(struct omap_dss_device *dssdev) 502static void dsi_bus_unlock(struct omap_dss_device *dssdev)
508{ 503{
509 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 504 struct dsi_data *dsi = to_dsi_data(dssdev);
510 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
511 505
512 up(&dsi->bus_lock); 506 up(&dsi->bus_lock);
513} 507}
514 508
515static bool dsi_bus_is_locked(struct platform_device *dsidev) 509static bool dsi_bus_is_locked(struct dsi_data *dsi)
516{ 510{
517 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
518
519 return dsi->bus_lock.count == 0; 511 return dsi->bus_lock.count == 0;
520} 512}
521 513
@@ -524,8 +516,9 @@ static void dsi_completion_handler(void *data, u32 mask)
524 complete((struct completion *)data); 516 complete((struct completion *)data);
525} 517}
526 518
527static inline int wait_for_bit_change(struct platform_device *dsidev, 519static inline bool wait_for_bit_change(struct dsi_data *dsi,
528 const struct dsi_reg idx, int bitnum, int value) 520 const struct dsi_reg idx,
521 int bitnum, int value)
529{ 522{
530 unsigned long timeout; 523 unsigned long timeout;
531 ktime_t wait; 524 ktime_t wait;
@@ -534,22 +527,22 @@ static inline int wait_for_bit_change(struct platform_device *dsidev,
534 /* first busyloop to see if the bit changes right away */ 527 /* first busyloop to see if the bit changes right away */
535 t = 100; 528 t = 100;
536 while (t-- > 0) { 529 while (t-- > 0) {
537 if (REG_GET(dsidev, idx, bitnum, bitnum) == value) 530 if (REG_GET(dsi, idx, bitnum, bitnum) == value)
538 return value; 531 return true;
539 } 532 }
540 533
541 /* then loop for 500ms, sleeping for 1ms in between */ 534 /* then loop for 500ms, sleeping for 1ms in between */
542 timeout = jiffies + msecs_to_jiffies(500); 535 timeout = jiffies + msecs_to_jiffies(500);
543 while (time_before(jiffies, timeout)) { 536 while (time_before(jiffies, timeout)) {
544 if (REG_GET(dsidev, idx, bitnum, bitnum) == value) 537 if (REG_GET(dsi, idx, bitnum, bitnum) == value)
545 return value; 538 return true;
546 539
547 wait = ns_to_ktime(1000 * 1000); 540 wait = ns_to_ktime(1000 * 1000);
548 set_current_state(TASK_UNINTERRUPTIBLE); 541 set_current_state(TASK_UNINTERRUPTIBLE);
549 schedule_hrtimeout(&wait, HRTIMER_MODE_REL); 542 schedule_hrtimeout(&wait, HRTIMER_MODE_REL);
550 } 543 }
551 544
552 return !value; 545 return false;
553} 546}
554 547
555static u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt) 548static u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt)
@@ -569,21 +562,18 @@ static u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt)
569} 562}
570 563
571#ifdef DSI_PERF_MEASURE 564#ifdef DSI_PERF_MEASURE
572static void dsi_perf_mark_setup(struct platform_device *dsidev) 565static void dsi_perf_mark_setup(struct dsi_data *dsi)
573{ 566{
574 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
575 dsi->perf_setup_time = ktime_get(); 567 dsi->perf_setup_time = ktime_get();
576} 568}
577 569
578static void dsi_perf_mark_start(struct platform_device *dsidev) 570static void dsi_perf_mark_start(struct dsi_data *dsi)
579{ 571{
580 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
581 dsi->perf_start_time = ktime_get(); 572 dsi->perf_start_time = ktime_get();
582} 573}
583 574
584static void dsi_perf_show(struct platform_device *dsidev, const char *name) 575static void dsi_perf_show(struct dsi_data *dsi, const char *name)
585{ 576{
586 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
587 ktime_t t, setup_time, trans_time; 577 ktime_t t, setup_time, trans_time;
588 u32 total_bytes; 578 u32 total_bytes;
589 u32 setup_us, trans_us, total_us; 579 u32 setup_us, trans_us, total_us;
@@ -617,16 +607,15 @@ static void dsi_perf_show(struct platform_device *dsidev, const char *name)
617 total_bytes * 1000 / total_us); 607 total_bytes * 1000 / total_us);
618} 608}
619#else 609#else
620static inline void dsi_perf_mark_setup(struct platform_device *dsidev) 610static inline void dsi_perf_mark_setup(struct dsi_data *dsi)
621{ 611{
622} 612}
623 613
624static inline void dsi_perf_mark_start(struct platform_device *dsidev) 614static inline void dsi_perf_mark_start(struct dsi_data *dsi)
625{ 615{
626} 616}
627 617
628static inline void dsi_perf_show(struct platform_device *dsidev, 618static inline void dsi_perf_show(struct dsi_data *dsi, const char *name)
629 const char *name)
630{ 619{
631} 620}
632#endif 621#endif
@@ -723,10 +712,9 @@ static void print_irq_status_cio(u32 status)
723} 712}
724 713
725#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS 714#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
726static void dsi_collect_irq_stats(struct platform_device *dsidev, u32 irqstatus, 715static void dsi_collect_irq_stats(struct dsi_data *dsi, u32 irqstatus,
727 u32 *vcstatus, u32 ciostatus) 716 u32 *vcstatus, u32 ciostatus)
728{ 717{
729 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
730 int i; 718 int i;
731 719
732 spin_lock(&dsi->irq_stats_lock); 720 spin_lock(&dsi->irq_stats_lock);
@@ -742,15 +730,14 @@ static void dsi_collect_irq_stats(struct platform_device *dsidev, u32 irqstatus,
742 spin_unlock(&dsi->irq_stats_lock); 730 spin_unlock(&dsi->irq_stats_lock);
743} 731}
744#else 732#else
745#define dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus) 733#define dsi_collect_irq_stats(dsi, irqstatus, vcstatus, ciostatus)
746#endif 734#endif
747 735
748static int debug_irq; 736static int debug_irq;
749 737
750static void dsi_handle_irq_errors(struct platform_device *dsidev, u32 irqstatus, 738static void dsi_handle_irq_errors(struct dsi_data *dsi, u32 irqstatus,
751 u32 *vcstatus, u32 ciostatus) 739 u32 *vcstatus, u32 ciostatus)
752{ 740{
753 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
754 int i; 741 int i;
755 742
756 if (irqstatus & DSI_IRQ_ERROR_MASK) { 743 if (irqstatus & DSI_IRQ_ERROR_MASK) {
@@ -782,7 +769,7 @@ static void dsi_handle_irq_errors(struct platform_device *dsidev, u32 irqstatus,
782} 769}
783 770
784static void dsi_call_isrs(struct dsi_isr_data *isr_array, 771static void dsi_call_isrs(struct dsi_isr_data *isr_array,
785 unsigned isr_array_size, u32 irqstatus) 772 unsigned int isr_array_size, u32 irqstatus)
786{ 773{
787 struct dsi_isr_data *isr_data; 774 struct dsi_isr_data *isr_data;
788 int i; 775 int i;
@@ -819,20 +806,16 @@ static void dsi_handle_isrs(struct dsi_isr_tables *isr_tables,
819 806
820static irqreturn_t omap_dsi_irq_handler(int irq, void *arg) 807static irqreturn_t omap_dsi_irq_handler(int irq, void *arg)
821{ 808{
822 struct platform_device *dsidev; 809 struct dsi_data *dsi = arg;
823 struct dsi_data *dsi;
824 u32 irqstatus, vcstatus[4], ciostatus; 810 u32 irqstatus, vcstatus[4], ciostatus;
825 int i; 811 int i;
826 812
827 dsidev = (struct platform_device *) arg;
828 dsi = dsi_get_dsidrv_data(dsidev);
829
830 if (!dsi->is_enabled) 813 if (!dsi->is_enabled)
831 return IRQ_NONE; 814 return IRQ_NONE;
832 815
833 spin_lock(&dsi->irq_lock); 816 spin_lock(&dsi->irq_lock);
834 817
835 irqstatus = dsi_read_reg(dsidev, DSI_IRQSTATUS); 818 irqstatus = dsi_read_reg(dsi, DSI_IRQSTATUS);
836 819
837 /* IRQ is not for us */ 820 /* IRQ is not for us */
838 if (!irqstatus) { 821 if (!irqstatus) {
@@ -840,9 +823,9 @@ static irqreturn_t omap_dsi_irq_handler(int irq, void *arg)
840 return IRQ_NONE; 823 return IRQ_NONE;
841 } 824 }
842 825
843 dsi_write_reg(dsidev, DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK); 826 dsi_write_reg(dsi, DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK);
844 /* flush posted write */ 827 /* flush posted write */
845 dsi_read_reg(dsidev, DSI_IRQSTATUS); 828 dsi_read_reg(dsi, DSI_IRQSTATUS);
846 829
847 for (i = 0; i < 4; ++i) { 830 for (i = 0; i < 4; ++i) {
848 if ((irqstatus & (1 << i)) == 0) { 831 if ((irqstatus & (1 << i)) == 0) {
@@ -850,19 +833,19 @@ static irqreturn_t omap_dsi_irq_handler(int irq, void *arg)
850 continue; 833 continue;
851 } 834 }
852 835
853 vcstatus[i] = dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i)); 836 vcstatus[i] = dsi_read_reg(dsi, DSI_VC_IRQSTATUS(i));
854 837
855 dsi_write_reg(dsidev, DSI_VC_IRQSTATUS(i), vcstatus[i]); 838 dsi_write_reg(dsi, DSI_VC_IRQSTATUS(i), vcstatus[i]);
856 /* flush posted write */ 839 /* flush posted write */
857 dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i)); 840 dsi_read_reg(dsi, DSI_VC_IRQSTATUS(i));
858 } 841 }
859 842
860 if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) { 843 if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) {
861 ciostatus = dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS); 844 ciostatus = dsi_read_reg(dsi, DSI_COMPLEXIO_IRQ_STATUS);
862 845
863 dsi_write_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS, ciostatus); 846 dsi_write_reg(dsi, DSI_COMPLEXIO_IRQ_STATUS, ciostatus);
864 /* flush posted write */ 847 /* flush posted write */
865 dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS); 848 dsi_read_reg(dsi, DSI_COMPLEXIO_IRQ_STATUS);
866 } else { 849 } else {
867 ciostatus = 0; 850 ciostatus = 0;
868 } 851 }
@@ -881,19 +864,20 @@ static irqreturn_t omap_dsi_irq_handler(int irq, void *arg)
881 864
882 dsi_handle_isrs(&dsi->isr_tables_copy, irqstatus, vcstatus, ciostatus); 865 dsi_handle_isrs(&dsi->isr_tables_copy, irqstatus, vcstatus, ciostatus);
883 866
884 dsi_handle_irq_errors(dsidev, irqstatus, vcstatus, ciostatus); 867 dsi_handle_irq_errors(dsi, irqstatus, vcstatus, ciostatus);
885 868
886 dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus); 869 dsi_collect_irq_stats(dsi, irqstatus, vcstatus, ciostatus);
887 870
888 return IRQ_HANDLED; 871 return IRQ_HANDLED;
889} 872}
890 873
891/* dsi->irq_lock has to be locked by the caller */ 874/* dsi->irq_lock has to be locked by the caller */
892static void _omap_dsi_configure_irqs(struct platform_device *dsidev, 875static void _omap_dsi_configure_irqs(struct dsi_data *dsi,
893 struct dsi_isr_data *isr_array, 876 struct dsi_isr_data *isr_array,
894 unsigned isr_array_size, u32 default_mask, 877 unsigned int isr_array_size,
895 const struct dsi_reg enable_reg, 878 u32 default_mask,
896 const struct dsi_reg status_reg) 879 const struct dsi_reg enable_reg,
880 const struct dsi_reg status_reg)
897{ 881{
898 struct dsi_isr_data *isr_data; 882 struct dsi_isr_data *isr_data;
899 u32 mask; 883 u32 mask;
@@ -911,54 +895,48 @@ static void _omap_dsi_configure_irqs(struct platform_device *dsidev,
911 mask |= isr_data->mask; 895 mask |= isr_data->mask;
912 } 896 }
913 897
914 old_mask = dsi_read_reg(dsidev, enable_reg); 898 old_mask = dsi_read_reg(dsi, enable_reg);
915 /* clear the irqstatus for newly enabled irqs */ 899 /* clear the irqstatus for newly enabled irqs */
916 dsi_write_reg(dsidev, status_reg, (mask ^ old_mask) & mask); 900 dsi_write_reg(dsi, status_reg, (mask ^ old_mask) & mask);
917 dsi_write_reg(dsidev, enable_reg, mask); 901 dsi_write_reg(dsi, enable_reg, mask);
918 902
919 /* flush posted writes */ 903 /* flush posted writes */
920 dsi_read_reg(dsidev, enable_reg); 904 dsi_read_reg(dsi, enable_reg);
921 dsi_read_reg(dsidev, status_reg); 905 dsi_read_reg(dsi, status_reg);
922} 906}
923 907
924/* dsi->irq_lock has to be locked by the caller */ 908/* dsi->irq_lock has to be locked by the caller */
925static void _omap_dsi_set_irqs(struct platform_device *dsidev) 909static void _omap_dsi_set_irqs(struct dsi_data *dsi)
926{ 910{
927 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
928 u32 mask = DSI_IRQ_ERROR_MASK; 911 u32 mask = DSI_IRQ_ERROR_MASK;
929#ifdef DSI_CATCH_MISSING_TE 912#ifdef DSI_CATCH_MISSING_TE
930 mask |= DSI_IRQ_TE_TRIGGER; 913 mask |= DSI_IRQ_TE_TRIGGER;
931#endif 914#endif
932 _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table, 915 _omap_dsi_configure_irqs(dsi, dsi->isr_tables.isr_table,
933 ARRAY_SIZE(dsi->isr_tables.isr_table), mask, 916 ARRAY_SIZE(dsi->isr_tables.isr_table), mask,
934 DSI_IRQENABLE, DSI_IRQSTATUS); 917 DSI_IRQENABLE, DSI_IRQSTATUS);
935} 918}
936 919
937/* dsi->irq_lock has to be locked by the caller */ 920/* dsi->irq_lock has to be locked by the caller */
938static void _omap_dsi_set_irqs_vc(struct platform_device *dsidev, int vc) 921static void _omap_dsi_set_irqs_vc(struct dsi_data *dsi, int vc)
939{ 922{
940 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 923 _omap_dsi_configure_irqs(dsi, dsi->isr_tables.isr_table_vc[vc],
941
942 _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_vc[vc],
943 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[vc]), 924 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[vc]),
944 DSI_VC_IRQ_ERROR_MASK, 925 DSI_VC_IRQ_ERROR_MASK,
945 DSI_VC_IRQENABLE(vc), DSI_VC_IRQSTATUS(vc)); 926 DSI_VC_IRQENABLE(vc), DSI_VC_IRQSTATUS(vc));
946} 927}
947 928
948/* dsi->irq_lock has to be locked by the caller */ 929/* dsi->irq_lock has to be locked by the caller */
949static void _omap_dsi_set_irqs_cio(struct platform_device *dsidev) 930static void _omap_dsi_set_irqs_cio(struct dsi_data *dsi)
950{ 931{
951 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 932 _omap_dsi_configure_irqs(dsi, dsi->isr_tables.isr_table_cio,
952
953 _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_cio,
954 ARRAY_SIZE(dsi->isr_tables.isr_table_cio), 933 ARRAY_SIZE(dsi->isr_tables.isr_table_cio),
955 DSI_CIO_IRQ_ERROR_MASK, 934 DSI_CIO_IRQ_ERROR_MASK,
956 DSI_COMPLEXIO_IRQ_ENABLE, DSI_COMPLEXIO_IRQ_STATUS); 935 DSI_COMPLEXIO_IRQ_ENABLE, DSI_COMPLEXIO_IRQ_STATUS);
957} 936}
958 937
959static void _dsi_initialize_irq(struct platform_device *dsidev) 938static void _dsi_initialize_irq(struct dsi_data *dsi)
960{ 939{
961 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
962 unsigned long flags; 940 unsigned long flags;
963 int vc; 941 int vc;
964 942
@@ -966,16 +944,16 @@ static void _dsi_initialize_irq(struct platform_device *dsidev)
966 944
967 memset(&dsi->isr_tables, 0, sizeof(dsi->isr_tables)); 945 memset(&dsi->isr_tables, 0, sizeof(dsi->isr_tables));
968 946
969 _omap_dsi_set_irqs(dsidev); 947 _omap_dsi_set_irqs(dsi);
970 for (vc = 0; vc < 4; ++vc) 948 for (vc = 0; vc < 4; ++vc)
971 _omap_dsi_set_irqs_vc(dsidev, vc); 949 _omap_dsi_set_irqs_vc(dsi, vc);
972 _omap_dsi_set_irqs_cio(dsidev); 950 _omap_dsi_set_irqs_cio(dsi);
973 951
974 spin_unlock_irqrestore(&dsi->irq_lock, flags); 952 spin_unlock_irqrestore(&dsi->irq_lock, flags);
975} 953}
976 954
977static int _dsi_register_isr(omap_dsi_isr_t isr, void *arg, u32 mask, 955static int _dsi_register_isr(omap_dsi_isr_t isr, void *arg, u32 mask,
978 struct dsi_isr_data *isr_array, unsigned isr_array_size) 956 struct dsi_isr_data *isr_array, unsigned int isr_array_size)
979{ 957{
980 struct dsi_isr_data *isr_data; 958 struct dsi_isr_data *isr_data;
981 int free_idx; 959 int free_idx;
@@ -1009,7 +987,7 @@ static int _dsi_register_isr(omap_dsi_isr_t isr, void *arg, u32 mask,
1009} 987}
1010 988
1011static int _dsi_unregister_isr(omap_dsi_isr_t isr, void *arg, u32 mask, 989static int _dsi_unregister_isr(omap_dsi_isr_t isr, void *arg, u32 mask,
1012 struct dsi_isr_data *isr_array, unsigned isr_array_size) 990 struct dsi_isr_data *isr_array, unsigned int isr_array_size)
1013{ 991{
1014 struct dsi_isr_data *isr_data; 992 struct dsi_isr_data *isr_data;
1015 int i; 993 int i;
@@ -1030,10 +1008,9 @@ static int _dsi_unregister_isr(omap_dsi_isr_t isr, void *arg, u32 mask,
1030 return -EINVAL; 1008 return -EINVAL;
1031} 1009}
1032 1010
1033static int dsi_register_isr(struct platform_device *dsidev, omap_dsi_isr_t isr, 1011static int dsi_register_isr(struct dsi_data *dsi, omap_dsi_isr_t isr,
1034 void *arg, u32 mask) 1012 void *arg, u32 mask)
1035{ 1013{
1036 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1037 unsigned long flags; 1014 unsigned long flags;
1038 int r; 1015 int r;
1039 1016
@@ -1043,17 +1020,16 @@ static int dsi_register_isr(struct platform_device *dsidev, omap_dsi_isr_t isr,
1043 ARRAY_SIZE(dsi->isr_tables.isr_table)); 1020 ARRAY_SIZE(dsi->isr_tables.isr_table));
1044 1021
1045 if (r == 0) 1022 if (r == 0)
1046 _omap_dsi_set_irqs(dsidev); 1023 _omap_dsi_set_irqs(dsi);
1047 1024
1048 spin_unlock_irqrestore(&dsi->irq_lock, flags); 1025 spin_unlock_irqrestore(&dsi->irq_lock, flags);
1049 1026
1050 return r; 1027 return r;
1051} 1028}
1052 1029
1053static int dsi_unregister_isr(struct platform_device *dsidev, 1030static int dsi_unregister_isr(struct dsi_data *dsi, omap_dsi_isr_t isr,
1054 omap_dsi_isr_t isr, void *arg, u32 mask) 1031 void *arg, u32 mask)
1055{ 1032{
1056 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1057 unsigned long flags; 1033 unsigned long flags;
1058 int r; 1034 int r;
1059 1035
@@ -1063,17 +1039,16 @@ static int dsi_unregister_isr(struct platform_device *dsidev,
1063 ARRAY_SIZE(dsi->isr_tables.isr_table)); 1039 ARRAY_SIZE(dsi->isr_tables.isr_table));
1064 1040
1065 if (r == 0) 1041 if (r == 0)
1066 _omap_dsi_set_irqs(dsidev); 1042 _omap_dsi_set_irqs(dsi);
1067 1043
1068 spin_unlock_irqrestore(&dsi->irq_lock, flags); 1044 spin_unlock_irqrestore(&dsi->irq_lock, flags);
1069 1045
1070 return r; 1046 return r;
1071} 1047}
1072 1048
1073static int dsi_register_isr_vc(struct platform_device *dsidev, int channel, 1049static int dsi_register_isr_vc(struct dsi_data *dsi, int channel,
1074 omap_dsi_isr_t isr, void *arg, u32 mask) 1050 omap_dsi_isr_t isr, void *arg, u32 mask)
1075{ 1051{
1076 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1077 unsigned long flags; 1052 unsigned long flags;
1078 int r; 1053 int r;
1079 1054
@@ -1084,17 +1059,16 @@ static int dsi_register_isr_vc(struct platform_device *dsidev, int channel,
1084 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel])); 1059 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel]));
1085 1060
1086 if (r == 0) 1061 if (r == 0)
1087 _omap_dsi_set_irqs_vc(dsidev, channel); 1062 _omap_dsi_set_irqs_vc(dsi, channel);
1088 1063
1089 spin_unlock_irqrestore(&dsi->irq_lock, flags); 1064 spin_unlock_irqrestore(&dsi->irq_lock, flags);
1090 1065
1091 return r; 1066 return r;
1092} 1067}
1093 1068
1094static int dsi_unregister_isr_vc(struct platform_device *dsidev, int channel, 1069static int dsi_unregister_isr_vc(struct dsi_data *dsi, int channel,
1095 omap_dsi_isr_t isr, void *arg, u32 mask) 1070 omap_dsi_isr_t isr, void *arg, u32 mask)
1096{ 1071{
1097 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1098 unsigned long flags; 1072 unsigned long flags;
1099 int r; 1073 int r;
1100 1074
@@ -1105,17 +1079,16 @@ static int dsi_unregister_isr_vc(struct platform_device *dsidev, int channel,
1105 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel])); 1079 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel]));
1106 1080
1107 if (r == 0) 1081 if (r == 0)
1108 _omap_dsi_set_irqs_vc(dsidev, channel); 1082 _omap_dsi_set_irqs_vc(dsi, channel);
1109 1083
1110 spin_unlock_irqrestore(&dsi->irq_lock, flags); 1084 spin_unlock_irqrestore(&dsi->irq_lock, flags);
1111 1085
1112 return r; 1086 return r;
1113} 1087}
1114 1088
1115static int dsi_register_isr_cio(struct platform_device *dsidev, 1089static int dsi_register_isr_cio(struct dsi_data *dsi, omap_dsi_isr_t isr,
1116 omap_dsi_isr_t isr, void *arg, u32 mask) 1090 void *arg, u32 mask)
1117{ 1091{
1118 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1119 unsigned long flags; 1092 unsigned long flags;
1120 int r; 1093 int r;
1121 1094
@@ -1125,17 +1098,16 @@ static int dsi_register_isr_cio(struct platform_device *dsidev,
1125 ARRAY_SIZE(dsi->isr_tables.isr_table_cio)); 1098 ARRAY_SIZE(dsi->isr_tables.isr_table_cio));
1126 1099
1127 if (r == 0) 1100 if (r == 0)
1128 _omap_dsi_set_irqs_cio(dsidev); 1101 _omap_dsi_set_irqs_cio(dsi);
1129 1102
1130 spin_unlock_irqrestore(&dsi->irq_lock, flags); 1103 spin_unlock_irqrestore(&dsi->irq_lock, flags);
1131 1104
1132 return r; 1105 return r;
1133} 1106}
1134 1107
1135static int dsi_unregister_isr_cio(struct platform_device *dsidev, 1108static int dsi_unregister_isr_cio(struct dsi_data *dsi, omap_dsi_isr_t isr,
1136 omap_dsi_isr_t isr, void *arg, u32 mask) 1109 void *arg, u32 mask)
1137{ 1110{
1138 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1139 unsigned long flags; 1111 unsigned long flags;
1140 int r; 1112 int r;
1141 1113
@@ -1145,18 +1117,18 @@ static int dsi_unregister_isr_cio(struct platform_device *dsidev,
1145 ARRAY_SIZE(dsi->isr_tables.isr_table_cio)); 1117 ARRAY_SIZE(dsi->isr_tables.isr_table_cio));
1146 1118
1147 if (r == 0) 1119 if (r == 0)
1148 _omap_dsi_set_irqs_cio(dsidev); 1120 _omap_dsi_set_irqs_cio(dsi);
1149 1121
1150 spin_unlock_irqrestore(&dsi->irq_lock, flags); 1122 spin_unlock_irqrestore(&dsi->irq_lock, flags);
1151 1123
1152 return r; 1124 return r;
1153} 1125}
1154 1126
1155static u32 dsi_get_errors(struct platform_device *dsidev) 1127static u32 dsi_get_errors(struct dsi_data *dsi)
1156{ 1128{
1157 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1158 unsigned long flags; 1129 unsigned long flags;
1159 u32 e; 1130 u32 e;
1131
1160 spin_lock_irqsave(&dsi->errors_lock, flags); 1132 spin_lock_irqsave(&dsi->errors_lock, flags);
1161 e = dsi->errors; 1133 e = dsi->errors;
1162 dsi->errors = 0; 1134 dsi->errors = 0;
@@ -1164,38 +1136,35 @@ static u32 dsi_get_errors(struct platform_device *dsidev)
1164 return e; 1136 return e;
1165} 1137}
1166 1138
1167static int dsi_runtime_get(struct platform_device *dsidev) 1139static int dsi_runtime_get(struct dsi_data *dsi)
1168{ 1140{
1169 int r; 1141 int r;
1170 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1171 1142
1172 DSSDBG("dsi_runtime_get\n"); 1143 DSSDBG("dsi_runtime_get\n");
1173 1144
1174 r = pm_runtime_get_sync(&dsi->pdev->dev); 1145 r = pm_runtime_get_sync(dsi->dev);
1175 WARN_ON(r < 0); 1146 WARN_ON(r < 0);
1176 return r < 0 ? r : 0; 1147 return r < 0 ? r : 0;
1177} 1148}
1178 1149
1179static void dsi_runtime_put(struct platform_device *dsidev) 1150static void dsi_runtime_put(struct dsi_data *dsi)
1180{ 1151{
1181 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1182 int r; 1152 int r;
1183 1153
1184 DSSDBG("dsi_runtime_put\n"); 1154 DSSDBG("dsi_runtime_put\n");
1185 1155
1186 r = pm_runtime_put_sync(&dsi->pdev->dev); 1156 r = pm_runtime_put_sync(dsi->dev);
1187 WARN_ON(r < 0 && r != -ENOSYS); 1157 WARN_ON(r < 0 && r != -ENOSYS);
1188} 1158}
1189 1159
1190static int dsi_regulator_init(struct platform_device *dsidev) 1160static int dsi_regulator_init(struct dsi_data *dsi)
1191{ 1161{
1192 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1193 struct regulator *vdds_dsi; 1162 struct regulator *vdds_dsi;
1194 1163
1195 if (dsi->vdds_dsi_reg != NULL) 1164 if (dsi->vdds_dsi_reg != NULL)
1196 return 0; 1165 return 0;
1197 1166
1198 vdds_dsi = devm_regulator_get(&dsi->pdev->dev, "vdd"); 1167 vdds_dsi = devm_regulator_get(dsi->dev, "vdd");
1199 1168
1200 if (IS_ERR(vdds_dsi)) { 1169 if (IS_ERR(vdds_dsi)) {
1201 if (PTR_ERR(vdds_dsi) != -EPROBE_DEFER) 1170 if (PTR_ERR(vdds_dsi) != -EPROBE_DEFER)
@@ -1208,16 +1177,15 @@ static int dsi_regulator_init(struct platform_device *dsidev)
1208 return 0; 1177 return 0;
1209} 1178}
1210 1179
1211static void _dsi_print_reset_status(struct platform_device *dsidev) 1180static void _dsi_print_reset_status(struct dsi_data *dsi)
1212{ 1181{
1213 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1214 u32 l; 1182 u32 l;
1215 int b0, b1, b2; 1183 int b0, b1, b2;
1216 1184
1217 /* A dummy read using the SCP interface to any DSIPHY register is 1185 /* A dummy read using the SCP interface to any DSIPHY register is
1218 * required after DSIPHY reset to complete the reset of the DSI complex 1186 * required after DSIPHY reset to complete the reset of the DSI complex
1219 * I/O. */ 1187 * I/O. */
1220 l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5); 1188 l = dsi_read_reg(dsi, DSI_DSIPHY_CFG5);
1221 1189
1222 if (dsi->data->quirks & DSI_QUIRK_REVERSE_TXCLKESC) { 1190 if (dsi->data->quirks & DSI_QUIRK_REVERSE_TXCLKESC) {
1223 b0 = 28; 1191 b0 = 28;
@@ -1230,7 +1198,7 @@ static void _dsi_print_reset_status(struct platform_device *dsidev)
1230 } 1198 }
1231 1199
1232#define DSI_FLD_GET(fld, start, end)\ 1200#define DSI_FLD_GET(fld, start, end)\
1233 FLD_GET(dsi_read_reg(dsidev, DSI_##fld), start, end) 1201 FLD_GET(dsi_read_reg(dsi, DSI_##fld), start, end)
1234 1202
1235 pr_debug("DSI resets: PLL (%d) CIO (%d) PHY (%x%x%x, %d, %d, %d)\n", 1203 pr_debug("DSI resets: PLL (%d) CIO (%d) PHY (%x%x%x, %d, %d, %d)\n",
1236 DSI_FLD_GET(PLL_STATUS, 0, 0), 1204 DSI_FLD_GET(PLL_STATUS, 0, 0),
@@ -1245,53 +1213,48 @@ static void _dsi_print_reset_status(struct platform_device *dsidev)
1245#undef DSI_FLD_GET 1213#undef DSI_FLD_GET
1246} 1214}
1247 1215
1248static inline int dsi_if_enable(struct platform_device *dsidev, bool enable) 1216static inline int dsi_if_enable(struct dsi_data *dsi, bool enable)
1249{ 1217{
1250 DSSDBG("dsi_if_enable(%d)\n", enable); 1218 DSSDBG("dsi_if_enable(%d)\n", enable);
1251 1219
1252 enable = enable ? 1 : 0; 1220 enable = enable ? 1 : 0;
1253 REG_FLD_MOD(dsidev, DSI_CTRL, enable, 0, 0); /* IF_EN */ 1221 REG_FLD_MOD(dsi, DSI_CTRL, enable, 0, 0); /* IF_EN */
1254 1222
1255 if (wait_for_bit_change(dsidev, DSI_CTRL, 0, enable) != enable) { 1223 if (!wait_for_bit_change(dsi, DSI_CTRL, 0, enable)) {
1256 DSSERR("Failed to set dsi_if_enable to %d\n", enable); 1224 DSSERR("Failed to set dsi_if_enable to %d\n", enable);
1257 return -EIO; 1225 return -EIO;
1258 } 1226 }
1259 1227
1260 return 0; 1228 return 0;
1261} 1229}
1262 1230
1263static unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev) 1231static unsigned long dsi_get_pll_hsdiv_dispc_rate(struct dsi_data *dsi)
1264{ 1232{
1265 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1266
1267 return dsi->pll.cinfo.clkout[HSDIV_DISPC]; 1233 return dsi->pll.cinfo.clkout[HSDIV_DISPC];
1268} 1234}
1269 1235
1270static unsigned long dsi_get_pll_hsdiv_dsi_rate(struct platform_device *dsidev) 1236static unsigned long dsi_get_pll_hsdiv_dsi_rate(struct dsi_data *dsi)
1271{ 1237{
1272 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1273
1274 return dsi->pll.cinfo.clkout[HSDIV_DSI]; 1238 return dsi->pll.cinfo.clkout[HSDIV_DSI];
1275} 1239}
1276 1240
1277static unsigned long dsi_get_txbyteclkhs(struct platform_device *dsidev) 1241static unsigned long dsi_get_txbyteclkhs(struct dsi_data *dsi)
1278{ 1242{
1279 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1280
1281 return dsi->pll.cinfo.clkdco / 16; 1243 return dsi->pll.cinfo.clkdco / 16;
1282} 1244}
1283 1245
1284static unsigned long dsi_fclk_rate(struct platform_device *dsidev) 1246static unsigned long dsi_fclk_rate(struct dsi_data *dsi)
1285{ 1247{
1286 unsigned long r; 1248 unsigned long r;
1287 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1249 enum dss_clk_source source;
1288 1250
1289 if (dss_get_dsi_clk_source(dsi->module_id) == DSS_CLK_SRC_FCK) { 1251 source = dss_get_dsi_clk_source(dsi->dss, dsi->module_id);
1252 if (source == DSS_CLK_SRC_FCK) {
1290 /* DSI FCLK source is DSS_CLK_FCK */ 1253 /* DSI FCLK source is DSS_CLK_FCK */
1291 r = clk_get_rate(dsi->dss_clk); 1254 r = clk_get_rate(dsi->dss_clk);
1292 } else { 1255 } else {
1293 /* DSI FCLK source is dsi_pll_hsdiv_dsi_clk */ 1256 /* DSI FCLK source is dsi_pll_hsdiv_dsi_clk */
1294 r = dsi_get_pll_hsdiv_dsi_rate(dsidev); 1257 r = dsi_get_pll_hsdiv_dsi_rate(dsi);
1295 } 1258 }
1296 1259
1297 return r; 1260 return r;
@@ -1301,7 +1264,7 @@ static int dsi_lp_clock_calc(unsigned long dsi_fclk,
1301 unsigned long lp_clk_min, unsigned long lp_clk_max, 1264 unsigned long lp_clk_min, unsigned long lp_clk_max,
1302 struct dsi_lp_clock_info *lp_cinfo) 1265 struct dsi_lp_clock_info *lp_cinfo)
1303{ 1266{
1304 unsigned lp_clk_div; 1267 unsigned int lp_clk_div;
1305 unsigned long lp_clk; 1268 unsigned long lp_clk;
1306 1269
1307 lp_clk_div = DIV_ROUND_UP(dsi_fclk, lp_clk_max * 2); 1270 lp_clk_div = DIV_ROUND_UP(dsi_fclk, lp_clk_max * 2);
@@ -1316,13 +1279,12 @@ static int dsi_lp_clock_calc(unsigned long dsi_fclk,
1316 return 0; 1279 return 0;
1317} 1280}
1318 1281
1319static int dsi_set_lp_clk_divisor(struct platform_device *dsidev) 1282static int dsi_set_lp_clk_divisor(struct dsi_data *dsi)
1320{ 1283{
1321 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1322 unsigned long dsi_fclk; 1284 unsigned long dsi_fclk;
1323 unsigned lp_clk_div; 1285 unsigned int lp_clk_div;
1324 unsigned long lp_clk; 1286 unsigned long lp_clk;
1325 unsigned lpdiv_max = dsi->data->max_pll_lpdiv; 1287 unsigned int lpdiv_max = dsi->data->max_pll_lpdiv;
1326 1288
1327 1289
1328 lp_clk_div = dsi->user_lp_cinfo.lp_clk_div; 1290 lp_clk_div = dsi->user_lp_cinfo.lp_clk_div;
@@ -1330,7 +1292,7 @@ static int dsi_set_lp_clk_divisor(struct platform_device *dsidev)
1330 if (lp_clk_div == 0 || lp_clk_div > lpdiv_max) 1292 if (lp_clk_div == 0 || lp_clk_div > lpdiv_max)
1331 return -EINVAL; 1293 return -EINVAL;
1332 1294
1333 dsi_fclk = dsi_fclk_rate(dsidev); 1295 dsi_fclk = dsi_fclk_rate(dsi);
1334 1296
1335 lp_clk = dsi_fclk / 2 / lp_clk_div; 1297 lp_clk = dsi_fclk / 2 / lp_clk_div;
1336 1298
@@ -1339,29 +1301,25 @@ static int dsi_set_lp_clk_divisor(struct platform_device *dsidev)
1339 dsi->current_lp_cinfo.lp_clk_div = lp_clk_div; 1301 dsi->current_lp_cinfo.lp_clk_div = lp_clk_div;
1340 1302
1341 /* LP_CLK_DIVISOR */ 1303 /* LP_CLK_DIVISOR */
1342 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, lp_clk_div, 12, 0); 1304 REG_FLD_MOD(dsi, DSI_CLK_CTRL, lp_clk_div, 12, 0);
1343 1305
1344 /* LP_RX_SYNCHRO_ENABLE */ 1306 /* LP_RX_SYNCHRO_ENABLE */
1345 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0, 21, 21); 1307 REG_FLD_MOD(dsi, DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0, 21, 21);
1346 1308
1347 return 0; 1309 return 0;
1348} 1310}
1349 1311
1350static void dsi_enable_scp_clk(struct platform_device *dsidev) 1312static void dsi_enable_scp_clk(struct dsi_data *dsi)
1351{ 1313{
1352 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1353
1354 if (dsi->scp_clk_refcount++ == 0) 1314 if (dsi->scp_clk_refcount++ == 0)
1355 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 14, 14); /* CIO_CLK_ICG */ 1315 REG_FLD_MOD(dsi, DSI_CLK_CTRL, 1, 14, 14); /* CIO_CLK_ICG */
1356} 1316}
1357 1317
1358static void dsi_disable_scp_clk(struct platform_device *dsidev) 1318static void dsi_disable_scp_clk(struct dsi_data *dsi)
1359{ 1319{
1360 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1361
1362 WARN_ON(dsi->scp_clk_refcount == 0); 1320 WARN_ON(dsi->scp_clk_refcount == 0);
1363 if (--dsi->scp_clk_refcount == 0) 1321 if (--dsi->scp_clk_refcount == 0)
1364 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 14, 14); /* CIO_CLK_ICG */ 1322 REG_FLD_MOD(dsi, DSI_CLK_CTRL, 0, 14, 14); /* CIO_CLK_ICG */
1365} 1323}
1366 1324
1367enum dsi_pll_power_state { 1325enum dsi_pll_power_state {
@@ -1371,10 +1329,8 @@ enum dsi_pll_power_state {
1371 DSI_PLL_POWER_ON_DIV = 0x3, 1329 DSI_PLL_POWER_ON_DIV = 0x3,
1372}; 1330};
1373 1331
1374static int dsi_pll_power(struct platform_device *dsidev, 1332static int dsi_pll_power(struct dsi_data *dsi, enum dsi_pll_power_state state)
1375 enum dsi_pll_power_state state)
1376{ 1333{
1377 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1378 int t = 0; 1334 int t = 0;
1379 1335
1380 /* DSI-PLL power command 0x3 is not working */ 1336 /* DSI-PLL power command 0x3 is not working */
@@ -1383,10 +1339,10 @@ static int dsi_pll_power(struct platform_device *dsidev,
1383 state = DSI_PLL_POWER_ON_ALL; 1339 state = DSI_PLL_POWER_ON_ALL;
1384 1340
1385 /* PLL_PWR_CMD */ 1341 /* PLL_PWR_CMD */
1386 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, state, 31, 30); 1342 REG_FLD_MOD(dsi, DSI_CLK_CTRL, state, 31, 30);
1387 1343
1388 /* PLL_PWR_STATUS */ 1344 /* PLL_PWR_STATUS */
1389 while (FLD_GET(dsi_read_reg(dsidev, DSI_CLK_CTRL), 29, 28) != state) { 1345 while (FLD_GET(dsi_read_reg(dsi, DSI_CLK_CTRL), 29, 28) != state) {
1390 if (++t > 1000) { 1346 if (++t > 1000) {
1391 DSSERR("Failed to set DSI PLL power mode to %d\n", 1347 DSSERR("Failed to set DSI PLL power mode to %d\n",
1392 state); 1348 state);
@@ -1413,23 +1369,22 @@ static void dsi_pll_calc_dsi_fck(struct dsi_data *dsi,
1413static int dsi_pll_enable(struct dss_pll *pll) 1369static int dsi_pll_enable(struct dss_pll *pll)
1414{ 1370{
1415 struct dsi_data *dsi = container_of(pll, struct dsi_data, pll); 1371 struct dsi_data *dsi = container_of(pll, struct dsi_data, pll);
1416 struct platform_device *dsidev = dsi->pdev;
1417 int r = 0; 1372 int r = 0;
1418 1373
1419 DSSDBG("PLL init\n"); 1374 DSSDBG("PLL init\n");
1420 1375
1421 r = dsi_regulator_init(dsidev); 1376 r = dsi_regulator_init(dsi);
1422 if (r) 1377 if (r)
1423 return r; 1378 return r;
1424 1379
1425 r = dsi_runtime_get(dsidev); 1380 r = dsi_runtime_get(dsi);
1426 if (r) 1381 if (r)
1427 return r; 1382 return r;
1428 1383
1429 /* 1384 /*
1430 * Note: SCP CLK is not required on OMAP3, but it is required on OMAP4. 1385 * Note: SCP CLK is not required on OMAP3, but it is required on OMAP4.
1431 */ 1386 */
1432 dsi_enable_scp_clk(dsidev); 1387 dsi_enable_scp_clk(dsi);
1433 1388
1434 if (!dsi->vdds_dsi_enabled) { 1389 if (!dsi->vdds_dsi_enabled) {
1435 r = regulator_enable(dsi->vdds_dsi_reg); 1390 r = regulator_enable(dsi->vdds_dsi_reg);
@@ -1439,20 +1394,20 @@ static int dsi_pll_enable(struct dss_pll *pll)
1439 } 1394 }
1440 1395
1441 /* XXX PLL does not come out of reset without this... */ 1396 /* XXX PLL does not come out of reset without this... */
1442 dispc_pck_free_enable(1); 1397 dispc_pck_free_enable(dsi->dss->dispc, 1);
1443 1398
1444 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 0, 1) != 1) { 1399 if (!wait_for_bit_change(dsi, DSI_PLL_STATUS, 0, 1)) {
1445 DSSERR("PLL not coming out of reset.\n"); 1400 DSSERR("PLL not coming out of reset.\n");
1446 r = -ENODEV; 1401 r = -ENODEV;
1447 dispc_pck_free_enable(0); 1402 dispc_pck_free_enable(dsi->dss->dispc, 0);
1448 goto err1; 1403 goto err1;
1449 } 1404 }
1450 1405
1451 /* XXX ... but if left on, we get problems when planes do not 1406 /* XXX ... but if left on, we get problems when planes do not
1452 * fill the whole display. No idea about this */ 1407 * fill the whole display. No idea about this */
1453 dispc_pck_free_enable(0); 1408 dispc_pck_free_enable(dsi->dss->dispc, 0);
1454 1409
1455 r = dsi_pll_power(dsidev, DSI_PLL_POWER_ON_ALL); 1410 r = dsi_pll_power(dsi, DSI_PLL_POWER_ON_ALL);
1456 1411
1457 if (r) 1412 if (r)
1458 goto err1; 1413 goto err1;
@@ -1466,24 +1421,22 @@ err1:
1466 dsi->vdds_dsi_enabled = false; 1421 dsi->vdds_dsi_enabled = false;
1467 } 1422 }
1468err0: 1423err0:
1469 dsi_disable_scp_clk(dsidev); 1424 dsi_disable_scp_clk(dsi);
1470 dsi_runtime_put(dsidev); 1425 dsi_runtime_put(dsi);
1471 return r; 1426 return r;
1472} 1427}
1473 1428
1474static void dsi_pll_uninit(struct platform_device *dsidev, bool disconnect_lanes) 1429static void dsi_pll_uninit(struct dsi_data *dsi, bool disconnect_lanes)
1475{ 1430{
1476 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1431 dsi_pll_power(dsi, DSI_PLL_POWER_OFF);
1477
1478 dsi_pll_power(dsidev, DSI_PLL_POWER_OFF);
1479 if (disconnect_lanes) { 1432 if (disconnect_lanes) {
1480 WARN_ON(!dsi->vdds_dsi_enabled); 1433 WARN_ON(!dsi->vdds_dsi_enabled);
1481 regulator_disable(dsi->vdds_dsi_reg); 1434 regulator_disable(dsi->vdds_dsi_reg);
1482 dsi->vdds_dsi_enabled = false; 1435 dsi->vdds_dsi_enabled = false;
1483 } 1436 }
1484 1437
1485 dsi_disable_scp_clk(dsidev); 1438 dsi_disable_scp_clk(dsi);
1486 dsi_runtime_put(dsidev); 1439 dsi_runtime_put(dsi);
1487 1440
1488 DSSDBG("PLL uninit done\n"); 1441 DSSDBG("PLL uninit done\n");
1489} 1442}
@@ -1491,24 +1444,21 @@ static void dsi_pll_uninit(struct platform_device *dsidev, bool disconnect_lanes
1491static void dsi_pll_disable(struct dss_pll *pll) 1444static void dsi_pll_disable(struct dss_pll *pll)
1492{ 1445{
1493 struct dsi_data *dsi = container_of(pll, struct dsi_data, pll); 1446 struct dsi_data *dsi = container_of(pll, struct dsi_data, pll);
1494 struct platform_device *dsidev = dsi->pdev;
1495 1447
1496 dsi_pll_uninit(dsidev, true); 1448 dsi_pll_uninit(dsi, true);
1497} 1449}
1498 1450
1499static void dsi_dump_dsidev_clocks(struct platform_device *dsidev, 1451static void dsi_dump_dsi_clocks(struct dsi_data *dsi, struct seq_file *s)
1500 struct seq_file *s)
1501{ 1452{
1502 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1503 struct dss_pll_clock_info *cinfo = &dsi->pll.cinfo; 1453 struct dss_pll_clock_info *cinfo = &dsi->pll.cinfo;
1504 enum dss_clk_source dispc_clk_src, dsi_clk_src; 1454 enum dss_clk_source dispc_clk_src, dsi_clk_src;
1505 int dsi_module = dsi->module_id; 1455 int dsi_module = dsi->module_id;
1506 struct dss_pll *pll = &dsi->pll; 1456 struct dss_pll *pll = &dsi->pll;
1507 1457
1508 dispc_clk_src = dss_get_dispc_clk_source(); 1458 dispc_clk_src = dss_get_dispc_clk_source(dsi->dss);
1509 dsi_clk_src = dss_get_dsi_clk_source(dsi_module); 1459 dsi_clk_src = dss_get_dsi_clk_source(dsi->dss, dsi_module);
1510 1460
1511 if (dsi_runtime_get(dsidev)) 1461 if (dsi_runtime_get(dsi))
1512 return; 1462 return;
1513 1463
1514 seq_printf(s, "- DSI%d PLL -\n", dsi_module + 1); 1464 seq_printf(s, "- DSI%d PLL -\n", dsi_module + 1);
@@ -1543,35 +1493,33 @@ static void dsi_dump_dsidev_clocks(struct platform_device *dsidev,
1543 seq_printf(s, "dsi fclk source = %s\n", 1493 seq_printf(s, "dsi fclk source = %s\n",
1544 dss_get_clk_source_name(dsi_clk_src)); 1494 dss_get_clk_source_name(dsi_clk_src));
1545 1495
1546 seq_printf(s, "DSI_FCLK\t%lu\n", dsi_fclk_rate(dsidev)); 1496 seq_printf(s, "DSI_FCLK\t%lu\n", dsi_fclk_rate(dsi));
1547 1497
1548 seq_printf(s, "DDR_CLK\t\t%lu\n", 1498 seq_printf(s, "DDR_CLK\t\t%lu\n",
1549 cinfo->clkdco / 4); 1499 cinfo->clkdco / 4);
1550 1500
1551 seq_printf(s, "TxByteClkHS\t%lu\n", dsi_get_txbyteclkhs(dsidev)); 1501 seq_printf(s, "TxByteClkHS\t%lu\n", dsi_get_txbyteclkhs(dsi));
1552 1502
1553 seq_printf(s, "LP_CLK\t\t%lu\n", dsi->current_lp_cinfo.lp_clk); 1503 seq_printf(s, "LP_CLK\t\t%lu\n", dsi->current_lp_cinfo.lp_clk);
1554 1504
1555 dsi_runtime_put(dsidev); 1505 dsi_runtime_put(dsi);
1556} 1506}
1557 1507
1558void dsi_dump_clocks(struct seq_file *s) 1508void dsi_dump_clocks(struct seq_file *s)
1559{ 1509{
1560 struct platform_device *dsidev; 1510 struct dsi_data *dsi;
1561 int i; 1511 int i;
1562 1512
1563 for (i = 0; i < MAX_NUM_DSI; i++) { 1513 for (i = 0; i < MAX_NUM_DSI; i++) {
1564 dsidev = dsi_get_dsidev_from_id(i); 1514 dsi = dsi_get_dsi_from_id(i);
1565 if (dsidev) 1515 if (dsi)
1566 dsi_dump_dsidev_clocks(dsidev, s); 1516 dsi_dump_dsi_clocks(dsi, s);
1567 } 1517 }
1568} 1518}
1569 1519
1570#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS 1520#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
1571static void dsi_dump_dsidev_irqs(struct platform_device *dsidev, 1521static void dsi_dump_dsi_irqs(struct dsi_data *dsi, struct seq_file *s)
1572 struct seq_file *s)
1573{ 1522{
1574 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1575 unsigned long flags; 1523 unsigned long flags;
1576 struct dsi_irq_stats stats; 1524 struct dsi_irq_stats stats;
1577 1525
@@ -1657,29 +1605,30 @@ static void dsi_dump_dsidev_irqs(struct platform_device *dsidev,
1657#undef PIS 1605#undef PIS
1658} 1606}
1659 1607
1660static void dsi1_dump_irqs(struct seq_file *s) 1608static int dsi1_dump_irqs(struct seq_file *s, void *p)
1661{ 1609{
1662 struct platform_device *dsidev = dsi_get_dsidev_from_id(0); 1610 struct dsi_data *dsi = dsi_get_dsi_from_id(0);
1663 1611
1664 dsi_dump_dsidev_irqs(dsidev, s); 1612 dsi_dump_dsi_irqs(dsi, s);
1613 return 0;
1665} 1614}
1666 1615
1667static void dsi2_dump_irqs(struct seq_file *s) 1616static int dsi2_dump_irqs(struct seq_file *s, void *p)
1668{ 1617{
1669 struct platform_device *dsidev = dsi_get_dsidev_from_id(1); 1618 struct dsi_data *dsi = dsi_get_dsi_from_id(1);
1670 1619
1671 dsi_dump_dsidev_irqs(dsidev, s); 1620 dsi_dump_dsi_irqs(dsi, s);
1621 return 0;
1672} 1622}
1673#endif 1623#endif
1674 1624
1675static void dsi_dump_dsidev_regs(struct platform_device *dsidev, 1625static void dsi_dump_dsi_regs(struct dsi_data *dsi, struct seq_file *s)
1676 struct seq_file *s)
1677{ 1626{
1678#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(dsidev, r)) 1627#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(dsi, r))
1679 1628
1680 if (dsi_runtime_get(dsidev)) 1629 if (dsi_runtime_get(dsi))
1681 return; 1630 return;
1682 dsi_enable_scp_clk(dsidev); 1631 dsi_enable_scp_clk(dsi);
1683 1632
1684 DUMPREG(DSI_REVISION); 1633 DUMPREG(DSI_REVISION);
1685 DUMPREG(DSI_SYSCONFIG); 1634 DUMPREG(DSI_SYSCONFIG);
@@ -1751,23 +1700,25 @@ static void dsi_dump_dsidev_regs(struct platform_device *dsidev,
1751 DUMPREG(DSI_PLL_CONFIGURATION1); 1700 DUMPREG(DSI_PLL_CONFIGURATION1);
1752 DUMPREG(DSI_PLL_CONFIGURATION2); 1701 DUMPREG(DSI_PLL_CONFIGURATION2);
1753 1702
1754 dsi_disable_scp_clk(dsidev); 1703 dsi_disable_scp_clk(dsi);
1755 dsi_runtime_put(dsidev); 1704 dsi_runtime_put(dsi);
1756#undef DUMPREG 1705#undef DUMPREG
1757} 1706}
1758 1707
1759static void dsi1_dump_regs(struct seq_file *s) 1708static int dsi1_dump_regs(struct seq_file *s, void *p)
1760{ 1709{
1761 struct platform_device *dsidev = dsi_get_dsidev_from_id(0); 1710 struct dsi_data *dsi = dsi_get_dsi_from_id(0);
1762 1711
1763 dsi_dump_dsidev_regs(dsidev, s); 1712 dsi_dump_dsi_regs(dsi, s);
1713 return 0;
1764} 1714}
1765 1715
1766static void dsi2_dump_regs(struct seq_file *s) 1716static int dsi2_dump_regs(struct seq_file *s, void *p)
1767{ 1717{
1768 struct platform_device *dsidev = dsi_get_dsidev_from_id(1); 1718 struct dsi_data *dsi = dsi_get_dsi_from_id(1);
1769 1719
1770 dsi_dump_dsidev_regs(dsidev, s); 1720 dsi_dump_dsi_regs(dsi, s);
1721 return 0;
1771} 1722}
1772 1723
1773enum dsi_cio_power_state { 1724enum dsi_cio_power_state {
@@ -1776,16 +1727,15 @@ enum dsi_cio_power_state {
1776 DSI_COMPLEXIO_POWER_ULPS = 0x2, 1727 DSI_COMPLEXIO_POWER_ULPS = 0x2,
1777}; 1728};
1778 1729
1779static int dsi_cio_power(struct platform_device *dsidev, 1730static int dsi_cio_power(struct dsi_data *dsi, enum dsi_cio_power_state state)
1780 enum dsi_cio_power_state state)
1781{ 1731{
1782 int t = 0; 1732 int t = 0;
1783 1733
1784 /* PWR_CMD */ 1734 /* PWR_CMD */
1785 REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG1, state, 28, 27); 1735 REG_FLD_MOD(dsi, DSI_COMPLEXIO_CFG1, state, 28, 27);
1786 1736
1787 /* PWR_STATUS */ 1737 /* PWR_STATUS */
1788 while (FLD_GET(dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1), 1738 while (FLD_GET(dsi_read_reg(dsi, DSI_COMPLEXIO_CFG1),
1789 26, 25) != state) { 1739 26, 25) != state) {
1790 if (++t > 1000) { 1740 if (++t > 1000) {
1791 DSSERR("failed to set complexio power state to " 1741 DSSERR("failed to set complexio power state to "
@@ -1798,9 +1748,8 @@ static int dsi_cio_power(struct platform_device *dsidev,
1798 return 0; 1748 return 0;
1799} 1749}
1800 1750
1801static unsigned dsi_get_line_buf_size(struct platform_device *dsidev) 1751static unsigned int dsi_get_line_buf_size(struct dsi_data *dsi)
1802{ 1752{
1803 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1804 int val; 1753 int val;
1805 1754
1806 /* line buffer on OMAP3 is 1024 x 24bits */ 1755 /* line buffer on OMAP3 is 1024 x 24bits */
@@ -1810,7 +1759,7 @@ static unsigned dsi_get_line_buf_size(struct platform_device *dsidev)
1810 if (!(dsi->data->quirks & DSI_QUIRK_GNQ)) 1759 if (!(dsi->data->quirks & DSI_QUIRK_GNQ))
1811 return 1023 * 3; 1760 return 1023 * 3;
1812 1761
1813 val = REG_GET(dsidev, DSI_GNQ, 14, 12); /* VP1_LINE_BUFFER_SIZE */ 1762 val = REG_GET(dsi, DSI_GNQ, 14, 12); /* VP1_LINE_BUFFER_SIZE */
1814 1763
1815 switch (val) { 1764 switch (val) {
1816 case 1: 1765 case 1:
@@ -1833,9 +1782,8 @@ static unsigned dsi_get_line_buf_size(struct platform_device *dsidev)
1833 } 1782 }
1834} 1783}
1835 1784
1836static int dsi_set_lane_config(struct platform_device *dsidev) 1785static int dsi_set_lane_config(struct dsi_data *dsi)
1837{ 1786{
1838 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1839 static const u8 offsets[] = { 0, 4, 8, 12, 16 }; 1787 static const u8 offsets[] = { 0, 4, 8, 12, 16 };
1840 static const enum dsi_lane_function functions[] = { 1788 static const enum dsi_lane_function functions[] = {
1841 DSI_LANE_CLK, 1789 DSI_LANE_CLK,
@@ -1847,12 +1795,12 @@ static int dsi_set_lane_config(struct platform_device *dsidev)
1847 u32 r; 1795 u32 r;
1848 int i; 1796 int i;
1849 1797
1850 r = dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1); 1798 r = dsi_read_reg(dsi, DSI_COMPLEXIO_CFG1);
1851 1799
1852 for (i = 0; i < dsi->num_lanes_used; ++i) { 1800 for (i = 0; i < dsi->num_lanes_used; ++i) {
1853 unsigned offset = offsets[i]; 1801 unsigned int offset = offsets[i];
1854 unsigned polarity, lane_number; 1802 unsigned int polarity, lane_number;
1855 unsigned t; 1803 unsigned int t;
1856 1804
1857 for (t = 0; t < dsi->num_lanes_supported; ++t) 1805 for (t = 0; t < dsi->num_lanes_supported; ++t)
1858 if (dsi->lanes[t].function == functions[i]) 1806 if (dsi->lanes[t].function == functions[i])
@@ -1870,37 +1818,34 @@ static int dsi_set_lane_config(struct platform_device *dsidev)
1870 1818
1871 /* clear the unused lanes */ 1819 /* clear the unused lanes */
1872 for (; i < dsi->num_lanes_supported; ++i) { 1820 for (; i < dsi->num_lanes_supported; ++i) {
1873 unsigned offset = offsets[i]; 1821 unsigned int offset = offsets[i];
1874 1822
1875 r = FLD_MOD(r, 0, offset + 2, offset); 1823 r = FLD_MOD(r, 0, offset + 2, offset);
1876 r = FLD_MOD(r, 0, offset + 3, offset + 3); 1824 r = FLD_MOD(r, 0, offset + 3, offset + 3);
1877 } 1825 }
1878 1826
1879 dsi_write_reg(dsidev, DSI_COMPLEXIO_CFG1, r); 1827 dsi_write_reg(dsi, DSI_COMPLEXIO_CFG1, r);
1880 1828
1881 return 0; 1829 return 0;
1882} 1830}
1883 1831
1884static inline unsigned ns2ddr(struct platform_device *dsidev, unsigned ns) 1832static inline unsigned int ns2ddr(struct dsi_data *dsi, unsigned int ns)
1885{ 1833{
1886 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1887
1888 /* convert time in ns to ddr ticks, rounding up */ 1834 /* convert time in ns to ddr ticks, rounding up */
1889 unsigned long ddr_clk = dsi->pll.cinfo.clkdco / 4; 1835 unsigned long ddr_clk = dsi->pll.cinfo.clkdco / 4;
1836
1890 return (ns * (ddr_clk / 1000 / 1000) + 999) / 1000; 1837 return (ns * (ddr_clk / 1000 / 1000) + 999) / 1000;
1891} 1838}
1892 1839
1893static inline unsigned ddr2ns(struct platform_device *dsidev, unsigned ddr) 1840static inline unsigned int ddr2ns(struct dsi_data *dsi, unsigned int ddr)
1894{ 1841{
1895 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1896
1897 unsigned long ddr_clk = dsi->pll.cinfo.clkdco / 4; 1842 unsigned long ddr_clk = dsi->pll.cinfo.clkdco / 4;
1843
1898 return ddr * 1000 * 1000 / (ddr_clk / 1000); 1844 return ddr * 1000 * 1000 / (ddr_clk / 1000);
1899} 1845}
1900 1846
1901static void dsi_cio_timings(struct platform_device *dsidev) 1847static void dsi_cio_timings(struct dsi_data *dsi)
1902{ 1848{
1903 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1904 u32 r; 1849 u32 r;
1905 u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit; 1850 u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit;
1906 u32 tlpx_half, tclk_trail, tclk_zero; 1851 u32 tlpx_half, tclk_trail, tclk_zero;
@@ -1911,54 +1856,54 @@ static void dsi_cio_timings(struct platform_device *dsidev)
1911 /* 1 * DDR_CLK = 2 * UI */ 1856 /* 1 * DDR_CLK = 2 * UI */
1912 1857
1913 /* min 40ns + 4*UI max 85ns + 6*UI */ 1858 /* min 40ns + 4*UI max 85ns + 6*UI */
1914 ths_prepare = ns2ddr(dsidev, 70) + 2; 1859 ths_prepare = ns2ddr(dsi, 70) + 2;
1915 1860
1916 /* min 145ns + 10*UI */ 1861 /* min 145ns + 10*UI */
1917 ths_prepare_ths_zero = ns2ddr(dsidev, 175) + 2; 1862 ths_prepare_ths_zero = ns2ddr(dsi, 175) + 2;
1918 1863
1919 /* min max(8*UI, 60ns+4*UI) */ 1864 /* min max(8*UI, 60ns+4*UI) */
1920 ths_trail = ns2ddr(dsidev, 60) + 5; 1865 ths_trail = ns2ddr(dsi, 60) + 5;
1921 1866
1922 /* min 100ns */ 1867 /* min 100ns */
1923 ths_exit = ns2ddr(dsidev, 145); 1868 ths_exit = ns2ddr(dsi, 145);
1924 1869
1925 /* tlpx min 50n */ 1870 /* tlpx min 50n */
1926 tlpx_half = ns2ddr(dsidev, 25); 1871 tlpx_half = ns2ddr(dsi, 25);
1927 1872
1928 /* min 60ns */ 1873 /* min 60ns */
1929 tclk_trail = ns2ddr(dsidev, 60) + 2; 1874 tclk_trail = ns2ddr(dsi, 60) + 2;
1930 1875
1931 /* min 38ns, max 95ns */ 1876 /* min 38ns, max 95ns */
1932 tclk_prepare = ns2ddr(dsidev, 65); 1877 tclk_prepare = ns2ddr(dsi, 65);
1933 1878
1934 /* min tclk-prepare + tclk-zero = 300ns */ 1879 /* min tclk-prepare + tclk-zero = 300ns */
1935 tclk_zero = ns2ddr(dsidev, 260); 1880 tclk_zero = ns2ddr(dsi, 260);
1936 1881
1937 DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n", 1882 DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n",
1938 ths_prepare, ddr2ns(dsidev, ths_prepare), 1883 ths_prepare, ddr2ns(dsi, ths_prepare),
1939 ths_prepare_ths_zero, ddr2ns(dsidev, ths_prepare_ths_zero)); 1884 ths_prepare_ths_zero, ddr2ns(dsi, ths_prepare_ths_zero));
1940 DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n", 1885 DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n",
1941 ths_trail, ddr2ns(dsidev, ths_trail), 1886 ths_trail, ddr2ns(dsi, ths_trail),
1942 ths_exit, ddr2ns(dsidev, ths_exit)); 1887 ths_exit, ddr2ns(dsi, ths_exit));
1943 1888
1944 DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), " 1889 DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), "
1945 "tclk_zero %u (%uns)\n", 1890 "tclk_zero %u (%uns)\n",
1946 tlpx_half, ddr2ns(dsidev, tlpx_half), 1891 tlpx_half, ddr2ns(dsi, tlpx_half),
1947 tclk_trail, ddr2ns(dsidev, tclk_trail), 1892 tclk_trail, ddr2ns(dsi, tclk_trail),
1948 tclk_zero, ddr2ns(dsidev, tclk_zero)); 1893 tclk_zero, ddr2ns(dsi, tclk_zero));
1949 DSSDBG("tclk_prepare %u (%uns)\n", 1894 DSSDBG("tclk_prepare %u (%uns)\n",
1950 tclk_prepare, ddr2ns(dsidev, tclk_prepare)); 1895 tclk_prepare, ddr2ns(dsi, tclk_prepare));
1951 1896
1952 /* program timings */ 1897 /* program timings */
1953 1898
1954 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0); 1899 r = dsi_read_reg(dsi, DSI_DSIPHY_CFG0);
1955 r = FLD_MOD(r, ths_prepare, 31, 24); 1900 r = FLD_MOD(r, ths_prepare, 31, 24);
1956 r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16); 1901 r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16);
1957 r = FLD_MOD(r, ths_trail, 15, 8); 1902 r = FLD_MOD(r, ths_trail, 15, 8);
1958 r = FLD_MOD(r, ths_exit, 7, 0); 1903 r = FLD_MOD(r, ths_exit, 7, 0);
1959 dsi_write_reg(dsidev, DSI_DSIPHY_CFG0, r); 1904 dsi_write_reg(dsi, DSI_DSIPHY_CFG0, r);
1960 1905
1961 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1); 1906 r = dsi_read_reg(dsi, DSI_DSIPHY_CFG1);
1962 r = FLD_MOD(r, tlpx_half, 20, 16); 1907 r = FLD_MOD(r, tlpx_half, 20, 16);
1963 r = FLD_MOD(r, tclk_trail, 15, 8); 1908 r = FLD_MOD(r, tclk_trail, 15, 8);
1964 r = FLD_MOD(r, tclk_zero, 7, 0); 1909 r = FLD_MOD(r, tclk_zero, 7, 0);
@@ -1969,18 +1914,18 @@ static void dsi_cio_timings(struct platform_device *dsidev)
1969 r = FLD_MOD(r, 1, 23, 23); /* CLKINP_SEL = enable */ 1914 r = FLD_MOD(r, 1, 23, 23); /* CLKINP_SEL = enable */
1970 } 1915 }
1971 1916
1972 dsi_write_reg(dsidev, DSI_DSIPHY_CFG1, r); 1917 dsi_write_reg(dsi, DSI_DSIPHY_CFG1, r);
1973 1918
1974 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2); 1919 r = dsi_read_reg(dsi, DSI_DSIPHY_CFG2);
1975 r = FLD_MOD(r, tclk_prepare, 7, 0); 1920 r = FLD_MOD(r, tclk_prepare, 7, 0);
1976 dsi_write_reg(dsidev, DSI_DSIPHY_CFG2, r); 1921 dsi_write_reg(dsi, DSI_DSIPHY_CFG2, r);
1977} 1922}
1978 1923
1979/* lane masks have lane 0 at lsb. mask_p for positive lines, n for negative */ 1924/* lane masks have lane 0 at lsb. mask_p for positive lines, n for negative */
1980static void dsi_cio_enable_lane_override(struct platform_device *dsidev, 1925static void dsi_cio_enable_lane_override(struct dsi_data *dsi,
1981 unsigned mask_p, unsigned mask_n) 1926 unsigned int mask_p,
1927 unsigned int mask_n)
1982{ 1928{
1983 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1984 int i; 1929 int i;
1985 u32 l; 1930 u32 l;
1986 u8 lptxscp_start = dsi->num_lanes_supported == 3 ? 22 : 26; 1931 u8 lptxscp_start = dsi->num_lanes_supported == 3 ? 22 : 26;
@@ -1988,7 +1933,7 @@ static void dsi_cio_enable_lane_override(struct platform_device *dsidev,
1988 l = 0; 1933 l = 0;
1989 1934
1990 for (i = 0; i < dsi->num_lanes_supported; ++i) { 1935 for (i = 0; i < dsi->num_lanes_supported; ++i) {
1991 unsigned p = dsi->lanes[i].polarity; 1936 unsigned int p = dsi->lanes[i].polarity;
1992 1937
1993 if (mask_p & (1 << i)) 1938 if (mask_p & (1 << i))
1994 l |= 1 << (i * 2 + (p ? 0 : 1)); 1939 l |= 1 << (i * 2 + (p ? 0 : 1));
@@ -2009,26 +1954,25 @@ static void dsi_cio_enable_lane_override(struct platform_device *dsidev,
2009 /* Set the lane override configuration */ 1954 /* Set the lane override configuration */
2010 1955
2011 /* REGLPTXSCPDAT4TO0DXDY */ 1956 /* REGLPTXSCPDAT4TO0DXDY */
2012 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, l, lptxscp_start, 17); 1957 REG_FLD_MOD(dsi, DSI_DSIPHY_CFG10, l, lptxscp_start, 17);
2013 1958
2014 /* Enable lane override */ 1959 /* Enable lane override */
2015 1960
2016 /* ENLPTXSCPDAT */ 1961 /* ENLPTXSCPDAT */
2017 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 1, 27, 27); 1962 REG_FLD_MOD(dsi, DSI_DSIPHY_CFG10, 1, 27, 27);
2018} 1963}
2019 1964
2020static void dsi_cio_disable_lane_override(struct platform_device *dsidev) 1965static void dsi_cio_disable_lane_override(struct dsi_data *dsi)
2021{ 1966{
2022 /* Disable lane override */ 1967 /* Disable lane override */
2023 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 27, 27); /* ENLPTXSCPDAT */ 1968 REG_FLD_MOD(dsi, DSI_DSIPHY_CFG10, 0, 27, 27); /* ENLPTXSCPDAT */
2024 /* Reset the lane override configuration */ 1969 /* Reset the lane override configuration */
2025 /* REGLPTXSCPDAT4TO0DXDY */ 1970 /* REGLPTXSCPDAT4TO0DXDY */
2026 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 22, 17); 1971 REG_FLD_MOD(dsi, DSI_DSIPHY_CFG10, 0, 22, 17);
2027} 1972}
2028 1973
2029static int dsi_cio_wait_tx_clk_esc_reset(struct platform_device *dsidev) 1974static int dsi_cio_wait_tx_clk_esc_reset(struct dsi_data *dsi)
2030{ 1975{
2031 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2032 int t, i; 1976 int t, i;
2033 bool in_use[DSI_MAX_NR_LANES]; 1977 bool in_use[DSI_MAX_NR_LANES];
2034 static const u8 offsets_old[] = { 28, 27, 26 }; 1978 static const u8 offsets_old[] = { 28, 27, 26 };
@@ -2048,7 +1992,7 @@ static int dsi_cio_wait_tx_clk_esc_reset(struct platform_device *dsidev)
2048 u32 l; 1992 u32 l;
2049 int ok; 1993 int ok;
2050 1994
2051 l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5); 1995 l = dsi_read_reg(dsi, DSI_DSIPHY_CFG5);
2052 1996
2053 ok = 0; 1997 ok = 0;
2054 for (i = 0; i < dsi->num_lanes_supported; ++i) { 1998 for (i = 0; i < dsi->num_lanes_supported; ++i) {
@@ -2075,10 +2019,9 @@ static int dsi_cio_wait_tx_clk_esc_reset(struct platform_device *dsidev)
2075} 2019}
2076 2020
2077/* return bitmask of enabled lanes, lane0 being the lsb */ 2021/* return bitmask of enabled lanes, lane0 being the lsb */
2078static unsigned dsi_get_lane_mask(struct platform_device *dsidev) 2022static unsigned int dsi_get_lane_mask(struct dsi_data *dsi)
2079{ 2023{
2080 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 2024 unsigned int mask = 0;
2081 unsigned mask = 0;
2082 int i; 2025 int i;
2083 2026
2084 for (i = 0; i < dsi->num_lanes_supported; ++i) { 2027 for (i = 0; i < dsi->num_lanes_supported; ++i) {
@@ -2166,45 +2109,44 @@ static void dsi_disable_pads(struct dsi_data *dsi)
2166 dsi_omap5_mux_pads(dsi, 0); 2109 dsi_omap5_mux_pads(dsi, 0);
2167} 2110}
2168 2111
2169static int dsi_cio_init(struct platform_device *dsidev) 2112static int dsi_cio_init(struct dsi_data *dsi)
2170{ 2113{
2171 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2172 int r; 2114 int r;
2173 u32 l; 2115 u32 l;
2174 2116
2175 DSSDBG("DSI CIO init starts"); 2117 DSSDBG("DSI CIO init starts");
2176 2118
2177 r = dsi_enable_pads(dsi, dsi_get_lane_mask(dsidev)); 2119 r = dsi_enable_pads(dsi, dsi_get_lane_mask(dsi));
2178 if (r) 2120 if (r)
2179 return r; 2121 return r;
2180 2122
2181 dsi_enable_scp_clk(dsidev); 2123 dsi_enable_scp_clk(dsi);
2182 2124
2183 /* A dummy read using the SCP interface to any DSIPHY register is 2125 /* A dummy read using the SCP interface to any DSIPHY register is
2184 * required after DSIPHY reset to complete the reset of the DSI complex 2126 * required after DSIPHY reset to complete the reset of the DSI complex
2185 * I/O. */ 2127 * I/O. */
2186 dsi_read_reg(dsidev, DSI_DSIPHY_CFG5); 2128 dsi_read_reg(dsi, DSI_DSIPHY_CFG5);
2187 2129
2188 if (wait_for_bit_change(dsidev, DSI_DSIPHY_CFG5, 30, 1) != 1) { 2130 if (!wait_for_bit_change(dsi, DSI_DSIPHY_CFG5, 30, 1)) {
2189 DSSERR("CIO SCP Clock domain not coming out of reset.\n"); 2131 DSSERR("CIO SCP Clock domain not coming out of reset.\n");
2190 r = -EIO; 2132 r = -EIO;
2191 goto err_scp_clk_dom; 2133 goto err_scp_clk_dom;
2192 } 2134 }
2193 2135
2194 r = dsi_set_lane_config(dsidev); 2136 r = dsi_set_lane_config(dsi);
2195 if (r) 2137 if (r)
2196 goto err_scp_clk_dom; 2138 goto err_scp_clk_dom;
2197 2139
2198 /* set TX STOP MODE timer to maximum for this operation */ 2140 /* set TX STOP MODE timer to maximum for this operation */
2199 l = dsi_read_reg(dsidev, DSI_TIMING1); 2141 l = dsi_read_reg(dsi, DSI_TIMING1);
2200 l = FLD_MOD(l, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */ 2142 l = FLD_MOD(l, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
2201 l = FLD_MOD(l, 1, 14, 14); /* STOP_STATE_X16_IO */ 2143 l = FLD_MOD(l, 1, 14, 14); /* STOP_STATE_X16_IO */
2202 l = FLD_MOD(l, 1, 13, 13); /* STOP_STATE_X4_IO */ 2144 l = FLD_MOD(l, 1, 13, 13); /* STOP_STATE_X4_IO */
2203 l = FLD_MOD(l, 0x1fff, 12, 0); /* STOP_STATE_COUNTER_IO */ 2145 l = FLD_MOD(l, 0x1fff, 12, 0); /* STOP_STATE_COUNTER_IO */
2204 dsi_write_reg(dsidev, DSI_TIMING1, l); 2146 dsi_write_reg(dsi, DSI_TIMING1, l);
2205 2147
2206 if (dsi->ulps_enabled) { 2148 if (dsi->ulps_enabled) {
2207 unsigned mask_p; 2149 unsigned int mask_p;
2208 int i; 2150 int i;
2209 2151
2210 DSSDBG("manual ulps exit\n"); 2152 DSSDBG("manual ulps exit\n");
@@ -2226,24 +2168,24 @@ static int dsi_cio_init(struct platform_device *dsidev)
2226 mask_p |= 1 << i; 2168 mask_p |= 1 << i;
2227 } 2169 }
2228 2170
2229 dsi_cio_enable_lane_override(dsidev, mask_p, 0); 2171 dsi_cio_enable_lane_override(dsi, mask_p, 0);
2230 } 2172 }
2231 2173
2232 r = dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ON); 2174 r = dsi_cio_power(dsi, DSI_COMPLEXIO_POWER_ON);
2233 if (r) 2175 if (r)
2234 goto err_cio_pwr; 2176 goto err_cio_pwr;
2235 2177
2236 if (wait_for_bit_change(dsidev, DSI_COMPLEXIO_CFG1, 29, 1) != 1) { 2178 if (!wait_for_bit_change(dsi, DSI_COMPLEXIO_CFG1, 29, 1)) {
2237 DSSERR("CIO PWR clock domain not coming out of reset.\n"); 2179 DSSERR("CIO PWR clock domain not coming out of reset.\n");
2238 r = -ENODEV; 2180 r = -ENODEV;
2239 goto err_cio_pwr_dom; 2181 goto err_cio_pwr_dom;
2240 } 2182 }
2241 2183
2242 dsi_if_enable(dsidev, true); 2184 dsi_if_enable(dsi, true);
2243 dsi_if_enable(dsidev, false); 2185 dsi_if_enable(dsi, false);
2244 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */ 2186 REG_FLD_MOD(dsi, DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */
2245 2187
2246 r = dsi_cio_wait_tx_clk_esc_reset(dsidev); 2188 r = dsi_cio_wait_tx_clk_esc_reset(dsi);
2247 if (r) 2189 if (r)
2248 goto err_tx_clk_esc_rst; 2190 goto err_tx_clk_esc_rst;
2249 2191
@@ -2255,17 +2197,17 @@ static int dsi_cio_init(struct platform_device *dsidev)
2255 2197
2256 /* Disable the override. The lanes should be set to Mark-11 2198 /* Disable the override. The lanes should be set to Mark-11
2257 * state by the HW */ 2199 * state by the HW */
2258 dsi_cio_disable_lane_override(dsidev); 2200 dsi_cio_disable_lane_override(dsi);
2259 } 2201 }
2260 2202
2261 /* FORCE_TX_STOP_MODE_IO */ 2203 /* FORCE_TX_STOP_MODE_IO */
2262 REG_FLD_MOD(dsidev, DSI_TIMING1, 0, 15, 15); 2204 REG_FLD_MOD(dsi, DSI_TIMING1, 0, 15, 15);
2263 2205
2264 dsi_cio_timings(dsidev); 2206 dsi_cio_timings(dsi);
2265 2207
2266 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { 2208 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
2267 /* DDR_CLK_ALWAYS_ON */ 2209 /* DDR_CLK_ALWAYS_ON */
2268 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 2210 REG_FLD_MOD(dsi, DSI_CLK_CTRL,
2269 dsi->vm_timings.ddr_clk_always_on, 13, 13); 2211 dsi->vm_timings.ddr_clk_always_on, 13, 13);
2270 } 2212 }
2271 2213
@@ -2276,35 +2218,32 @@ static int dsi_cio_init(struct platform_device *dsidev)
2276 return 0; 2218 return 0;
2277 2219
2278err_tx_clk_esc_rst: 2220err_tx_clk_esc_rst:
2279 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 20, 20); /* LP_CLK_ENABLE */ 2221 REG_FLD_MOD(dsi, DSI_CLK_CTRL, 0, 20, 20); /* LP_CLK_ENABLE */
2280err_cio_pwr_dom: 2222err_cio_pwr_dom:
2281 dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF); 2223 dsi_cio_power(dsi, DSI_COMPLEXIO_POWER_OFF);
2282err_cio_pwr: 2224err_cio_pwr:
2283 if (dsi->ulps_enabled) 2225 if (dsi->ulps_enabled)
2284 dsi_cio_disable_lane_override(dsidev); 2226 dsi_cio_disable_lane_override(dsi);
2285err_scp_clk_dom: 2227err_scp_clk_dom:
2286 dsi_disable_scp_clk(dsidev); 2228 dsi_disable_scp_clk(dsi);
2287 dsi_disable_pads(dsi); 2229 dsi_disable_pads(dsi);
2288 return r; 2230 return r;
2289} 2231}
2290 2232
2291static void dsi_cio_uninit(struct platform_device *dsidev) 2233static void dsi_cio_uninit(struct dsi_data *dsi)
2292{ 2234{
2293 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2294
2295 /* DDR_CLK_ALWAYS_ON */ 2235 /* DDR_CLK_ALWAYS_ON */
2296 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 13, 13); 2236 REG_FLD_MOD(dsi, DSI_CLK_CTRL, 0, 13, 13);
2297 2237
2298 dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF); 2238 dsi_cio_power(dsi, DSI_COMPLEXIO_POWER_OFF);
2299 dsi_disable_scp_clk(dsidev); 2239 dsi_disable_scp_clk(dsi);
2300 dsi_disable_pads(dsi); 2240 dsi_disable_pads(dsi);
2301} 2241}
2302 2242
2303static void dsi_config_tx_fifo(struct platform_device *dsidev, 2243static void dsi_config_tx_fifo(struct dsi_data *dsi,
2304 enum fifo_size size1, enum fifo_size size2, 2244 enum fifo_size size1, enum fifo_size size2,
2305 enum fifo_size size3, enum fifo_size size4) 2245 enum fifo_size size3, enum fifo_size size4)
2306{ 2246{
2307 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2308 u32 r = 0; 2247 u32 r = 0;
2309 int add = 0; 2248 int add = 0;
2310 int i; 2249 int i;
@@ -2330,14 +2269,13 @@ static void dsi_config_tx_fifo(struct platform_device *dsidev,
2330 add += size; 2269 add += size;
2331 } 2270 }
2332 2271
2333 dsi_write_reg(dsidev, DSI_TX_FIFO_VC_SIZE, r); 2272 dsi_write_reg(dsi, DSI_TX_FIFO_VC_SIZE, r);
2334} 2273}
2335 2274
2336static void dsi_config_rx_fifo(struct platform_device *dsidev, 2275static void dsi_config_rx_fifo(struct dsi_data *dsi,
2337 enum fifo_size size1, enum fifo_size size2, 2276 enum fifo_size size1, enum fifo_size size2,
2338 enum fifo_size size3, enum fifo_size size4) 2277 enum fifo_size size3, enum fifo_size size4)
2339{ 2278{
2340 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2341 u32 r = 0; 2279 u32 r = 0;
2342 int add = 0; 2280 int add = 0;
2343 int i; 2281 int i;
@@ -2363,18 +2301,18 @@ static void dsi_config_rx_fifo(struct platform_device *dsidev,
2363 add += size; 2301 add += size;
2364 } 2302 }
2365 2303
2366 dsi_write_reg(dsidev, DSI_RX_FIFO_VC_SIZE, r); 2304 dsi_write_reg(dsi, DSI_RX_FIFO_VC_SIZE, r);
2367} 2305}
2368 2306
2369static int dsi_force_tx_stop_mode_io(struct platform_device *dsidev) 2307static int dsi_force_tx_stop_mode_io(struct dsi_data *dsi)
2370{ 2308{
2371 u32 r; 2309 u32 r;
2372 2310
2373 r = dsi_read_reg(dsidev, DSI_TIMING1); 2311 r = dsi_read_reg(dsi, DSI_TIMING1);
2374 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */ 2312 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
2375 dsi_write_reg(dsidev, DSI_TIMING1, r); 2313 dsi_write_reg(dsi, DSI_TIMING1, r);
2376 2314
2377 if (wait_for_bit_change(dsidev, DSI_TIMING1, 15, 0) != 0) { 2315 if (!wait_for_bit_change(dsi, DSI_TIMING1, 15, 0)) {
2378 DSSERR("TX_STOP bit not going down\n"); 2316 DSSERR("TX_STOP bit not going down\n");
2379 return -EIO; 2317 return -EIO;
2380 } 2318 }
@@ -2382,29 +2320,28 @@ static int dsi_force_tx_stop_mode_io(struct platform_device *dsidev)
2382 return 0; 2320 return 0;
2383} 2321}
2384 2322
2385static bool dsi_vc_is_enabled(struct platform_device *dsidev, int channel) 2323static bool dsi_vc_is_enabled(struct dsi_data *dsi, int channel)
2386{ 2324{
2387 return REG_GET(dsidev, DSI_VC_CTRL(channel), 0, 0); 2325 return REG_GET(dsi, DSI_VC_CTRL(channel), 0, 0);
2388} 2326}
2389 2327
2390static void dsi_packet_sent_handler_vp(void *data, u32 mask) 2328static void dsi_packet_sent_handler_vp(void *data, u32 mask)
2391{ 2329{
2392 struct dsi_packet_sent_handler_data *vp_data = 2330 struct dsi_packet_sent_handler_data *vp_data =
2393 (struct dsi_packet_sent_handler_data *) data; 2331 (struct dsi_packet_sent_handler_data *) data;
2394 struct dsi_data *dsi = dsi_get_dsidrv_data(vp_data->dsidev); 2332 struct dsi_data *dsi = vp_data->dsi;
2395 const int channel = dsi->update_channel; 2333 const int channel = dsi->update_channel;
2396 u8 bit = dsi->te_enabled ? 30 : 31; 2334 u8 bit = dsi->te_enabled ? 30 : 31;
2397 2335
2398 if (REG_GET(vp_data->dsidev, DSI_VC_TE(channel), bit, bit) == 0) 2336 if (REG_GET(dsi, DSI_VC_TE(channel), bit, bit) == 0)
2399 complete(vp_data->completion); 2337 complete(vp_data->completion);
2400} 2338}
2401 2339
2402static int dsi_sync_vc_vp(struct platform_device *dsidev, int channel) 2340static int dsi_sync_vc_vp(struct dsi_data *dsi, int channel)
2403{ 2341{
2404 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2405 DECLARE_COMPLETION_ONSTACK(completion); 2342 DECLARE_COMPLETION_ONSTACK(completion);
2406 struct dsi_packet_sent_handler_data vp_data = { 2343 struct dsi_packet_sent_handler_data vp_data = {
2407 .dsidev = dsidev, 2344 .dsi = dsi,
2408 .completion = &completion 2345 .completion = &completion
2409 }; 2346 };
2410 int r = 0; 2347 int r = 0;
@@ -2412,13 +2349,13 @@ static int dsi_sync_vc_vp(struct platform_device *dsidev, int channel)
2412 2349
2413 bit = dsi->te_enabled ? 30 : 31; 2350 bit = dsi->te_enabled ? 30 : 31;
2414 2351
2415 r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp, 2352 r = dsi_register_isr_vc(dsi, channel, dsi_packet_sent_handler_vp,
2416 &vp_data, DSI_VC_IRQ_PACKET_SENT); 2353 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2417 if (r) 2354 if (r)
2418 goto err0; 2355 goto err0;
2419 2356
2420 /* Wait for completion only if TE_EN/TE_START is still set */ 2357 /* Wait for completion only if TE_EN/TE_START is still set */
2421 if (REG_GET(dsidev, DSI_VC_TE(channel), bit, bit)) { 2358 if (REG_GET(dsi, DSI_VC_TE(channel), bit, bit)) {
2422 if (wait_for_completion_timeout(&completion, 2359 if (wait_for_completion_timeout(&completion,
2423 msecs_to_jiffies(10)) == 0) { 2360 msecs_to_jiffies(10)) == 0) {
2424 DSSERR("Failed to complete previous frame transfer\n"); 2361 DSSERR("Failed to complete previous frame transfer\n");
@@ -2427,12 +2364,12 @@ static int dsi_sync_vc_vp(struct platform_device *dsidev, int channel)
2427 } 2364 }
2428 } 2365 }
2429 2366
2430 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp, 2367 dsi_unregister_isr_vc(dsi, channel, dsi_packet_sent_handler_vp,
2431 &vp_data, DSI_VC_IRQ_PACKET_SENT); 2368 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2432 2369
2433 return 0; 2370 return 0;
2434err1: 2371err1:
2435 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp, 2372 dsi_unregister_isr_vc(dsi, channel, dsi_packet_sent_handler_vp,
2436 &vp_data, DSI_VC_IRQ_PACKET_SENT); 2373 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2437err0: 2374err0:
2438 return r; 2375 return r;
@@ -2442,29 +2379,29 @@ static void dsi_packet_sent_handler_l4(void *data, u32 mask)
2442{ 2379{
2443 struct dsi_packet_sent_handler_data *l4_data = 2380 struct dsi_packet_sent_handler_data *l4_data =
2444 (struct dsi_packet_sent_handler_data *) data; 2381 (struct dsi_packet_sent_handler_data *) data;
2445 struct dsi_data *dsi = dsi_get_dsidrv_data(l4_data->dsidev); 2382 struct dsi_data *dsi = l4_data->dsi;
2446 const int channel = dsi->update_channel; 2383 const int channel = dsi->update_channel;
2447 2384
2448 if (REG_GET(l4_data->dsidev, DSI_VC_CTRL(channel), 5, 5) == 0) 2385 if (REG_GET(dsi, DSI_VC_CTRL(channel), 5, 5) == 0)
2449 complete(l4_data->completion); 2386 complete(l4_data->completion);
2450} 2387}
2451 2388
2452static int dsi_sync_vc_l4(struct platform_device *dsidev, int channel) 2389static int dsi_sync_vc_l4(struct dsi_data *dsi, int channel)
2453{ 2390{
2454 DECLARE_COMPLETION_ONSTACK(completion); 2391 DECLARE_COMPLETION_ONSTACK(completion);
2455 struct dsi_packet_sent_handler_data l4_data = { 2392 struct dsi_packet_sent_handler_data l4_data = {
2456 .dsidev = dsidev, 2393 .dsi = dsi,
2457 .completion = &completion 2394 .completion = &completion
2458 }; 2395 };
2459 int r = 0; 2396 int r = 0;
2460 2397
2461 r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4, 2398 r = dsi_register_isr_vc(dsi, channel, dsi_packet_sent_handler_l4,
2462 &l4_data, DSI_VC_IRQ_PACKET_SENT); 2399 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2463 if (r) 2400 if (r)
2464 goto err0; 2401 goto err0;
2465 2402
2466 /* Wait for completion only if TX_FIFO_NOT_EMPTY is still set */ 2403 /* Wait for completion only if TX_FIFO_NOT_EMPTY is still set */
2467 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 5, 5)) { 2404 if (REG_GET(dsi, DSI_VC_CTRL(channel), 5, 5)) {
2468 if (wait_for_completion_timeout(&completion, 2405 if (wait_for_completion_timeout(&completion,
2469 msecs_to_jiffies(10)) == 0) { 2406 msecs_to_jiffies(10)) == 0) {
2470 DSSERR("Failed to complete previous l4 transfer\n"); 2407 DSSERR("Failed to complete previous l4 transfer\n");
@@ -2473,66 +2410,61 @@ static int dsi_sync_vc_l4(struct platform_device *dsidev, int channel)
2473 } 2410 }
2474 } 2411 }
2475 2412
2476 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4, 2413 dsi_unregister_isr_vc(dsi, channel, dsi_packet_sent_handler_l4,
2477 &l4_data, DSI_VC_IRQ_PACKET_SENT); 2414 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2478 2415
2479 return 0; 2416 return 0;
2480err1: 2417err1:
2481 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4, 2418 dsi_unregister_isr_vc(dsi, channel, dsi_packet_sent_handler_l4,
2482 &l4_data, DSI_VC_IRQ_PACKET_SENT); 2419 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2483err0: 2420err0:
2484 return r; 2421 return r;
2485} 2422}
2486 2423
2487static int dsi_sync_vc(struct platform_device *dsidev, int channel) 2424static int dsi_sync_vc(struct dsi_data *dsi, int channel)
2488{ 2425{
2489 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 2426 WARN_ON(!dsi_bus_is_locked(dsi));
2490
2491 WARN_ON(!dsi_bus_is_locked(dsidev));
2492 2427
2493 WARN_ON(in_interrupt()); 2428 WARN_ON(in_interrupt());
2494 2429
2495 if (!dsi_vc_is_enabled(dsidev, channel)) 2430 if (!dsi_vc_is_enabled(dsi, channel))
2496 return 0; 2431 return 0;
2497 2432
2498 switch (dsi->vc[channel].source) { 2433 switch (dsi->vc[channel].source) {
2499 case DSI_VC_SOURCE_VP: 2434 case DSI_VC_SOURCE_VP:
2500 return dsi_sync_vc_vp(dsidev, channel); 2435 return dsi_sync_vc_vp(dsi, channel);
2501 case DSI_VC_SOURCE_L4: 2436 case DSI_VC_SOURCE_L4:
2502 return dsi_sync_vc_l4(dsidev, channel); 2437 return dsi_sync_vc_l4(dsi, channel);
2503 default: 2438 default:
2504 BUG(); 2439 BUG();
2505 return -EINVAL; 2440 return -EINVAL;
2506 } 2441 }
2507} 2442}
2508 2443
2509static int dsi_vc_enable(struct platform_device *dsidev, int channel, 2444static int dsi_vc_enable(struct dsi_data *dsi, int channel, bool enable)
2510 bool enable)
2511{ 2445{
2512 DSSDBG("dsi_vc_enable channel %d, enable %d\n", 2446 DSSDBG("dsi_vc_enable channel %d, enable %d\n",
2513 channel, enable); 2447 channel, enable);
2514 2448
2515 enable = enable ? 1 : 0; 2449 enable = enable ? 1 : 0;
2516 2450
2517 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 0, 0); 2451 REG_FLD_MOD(dsi, DSI_VC_CTRL(channel), enable, 0, 0);
2518 2452
2519 if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel), 2453 if (!wait_for_bit_change(dsi, DSI_VC_CTRL(channel), 0, enable)) {
2520 0, enable) != enable) { 2454 DSSERR("Failed to set dsi_vc_enable to %d\n", enable);
2521 DSSERR("Failed to set dsi_vc_enable to %d\n", enable); 2455 return -EIO;
2522 return -EIO;
2523 } 2456 }
2524 2457
2525 return 0; 2458 return 0;
2526} 2459}
2527 2460
2528static void dsi_vc_initial_config(struct platform_device *dsidev, int channel) 2461static void dsi_vc_initial_config(struct dsi_data *dsi, int channel)
2529{ 2462{
2530 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2531 u32 r; 2463 u32 r;
2532 2464
2533 DSSDBG("Initial config of virtual channel %d", channel); 2465 DSSDBG("Initial config of virtual channel %d", channel);
2534 2466
2535 r = dsi_read_reg(dsidev, DSI_VC_CTRL(channel)); 2467 r = dsi_read_reg(dsi, DSI_VC_CTRL(channel));
2536 2468
2537 if (FLD_GET(r, 15, 15)) /* VC_BUSY */ 2469 if (FLD_GET(r, 15, 15)) /* VC_BUSY */
2538 DSSERR("VC(%d) busy when trying to configure it!\n", 2470 DSSERR("VC(%d) busy when trying to configure it!\n",
@@ -2551,41 +2483,39 @@ static void dsi_vc_initial_config(struct platform_device *dsidev, int channel)
2551 r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */ 2483 r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */
2552 r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */ 2484 r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */
2553 2485
2554 dsi_write_reg(dsidev, DSI_VC_CTRL(channel), r); 2486 dsi_write_reg(dsi, DSI_VC_CTRL(channel), r);
2555 2487
2556 dsi->vc[channel].source = DSI_VC_SOURCE_L4; 2488 dsi->vc[channel].source = DSI_VC_SOURCE_L4;
2557} 2489}
2558 2490
2559static int dsi_vc_config_source(struct platform_device *dsidev, int channel, 2491static int dsi_vc_config_source(struct dsi_data *dsi, int channel,
2560 enum dsi_vc_source source) 2492 enum dsi_vc_source source)
2561{ 2493{
2562 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2563
2564 if (dsi->vc[channel].source == source) 2494 if (dsi->vc[channel].source == source)
2565 return 0; 2495 return 0;
2566 2496
2567 DSSDBG("Source config of virtual channel %d", channel); 2497 DSSDBG("Source config of virtual channel %d", channel);
2568 2498
2569 dsi_sync_vc(dsidev, channel); 2499 dsi_sync_vc(dsi, channel);
2570 2500
2571 dsi_vc_enable(dsidev, channel, 0); 2501 dsi_vc_enable(dsi, channel, 0);
2572 2502
2573 /* VC_BUSY */ 2503 /* VC_BUSY */
2574 if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel), 15, 0) != 0) { 2504 if (!wait_for_bit_change(dsi, DSI_VC_CTRL(channel), 15, 0)) {
2575 DSSERR("vc(%d) busy when trying to config for VP\n", channel); 2505 DSSERR("vc(%d) busy when trying to config for VP\n", channel);
2576 return -EIO; 2506 return -EIO;
2577 } 2507 }
2578 2508
2579 /* SOURCE, 0 = L4, 1 = video port */ 2509 /* SOURCE, 0 = L4, 1 = video port */
2580 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), source, 1, 1); 2510 REG_FLD_MOD(dsi, DSI_VC_CTRL(channel), source, 1, 1);
2581 2511
2582 /* DCS_CMD_ENABLE */ 2512 /* DCS_CMD_ENABLE */
2583 if (dsi->data->quirks & DSI_QUIRK_DCS_CMD_CONFIG_VC) { 2513 if (dsi->data->quirks & DSI_QUIRK_DCS_CMD_CONFIG_VC) {
2584 bool enable = source == DSI_VC_SOURCE_VP; 2514 bool enable = source == DSI_VC_SOURCE_VP;
2585 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 30, 30); 2515 REG_FLD_MOD(dsi, DSI_VC_CTRL(channel), enable, 30, 30);
2586 } 2516 }
2587 2517
2588 dsi_vc_enable(dsidev, channel, 1); 2518 dsi_vc_enable(dsi, channel, 1);
2589 2519
2590 dsi->vc[channel].source = source; 2520 dsi->vc[channel].source = source;
2591 2521
@@ -2595,33 +2525,32 @@ static int dsi_vc_config_source(struct platform_device *dsidev, int channel,
2595static void dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel, 2525static void dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel,
2596 bool enable) 2526 bool enable)
2597{ 2527{
2598 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 2528 struct dsi_data *dsi = to_dsi_data(dssdev);
2599 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2600 2529
2601 DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel, enable); 2530 DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel, enable);
2602 2531
2603 WARN_ON(!dsi_bus_is_locked(dsidev)); 2532 WARN_ON(!dsi_bus_is_locked(dsi));
2604 2533
2605 dsi_vc_enable(dsidev, channel, 0); 2534 dsi_vc_enable(dsi, channel, 0);
2606 dsi_if_enable(dsidev, 0); 2535 dsi_if_enable(dsi, 0);
2607 2536
2608 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 9, 9); 2537 REG_FLD_MOD(dsi, DSI_VC_CTRL(channel), enable, 9, 9);
2609 2538
2610 dsi_vc_enable(dsidev, channel, 1); 2539 dsi_vc_enable(dsi, channel, 1);
2611 dsi_if_enable(dsidev, 1); 2540 dsi_if_enable(dsi, 1);
2612 2541
2613 dsi_force_tx_stop_mode_io(dsidev); 2542 dsi_force_tx_stop_mode_io(dsi);
2614 2543
2615 /* start the DDR clock by sending a NULL packet */ 2544 /* start the DDR clock by sending a NULL packet */
2616 if (dsi->vm_timings.ddr_clk_always_on && enable) 2545 if (dsi->vm_timings.ddr_clk_always_on && enable)
2617 dsi_vc_send_null(dssdev, channel); 2546 dsi_vc_send_null(dsi, channel);
2618} 2547}
2619 2548
2620static void dsi_vc_flush_long_data(struct platform_device *dsidev, int channel) 2549static void dsi_vc_flush_long_data(struct dsi_data *dsi, int channel)
2621{ 2550{
2622 while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) { 2551 while (REG_GET(dsi, DSI_VC_CTRL(channel), 20, 20)) {
2623 u32 val; 2552 u32 val;
2624 val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel)); 2553 val = dsi_read_reg(dsi, DSI_VC_SHORT_PACKET_HEADER(channel));
2625 DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n", 2554 DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n",
2626 (val >> 0) & 0xff, 2555 (val >> 0) & 0xff,
2627 (val >> 8) & 0xff, 2556 (val >> 8) & 0xff,
@@ -2667,14 +2596,13 @@ static void dsi_show_rx_ack_with_err(u16 err)
2667 DSSERR("\t\tDSI Protocol Violation\n"); 2596 DSSERR("\t\tDSI Protocol Violation\n");
2668} 2597}
2669 2598
2670static u16 dsi_vc_flush_receive_data(struct platform_device *dsidev, 2599static u16 dsi_vc_flush_receive_data(struct dsi_data *dsi, int channel)
2671 int channel)
2672{ 2600{
2673 /* RX_FIFO_NOT_EMPTY */ 2601 /* RX_FIFO_NOT_EMPTY */
2674 while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) { 2602 while (REG_GET(dsi, DSI_VC_CTRL(channel), 20, 20)) {
2675 u32 val; 2603 u32 val;
2676 u8 dt; 2604 u8 dt;
2677 val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel)); 2605 val = dsi_read_reg(dsi, DSI_VC_SHORT_PACKET_HEADER(channel));
2678 DSSERR("\trawval %#08x\n", val); 2606 DSSERR("\trawval %#08x\n", val);
2679 dt = FLD_GET(val, 5, 0); 2607 dt = FLD_GET(val, 5, 0);
2680 if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) { 2608 if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) {
@@ -2689,7 +2617,7 @@ static u16 dsi_vc_flush_receive_data(struct platform_device *dsidev,
2689 } else if (dt == MIPI_DSI_RX_DCS_LONG_READ_RESPONSE) { 2617 } else if (dt == MIPI_DSI_RX_DCS_LONG_READ_RESPONSE) {
2690 DSSERR("\tDCS long response, len %d\n", 2618 DSSERR("\tDCS long response, len %d\n",
2691 FLD_GET(val, 23, 8)); 2619 FLD_GET(val, 23, 8));
2692 dsi_vc_flush_long_data(dsidev, channel); 2620 dsi_vc_flush_long_data(dsi, channel);
2693 } else { 2621 } else {
2694 DSSERR("\tunknown datatype 0x%02x\n", dt); 2622 DSSERR("\tunknown datatype 0x%02x\n", dt);
2695 } 2623 }
@@ -2697,47 +2625,45 @@ static u16 dsi_vc_flush_receive_data(struct platform_device *dsidev,
2697 return 0; 2625 return 0;
2698} 2626}
2699 2627
2700static int dsi_vc_send_bta(struct platform_device *dsidev, int channel) 2628static int dsi_vc_send_bta(struct dsi_data *dsi, int channel)
2701{ 2629{
2702 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2703
2704 if (dsi->debug_write || dsi->debug_read) 2630 if (dsi->debug_write || dsi->debug_read)
2705 DSSDBG("dsi_vc_send_bta %d\n", channel); 2631 DSSDBG("dsi_vc_send_bta %d\n", channel);
2706 2632
2707 WARN_ON(!dsi_bus_is_locked(dsidev)); 2633 WARN_ON(!dsi_bus_is_locked(dsi));
2708 2634
2709 /* RX_FIFO_NOT_EMPTY */ 2635 /* RX_FIFO_NOT_EMPTY */
2710 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) { 2636 if (REG_GET(dsi, DSI_VC_CTRL(channel), 20, 20)) {
2711 DSSERR("rx fifo not empty when sending BTA, dumping data:\n"); 2637 DSSERR("rx fifo not empty when sending BTA, dumping data:\n");
2712 dsi_vc_flush_receive_data(dsidev, channel); 2638 dsi_vc_flush_receive_data(dsi, channel);
2713 } 2639 }
2714 2640
2715 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */ 2641 REG_FLD_MOD(dsi, DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */
2716 2642
2717 /* flush posted write */ 2643 /* flush posted write */
2718 dsi_read_reg(dsidev, DSI_VC_CTRL(channel)); 2644 dsi_read_reg(dsi, DSI_VC_CTRL(channel));
2719 2645
2720 return 0; 2646 return 0;
2721} 2647}
2722 2648
2723static int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel) 2649static int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel)
2724{ 2650{
2725 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 2651 struct dsi_data *dsi = to_dsi_data(dssdev);
2726 DECLARE_COMPLETION_ONSTACK(completion); 2652 DECLARE_COMPLETION_ONSTACK(completion);
2727 int r = 0; 2653 int r = 0;
2728 u32 err; 2654 u32 err;
2729 2655
2730 r = dsi_register_isr_vc(dsidev, channel, dsi_completion_handler, 2656 r = dsi_register_isr_vc(dsi, channel, dsi_completion_handler,
2731 &completion, DSI_VC_IRQ_BTA); 2657 &completion, DSI_VC_IRQ_BTA);
2732 if (r) 2658 if (r)
2733 goto err0; 2659 goto err0;
2734 2660
2735 r = dsi_register_isr(dsidev, dsi_completion_handler, &completion, 2661 r = dsi_register_isr(dsi, dsi_completion_handler, &completion,
2736 DSI_IRQ_ERROR_MASK); 2662 DSI_IRQ_ERROR_MASK);
2737 if (r) 2663 if (r)
2738 goto err1; 2664 goto err1;
2739 2665
2740 r = dsi_vc_send_bta(dsidev, channel); 2666 r = dsi_vc_send_bta(dsi, channel);
2741 if (r) 2667 if (r)
2742 goto err2; 2668 goto err2;
2743 2669
@@ -2748,41 +2674,40 @@ static int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel)
2748 goto err2; 2674 goto err2;
2749 } 2675 }
2750 2676
2751 err = dsi_get_errors(dsidev); 2677 err = dsi_get_errors(dsi);
2752 if (err) { 2678 if (err) {
2753 DSSERR("Error while sending BTA: %x\n", err); 2679 DSSERR("Error while sending BTA: %x\n", err);
2754 r = -EIO; 2680 r = -EIO;
2755 goto err2; 2681 goto err2;
2756 } 2682 }
2757err2: 2683err2:
2758 dsi_unregister_isr(dsidev, dsi_completion_handler, &completion, 2684 dsi_unregister_isr(dsi, dsi_completion_handler, &completion,
2759 DSI_IRQ_ERROR_MASK); 2685 DSI_IRQ_ERROR_MASK);
2760err1: 2686err1:
2761 dsi_unregister_isr_vc(dsidev, channel, dsi_completion_handler, 2687 dsi_unregister_isr_vc(dsi, channel, dsi_completion_handler,
2762 &completion, DSI_VC_IRQ_BTA); 2688 &completion, DSI_VC_IRQ_BTA);
2763err0: 2689err0:
2764 return r; 2690 return r;
2765} 2691}
2766 2692
2767static inline void dsi_vc_write_long_header(struct platform_device *dsidev, 2693static inline void dsi_vc_write_long_header(struct dsi_data *dsi, int channel,
2768 int channel, u8 data_type, u16 len, u8 ecc) 2694 u8 data_type, u16 len, u8 ecc)
2769{ 2695{
2770 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2771 u32 val; 2696 u32 val;
2772 u8 data_id; 2697 u8 data_id;
2773 2698
2774 WARN_ON(!dsi_bus_is_locked(dsidev)); 2699 WARN_ON(!dsi_bus_is_locked(dsi));
2775 2700
2776 data_id = data_type | dsi->vc[channel].vc_id << 6; 2701 data_id = data_type | dsi->vc[channel].vc_id << 6;
2777 2702
2778 val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) | 2703 val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) |
2779 FLD_VAL(ecc, 31, 24); 2704 FLD_VAL(ecc, 31, 24);
2780 2705
2781 dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_HEADER(channel), val); 2706 dsi_write_reg(dsi, DSI_VC_LONG_PACKET_HEADER(channel), val);
2782} 2707}
2783 2708
2784static inline void dsi_vc_write_long_payload(struct platform_device *dsidev, 2709static inline void dsi_vc_write_long_payload(struct dsi_data *dsi, int channel,
2785 int channel, u8 b1, u8 b2, u8 b3, u8 b4) 2710 u8 b1, u8 b2, u8 b3, u8 b4)
2786{ 2711{
2787 u32 val; 2712 u32 val;
2788 2713
@@ -2791,14 +2716,13 @@ static inline void dsi_vc_write_long_payload(struct platform_device *dsidev,
2791/* DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n", 2716/* DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n",
2792 b1, b2, b3, b4, val); */ 2717 b1, b2, b3, b4, val); */
2793 2718
2794 dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_PAYLOAD(channel), val); 2719 dsi_write_reg(dsi, DSI_VC_LONG_PACKET_PAYLOAD(channel), val);
2795} 2720}
2796 2721
2797static int dsi_vc_send_long(struct platform_device *dsidev, int channel, 2722static int dsi_vc_send_long(struct dsi_data *dsi, int channel, u8 data_type,
2798 u8 data_type, u8 *data, u16 len, u8 ecc) 2723 u8 *data, u16 len, u8 ecc)
2799{ 2724{
2800 /*u32 val; */ 2725 /*u32 val; */
2801 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2802 int i; 2726 int i;
2803 u8 *p; 2727 u8 *p;
2804 int r = 0; 2728 int r = 0;
@@ -2813,9 +2737,9 @@ static int dsi_vc_send_long(struct platform_device *dsidev, int channel,
2813 return -EINVAL; 2737 return -EINVAL;
2814 } 2738 }
2815 2739
2816 dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_L4); 2740 dsi_vc_config_source(dsi, channel, DSI_VC_SOURCE_L4);
2817 2741
2818 dsi_vc_write_long_header(dsidev, channel, data_type, len, ecc); 2742 dsi_vc_write_long_header(dsi, channel, data_type, len, ecc);
2819 2743
2820 p = data; 2744 p = data;
2821 for (i = 0; i < len >> 2; i++) { 2745 for (i = 0; i < len >> 2; i++) {
@@ -2827,7 +2751,7 @@ static int dsi_vc_send_long(struct platform_device *dsidev, int channel,
2827 b3 = *p++; 2751 b3 = *p++;
2828 b4 = *p++; 2752 b4 = *p++;
2829 2753
2830 dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, b4); 2754 dsi_vc_write_long_payload(dsi, channel, b1, b2, b3, b4);
2831 } 2755 }
2832 2756
2833 i = len % 4; 2757 i = len % 4;
@@ -2852,29 +2776,28 @@ static int dsi_vc_send_long(struct platform_device *dsidev, int channel,
2852 break; 2776 break;
2853 } 2777 }
2854 2778
2855 dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, 0); 2779 dsi_vc_write_long_payload(dsi, channel, b1, b2, b3, 0);
2856 } 2780 }
2857 2781
2858 return r; 2782 return r;
2859} 2783}
2860 2784
2861static int dsi_vc_send_short(struct platform_device *dsidev, int channel, 2785static int dsi_vc_send_short(struct dsi_data *dsi, int channel, u8 data_type,
2862 u8 data_type, u16 data, u8 ecc) 2786 u16 data, u8 ecc)
2863{ 2787{
2864 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2865 u32 r; 2788 u32 r;
2866 u8 data_id; 2789 u8 data_id;
2867 2790
2868 WARN_ON(!dsi_bus_is_locked(dsidev)); 2791 WARN_ON(!dsi_bus_is_locked(dsi));
2869 2792
2870 if (dsi->debug_write) 2793 if (dsi->debug_write)
2871 DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n", 2794 DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n",
2872 channel, 2795 channel,
2873 data_type, data & 0xff, (data >> 8) & 0xff); 2796 data_type, data & 0xff, (data >> 8) & 0xff);
2874 2797
2875 dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_L4); 2798 dsi_vc_config_source(dsi, channel, DSI_VC_SOURCE_L4);
2876 2799
2877 if (FLD_GET(dsi_read_reg(dsidev, DSI_VC_CTRL(channel)), 16, 16)) { 2800 if (FLD_GET(dsi_read_reg(dsi, DSI_VC_CTRL(channel)), 16, 16)) {
2878 DSSERR("ERROR FIFO FULL, aborting transfer\n"); 2801 DSSERR("ERROR FIFO FULL, aborting transfer\n");
2879 return -EINVAL; 2802 return -EINVAL;
2880 } 2803 }
@@ -2883,41 +2806,39 @@ static int dsi_vc_send_short(struct platform_device *dsidev, int channel,
2883 2806
2884 r = (data_id << 0) | (data << 8) | (ecc << 24); 2807 r = (data_id << 0) | (data << 8) | (ecc << 24);
2885 2808
2886 dsi_write_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel), r); 2809 dsi_write_reg(dsi, DSI_VC_SHORT_PACKET_HEADER(channel), r);
2887 2810
2888 return 0; 2811 return 0;
2889} 2812}
2890 2813
2891static int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel) 2814static int dsi_vc_send_null(struct dsi_data *dsi, int channel)
2892{ 2815{
2893 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 2816 return dsi_vc_send_long(dsi, channel, MIPI_DSI_NULL_PACKET, NULL, 0, 0);
2894
2895 return dsi_vc_send_long(dsidev, channel, MIPI_DSI_NULL_PACKET, NULL,
2896 0, 0);
2897} 2817}
2898 2818
2899static int dsi_vc_write_nosync_common(struct platform_device *dsidev, 2819static int dsi_vc_write_nosync_common(struct dsi_data *dsi, int channel,
2900 int channel, u8 *data, int len, enum dss_dsi_content_type type) 2820 u8 *data, int len,
2821 enum dss_dsi_content_type type)
2901{ 2822{
2902 int r; 2823 int r;
2903 2824
2904 if (len == 0) { 2825 if (len == 0) {
2905 BUG_ON(type == DSS_DSI_CONTENT_DCS); 2826 BUG_ON(type == DSS_DSI_CONTENT_DCS);
2906 r = dsi_vc_send_short(dsidev, channel, 2827 r = dsi_vc_send_short(dsi, channel,
2907 MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM, 0, 0); 2828 MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM, 0, 0);
2908 } else if (len == 1) { 2829 } else if (len == 1) {
2909 r = dsi_vc_send_short(dsidev, channel, 2830 r = dsi_vc_send_short(dsi, channel,
2910 type == DSS_DSI_CONTENT_GENERIC ? 2831 type == DSS_DSI_CONTENT_GENERIC ?
2911 MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM : 2832 MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM :
2912 MIPI_DSI_DCS_SHORT_WRITE, data[0], 0); 2833 MIPI_DSI_DCS_SHORT_WRITE, data[0], 0);
2913 } else if (len == 2) { 2834 } else if (len == 2) {
2914 r = dsi_vc_send_short(dsidev, channel, 2835 r = dsi_vc_send_short(dsi, channel,
2915 type == DSS_DSI_CONTENT_GENERIC ? 2836 type == DSS_DSI_CONTENT_GENERIC ?
2916 MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM : 2837 MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM :
2917 MIPI_DSI_DCS_SHORT_WRITE_PARAM, 2838 MIPI_DSI_DCS_SHORT_WRITE_PARAM,
2918 data[0] | (data[1] << 8), 0); 2839 data[0] | (data[1] << 8), 0);
2919 } else { 2840 } else {
2920 r = dsi_vc_send_long(dsidev, channel, 2841 r = dsi_vc_send_long(dsi, channel,
2921 type == DSS_DSI_CONTENT_GENERIC ? 2842 type == DSS_DSI_CONTENT_GENERIC ?
2922 MIPI_DSI_GENERIC_LONG_WRITE : 2843 MIPI_DSI_GENERIC_LONG_WRITE :
2923 MIPI_DSI_DCS_LONG_WRITE, data, len, 0); 2844 MIPI_DSI_DCS_LONG_WRITE, data, len, 0);
@@ -2929,28 +2850,29 @@ static int dsi_vc_write_nosync_common(struct platform_device *dsidev,
2929static int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel, 2850static int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel,
2930 u8 *data, int len) 2851 u8 *data, int len)
2931{ 2852{
2932 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 2853 struct dsi_data *dsi = to_dsi_data(dssdev);
2933 2854
2934 return dsi_vc_write_nosync_common(dsidev, channel, data, len, 2855 return dsi_vc_write_nosync_common(dsi, channel, data, len,
2935 DSS_DSI_CONTENT_DCS); 2856 DSS_DSI_CONTENT_DCS);
2936} 2857}
2937 2858
2938static int dsi_vc_generic_write_nosync(struct omap_dss_device *dssdev, int channel, 2859static int dsi_vc_generic_write_nosync(struct omap_dss_device *dssdev, int channel,
2939 u8 *data, int len) 2860 u8 *data, int len)
2940{ 2861{
2941 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 2862 struct dsi_data *dsi = to_dsi_data(dssdev);
2942 2863
2943 return dsi_vc_write_nosync_common(dsidev, channel, data, len, 2864 return dsi_vc_write_nosync_common(dsi, channel, data, len,
2944 DSS_DSI_CONTENT_GENERIC); 2865 DSS_DSI_CONTENT_GENERIC);
2945} 2866}
2946 2867
2947static int dsi_vc_write_common(struct omap_dss_device *dssdev, int channel, 2868static int dsi_vc_write_common(struct omap_dss_device *dssdev,
2948 u8 *data, int len, enum dss_dsi_content_type type) 2869 int channel, u8 *data, int len,
2870 enum dss_dsi_content_type type)
2949{ 2871{
2950 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 2872 struct dsi_data *dsi = to_dsi_data(dssdev);
2951 int r; 2873 int r;
2952 2874
2953 r = dsi_vc_write_nosync_common(dsidev, channel, data, len, type); 2875 r = dsi_vc_write_nosync_common(dsi, channel, data, len, type);
2954 if (r) 2876 if (r)
2955 goto err; 2877 goto err;
2956 2878
@@ -2959,9 +2881,9 @@ static int dsi_vc_write_common(struct omap_dss_device *dssdev, int channel,
2959 goto err; 2881 goto err;
2960 2882
2961 /* RX_FIFO_NOT_EMPTY */ 2883 /* RX_FIFO_NOT_EMPTY */
2962 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) { 2884 if (REG_GET(dsi, DSI_VC_CTRL(channel), 20, 20)) {
2963 DSSERR("rx fifo not empty after write, dumping data:\n"); 2885 DSSERR("rx fifo not empty after write, dumping data:\n");
2964 dsi_vc_flush_receive_data(dsidev, channel); 2886 dsi_vc_flush_receive_data(dsi, channel);
2965 r = -EIO; 2887 r = -EIO;
2966 goto err; 2888 goto err;
2967 } 2889 }
@@ -2987,17 +2909,16 @@ static int dsi_vc_generic_write(struct omap_dss_device *dssdev, int channel, u8
2987 DSS_DSI_CONTENT_GENERIC); 2909 DSS_DSI_CONTENT_GENERIC);
2988} 2910}
2989 2911
2990static int dsi_vc_dcs_send_read_request(struct platform_device *dsidev, 2912static int dsi_vc_dcs_send_read_request(struct dsi_data *dsi, int channel,
2991 int channel, u8 dcs_cmd) 2913 u8 dcs_cmd)
2992{ 2914{
2993 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2994 int r; 2915 int r;
2995 2916
2996 if (dsi->debug_read) 2917 if (dsi->debug_read)
2997 DSSDBG("dsi_vc_dcs_send_read_request(ch%d, dcs_cmd %x)\n", 2918 DSSDBG("dsi_vc_dcs_send_read_request(ch%d, dcs_cmd %x)\n",
2998 channel, dcs_cmd); 2919 channel, dcs_cmd);
2999 2920
3000 r = dsi_vc_send_short(dsidev, channel, MIPI_DSI_DCS_READ, dcs_cmd, 0); 2921 r = dsi_vc_send_short(dsi, channel, MIPI_DSI_DCS_READ, dcs_cmd, 0);
3001 if (r) { 2922 if (r) {
3002 DSSERR("dsi_vc_dcs_send_read_request(ch %d, cmd 0x%02x)" 2923 DSSERR("dsi_vc_dcs_send_read_request(ch %d, cmd 0x%02x)"
3003 " failed\n", channel, dcs_cmd); 2924 " failed\n", channel, dcs_cmd);
@@ -3007,10 +2928,9 @@ static int dsi_vc_dcs_send_read_request(struct platform_device *dsidev,
3007 return 0; 2928 return 0;
3008} 2929}
3009 2930
3010static int dsi_vc_generic_send_read_request(struct platform_device *dsidev, 2931static int dsi_vc_generic_send_read_request(struct dsi_data *dsi, int channel,
3011 int channel, u8 *reqdata, int reqlen) 2932 u8 *reqdata, int reqlen)
3012{ 2933{
3013 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3014 u16 data; 2934 u16 data;
3015 u8 data_type; 2935 u8 data_type;
3016 int r; 2936 int r;
@@ -3033,7 +2953,7 @@ static int dsi_vc_generic_send_read_request(struct platform_device *dsidev,
3033 return -EINVAL; 2953 return -EINVAL;
3034 } 2954 }
3035 2955
3036 r = dsi_vc_send_short(dsidev, channel, data_type, data, 0); 2956 r = dsi_vc_send_short(dsi, channel, data_type, data, 0);
3037 if (r) { 2957 if (r) {
3038 DSSERR("dsi_vc_generic_send_read_request(ch %d, reqlen %d)" 2958 DSSERR("dsi_vc_generic_send_read_request(ch %d, reqlen %d)"
3039 " failed\n", channel, reqlen); 2959 " failed\n", channel, reqlen);
@@ -3043,22 +2963,21 @@ static int dsi_vc_generic_send_read_request(struct platform_device *dsidev,
3043 return 0; 2963 return 0;
3044} 2964}
3045 2965
3046static int dsi_vc_read_rx_fifo(struct platform_device *dsidev, int channel, 2966static int dsi_vc_read_rx_fifo(struct dsi_data *dsi, int channel, u8 *buf,
3047 u8 *buf, int buflen, enum dss_dsi_content_type type) 2967 int buflen, enum dss_dsi_content_type type)
3048{ 2968{
3049 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3050 u32 val; 2969 u32 val;
3051 u8 dt; 2970 u8 dt;
3052 int r; 2971 int r;
3053 2972
3054 /* RX_FIFO_NOT_EMPTY */ 2973 /* RX_FIFO_NOT_EMPTY */
3055 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20) == 0) { 2974 if (REG_GET(dsi, DSI_VC_CTRL(channel), 20, 20) == 0) {
3056 DSSERR("RX fifo empty when trying to read.\n"); 2975 DSSERR("RX fifo empty when trying to read.\n");
3057 r = -EIO; 2976 r = -EIO;
3058 goto err; 2977 goto err;
3059 } 2978 }
3060 2979
3061 val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel)); 2980 val = dsi_read_reg(dsi, DSI_VC_SHORT_PACKET_HEADER(channel));
3062 if (dsi->debug_read) 2981 if (dsi->debug_read)
3063 DSSDBG("\theader: %08x\n", val); 2982 DSSDBG("\theader: %08x\n", val);
3064 dt = FLD_GET(val, 5, 0); 2983 dt = FLD_GET(val, 5, 0);
@@ -3121,7 +3040,7 @@ static int dsi_vc_read_rx_fifo(struct platform_device *dsidev, int channel,
3121 /* two byte checksum ends the packet, not included in len */ 3040 /* two byte checksum ends the packet, not included in len */
3122 for (w = 0; w < len + 2;) { 3041 for (w = 0; w < len + 2;) {
3123 int b; 3042 int b;
3124 val = dsi_read_reg(dsidev, 3043 val = dsi_read_reg(dsi,
3125 DSI_VC_SHORT_PACKET_HEADER(channel)); 3044 DSI_VC_SHORT_PACKET_HEADER(channel));
3126 if (dsi->debug_read) 3045 if (dsi->debug_read)
3127 DSSDBG("\t\t%02x %02x %02x %02x\n", 3046 DSSDBG("\t\t%02x %02x %02x %02x\n",
@@ -3155,10 +3074,10 @@ err:
3155static int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd, 3074static int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
3156 u8 *buf, int buflen) 3075 u8 *buf, int buflen)
3157{ 3076{
3158 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 3077 struct dsi_data *dsi = to_dsi_data(dssdev);
3159 int r; 3078 int r;
3160 3079
3161 r = dsi_vc_dcs_send_read_request(dsidev, channel, dcs_cmd); 3080 r = dsi_vc_dcs_send_read_request(dsi, channel, dcs_cmd);
3162 if (r) 3081 if (r)
3163 goto err; 3082 goto err;
3164 3083
@@ -3166,7 +3085,7 @@ static int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_c
3166 if (r) 3085 if (r)
3167 goto err; 3086 goto err;
3168 3087
3169 r = dsi_vc_read_rx_fifo(dsidev, channel, buf, buflen, 3088 r = dsi_vc_read_rx_fifo(dsi, channel, buf, buflen,
3170 DSS_DSI_CONTENT_DCS); 3089 DSS_DSI_CONTENT_DCS);
3171 if (r < 0) 3090 if (r < 0)
3172 goto err; 3091 goto err;
@@ -3185,10 +3104,10 @@ err:
3185static int dsi_vc_generic_read(struct omap_dss_device *dssdev, int channel, 3104static int dsi_vc_generic_read(struct omap_dss_device *dssdev, int channel,
3186 u8 *reqdata, int reqlen, u8 *buf, int buflen) 3105 u8 *reqdata, int reqlen, u8 *buf, int buflen)
3187{ 3106{
3188 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 3107 struct dsi_data *dsi = to_dsi_data(dssdev);
3189 int r; 3108 int r;
3190 3109
3191 r = dsi_vc_generic_send_read_request(dsidev, channel, reqdata, reqlen); 3110 r = dsi_vc_generic_send_read_request(dsi, channel, reqdata, reqlen);
3192 if (r) 3111 if (r)
3193 return r; 3112 return r;
3194 3113
@@ -3196,7 +3115,7 @@ static int dsi_vc_generic_read(struct omap_dss_device *dssdev, int channel,
3196 if (r) 3115 if (r)
3197 return r; 3116 return r;
3198 3117
3199 r = dsi_vc_read_rx_fifo(dsidev, channel, buf, buflen, 3118 r = dsi_vc_read_rx_fifo(dsi, channel, buf, buflen,
3200 DSS_DSI_CONTENT_GENERIC); 3119 DSS_DSI_CONTENT_GENERIC);
3201 if (r < 0) 3120 if (r < 0)
3202 return r; 3121 return r;
@@ -3212,22 +3131,21 @@ static int dsi_vc_generic_read(struct omap_dss_device *dssdev, int channel,
3212static int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel, 3131static int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel,
3213 u16 len) 3132 u16 len)
3214{ 3133{
3215 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 3134 struct dsi_data *dsi = to_dsi_data(dssdev);
3216 3135
3217 return dsi_vc_send_short(dsidev, channel, 3136 return dsi_vc_send_short(dsi, channel,
3218 MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, len, 0); 3137 MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, len, 0);
3219} 3138}
3220 3139
3221static int dsi_enter_ulps(struct platform_device *dsidev) 3140static int dsi_enter_ulps(struct dsi_data *dsi)
3222{ 3141{
3223 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3224 DECLARE_COMPLETION_ONSTACK(completion); 3142 DECLARE_COMPLETION_ONSTACK(completion);
3225 int r, i; 3143 int r, i;
3226 unsigned mask; 3144 unsigned int mask;
3227 3145
3228 DSSDBG("Entering ULPS"); 3146 DSSDBG("Entering ULPS");
3229 3147
3230 WARN_ON(!dsi_bus_is_locked(dsidev)); 3148 WARN_ON(!dsi_bus_is_locked(dsi));
3231 3149
3232 WARN_ON(dsi->ulps_enabled); 3150 WARN_ON(dsi->ulps_enabled);
3233 3151
@@ -3235,35 +3153,35 @@ static int dsi_enter_ulps(struct platform_device *dsidev)
3235 return 0; 3153 return 0;
3236 3154
3237 /* DDR_CLK_ALWAYS_ON */ 3155 /* DDR_CLK_ALWAYS_ON */
3238 if (REG_GET(dsidev, DSI_CLK_CTRL, 13, 13)) { 3156 if (REG_GET(dsi, DSI_CLK_CTRL, 13, 13)) {
3239 dsi_if_enable(dsidev, 0); 3157 dsi_if_enable(dsi, 0);
3240 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 13, 13); 3158 REG_FLD_MOD(dsi, DSI_CLK_CTRL, 0, 13, 13);
3241 dsi_if_enable(dsidev, 1); 3159 dsi_if_enable(dsi, 1);
3242 } 3160 }
3243 3161
3244 dsi_sync_vc(dsidev, 0); 3162 dsi_sync_vc(dsi, 0);
3245 dsi_sync_vc(dsidev, 1); 3163 dsi_sync_vc(dsi, 1);
3246 dsi_sync_vc(dsidev, 2); 3164 dsi_sync_vc(dsi, 2);
3247 dsi_sync_vc(dsidev, 3); 3165 dsi_sync_vc(dsi, 3);
3248 3166
3249 dsi_force_tx_stop_mode_io(dsidev); 3167 dsi_force_tx_stop_mode_io(dsi);
3250 3168
3251 dsi_vc_enable(dsidev, 0, false); 3169 dsi_vc_enable(dsi, 0, false);
3252 dsi_vc_enable(dsidev, 1, false); 3170 dsi_vc_enable(dsi, 1, false);
3253 dsi_vc_enable(dsidev, 2, false); 3171 dsi_vc_enable(dsi, 2, false);
3254 dsi_vc_enable(dsidev, 3, false); 3172 dsi_vc_enable(dsi, 3, false);
3255 3173
3256 if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 16, 16)) { /* HS_BUSY */ 3174 if (REG_GET(dsi, DSI_COMPLEXIO_CFG2, 16, 16)) { /* HS_BUSY */
3257 DSSERR("HS busy when enabling ULPS\n"); 3175 DSSERR("HS busy when enabling ULPS\n");
3258 return -EIO; 3176 return -EIO;
3259 } 3177 }
3260 3178
3261 if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 17, 17)) { /* LP_BUSY */ 3179 if (REG_GET(dsi, DSI_COMPLEXIO_CFG2, 17, 17)) { /* LP_BUSY */
3262 DSSERR("LP busy when enabling ULPS\n"); 3180 DSSERR("LP busy when enabling ULPS\n");
3263 return -EIO; 3181 return -EIO;
3264 } 3182 }
3265 3183
3266 r = dsi_register_isr_cio(dsidev, dsi_completion_handler, &completion, 3184 r = dsi_register_isr_cio(dsi, dsi_completion_handler, &completion,
3267 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0); 3185 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3268 if (r) 3186 if (r)
3269 return r; 3187 return r;
@@ -3277,10 +3195,10 @@ static int dsi_enter_ulps(struct platform_device *dsidev)
3277 } 3195 }
3278 /* Assert TxRequestEsc for data lanes and TxUlpsClk for clk lane */ 3196 /* Assert TxRequestEsc for data lanes and TxUlpsClk for clk lane */
3279 /* LANEx_ULPS_SIG2 */ 3197 /* LANEx_ULPS_SIG2 */
3280 REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, mask, 9, 5); 3198 REG_FLD_MOD(dsi, DSI_COMPLEXIO_CFG2, mask, 9, 5);
3281 3199
3282 /* flush posted write and wait for SCP interface to finish the write */ 3200 /* flush posted write and wait for SCP interface to finish the write */
3283 dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG2); 3201 dsi_read_reg(dsi, DSI_COMPLEXIO_CFG2);
3284 3202
3285 if (wait_for_completion_timeout(&completion, 3203 if (wait_for_completion_timeout(&completion,
3286 msecs_to_jiffies(1000)) == 0) { 3204 msecs_to_jiffies(1000)) == 0) {
@@ -3289,31 +3207,31 @@ static int dsi_enter_ulps(struct platform_device *dsidev)
3289 goto err; 3207 goto err;
3290 } 3208 }
3291 3209
3292 dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion, 3210 dsi_unregister_isr_cio(dsi, dsi_completion_handler, &completion,
3293 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0); 3211 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3294 3212
3295 /* Reset LANEx_ULPS_SIG2 */ 3213 /* Reset LANEx_ULPS_SIG2 */
3296 REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, 0, 9, 5); 3214 REG_FLD_MOD(dsi, DSI_COMPLEXIO_CFG2, 0, 9, 5);
3297 3215
3298 /* flush posted write and wait for SCP interface to finish the write */ 3216 /* flush posted write and wait for SCP interface to finish the write */
3299 dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG2); 3217 dsi_read_reg(dsi, DSI_COMPLEXIO_CFG2);
3300 3218
3301 dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ULPS); 3219 dsi_cio_power(dsi, DSI_COMPLEXIO_POWER_ULPS);
3302 3220
3303 dsi_if_enable(dsidev, false); 3221 dsi_if_enable(dsi, false);
3304 3222
3305 dsi->ulps_enabled = true; 3223 dsi->ulps_enabled = true;
3306 3224
3307 return 0; 3225 return 0;
3308 3226
3309err: 3227err:
3310 dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion, 3228 dsi_unregister_isr_cio(dsi, dsi_completion_handler, &completion,
3311 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0); 3229 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3312 return r; 3230 return r;
3313} 3231}
3314 3232
3315static void dsi_set_lp_rx_timeout(struct platform_device *dsidev, 3233static void dsi_set_lp_rx_timeout(struct dsi_data *dsi, unsigned int ticks,
3316 unsigned ticks, bool x4, bool x16) 3234 bool x4, bool x16)
3317{ 3235{
3318 unsigned long fck; 3236 unsigned long fck;
3319 unsigned long total_ticks; 3237 unsigned long total_ticks;
@@ -3322,14 +3240,14 @@ static void dsi_set_lp_rx_timeout(struct platform_device *dsidev,
3322 BUG_ON(ticks > 0x1fff); 3240 BUG_ON(ticks > 0x1fff);
3323 3241
3324 /* ticks in DSI_FCK */ 3242 /* ticks in DSI_FCK */
3325 fck = dsi_fclk_rate(dsidev); 3243 fck = dsi_fclk_rate(dsi);
3326 3244
3327 r = dsi_read_reg(dsidev, DSI_TIMING2); 3245 r = dsi_read_reg(dsi, DSI_TIMING2);
3328 r = FLD_MOD(r, 1, 15, 15); /* LP_RX_TO */ 3246 r = FLD_MOD(r, 1, 15, 15); /* LP_RX_TO */
3329 r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* LP_RX_TO_X16 */ 3247 r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* LP_RX_TO_X16 */
3330 r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* LP_RX_TO_X4 */ 3248 r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* LP_RX_TO_X4 */
3331 r = FLD_MOD(r, ticks, 12, 0); /* LP_RX_COUNTER */ 3249 r = FLD_MOD(r, ticks, 12, 0); /* LP_RX_COUNTER */
3332 dsi_write_reg(dsidev, DSI_TIMING2, r); 3250 dsi_write_reg(dsi, DSI_TIMING2, r);
3333 3251
3334 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1); 3252 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3335 3253
@@ -3339,8 +3257,8 @@ static void dsi_set_lp_rx_timeout(struct platform_device *dsidev,
3339 (total_ticks * 1000) / (fck / 1000 / 1000)); 3257 (total_ticks * 1000) / (fck / 1000 / 1000));
3340} 3258}
3341 3259
3342static void dsi_set_ta_timeout(struct platform_device *dsidev, unsigned ticks, 3260static void dsi_set_ta_timeout(struct dsi_data *dsi, unsigned int ticks,
3343 bool x8, bool x16) 3261 bool x8, bool x16)
3344{ 3262{
3345 unsigned long fck; 3263 unsigned long fck;
3346 unsigned long total_ticks; 3264 unsigned long total_ticks;
@@ -3349,14 +3267,14 @@ static void dsi_set_ta_timeout(struct platform_device *dsidev, unsigned ticks,
3349 BUG_ON(ticks > 0x1fff); 3267 BUG_ON(ticks > 0x1fff);
3350 3268
3351 /* ticks in DSI_FCK */ 3269 /* ticks in DSI_FCK */
3352 fck = dsi_fclk_rate(dsidev); 3270 fck = dsi_fclk_rate(dsi);
3353 3271
3354 r = dsi_read_reg(dsidev, DSI_TIMING1); 3272 r = dsi_read_reg(dsi, DSI_TIMING1);
3355 r = FLD_MOD(r, 1, 31, 31); /* TA_TO */ 3273 r = FLD_MOD(r, 1, 31, 31); /* TA_TO */
3356 r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* TA_TO_X16 */ 3274 r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* TA_TO_X16 */
3357 r = FLD_MOD(r, x8 ? 1 : 0, 29, 29); /* TA_TO_X8 */ 3275 r = FLD_MOD(r, x8 ? 1 : 0, 29, 29); /* TA_TO_X8 */
3358 r = FLD_MOD(r, ticks, 28, 16); /* TA_TO_COUNTER */ 3276 r = FLD_MOD(r, ticks, 28, 16); /* TA_TO_COUNTER */
3359 dsi_write_reg(dsidev, DSI_TIMING1, r); 3277 dsi_write_reg(dsi, DSI_TIMING1, r);
3360 3278
3361 total_ticks = ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1); 3279 total_ticks = ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1);
3362 3280
@@ -3366,8 +3284,8 @@ static void dsi_set_ta_timeout(struct platform_device *dsidev, unsigned ticks,
3366 (total_ticks * 1000) / (fck / 1000 / 1000)); 3284 (total_ticks * 1000) / (fck / 1000 / 1000));
3367} 3285}
3368 3286
3369static void dsi_set_stop_state_counter(struct platform_device *dsidev, 3287static void dsi_set_stop_state_counter(struct dsi_data *dsi, unsigned int ticks,
3370 unsigned ticks, bool x4, bool x16) 3288 bool x4, bool x16)
3371{ 3289{
3372 unsigned long fck; 3290 unsigned long fck;
3373 unsigned long total_ticks; 3291 unsigned long total_ticks;
@@ -3376,14 +3294,14 @@ static void dsi_set_stop_state_counter(struct platform_device *dsidev,
3376 BUG_ON(ticks > 0x1fff); 3294 BUG_ON(ticks > 0x1fff);
3377 3295
3378 /* ticks in DSI_FCK */ 3296 /* ticks in DSI_FCK */
3379 fck = dsi_fclk_rate(dsidev); 3297 fck = dsi_fclk_rate(dsi);
3380 3298
3381 r = dsi_read_reg(dsidev, DSI_TIMING1); 3299 r = dsi_read_reg(dsi, DSI_TIMING1);
3382 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */ 3300 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
3383 r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* STOP_STATE_X16_IO */ 3301 r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* STOP_STATE_X16_IO */
3384 r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* STOP_STATE_X4_IO */ 3302 r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* STOP_STATE_X4_IO */
3385 r = FLD_MOD(r, ticks, 12, 0); /* STOP_STATE_COUNTER_IO */ 3303 r = FLD_MOD(r, ticks, 12, 0); /* STOP_STATE_COUNTER_IO */
3386 dsi_write_reg(dsidev, DSI_TIMING1, r); 3304 dsi_write_reg(dsi, DSI_TIMING1, r);
3387 3305
3388 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1); 3306 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3389 3307
@@ -3393,8 +3311,8 @@ static void dsi_set_stop_state_counter(struct platform_device *dsidev,
3393 (total_ticks * 1000) / (fck / 1000 / 1000)); 3311 (total_ticks * 1000) / (fck / 1000 / 1000));
3394} 3312}
3395 3313
3396static void dsi_set_hs_tx_timeout(struct platform_device *dsidev, 3314static void dsi_set_hs_tx_timeout(struct dsi_data *dsi, unsigned int ticks,
3397 unsigned ticks, bool x4, bool x16) 3315 bool x4, bool x16)
3398{ 3316{
3399 unsigned long fck; 3317 unsigned long fck;
3400 unsigned long total_ticks; 3318 unsigned long total_ticks;
@@ -3403,14 +3321,14 @@ static void dsi_set_hs_tx_timeout(struct platform_device *dsidev,
3403 BUG_ON(ticks > 0x1fff); 3321 BUG_ON(ticks > 0x1fff);
3404 3322
3405 /* ticks in TxByteClkHS */ 3323 /* ticks in TxByteClkHS */
3406 fck = dsi_get_txbyteclkhs(dsidev); 3324 fck = dsi_get_txbyteclkhs(dsi);
3407 3325
3408 r = dsi_read_reg(dsidev, DSI_TIMING2); 3326 r = dsi_read_reg(dsi, DSI_TIMING2);
3409 r = FLD_MOD(r, 1, 31, 31); /* HS_TX_TO */ 3327 r = FLD_MOD(r, 1, 31, 31); /* HS_TX_TO */
3410 r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* HS_TX_TO_X16 */ 3328 r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* HS_TX_TO_X16 */
3411 r = FLD_MOD(r, x4 ? 1 : 0, 29, 29); /* HS_TX_TO_X8 (4 really) */ 3329 r = FLD_MOD(r, x4 ? 1 : 0, 29, 29); /* HS_TX_TO_X8 (4 really) */
3412 r = FLD_MOD(r, ticks, 28, 16); /* HS_TX_TO_COUNTER */ 3330 r = FLD_MOD(r, ticks, 28, 16); /* HS_TX_TO_COUNTER */
3413 dsi_write_reg(dsidev, DSI_TIMING2, r); 3331 dsi_write_reg(dsi, DSI_TIMING2, r);
3414 3332
3415 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1); 3333 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3416 3334
@@ -3420,9 +3338,8 @@ static void dsi_set_hs_tx_timeout(struct platform_device *dsidev,
3420 (total_ticks * 1000) / (fck / 1000 / 1000)); 3338 (total_ticks * 1000) / (fck / 1000 / 1000));
3421} 3339}
3422 3340
3423static void dsi_config_vp_num_line_buffers(struct platform_device *dsidev) 3341static void dsi_config_vp_num_line_buffers(struct dsi_data *dsi)
3424{ 3342{
3425 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3426 int num_line_buffers; 3343 int num_line_buffers;
3427 3344
3428 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { 3345 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
@@ -3442,12 +3359,11 @@ static void dsi_config_vp_num_line_buffers(struct platform_device *dsidev)
3442 } 3359 }
3443 3360
3444 /* LINE_BUFFER */ 3361 /* LINE_BUFFER */
3445 REG_FLD_MOD(dsidev, DSI_CTRL, num_line_buffers, 13, 12); 3362 REG_FLD_MOD(dsi, DSI_CTRL, num_line_buffers, 13, 12);
3446} 3363}
3447 3364
3448static void dsi_config_vp_sync_events(struct platform_device *dsidev) 3365static void dsi_config_vp_sync_events(struct dsi_data *dsi)
3449{ 3366{
3450 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3451 bool sync_end; 3367 bool sync_end;
3452 u32 r; 3368 u32 r;
3453 3369
@@ -3456,7 +3372,7 @@ static void dsi_config_vp_sync_events(struct platform_device *dsidev)
3456 else 3372 else
3457 sync_end = false; 3373 sync_end = false;
3458 3374
3459 r = dsi_read_reg(dsidev, DSI_CTRL); 3375 r = dsi_read_reg(dsi, DSI_CTRL);
3460 r = FLD_MOD(r, 1, 9, 9); /* VP_DE_POL */ 3376 r = FLD_MOD(r, 1, 9, 9); /* VP_DE_POL */
3461 r = FLD_MOD(r, 1, 10, 10); /* VP_HSYNC_POL */ 3377 r = FLD_MOD(r, 1, 10, 10); /* VP_HSYNC_POL */
3462 r = FLD_MOD(r, 1, 11, 11); /* VP_VSYNC_POL */ 3378 r = FLD_MOD(r, 1, 11, 11); /* VP_VSYNC_POL */
@@ -3464,12 +3380,11 @@ static void dsi_config_vp_sync_events(struct platform_device *dsidev)
3464 r = FLD_MOD(r, sync_end, 16, 16); /* VP_VSYNC_END */ 3380 r = FLD_MOD(r, sync_end, 16, 16); /* VP_VSYNC_END */
3465 r = FLD_MOD(r, 1, 17, 17); /* VP_HSYNC_START */ 3381 r = FLD_MOD(r, 1, 17, 17); /* VP_HSYNC_START */
3466 r = FLD_MOD(r, sync_end, 18, 18); /* VP_HSYNC_END */ 3382 r = FLD_MOD(r, sync_end, 18, 18); /* VP_HSYNC_END */
3467 dsi_write_reg(dsidev, DSI_CTRL, r); 3383 dsi_write_reg(dsi, DSI_CTRL, r);
3468} 3384}
3469 3385
3470static void dsi_config_blanking_modes(struct platform_device *dsidev) 3386static void dsi_config_blanking_modes(struct dsi_data *dsi)
3471{ 3387{
3472 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3473 int blanking_mode = dsi->vm_timings.blanking_mode; 3388 int blanking_mode = dsi->vm_timings.blanking_mode;
3474 int hfp_blanking_mode = dsi->vm_timings.hfp_blanking_mode; 3389 int hfp_blanking_mode = dsi->vm_timings.hfp_blanking_mode;
3475 int hbp_blanking_mode = dsi->vm_timings.hbp_blanking_mode; 3390 int hbp_blanking_mode = dsi->vm_timings.hbp_blanking_mode;
@@ -3480,12 +3395,12 @@ static void dsi_config_blanking_modes(struct platform_device *dsidev)
3480 * 0 = TX FIFO packets sent or LPS in corresponding blanking periods 3395 * 0 = TX FIFO packets sent or LPS in corresponding blanking periods
3481 * 1 = Long blanking packets are sent in corresponding blanking periods 3396 * 1 = Long blanking packets are sent in corresponding blanking periods
3482 */ 3397 */
3483 r = dsi_read_reg(dsidev, DSI_CTRL); 3398 r = dsi_read_reg(dsi, DSI_CTRL);
3484 r = FLD_MOD(r, blanking_mode, 20, 20); /* BLANKING_MODE */ 3399 r = FLD_MOD(r, blanking_mode, 20, 20); /* BLANKING_MODE */
3485 r = FLD_MOD(r, hfp_blanking_mode, 21, 21); /* HFP_BLANKING */ 3400 r = FLD_MOD(r, hfp_blanking_mode, 21, 21); /* HFP_BLANKING */
3486 r = FLD_MOD(r, hbp_blanking_mode, 22, 22); /* HBP_BLANKING */ 3401 r = FLD_MOD(r, hbp_blanking_mode, 22, 22); /* HBP_BLANKING */
3487 r = FLD_MOD(r, hsa_blanking_mode, 23, 23); /* HSA_BLANKING */ 3402 r = FLD_MOD(r, hsa_blanking_mode, 23, 23); /* HSA_BLANKING */
3488 dsi_write_reg(dsidev, DSI_CTRL, r); 3403 dsi_write_reg(dsi, DSI_CTRL, r);
3489} 3404}
3490 3405
3491/* 3406/*
@@ -3550,9 +3465,8 @@ static int dsi_compute_interleave_lp(int blank, int enter_hs, int exit_hs,
3550 return max(lp_inter, 0); 3465 return max(lp_inter, 0);
3551} 3466}
3552 3467
3553static void dsi_config_cmd_mode_interleaving(struct platform_device *dsidev) 3468static void dsi_config_cmd_mode_interleaving(struct dsi_data *dsi)
3554{ 3469{
3555 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3556 int blanking_mode; 3470 int blanking_mode;
3557 int hfp_blanking_mode, hbp_blanking_mode, hsa_blanking_mode; 3471 int hfp_blanking_mode, hbp_blanking_mode, hsa_blanking_mode;
3558 int hsa, hfp, hbp, width_bytes, bllp, lp_clk_div; 3472 int hsa, hfp, hbp, width_bytes, bllp, lp_clk_div;
@@ -3569,33 +3483,33 @@ static void dsi_config_cmd_mode_interleaving(struct platform_device *dsidev)
3569 int bl_interleave_hs = 0, bl_interleave_lp = 0; 3483 int bl_interleave_hs = 0, bl_interleave_lp = 0;
3570 u32 r; 3484 u32 r;
3571 3485
3572 r = dsi_read_reg(dsidev, DSI_CTRL); 3486 r = dsi_read_reg(dsi, DSI_CTRL);
3573 blanking_mode = FLD_GET(r, 20, 20); 3487 blanking_mode = FLD_GET(r, 20, 20);
3574 hfp_blanking_mode = FLD_GET(r, 21, 21); 3488 hfp_blanking_mode = FLD_GET(r, 21, 21);
3575 hbp_blanking_mode = FLD_GET(r, 22, 22); 3489 hbp_blanking_mode = FLD_GET(r, 22, 22);
3576 hsa_blanking_mode = FLD_GET(r, 23, 23); 3490 hsa_blanking_mode = FLD_GET(r, 23, 23);
3577 3491
3578 r = dsi_read_reg(dsidev, DSI_VM_TIMING1); 3492 r = dsi_read_reg(dsi, DSI_VM_TIMING1);
3579 hbp = FLD_GET(r, 11, 0); 3493 hbp = FLD_GET(r, 11, 0);
3580 hfp = FLD_GET(r, 23, 12); 3494 hfp = FLD_GET(r, 23, 12);
3581 hsa = FLD_GET(r, 31, 24); 3495 hsa = FLD_GET(r, 31, 24);
3582 3496
3583 r = dsi_read_reg(dsidev, DSI_CLK_TIMING); 3497 r = dsi_read_reg(dsi, DSI_CLK_TIMING);
3584 ddr_clk_post = FLD_GET(r, 7, 0); 3498 ddr_clk_post = FLD_GET(r, 7, 0);
3585 ddr_clk_pre = FLD_GET(r, 15, 8); 3499 ddr_clk_pre = FLD_GET(r, 15, 8);
3586 3500
3587 r = dsi_read_reg(dsidev, DSI_VM_TIMING7); 3501 r = dsi_read_reg(dsi, DSI_VM_TIMING7);
3588 exit_hs_mode_lat = FLD_GET(r, 15, 0); 3502 exit_hs_mode_lat = FLD_GET(r, 15, 0);
3589 enter_hs_mode_lat = FLD_GET(r, 31, 16); 3503 enter_hs_mode_lat = FLD_GET(r, 31, 16);
3590 3504
3591 r = dsi_read_reg(dsidev, DSI_CLK_CTRL); 3505 r = dsi_read_reg(dsi, DSI_CLK_CTRL);
3592 lp_clk_div = FLD_GET(r, 12, 0); 3506 lp_clk_div = FLD_GET(r, 12, 0);
3593 ddr_alwon = FLD_GET(r, 13, 13); 3507 ddr_alwon = FLD_GET(r, 13, 13);
3594 3508
3595 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0); 3509 r = dsi_read_reg(dsi, DSI_DSIPHY_CFG0);
3596 ths_exit = FLD_GET(r, 7, 0); 3510 ths_exit = FLD_GET(r, 7, 0);
3597 3511
3598 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1); 3512 r = dsi_read_reg(dsi, DSI_DSIPHY_CFG1);
3599 tclk_trail = FLD_GET(r, 15, 8); 3513 tclk_trail = FLD_GET(r, 15, 8);
3600 3514
3601 exiths_clk = ths_exit + tclk_trail; 3515 exiths_clk = ths_exit + tclk_trail;
@@ -3649,45 +3563,44 @@ static void dsi_config_cmd_mode_interleaving(struct platform_device *dsidev)
3649 hsa_interleave_lp, hfp_interleave_lp, hbp_interleave_lp, 3563 hsa_interleave_lp, hfp_interleave_lp, hbp_interleave_lp,
3650 bl_interleave_lp); 3564 bl_interleave_lp);
3651 3565
3652 r = dsi_read_reg(dsidev, DSI_VM_TIMING4); 3566 r = dsi_read_reg(dsi, DSI_VM_TIMING4);
3653 r = FLD_MOD(r, hsa_interleave_hs, 23, 16); 3567 r = FLD_MOD(r, hsa_interleave_hs, 23, 16);
3654 r = FLD_MOD(r, hfp_interleave_hs, 15, 8); 3568 r = FLD_MOD(r, hfp_interleave_hs, 15, 8);
3655 r = FLD_MOD(r, hbp_interleave_hs, 7, 0); 3569 r = FLD_MOD(r, hbp_interleave_hs, 7, 0);
3656 dsi_write_reg(dsidev, DSI_VM_TIMING4, r); 3570 dsi_write_reg(dsi, DSI_VM_TIMING4, r);
3657 3571
3658 r = dsi_read_reg(dsidev, DSI_VM_TIMING5); 3572 r = dsi_read_reg(dsi, DSI_VM_TIMING5);
3659 r = FLD_MOD(r, hsa_interleave_lp, 23, 16); 3573 r = FLD_MOD(r, hsa_interleave_lp, 23, 16);
3660 r = FLD_MOD(r, hfp_interleave_lp, 15, 8); 3574 r = FLD_MOD(r, hfp_interleave_lp, 15, 8);
3661 r = FLD_MOD(r, hbp_interleave_lp, 7, 0); 3575 r = FLD_MOD(r, hbp_interleave_lp, 7, 0);
3662 dsi_write_reg(dsidev, DSI_VM_TIMING5, r); 3576 dsi_write_reg(dsi, DSI_VM_TIMING5, r);
3663 3577
3664 r = dsi_read_reg(dsidev, DSI_VM_TIMING6); 3578 r = dsi_read_reg(dsi, DSI_VM_TIMING6);
3665 r = FLD_MOD(r, bl_interleave_hs, 31, 15); 3579 r = FLD_MOD(r, bl_interleave_hs, 31, 15);
3666 r = FLD_MOD(r, bl_interleave_lp, 16, 0); 3580 r = FLD_MOD(r, bl_interleave_lp, 16, 0);
3667 dsi_write_reg(dsidev, DSI_VM_TIMING6, r); 3581 dsi_write_reg(dsi, DSI_VM_TIMING6, r);
3668} 3582}
3669 3583
3670static int dsi_proto_config(struct platform_device *dsidev) 3584static int dsi_proto_config(struct dsi_data *dsi)
3671{ 3585{
3672 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3673 u32 r; 3586 u32 r;
3674 int buswidth = 0; 3587 int buswidth = 0;
3675 3588
3676 dsi_config_tx_fifo(dsidev, DSI_FIFO_SIZE_32, 3589 dsi_config_tx_fifo(dsi, DSI_FIFO_SIZE_32,
3677 DSI_FIFO_SIZE_32, 3590 DSI_FIFO_SIZE_32,
3678 DSI_FIFO_SIZE_32, 3591 DSI_FIFO_SIZE_32,
3679 DSI_FIFO_SIZE_32); 3592 DSI_FIFO_SIZE_32);
3680 3593
3681 dsi_config_rx_fifo(dsidev, DSI_FIFO_SIZE_32, 3594 dsi_config_rx_fifo(dsi, DSI_FIFO_SIZE_32,
3682 DSI_FIFO_SIZE_32, 3595 DSI_FIFO_SIZE_32,
3683 DSI_FIFO_SIZE_32, 3596 DSI_FIFO_SIZE_32,
3684 DSI_FIFO_SIZE_32); 3597 DSI_FIFO_SIZE_32);
3685 3598
3686 /* XXX what values for the timeouts? */ 3599 /* XXX what values for the timeouts? */
3687 dsi_set_stop_state_counter(dsidev, 0x1000, false, false); 3600 dsi_set_stop_state_counter(dsi, 0x1000, false, false);
3688 dsi_set_ta_timeout(dsidev, 0x1fff, true, true); 3601 dsi_set_ta_timeout(dsi, 0x1fff, true, true);
3689 dsi_set_lp_rx_timeout(dsidev, 0x1fff, true, true); 3602 dsi_set_lp_rx_timeout(dsi, 0x1fff, true, true);
3690 dsi_set_hs_tx_timeout(dsidev, 0x1fff, true, true); 3603 dsi_set_hs_tx_timeout(dsi, 0x1fff, true, true);
3691 3604
3692 switch (dsi_get_pixel_size(dsi->pix_fmt)) { 3605 switch (dsi_get_pixel_size(dsi->pix_fmt)) {
3693 case 16: 3606 case 16:
@@ -3704,7 +3617,7 @@ static int dsi_proto_config(struct platform_device *dsidev)
3704 return -EINVAL; 3617 return -EINVAL;
3705 } 3618 }
3706 3619
3707 r = dsi_read_reg(dsidev, DSI_CTRL); 3620 r = dsi_read_reg(dsi, DSI_CTRL);
3708 r = FLD_MOD(r, 1, 1, 1); /* CS_RX_EN */ 3621 r = FLD_MOD(r, 1, 1, 1); /* CS_RX_EN */
3709 r = FLD_MOD(r, 1, 2, 2); /* ECC_RX_EN */ 3622 r = FLD_MOD(r, 1, 2, 2); /* ECC_RX_EN */
3710 r = FLD_MOD(r, 1, 3, 3); /* TX_FIFO_ARBITRATION */ 3623 r = FLD_MOD(r, 1, 3, 3); /* TX_FIFO_ARBITRATION */
@@ -3719,56 +3632,55 @@ static int dsi_proto_config(struct platform_device *dsidev)
3719 r = FLD_MOD(r, 0, 25, 25); 3632 r = FLD_MOD(r, 0, 25, 25);
3720 } 3633 }
3721 3634
3722 dsi_write_reg(dsidev, DSI_CTRL, r); 3635 dsi_write_reg(dsi, DSI_CTRL, r);
3723 3636
3724 dsi_config_vp_num_line_buffers(dsidev); 3637 dsi_config_vp_num_line_buffers(dsi);
3725 3638
3726 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { 3639 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3727 dsi_config_vp_sync_events(dsidev); 3640 dsi_config_vp_sync_events(dsi);
3728 dsi_config_blanking_modes(dsidev); 3641 dsi_config_blanking_modes(dsi);
3729 dsi_config_cmd_mode_interleaving(dsidev); 3642 dsi_config_cmd_mode_interleaving(dsi);
3730 } 3643 }
3731 3644
3732 dsi_vc_initial_config(dsidev, 0); 3645 dsi_vc_initial_config(dsi, 0);
3733 dsi_vc_initial_config(dsidev, 1); 3646 dsi_vc_initial_config(dsi, 1);
3734 dsi_vc_initial_config(dsidev, 2); 3647 dsi_vc_initial_config(dsi, 2);
3735 dsi_vc_initial_config(dsidev, 3); 3648 dsi_vc_initial_config(dsi, 3);
3736 3649
3737 return 0; 3650 return 0;
3738} 3651}
3739 3652
3740static void dsi_proto_timings(struct platform_device *dsidev) 3653static void dsi_proto_timings(struct dsi_data *dsi)
3741{ 3654{
3742 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 3655 unsigned int tlpx, tclk_zero, tclk_prepare, tclk_trail;
3743 unsigned tlpx, tclk_zero, tclk_prepare, tclk_trail; 3656 unsigned int tclk_pre, tclk_post;
3744 unsigned tclk_pre, tclk_post; 3657 unsigned int ths_prepare, ths_prepare_ths_zero, ths_zero;
3745 unsigned ths_prepare, ths_prepare_ths_zero, ths_zero; 3658 unsigned int ths_trail, ths_exit;
3746 unsigned ths_trail, ths_exit; 3659 unsigned int ddr_clk_pre, ddr_clk_post;
3747 unsigned ddr_clk_pre, ddr_clk_post; 3660 unsigned int enter_hs_mode_lat, exit_hs_mode_lat;
3748 unsigned enter_hs_mode_lat, exit_hs_mode_lat; 3661 unsigned int ths_eot;
3749 unsigned ths_eot;
3750 int ndl = dsi->num_lanes_used - 1; 3662 int ndl = dsi->num_lanes_used - 1;
3751 u32 r; 3663 u32 r;
3752 3664
3753 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0); 3665 r = dsi_read_reg(dsi, DSI_DSIPHY_CFG0);
3754 ths_prepare = FLD_GET(r, 31, 24); 3666 ths_prepare = FLD_GET(r, 31, 24);
3755 ths_prepare_ths_zero = FLD_GET(r, 23, 16); 3667 ths_prepare_ths_zero = FLD_GET(r, 23, 16);
3756 ths_zero = ths_prepare_ths_zero - ths_prepare; 3668 ths_zero = ths_prepare_ths_zero - ths_prepare;
3757 ths_trail = FLD_GET(r, 15, 8); 3669 ths_trail = FLD_GET(r, 15, 8);
3758 ths_exit = FLD_GET(r, 7, 0); 3670 ths_exit = FLD_GET(r, 7, 0);
3759 3671
3760 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1); 3672 r = dsi_read_reg(dsi, DSI_DSIPHY_CFG1);
3761 tlpx = FLD_GET(r, 20, 16) * 2; 3673 tlpx = FLD_GET(r, 20, 16) * 2;
3762 tclk_trail = FLD_GET(r, 15, 8); 3674 tclk_trail = FLD_GET(r, 15, 8);
3763 tclk_zero = FLD_GET(r, 7, 0); 3675 tclk_zero = FLD_GET(r, 7, 0);
3764 3676
3765 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2); 3677 r = dsi_read_reg(dsi, DSI_DSIPHY_CFG2);
3766 tclk_prepare = FLD_GET(r, 7, 0); 3678 tclk_prepare = FLD_GET(r, 7, 0);
3767 3679
3768 /* min 8*UI */ 3680 /* min 8*UI */
3769 tclk_pre = 20; 3681 tclk_pre = 20;
3770 /* min 60ns + 52*UI */ 3682 /* min 60ns + 52*UI */
3771 tclk_post = ns2ddr(dsidev, 60) + 26; 3683 tclk_post = ns2ddr(dsi, 60) + 26;
3772 3684
3773 ths_eot = DIV_ROUND_UP(4, ndl); 3685 ths_eot = DIV_ROUND_UP(4, ndl);
3774 3686
@@ -3779,10 +3691,10 @@ static void dsi_proto_timings(struct platform_device *dsidev)
3779 BUG_ON(ddr_clk_pre == 0 || ddr_clk_pre > 255); 3691 BUG_ON(ddr_clk_pre == 0 || ddr_clk_pre > 255);
3780 BUG_ON(ddr_clk_post == 0 || ddr_clk_post > 255); 3692 BUG_ON(ddr_clk_post == 0 || ddr_clk_post > 255);
3781 3693
3782 r = dsi_read_reg(dsidev, DSI_CLK_TIMING); 3694 r = dsi_read_reg(dsi, DSI_CLK_TIMING);
3783 r = FLD_MOD(r, ddr_clk_pre, 15, 8); 3695 r = FLD_MOD(r, ddr_clk_pre, 15, 8);
3784 r = FLD_MOD(r, ddr_clk_post, 7, 0); 3696 r = FLD_MOD(r, ddr_clk_post, 7, 0);
3785 dsi_write_reg(dsidev, DSI_CLK_TIMING, r); 3697 dsi_write_reg(dsi, DSI_CLK_TIMING, r);
3786 3698
3787 DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n", 3699 DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n",
3788 ddr_clk_pre, 3700 ddr_clk_pre,
@@ -3796,7 +3708,7 @@ static void dsi_proto_timings(struct platform_device *dsidev)
3796 3708
3797 r = FLD_VAL(enter_hs_mode_lat, 31, 16) | 3709 r = FLD_VAL(enter_hs_mode_lat, 31, 16) |
3798 FLD_VAL(exit_hs_mode_lat, 15, 0); 3710 FLD_VAL(exit_hs_mode_lat, 15, 0);
3799 dsi_write_reg(dsidev, DSI_VM_TIMING7, r); 3711 dsi_write_reg(dsi, DSI_VM_TIMING7, r);
3800 3712
3801 DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n", 3713 DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n",
3802 enter_hs_mode_lat, exit_hs_mode_lat); 3714 enter_hs_mode_lat, exit_hs_mode_lat);
@@ -3830,31 +3742,30 @@ static void dsi_proto_timings(struct platform_device *dsidev)
3830 DSSDBG("VBP: %d, VFP: %d, VSA: %d, VACT: %d lines\n", vbp, vfp, 3742 DSSDBG("VBP: %d, VFP: %d, VSA: %d, VACT: %d lines\n", vbp, vfp,
3831 vsa, vm->vactive); 3743 vsa, vm->vactive);
3832 3744
3833 r = dsi_read_reg(dsidev, DSI_VM_TIMING1); 3745 r = dsi_read_reg(dsi, DSI_VM_TIMING1);
3834 r = FLD_MOD(r, hbp, 11, 0); /* HBP */ 3746 r = FLD_MOD(r, hbp, 11, 0); /* HBP */
3835 r = FLD_MOD(r, hfp, 23, 12); /* HFP */ 3747 r = FLD_MOD(r, hfp, 23, 12); /* HFP */
3836 r = FLD_MOD(r, hsync_end ? hsa : 0, 31, 24); /* HSA */ 3748 r = FLD_MOD(r, hsync_end ? hsa : 0, 31, 24); /* HSA */
3837 dsi_write_reg(dsidev, DSI_VM_TIMING1, r); 3749 dsi_write_reg(dsi, DSI_VM_TIMING1, r);
3838 3750
3839 r = dsi_read_reg(dsidev, DSI_VM_TIMING2); 3751 r = dsi_read_reg(dsi, DSI_VM_TIMING2);
3840 r = FLD_MOD(r, vbp, 7, 0); /* VBP */ 3752 r = FLD_MOD(r, vbp, 7, 0); /* VBP */
3841 r = FLD_MOD(r, vfp, 15, 8); /* VFP */ 3753 r = FLD_MOD(r, vfp, 15, 8); /* VFP */
3842 r = FLD_MOD(r, vsa, 23, 16); /* VSA */ 3754 r = FLD_MOD(r, vsa, 23, 16); /* VSA */
3843 r = FLD_MOD(r, window_sync, 27, 24); /* WINDOW_SYNC */ 3755 r = FLD_MOD(r, window_sync, 27, 24); /* WINDOW_SYNC */
3844 dsi_write_reg(dsidev, DSI_VM_TIMING2, r); 3756 dsi_write_reg(dsi, DSI_VM_TIMING2, r);
3845 3757
3846 r = dsi_read_reg(dsidev, DSI_VM_TIMING3); 3758 r = dsi_read_reg(dsi, DSI_VM_TIMING3);
3847 r = FLD_MOD(r, vm->vactive, 14, 0); /* VACT */ 3759 r = FLD_MOD(r, vm->vactive, 14, 0); /* VACT */
3848 r = FLD_MOD(r, tl, 31, 16); /* TL */ 3760 r = FLD_MOD(r, tl, 31, 16); /* TL */
3849 dsi_write_reg(dsidev, DSI_VM_TIMING3, r); 3761 dsi_write_reg(dsi, DSI_VM_TIMING3, r);
3850 } 3762 }
3851} 3763}
3852 3764
3853static int dsi_configure_pins(struct omap_dss_device *dssdev, 3765static int dsi_configure_pins(struct omap_dss_device *dssdev,
3854 const struct omap_dsi_pin_config *pin_cfg) 3766 const struct omap_dsi_pin_config *pin_cfg)
3855{ 3767{
3856 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 3768 struct dsi_data *dsi = to_dsi_data(dssdev);
3857 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3858 int num_pins; 3769 int num_pins;
3859 const int *pins; 3770 const int *pins;
3860 struct dsi_lane_config lanes[DSI_MAX_NR_LANES]; 3771 struct dsi_lane_config lanes[DSI_MAX_NR_LANES];
@@ -3919,9 +3830,7 @@ static int dsi_configure_pins(struct omap_dss_device *dssdev,
3919 3830
3920static int dsi_enable_video_output(struct omap_dss_device *dssdev, int channel) 3831static int dsi_enable_video_output(struct omap_dss_device *dssdev, int channel)
3921{ 3832{
3922 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 3833 struct dsi_data *dsi = to_dsi_data(dssdev);
3923 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3924 enum omap_channel dispc_channel = dssdev->dispc_channel;
3925 int bpp = dsi_get_pixel_size(dsi->pix_fmt); 3834 int bpp = dsi_get_pixel_size(dsi->pix_fmt);
3926 struct omap_dss_device *out = &dsi->output; 3835 struct omap_dss_device *out = &dsi->output;
3927 u8 data_type; 3836 u8 data_type;
@@ -3933,7 +3842,7 @@ static int dsi_enable_video_output(struct omap_dss_device *dssdev, int channel)
3933 return -ENODEV; 3842 return -ENODEV;
3934 } 3843 }
3935 3844
3936 r = dsi_display_init_dispc(dsidev, dispc_channel); 3845 r = dsi_display_init_dispc(dsi);
3937 if (r) 3846 if (r)
3938 goto err_init_dispc; 3847 goto err_init_dispc;
3939 3848
@@ -3956,22 +3865,22 @@ static int dsi_enable_video_output(struct omap_dss_device *dssdev, int channel)
3956 goto err_pix_fmt; 3865 goto err_pix_fmt;
3957 } 3866 }
3958 3867
3959 dsi_if_enable(dsidev, false); 3868 dsi_if_enable(dsi, false);
3960 dsi_vc_enable(dsidev, channel, false); 3869 dsi_vc_enable(dsi, channel, false);
3961 3870
3962 /* MODE, 1 = video mode */ 3871 /* MODE, 1 = video mode */
3963 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 4, 4); 3872 REG_FLD_MOD(dsi, DSI_VC_CTRL(channel), 1, 4, 4);
3964 3873
3965 word_count = DIV_ROUND_UP(dsi->vm.hactive * bpp, 8); 3874 word_count = DIV_ROUND_UP(dsi->vm.hactive * bpp, 8);
3966 3875
3967 dsi_vc_write_long_header(dsidev, channel, data_type, 3876 dsi_vc_write_long_header(dsi, channel, data_type,
3968 word_count, 0); 3877 word_count, 0);
3969 3878
3970 dsi_vc_enable(dsidev, channel, true); 3879 dsi_vc_enable(dsi, channel, true);
3971 dsi_if_enable(dsidev, true); 3880 dsi_if_enable(dsi, true);
3972 } 3881 }
3973 3882
3974 r = dss_mgr_enable(dispc_channel); 3883 r = dss_mgr_enable(&dsi->output);
3975 if (r) 3884 if (r)
3976 goto err_mgr_enable; 3885 goto err_mgr_enable;
3977 3886
@@ -3979,57 +3888,53 @@ static int dsi_enable_video_output(struct omap_dss_device *dssdev, int channel)
3979 3888
3980err_mgr_enable: 3889err_mgr_enable:
3981 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { 3890 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3982 dsi_if_enable(dsidev, false); 3891 dsi_if_enable(dsi, false);
3983 dsi_vc_enable(dsidev, channel, false); 3892 dsi_vc_enable(dsi, channel, false);
3984 } 3893 }
3985err_pix_fmt: 3894err_pix_fmt:
3986 dsi_display_uninit_dispc(dsidev, dispc_channel); 3895 dsi_display_uninit_dispc(dsi);
3987err_init_dispc: 3896err_init_dispc:
3988 return r; 3897 return r;
3989} 3898}
3990 3899
3991static void dsi_disable_video_output(struct omap_dss_device *dssdev, int channel) 3900static void dsi_disable_video_output(struct omap_dss_device *dssdev, int channel)
3992{ 3901{
3993 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 3902 struct dsi_data *dsi = to_dsi_data(dssdev);
3994 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3995 enum omap_channel dispc_channel = dssdev->dispc_channel;
3996 3903
3997 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { 3904 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3998 dsi_if_enable(dsidev, false); 3905 dsi_if_enable(dsi, false);
3999 dsi_vc_enable(dsidev, channel, false); 3906 dsi_vc_enable(dsi, channel, false);
4000 3907
4001 /* MODE, 0 = command mode */ 3908 /* MODE, 0 = command mode */
4002 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 0, 4, 4); 3909 REG_FLD_MOD(dsi, DSI_VC_CTRL(channel), 0, 4, 4);
4003 3910
4004 dsi_vc_enable(dsidev, channel, true); 3911 dsi_vc_enable(dsi, channel, true);
4005 dsi_if_enable(dsidev, true); 3912 dsi_if_enable(dsi, true);
4006 } 3913 }
4007 3914
4008 dss_mgr_disable(dispc_channel); 3915 dss_mgr_disable(&dsi->output);
4009 3916
4010 dsi_display_uninit_dispc(dsidev, dispc_channel); 3917 dsi_display_uninit_dispc(dsi);
4011} 3918}
4012 3919
4013static void dsi_update_screen_dispc(struct platform_device *dsidev) 3920static void dsi_update_screen_dispc(struct dsi_data *dsi)
4014{ 3921{
4015 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 3922 unsigned int bytespp;
4016 enum omap_channel dispc_channel = dsi->output.dispc_channel; 3923 unsigned int bytespl;
4017 unsigned bytespp; 3924 unsigned int bytespf;
4018 unsigned bytespl; 3925 unsigned int total_len;
4019 unsigned bytespf; 3926 unsigned int packet_payload;
4020 unsigned total_len; 3927 unsigned int packet_len;
4021 unsigned packet_payload;
4022 unsigned packet_len;
4023 u32 l; 3928 u32 l;
4024 int r; 3929 int r;
4025 const unsigned channel = dsi->update_channel; 3930 const unsigned channel = dsi->update_channel;
4026 const unsigned line_buf_size = dsi->line_buffer_size; 3931 const unsigned int line_buf_size = dsi->line_buffer_size;
4027 u16 w = dsi->vm.hactive; 3932 u16 w = dsi->vm.hactive;
4028 u16 h = dsi->vm.vactive; 3933 u16 h = dsi->vm.vactive;
4029 3934
4030 DSSDBG("dsi_update_screen_dispc(%dx%d)\n", w, h); 3935 DSSDBG("dsi_update_screen_dispc(%dx%d)\n", w, h);
4031 3936
4032 dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_VP); 3937 dsi_vc_config_source(dsi, channel, DSI_VC_SOURCE_VP);
4033 3938
4034 bytespp = dsi_get_pixel_size(dsi->pix_fmt) / 8; 3939 bytespp = dsi_get_pixel_size(dsi->pix_fmt) / 8;
4035 bytespl = w * bytespp; 3940 bytespl = w * bytespp;
@@ -4050,16 +3955,16 @@ static void dsi_update_screen_dispc(struct platform_device *dsidev)
4050 total_len += (bytespf % packet_payload) + 1; 3955 total_len += (bytespf % packet_payload) + 1;
4051 3956
4052 l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */ 3957 l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */
4053 dsi_write_reg(dsidev, DSI_VC_TE(channel), l); 3958 dsi_write_reg(dsi, DSI_VC_TE(channel), l);
4054 3959
4055 dsi_vc_write_long_header(dsidev, channel, MIPI_DSI_DCS_LONG_WRITE, 3960 dsi_vc_write_long_header(dsi, channel, MIPI_DSI_DCS_LONG_WRITE,
4056 packet_len, 0); 3961 packet_len, 0);
4057 3962
4058 if (dsi->te_enabled) 3963 if (dsi->te_enabled)
4059 l = FLD_MOD(l, 1, 30, 30); /* TE_EN */ 3964 l = FLD_MOD(l, 1, 30, 30); /* TE_EN */
4060 else 3965 else
4061 l = FLD_MOD(l, 1, 31, 31); /* TE_START */ 3966 l = FLD_MOD(l, 1, 31, 31); /* TE_START */
4062 dsi_write_reg(dsidev, DSI_VC_TE(channel), l); 3967 dsi_write_reg(dsi, DSI_VC_TE(channel), l);
4063 3968
4064 /* We put SIDLEMODE to no-idle for the duration of the transfer, 3969 /* We put SIDLEMODE to no-idle for the duration of the transfer,
4065 * because DSS interrupts are not capable of waking up the CPU and the 3970 * because DSS interrupts are not capable of waking up the CPU and the
@@ -4067,24 +3972,24 @@ static void dsi_update_screen_dispc(struct platform_device *dsidev)
4067 * the same goes for any DSS interrupts, but for some reason I have not 3972 * the same goes for any DSS interrupts, but for some reason I have not
4068 * seen the problem anywhere else than here. 3973 * seen the problem anywhere else than here.
4069 */ 3974 */
4070 dispc_disable_sidle(); 3975 dispc_disable_sidle(dsi->dss->dispc);
4071 3976
4072 dsi_perf_mark_start(dsidev); 3977 dsi_perf_mark_start(dsi);
4073 3978
4074 r = schedule_delayed_work(&dsi->framedone_timeout_work, 3979 r = schedule_delayed_work(&dsi->framedone_timeout_work,
4075 msecs_to_jiffies(250)); 3980 msecs_to_jiffies(250));
4076 BUG_ON(r == 0); 3981 BUG_ON(r == 0);
4077 3982
4078 dss_mgr_set_timings(dispc_channel, &dsi->vm); 3983 dss_mgr_set_timings(&dsi->output, &dsi->vm);
4079 3984
4080 dss_mgr_start_update(dispc_channel); 3985 dss_mgr_start_update(&dsi->output);
4081 3986
4082 if (dsi->te_enabled) { 3987 if (dsi->te_enabled) {
4083 /* disable LP_RX_TO, so that we can receive TE. Time to wait 3988 /* disable LP_RX_TO, so that we can receive TE. Time to wait
4084 * for TE is longer than the timer allows */ 3989 * for TE is longer than the timer allows */
4085 REG_FLD_MOD(dsidev, DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */ 3990 REG_FLD_MOD(dsi, DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */
4086 3991
4087 dsi_vc_send_bta(dsidev, channel); 3992 dsi_vc_send_bta(dsi, channel);
4088 3993
4089#ifdef DSI_CATCH_MISSING_TE 3994#ifdef DSI_CATCH_MISSING_TE
4090 mod_timer(&dsi->te_timer, jiffies + msecs_to_jiffies(250)); 3995 mod_timer(&dsi->te_timer, jiffies + msecs_to_jiffies(250));
@@ -4099,22 +4004,20 @@ static void dsi_te_timeout(struct timer_list *unused)
4099} 4004}
4100#endif 4005#endif
4101 4006
4102static void dsi_handle_framedone(struct platform_device *dsidev, int error) 4007static void dsi_handle_framedone(struct dsi_data *dsi, int error)
4103{ 4008{
4104 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4105
4106 /* SIDLEMODE back to smart-idle */ 4009 /* SIDLEMODE back to smart-idle */
4107 dispc_enable_sidle(); 4010 dispc_enable_sidle(dsi->dss->dispc);
4108 4011
4109 if (dsi->te_enabled) { 4012 if (dsi->te_enabled) {
4110 /* enable LP_RX_TO again after the TE */ 4013 /* enable LP_RX_TO again after the TE */
4111 REG_FLD_MOD(dsidev, DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */ 4014 REG_FLD_MOD(dsi, DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */
4112 } 4015 }
4113 4016
4114 dsi->framedone_callback(error, dsi->framedone_data); 4017 dsi->framedone_callback(error, dsi->framedone_data);
4115 4018
4116 if (!error) 4019 if (!error)
4117 dsi_perf_show(dsidev, "DISPC"); 4020 dsi_perf_show(dsi, "DISPC");
4118} 4021}
4119 4022
4120static void dsi_framedone_timeout_work_callback(struct work_struct *work) 4023static void dsi_framedone_timeout_work_callback(struct work_struct *work)
@@ -4130,13 +4033,12 @@ static void dsi_framedone_timeout_work_callback(struct work_struct *work)
4130 4033
4131 DSSERR("Framedone not received for 250ms!\n"); 4034 DSSERR("Framedone not received for 250ms!\n");
4132 4035
4133 dsi_handle_framedone(dsi->pdev, -ETIMEDOUT); 4036 dsi_handle_framedone(dsi, -ETIMEDOUT);
4134} 4037}
4135 4038
4136static void dsi_framedone_irq_callback(void *data) 4039static void dsi_framedone_irq_callback(void *data)
4137{ 4040{
4138 struct platform_device *dsidev = (struct platform_device *) data; 4041 struct dsi_data *dsi = data;
4139 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4140 4042
4141 /* Note: We get FRAMEDONE when DISPC has finished sending pixels and 4043 /* Note: We get FRAMEDONE when DISPC has finished sending pixels and
4142 * turns itself off. However, DSI still has the pixels in its buffers, 4044 * turns itself off. However, DSI still has the pixels in its buffers,
@@ -4145,17 +4047,16 @@ static void dsi_framedone_irq_callback(void *data)
4145 4047
4146 cancel_delayed_work(&dsi->framedone_timeout_work); 4048 cancel_delayed_work(&dsi->framedone_timeout_work);
4147 4049
4148 dsi_handle_framedone(dsidev, 0); 4050 dsi_handle_framedone(dsi, 0);
4149} 4051}
4150 4052
4151static int dsi_update(struct omap_dss_device *dssdev, int channel, 4053static int dsi_update(struct omap_dss_device *dssdev, int channel,
4152 void (*callback)(int, void *), void *data) 4054 void (*callback)(int, void *), void *data)
4153{ 4055{
4154 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 4056 struct dsi_data *dsi = to_dsi_data(dssdev);
4155 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4156 u16 dw, dh; 4057 u16 dw, dh;
4157 4058
4158 dsi_perf_mark_setup(dsidev); 4059 dsi_perf_mark_setup(dsi);
4159 4060
4160 dsi->update_channel = channel; 4061 dsi->update_channel = channel;
4161 4062
@@ -4169,26 +4070,25 @@ static int dsi_update(struct omap_dss_device *dssdev, int channel,
4169 dsi->update_bytes = dw * dh * 4070 dsi->update_bytes = dw * dh *
4170 dsi_get_pixel_size(dsi->pix_fmt) / 8; 4071 dsi_get_pixel_size(dsi->pix_fmt) / 8;
4171#endif 4072#endif
4172 dsi_update_screen_dispc(dsidev); 4073 dsi_update_screen_dispc(dsi);
4173 4074
4174 return 0; 4075 return 0;
4175} 4076}
4176 4077
4177/* Display funcs */ 4078/* Display funcs */
4178 4079
4179static int dsi_configure_dispc_clocks(struct platform_device *dsidev) 4080static int dsi_configure_dispc_clocks(struct dsi_data *dsi)
4180{ 4081{
4181 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4182 struct dispc_clock_info dispc_cinfo; 4082 struct dispc_clock_info dispc_cinfo;
4183 int r; 4083 int r;
4184 unsigned long fck; 4084 unsigned long fck;
4185 4085
4186 fck = dsi_get_pll_hsdiv_dispc_rate(dsidev); 4086 fck = dsi_get_pll_hsdiv_dispc_rate(dsi);
4187 4087
4188 dispc_cinfo.lck_div = dsi->user_dispc_cinfo.lck_div; 4088 dispc_cinfo.lck_div = dsi->user_dispc_cinfo.lck_div;
4189 dispc_cinfo.pck_div = dsi->user_dispc_cinfo.pck_div; 4089 dispc_cinfo.pck_div = dsi->user_dispc_cinfo.pck_div;
4190 4090
4191 r = dispc_calc_clock_rates(fck, &dispc_cinfo); 4091 r = dispc_calc_clock_rates(dsi->dss->dispc, fck, &dispc_cinfo);
4192 if (r) { 4092 if (r) {
4193 DSSERR("Failed to calc dispc clocks\n"); 4093 DSSERR("Failed to calc dispc clocks\n");
4194 return r; 4094 return r;
@@ -4199,19 +4099,18 @@ static int dsi_configure_dispc_clocks(struct platform_device *dsidev)
4199 return 0; 4099 return 0;
4200} 4100}
4201 4101
4202static int dsi_display_init_dispc(struct platform_device *dsidev, 4102static int dsi_display_init_dispc(struct dsi_data *dsi)
4203 enum omap_channel channel)
4204{ 4103{
4205 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 4104 enum omap_channel channel = dsi->output.dispc_channel;
4206 int r; 4105 int r;
4207 4106
4208 dss_select_lcd_clk_source(channel, dsi->module_id == 0 ? 4107 dss_select_lcd_clk_source(dsi->dss, channel, dsi->module_id == 0 ?
4209 DSS_CLK_SRC_PLL1_1 : 4108 DSS_CLK_SRC_PLL1_1 :
4210 DSS_CLK_SRC_PLL2_1); 4109 DSS_CLK_SRC_PLL2_1);
4211 4110
4212 if (dsi->mode == OMAP_DSS_DSI_CMD_MODE) { 4111 if (dsi->mode == OMAP_DSS_DSI_CMD_MODE) {
4213 r = dss_mgr_register_framedone_handler(channel, 4112 r = dss_mgr_register_framedone_handler(&dsi->output,
4214 dsi_framedone_irq_callback, dsidev); 4113 dsi_framedone_irq_callback, dsi);
4215 if (r) { 4114 if (r) {
4216 DSSERR("can't register FRAMEDONE handler\n"); 4115 DSSERR("can't register FRAMEDONE handler\n");
4217 goto err; 4116 goto err;
@@ -4240,9 +4139,9 @@ static int dsi_display_init_dispc(struct platform_device *dsidev,
4240 dsi->vm.flags &= ~DISPLAY_FLAGS_SYNC_POSEDGE; 4139 dsi->vm.flags &= ~DISPLAY_FLAGS_SYNC_POSEDGE;
4241 dsi->vm.flags |= DISPLAY_FLAGS_SYNC_NEGEDGE; 4140 dsi->vm.flags |= DISPLAY_FLAGS_SYNC_NEGEDGE;
4242 4141
4243 dss_mgr_set_timings(channel, &dsi->vm); 4142 dss_mgr_set_timings(&dsi->output, &dsi->vm);
4244 4143
4245 r = dsi_configure_dispc_clocks(dsidev); 4144 r = dsi_configure_dispc_clocks(dsi);
4246 if (r) 4145 if (r)
4247 goto err1; 4146 goto err1;
4248 4147
@@ -4251,33 +4150,31 @@ static int dsi_display_init_dispc(struct platform_device *dsidev,
4251 dsi_get_pixel_size(dsi->pix_fmt); 4150 dsi_get_pixel_size(dsi->pix_fmt);
4252 dsi->mgr_config.lcden_sig_polarity = 0; 4151 dsi->mgr_config.lcden_sig_polarity = 0;
4253 4152
4254 dss_mgr_set_lcd_config(channel, &dsi->mgr_config); 4153 dss_mgr_set_lcd_config(&dsi->output, &dsi->mgr_config);
4255 4154
4256 return 0; 4155 return 0;
4257err1: 4156err1:
4258 if (dsi->mode == OMAP_DSS_DSI_CMD_MODE) 4157 if (dsi->mode == OMAP_DSS_DSI_CMD_MODE)
4259 dss_mgr_unregister_framedone_handler(channel, 4158 dss_mgr_unregister_framedone_handler(&dsi->output,
4260 dsi_framedone_irq_callback, dsidev); 4159 dsi_framedone_irq_callback, dsi);
4261err: 4160err:
4262 dss_select_lcd_clk_source(channel, DSS_CLK_SRC_FCK); 4161 dss_select_lcd_clk_source(dsi->dss, channel, DSS_CLK_SRC_FCK);
4263 return r; 4162 return r;
4264} 4163}
4265 4164
4266static void dsi_display_uninit_dispc(struct platform_device *dsidev, 4165static void dsi_display_uninit_dispc(struct dsi_data *dsi)
4267 enum omap_channel channel)
4268{ 4166{
4269 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 4167 enum omap_channel channel = dsi->output.dispc_channel;
4270 4168
4271 if (dsi->mode == OMAP_DSS_DSI_CMD_MODE) 4169 if (dsi->mode == OMAP_DSS_DSI_CMD_MODE)
4272 dss_mgr_unregister_framedone_handler(channel, 4170 dss_mgr_unregister_framedone_handler(&dsi->output,
4273 dsi_framedone_irq_callback, dsidev); 4171 dsi_framedone_irq_callback, dsi);
4274 4172
4275 dss_select_lcd_clk_source(channel, DSS_CLK_SRC_FCK); 4173 dss_select_lcd_clk_source(dsi->dss, channel, DSS_CLK_SRC_FCK);
4276} 4174}
4277 4175
4278static int dsi_configure_dsi_clocks(struct platform_device *dsidev) 4176static int dsi_configure_dsi_clocks(struct dsi_data *dsi)
4279{ 4177{
4280 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4281 struct dss_pll_clock_info cinfo; 4178 struct dss_pll_clock_info cinfo;
4282 int r; 4179 int r;
4283 4180
@@ -4292,99 +4189,95 @@ static int dsi_configure_dsi_clocks(struct platform_device *dsidev)
4292 return 0; 4189 return 0;
4293} 4190}
4294 4191
4295static int dsi_display_init_dsi(struct platform_device *dsidev) 4192static int dsi_display_init_dsi(struct dsi_data *dsi)
4296{ 4193{
4297 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4298 int r; 4194 int r;
4299 4195
4300 r = dss_pll_enable(&dsi->pll); 4196 r = dss_pll_enable(&dsi->pll);
4301 if (r) 4197 if (r)
4302 goto err0; 4198 goto err0;
4303 4199
4304 r = dsi_configure_dsi_clocks(dsidev); 4200 r = dsi_configure_dsi_clocks(dsi);
4305 if (r) 4201 if (r)
4306 goto err1; 4202 goto err1;
4307 4203
4308 dss_select_dsi_clk_source(dsi->module_id, dsi->module_id == 0 ? 4204 dss_select_dsi_clk_source(dsi->dss, dsi->module_id,
4309 DSS_CLK_SRC_PLL1_2 : 4205 dsi->module_id == 0 ?
4310 DSS_CLK_SRC_PLL2_2); 4206 DSS_CLK_SRC_PLL1_2 : DSS_CLK_SRC_PLL2_2);
4311 4207
4312 DSSDBG("PLL OK\n"); 4208 DSSDBG("PLL OK\n");
4313 4209
4314 r = dsi_cio_init(dsidev); 4210 r = dsi_cio_init(dsi);
4315 if (r) 4211 if (r)
4316 goto err2; 4212 goto err2;
4317 4213
4318 _dsi_print_reset_status(dsidev); 4214 _dsi_print_reset_status(dsi);
4319 4215
4320 dsi_proto_timings(dsidev); 4216 dsi_proto_timings(dsi);
4321 dsi_set_lp_clk_divisor(dsidev); 4217 dsi_set_lp_clk_divisor(dsi);
4322 4218
4323 if (1) 4219 if (1)
4324 _dsi_print_reset_status(dsidev); 4220 _dsi_print_reset_status(dsi);
4325 4221
4326 r = dsi_proto_config(dsidev); 4222 r = dsi_proto_config(dsi);
4327 if (r) 4223 if (r)
4328 goto err3; 4224 goto err3;
4329 4225
4330 /* enable interface */ 4226 /* enable interface */
4331 dsi_vc_enable(dsidev, 0, 1); 4227 dsi_vc_enable(dsi, 0, 1);
4332 dsi_vc_enable(dsidev, 1, 1); 4228 dsi_vc_enable(dsi, 1, 1);
4333 dsi_vc_enable(dsidev, 2, 1); 4229 dsi_vc_enable(dsi, 2, 1);
4334 dsi_vc_enable(dsidev, 3, 1); 4230 dsi_vc_enable(dsi, 3, 1);
4335 dsi_if_enable(dsidev, 1); 4231 dsi_if_enable(dsi, 1);
4336 dsi_force_tx_stop_mode_io(dsidev); 4232 dsi_force_tx_stop_mode_io(dsi);
4337 4233
4338 return 0; 4234 return 0;
4339err3: 4235err3:
4340 dsi_cio_uninit(dsidev); 4236 dsi_cio_uninit(dsi);
4341err2: 4237err2:
4342 dss_select_dsi_clk_source(dsi->module_id, DSS_CLK_SRC_FCK); 4238 dss_select_dsi_clk_source(dsi->dss, dsi->module_id, DSS_CLK_SRC_FCK);
4343err1: 4239err1:
4344 dss_pll_disable(&dsi->pll); 4240 dss_pll_disable(&dsi->pll);
4345err0: 4241err0:
4346 return r; 4242 return r;
4347} 4243}
4348 4244
4349static void dsi_display_uninit_dsi(struct platform_device *dsidev, 4245static void dsi_display_uninit_dsi(struct dsi_data *dsi, bool disconnect_lanes,
4350 bool disconnect_lanes, bool enter_ulps) 4246 bool enter_ulps)
4351{ 4247{
4352 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4353
4354 if (enter_ulps && !dsi->ulps_enabled) 4248 if (enter_ulps && !dsi->ulps_enabled)
4355 dsi_enter_ulps(dsidev); 4249 dsi_enter_ulps(dsi);
4356 4250
4357 /* disable interface */ 4251 /* disable interface */
4358 dsi_if_enable(dsidev, 0); 4252 dsi_if_enable(dsi, 0);
4359 dsi_vc_enable(dsidev, 0, 0); 4253 dsi_vc_enable(dsi, 0, 0);
4360 dsi_vc_enable(dsidev, 1, 0); 4254 dsi_vc_enable(dsi, 1, 0);
4361 dsi_vc_enable(dsidev, 2, 0); 4255 dsi_vc_enable(dsi, 2, 0);
4362 dsi_vc_enable(dsidev, 3, 0); 4256 dsi_vc_enable(dsi, 3, 0);
4363 4257
4364 dss_select_dsi_clk_source(dsi->module_id, DSS_CLK_SRC_FCK); 4258 dss_select_dsi_clk_source(dsi->dss, dsi->module_id, DSS_CLK_SRC_FCK);
4365 dsi_cio_uninit(dsidev); 4259 dsi_cio_uninit(dsi);
4366 dsi_pll_uninit(dsidev, disconnect_lanes); 4260 dsi_pll_uninit(dsi, disconnect_lanes);
4367} 4261}
4368 4262
4369static int dsi_display_enable(struct omap_dss_device *dssdev) 4263static int dsi_display_enable(struct omap_dss_device *dssdev)
4370{ 4264{
4371 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 4265 struct dsi_data *dsi = to_dsi_data(dssdev);
4372 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4373 int r = 0; 4266 int r = 0;
4374 4267
4375 DSSDBG("dsi_display_enable\n"); 4268 DSSDBG("dsi_display_enable\n");
4376 4269
4377 WARN_ON(!dsi_bus_is_locked(dsidev)); 4270 WARN_ON(!dsi_bus_is_locked(dsi));
4378 4271
4379 mutex_lock(&dsi->lock); 4272 mutex_lock(&dsi->lock);
4380 4273
4381 r = dsi_runtime_get(dsidev); 4274 r = dsi_runtime_get(dsi);
4382 if (r) 4275 if (r)
4383 goto err_get_dsi; 4276 goto err_get_dsi;
4384 4277
4385 _dsi_initialize_irq(dsidev); 4278 _dsi_initialize_irq(dsi);
4386 4279
4387 r = dsi_display_init_dsi(dsidev); 4280 r = dsi_display_init_dsi(dsi);
4388 if (r) 4281 if (r)
4389 goto err_init_dsi; 4282 goto err_init_dsi;
4390 4283
@@ -4393,7 +4286,7 @@ static int dsi_display_enable(struct omap_dss_device *dssdev)
4393 return 0; 4286 return 0;
4394 4287
4395err_init_dsi: 4288err_init_dsi:
4396 dsi_runtime_put(dsidev); 4289 dsi_runtime_put(dsi);
4397err_get_dsi: 4290err_get_dsi:
4398 mutex_unlock(&dsi->lock); 4291 mutex_unlock(&dsi->lock);
4399 DSSDBG("dsi_display_enable FAILED\n"); 4292 DSSDBG("dsi_display_enable FAILED\n");
@@ -4403,31 +4296,29 @@ err_get_dsi:
4403static void dsi_display_disable(struct omap_dss_device *dssdev, 4296static void dsi_display_disable(struct omap_dss_device *dssdev,
4404 bool disconnect_lanes, bool enter_ulps) 4297 bool disconnect_lanes, bool enter_ulps)
4405{ 4298{
4406 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 4299 struct dsi_data *dsi = to_dsi_data(dssdev);
4407 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4408 4300
4409 DSSDBG("dsi_display_disable\n"); 4301 DSSDBG("dsi_display_disable\n");
4410 4302
4411 WARN_ON(!dsi_bus_is_locked(dsidev)); 4303 WARN_ON(!dsi_bus_is_locked(dsi));
4412 4304
4413 mutex_lock(&dsi->lock); 4305 mutex_lock(&dsi->lock);
4414 4306
4415 dsi_sync_vc(dsidev, 0); 4307 dsi_sync_vc(dsi, 0);
4416 dsi_sync_vc(dsidev, 1); 4308 dsi_sync_vc(dsi, 1);
4417 dsi_sync_vc(dsidev, 2); 4309 dsi_sync_vc(dsi, 2);
4418 dsi_sync_vc(dsidev, 3); 4310 dsi_sync_vc(dsi, 3);
4419 4311
4420 dsi_display_uninit_dsi(dsidev, disconnect_lanes, enter_ulps); 4312 dsi_display_uninit_dsi(dsi, disconnect_lanes, enter_ulps);
4421 4313
4422 dsi_runtime_put(dsidev); 4314 dsi_runtime_put(dsi);
4423 4315
4424 mutex_unlock(&dsi->lock); 4316 mutex_unlock(&dsi->lock);
4425} 4317}
4426 4318
4427static int dsi_enable_te(struct omap_dss_device *dssdev, bool enable) 4319static int dsi_enable_te(struct omap_dss_device *dssdev, bool enable)
4428{ 4320{
4429 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 4321 struct dsi_data *dsi = to_dsi_data(dssdev);
4430 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4431 4322
4432 dsi->te_enabled = enable; 4323 dsi->te_enabled = enable;
4433 return 0; 4324 return 0;
@@ -4548,15 +4439,16 @@ static bool dsi_cm_calc_hsdiv_cb(int m_dispc, unsigned long dispc,
4548 ctx->dsi_cinfo.mX[HSDIV_DISPC] = m_dispc; 4439 ctx->dsi_cinfo.mX[HSDIV_DISPC] = m_dispc;
4549 ctx->dsi_cinfo.clkout[HSDIV_DISPC] = dispc; 4440 ctx->dsi_cinfo.clkout[HSDIV_DISPC] = dispc;
4550 4441
4551 return dispc_div_calc(dispc, ctx->req_pck_min, ctx->req_pck_max, 4442 return dispc_div_calc(ctx->dsi->dss->dispc, dispc,
4552 dsi_cm_calc_dispc_cb, ctx); 4443 ctx->req_pck_min, ctx->req_pck_max,
4444 dsi_cm_calc_dispc_cb, ctx);
4553} 4445}
4554 4446
4555static bool dsi_cm_calc_pll_cb(int n, int m, unsigned long fint, 4447static bool dsi_cm_calc_pll_cb(int n, int m, unsigned long fint,
4556 unsigned long clkdco, void *data) 4448 unsigned long clkdco, void *data)
4557{ 4449{
4558 struct dsi_clk_calc_ctx *ctx = data; 4450 struct dsi_clk_calc_ctx *ctx = data;
4559 struct dsi_data *dsi = dsi_get_dsidrv_data(ctx->dsidev); 4451 struct dsi_data *dsi = ctx->dsi;
4560 4452
4561 ctx->dsi_cinfo.n = n; 4453 ctx->dsi_cinfo.n = n;
4562 ctx->dsi_cinfo.m = m; 4454 ctx->dsi_cinfo.m = m;
@@ -4592,7 +4484,7 @@ static bool dsi_cm_calc(struct dsi_data *dsi,
4592 txbyteclk = pck * bitspp / 8 / ndl; 4484 txbyteclk = pck * bitspp / 8 / ndl;
4593 4485
4594 memset(ctx, 0, sizeof(*ctx)); 4486 memset(ctx, 0, sizeof(*ctx));
4595 ctx->dsidev = dsi->pdev; 4487 ctx->dsi = dsi;
4596 ctx->pll = &dsi->pll; 4488 ctx->pll = &dsi->pll;
4597 ctx->config = cfg; 4489 ctx->config = cfg;
4598 ctx->req_pck_min = pck; 4490 ctx->req_pck_min = pck;
@@ -4609,7 +4501,7 @@ static bool dsi_cm_calc(struct dsi_data *dsi,
4609 4501
4610static bool dsi_vm_calc_blanking(struct dsi_clk_calc_ctx *ctx) 4502static bool dsi_vm_calc_blanking(struct dsi_clk_calc_ctx *ctx)
4611{ 4503{
4612 struct dsi_data *dsi = dsi_get_dsidrv_data(ctx->dsidev); 4504 struct dsi_data *dsi = ctx->dsi;
4613 const struct omap_dss_dsi_config *cfg = ctx->config; 4505 const struct omap_dss_dsi_config *cfg = ctx->config;
4614 int bitspp = dsi_get_pixel_size(cfg->pixel_format); 4506 int bitspp = dsi_get_pixel_size(cfg->pixel_format);
4615 int ndl = dsi->num_lanes_used - 1; 4507 int ndl = dsi->num_lanes_used - 1;
@@ -4848,15 +4740,16 @@ static bool dsi_vm_calc_hsdiv_cb(int m_dispc, unsigned long dispc,
4848 else 4740 else
4849 pck_max = ctx->req_pck_max; 4741 pck_max = ctx->req_pck_max;
4850 4742
4851 return dispc_div_calc(dispc, ctx->req_pck_min, pck_max, 4743 return dispc_div_calc(ctx->dsi->dss->dispc, dispc,
4852 dsi_vm_calc_dispc_cb, ctx); 4744 ctx->req_pck_min, pck_max,
4745 dsi_vm_calc_dispc_cb, ctx);
4853} 4746}
4854 4747
4855static bool dsi_vm_calc_pll_cb(int n, int m, unsigned long fint, 4748static bool dsi_vm_calc_pll_cb(int n, int m, unsigned long fint,
4856 unsigned long clkdco, void *data) 4749 unsigned long clkdco, void *data)
4857{ 4750{
4858 struct dsi_clk_calc_ctx *ctx = data; 4751 struct dsi_clk_calc_ctx *ctx = data;
4859 struct dsi_data *dsi = dsi_get_dsidrv_data(ctx->dsidev); 4752 struct dsi_data *dsi = ctx->dsi;
4860 4753
4861 ctx->dsi_cinfo.n = n; 4754 ctx->dsi_cinfo.n = n;
4862 ctx->dsi_cinfo.m = m; 4755 ctx->dsi_cinfo.m = m;
@@ -4883,7 +4776,7 @@ static bool dsi_vm_calc(struct dsi_data *dsi,
4883 clkin = clk_get_rate(dsi->pll.clkin); 4776 clkin = clk_get_rate(dsi->pll.clkin);
4884 4777
4885 memset(ctx, 0, sizeof(*ctx)); 4778 memset(ctx, 0, sizeof(*ctx));
4886 ctx->dsidev = dsi->pdev; 4779 ctx->dsi = dsi;
4887 ctx->pll = &dsi->pll; 4780 ctx->pll = &dsi->pll;
4888 ctx->config = cfg; 4781 ctx->config = cfg;
4889 4782
@@ -4913,8 +4806,7 @@ static bool dsi_vm_calc(struct dsi_data *dsi,
4913static int dsi_set_config(struct omap_dss_device *dssdev, 4806static int dsi_set_config(struct omap_dss_device *dssdev,
4914 const struct omap_dss_dsi_config *config) 4807 const struct omap_dss_dsi_config *config)
4915{ 4808{
4916 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 4809 struct dsi_data *dsi = to_dsi_data(dssdev);
4917 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4918 struct dsi_clk_calc_ctx ctx; 4810 struct dsi_clk_calc_ctx ctx;
4919 bool ok; 4811 bool ok;
4920 int r; 4812 int r;
@@ -5001,8 +4893,7 @@ static enum omap_channel dsi_get_channel(struct dsi_data *dsi)
5001 4893
5002static int dsi_request_vc(struct omap_dss_device *dssdev, int *channel) 4894static int dsi_request_vc(struct omap_dss_device *dssdev, int *channel)
5003{ 4895{
5004 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 4896 struct dsi_data *dsi = to_dsi_data(dssdev);
5005 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5006 int i; 4897 int i;
5007 4898
5008 for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) { 4899 for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) {
@@ -5019,8 +4910,7 @@ static int dsi_request_vc(struct omap_dss_device *dssdev, int *channel)
5019 4910
5020static int dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id) 4911static int dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id)
5021{ 4912{
5022 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 4913 struct dsi_data *dsi = to_dsi_data(dssdev);
5023 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5024 4914
5025 if (vc_id < 0 || vc_id > 3) { 4915 if (vc_id < 0 || vc_id > 3) {
5026 DSSERR("VC ID out of range\n"); 4916 DSSERR("VC ID out of range\n");
@@ -5045,8 +4935,7 @@ static int dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id)
5045 4935
5046static void dsi_release_vc(struct omap_dss_device *dssdev, int channel) 4936static void dsi_release_vc(struct omap_dss_device *dssdev, int channel)
5047{ 4937{
5048 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 4938 struct dsi_data *dsi = to_dsi_data(dssdev);
5049 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5050 4939
5051 if ((channel >= 0 && channel <= 3) && 4940 if ((channel >= 0 && channel <= 3) &&
5052 dsi->vc[channel].dssdev == dssdev) { 4941 dsi->vc[channel].dssdev == dssdev) {
@@ -5056,12 +4945,11 @@ static void dsi_release_vc(struct omap_dss_device *dssdev, int channel)
5056} 4945}
5057 4946
5058 4947
5059static int dsi_get_clocks(struct platform_device *dsidev) 4948static int dsi_get_clocks(struct dsi_data *dsi)
5060{ 4949{
5061 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5062 struct clk *clk; 4950 struct clk *clk;
5063 4951
5064 clk = devm_clk_get(&dsidev->dev, "fck"); 4952 clk = devm_clk_get(dsi->dev, "fck");
5065 if (IS_ERR(clk)) { 4953 if (IS_ERR(clk)) {
5066 DSSERR("can't get fck\n"); 4954 DSSERR("can't get fck\n");
5067 return PTR_ERR(clk); 4955 return PTR_ERR(clk);
@@ -5075,15 +4963,14 @@ static int dsi_get_clocks(struct platform_device *dsidev)
5075static int dsi_connect(struct omap_dss_device *dssdev, 4963static int dsi_connect(struct omap_dss_device *dssdev,
5076 struct omap_dss_device *dst) 4964 struct omap_dss_device *dst)
5077{ 4965{
5078 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); 4966 struct dsi_data *dsi = to_dsi_data(dssdev);
5079 enum omap_channel dispc_channel = dssdev->dispc_channel;
5080 int r; 4967 int r;
5081 4968
5082 r = dsi_regulator_init(dsidev); 4969 r = dsi_regulator_init(dsi);
5083 if (r) 4970 if (r)
5084 return r; 4971 return r;
5085 4972
5086 r = dss_mgr_connect(dispc_channel, dssdev); 4973 r = dss_mgr_connect(&dsi->output, dssdev);
5087 if (r) 4974 if (r)
5088 return r; 4975 return r;
5089 4976
@@ -5091,7 +4978,7 @@ static int dsi_connect(struct omap_dss_device *dssdev,
5091 if (r) { 4978 if (r) {
5092 DSSERR("failed to connect output to new device: %s\n", 4979 DSSERR("failed to connect output to new device: %s\n",
5093 dssdev->name); 4980 dssdev->name);
5094 dss_mgr_disconnect(dispc_channel, dssdev); 4981 dss_mgr_disconnect(&dsi->output, dssdev);
5095 return r; 4982 return r;
5096 } 4983 }
5097 4984
@@ -5101,7 +4988,7 @@ static int dsi_connect(struct omap_dss_device *dssdev,
5101static void dsi_disconnect(struct omap_dss_device *dssdev, 4988static void dsi_disconnect(struct omap_dss_device *dssdev,
5102 struct omap_dss_device *dst) 4989 struct omap_dss_device *dst)
5103{ 4990{
5104 enum omap_channel dispc_channel = dssdev->dispc_channel; 4991 struct dsi_data *dsi = to_dsi_data(dssdev);
5105 4992
5106 WARN_ON(dst != dssdev->dst); 4993 WARN_ON(dst != dssdev->dst);
5107 4994
@@ -5110,7 +4997,7 @@ static void dsi_disconnect(struct omap_dss_device *dssdev,
5110 4997
5111 omapdss_output_unset_device(dssdev); 4998 omapdss_output_unset_device(dssdev);
5112 4999
5113 dss_mgr_disconnect(dispc_channel, dssdev); 5000 dss_mgr_disconnect(&dsi->output, dssdev);
5114} 5001}
5115 5002
5116static const struct omapdss_dsi_ops dsi_ops = { 5003static const struct omapdss_dsi_ops dsi_ops = {
@@ -5152,12 +5039,11 @@ static const struct omapdss_dsi_ops dsi_ops = {
5152 .set_max_rx_packet_size = dsi_vc_set_max_rx_packet_size, 5039 .set_max_rx_packet_size = dsi_vc_set_max_rx_packet_size,
5153}; 5040};
5154 5041
5155static void dsi_init_output(struct platform_device *dsidev) 5042static void dsi_init_output(struct dsi_data *dsi)
5156{ 5043{
5157 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5158 struct omap_dss_device *out = &dsi->output; 5044 struct omap_dss_device *out = &dsi->output;
5159 5045
5160 out->dev = &dsidev->dev; 5046 out->dev = dsi->dev;
5161 out->id = dsi->module_id == 0 ? 5047 out->id = dsi->module_id == 0 ?
5162 OMAP_DSS_OUTPUT_DSI1 : OMAP_DSS_OUTPUT_DSI2; 5048 OMAP_DSS_OUTPUT_DSI1 : OMAP_DSS_OUTPUT_DSI2;
5163 5049
@@ -5170,18 +5056,16 @@ static void dsi_init_output(struct platform_device *dsidev)
5170 omapdss_register_output(out); 5056 omapdss_register_output(out);
5171} 5057}
5172 5058
5173static void dsi_uninit_output(struct platform_device *dsidev) 5059static void dsi_uninit_output(struct dsi_data *dsi)
5174{ 5060{
5175 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5176 struct omap_dss_device *out = &dsi->output; 5061 struct omap_dss_device *out = &dsi->output;
5177 5062
5178 omapdss_unregister_output(out); 5063 omapdss_unregister_output(out);
5179} 5064}
5180 5065
5181static int dsi_probe_of(struct platform_device *pdev) 5066static int dsi_probe_of(struct dsi_data *dsi)
5182{ 5067{
5183 struct device_node *node = pdev->dev.of_node; 5068 struct device_node *node = dsi->dev->of_node;
5184 struct dsi_data *dsi = dsi_get_dsidrv_data(pdev);
5185 struct property *prop; 5069 struct property *prop;
5186 u32 lane_arr[10]; 5070 u32 lane_arr[10];
5187 int len, num_pins; 5071 int len, num_pins;
@@ -5195,7 +5079,7 @@ static int dsi_probe_of(struct platform_device *pdev)
5195 5079
5196 prop = of_find_property(ep, "lanes", &len); 5080 prop = of_find_property(ep, "lanes", &len);
5197 if (prop == NULL) { 5081 if (prop == NULL) {
5198 dev_err(&pdev->dev, "failed to find lane data\n"); 5082 dev_err(dsi->dev, "failed to find lane data\n");
5199 r = -EINVAL; 5083 r = -EINVAL;
5200 goto err; 5084 goto err;
5201 } 5085 }
@@ -5204,14 +5088,14 @@ static int dsi_probe_of(struct platform_device *pdev)
5204 5088
5205 if (num_pins < 4 || num_pins % 2 != 0 || 5089 if (num_pins < 4 || num_pins % 2 != 0 ||
5206 num_pins > dsi->num_lanes_supported * 2) { 5090 num_pins > dsi->num_lanes_supported * 2) {
5207 dev_err(&pdev->dev, "bad number of lanes\n"); 5091 dev_err(dsi->dev, "bad number of lanes\n");
5208 r = -EINVAL; 5092 r = -EINVAL;
5209 goto err; 5093 goto err;
5210 } 5094 }
5211 5095
5212 r = of_property_read_u32_array(ep, "lanes", lane_arr, num_pins); 5096 r = of_property_read_u32_array(ep, "lanes", lane_arr, num_pins);
5213 if (r) { 5097 if (r) {
5214 dev_err(&pdev->dev, "failed to read lane data\n"); 5098 dev_err(dsi->dev, "failed to read lane data\n");
5215 goto err; 5099 goto err;
5216 } 5100 }
5217 5101
@@ -5221,7 +5105,7 @@ static int dsi_probe_of(struct platform_device *pdev)
5221 5105
5222 r = dsi_configure_pins(&dsi->output, &pin_cfg); 5106 r = dsi_configure_pins(&dsi->output, &pin_cfg);
5223 if (r) { 5107 if (r) {
5224 dev_err(&pdev->dev, "failed to configure pins"); 5108 dev_err(dsi->dev, "failed to configure pins");
5225 goto err; 5109 goto err;
5226 } 5110 }
5227 5111
@@ -5321,14 +5205,13 @@ static const struct dss_pll_hw dss_omap5_dsi_pll_hw = {
5321 .has_refsel = true, 5205 .has_refsel = true,
5322}; 5206};
5323 5207
5324static int dsi_init_pll_data(struct platform_device *dsidev) 5208static int dsi_init_pll_data(struct dss_device *dss, struct dsi_data *dsi)
5325{ 5209{
5326 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5327 struct dss_pll *pll = &dsi->pll; 5210 struct dss_pll *pll = &dsi->pll;
5328 struct clk *clk; 5211 struct clk *clk;
5329 int r; 5212 int r;
5330 5213
5331 clk = devm_clk_get(&dsidev->dev, "sys_clk"); 5214 clk = devm_clk_get(dsi->dev, "sys_clk");
5332 if (IS_ERR(clk)) { 5215 if (IS_ERR(clk)) {
5333 DSSERR("can't get sys_clk\n"); 5216 DSSERR("can't get sys_clk\n");
5334 return PTR_ERR(clk); 5217 return PTR_ERR(clk);
@@ -5341,7 +5224,7 @@ static int dsi_init_pll_data(struct platform_device *dsidev)
5341 pll->hw = dsi->data->pll_hw; 5224 pll->hw = dsi->data->pll_hw;
5342 pll->ops = &dsi_pll_ops; 5225 pll->ops = &dsi_pll_ops;
5343 5226
5344 r = dss_pll_register(pll); 5227 r = dss_pll_register(dss, pll);
5345 if (r) 5228 if (r)
5346 return r; 5229 return r;
5347 5230
@@ -5413,9 +5296,11 @@ static const struct soc_device_attribute dsi_soc_devices[] = {
5413 { .machine = "AM35*", .data = &dsi_of_data_omap34xx }, 5296 { .machine = "AM35*", .data = &dsi_of_data_omap34xx },
5414 { /* sentinel */ } 5297 { /* sentinel */ }
5415}; 5298};
5299
5416static int dsi_bind(struct device *dev, struct device *master, void *data) 5300static int dsi_bind(struct device *dev, struct device *master, void *data)
5417{ 5301{
5418 struct platform_device *dsidev = to_platform_device(dev); 5302 struct platform_device *pdev = to_platform_device(dev);
5303 struct dss_device *dss = dss_get_device(master);
5419 const struct soc_device_attribute *soc; 5304 const struct soc_device_attribute *soc;
5420 const struct dsi_module_id_data *d; 5305 const struct dsi_module_id_data *d;
5421 u32 rev; 5306 u32 rev;
@@ -5424,12 +5309,13 @@ static int dsi_bind(struct device *dev, struct device *master, void *data)
5424 struct resource *dsi_mem; 5309 struct resource *dsi_mem;
5425 struct resource *res; 5310 struct resource *res;
5426 5311
5427 dsi = devm_kzalloc(&dsidev->dev, sizeof(*dsi), GFP_KERNEL); 5312 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
5428 if (!dsi) 5313 if (!dsi)
5429 return -ENOMEM; 5314 return -ENOMEM;
5430 5315
5431 dsi->pdev = dsidev; 5316 dsi->dss = dss;
5432 dev_set_drvdata(&dsidev->dev, dsi); 5317 dsi->dev = dev;
5318 dev_set_drvdata(dev, dsi);
5433 5319
5434 spin_lock_init(&dsi->irq_lock); 5320 spin_lock_init(&dsi->irq_lock);
5435 spin_lock_init(&dsi->errors_lock); 5321 spin_lock_init(&dsi->errors_lock);
@@ -5450,29 +5336,29 @@ static int dsi_bind(struct device *dev, struct device *master, void *data)
5450 timer_setup(&dsi->te_timer, dsi_te_timeout, 0); 5336 timer_setup(&dsi->te_timer, dsi_te_timeout, 0);
5451#endif 5337#endif
5452 5338
5453 dsi_mem = platform_get_resource_byname(dsidev, IORESOURCE_MEM, "proto"); 5339 dsi_mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "proto");
5454 dsi->proto_base = devm_ioremap_resource(&dsidev->dev, dsi_mem); 5340 dsi->proto_base = devm_ioremap_resource(dev, dsi_mem);
5455 if (IS_ERR(dsi->proto_base)) 5341 if (IS_ERR(dsi->proto_base))
5456 return PTR_ERR(dsi->proto_base); 5342 return PTR_ERR(dsi->proto_base);
5457 5343
5458 res = platform_get_resource_byname(dsidev, IORESOURCE_MEM, "phy"); 5344 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
5459 dsi->phy_base = devm_ioremap_resource(&dsidev->dev, res); 5345 dsi->phy_base = devm_ioremap_resource(dev, res);
5460 if (IS_ERR(dsi->phy_base)) 5346 if (IS_ERR(dsi->phy_base))
5461 return PTR_ERR(dsi->phy_base); 5347 return PTR_ERR(dsi->phy_base);
5462 5348
5463 res = platform_get_resource_byname(dsidev, IORESOURCE_MEM, "pll"); 5349 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pll");
5464 dsi->pll_base = devm_ioremap_resource(&dsidev->dev, res); 5350 dsi->pll_base = devm_ioremap_resource(dev, res);
5465 if (IS_ERR(dsi->pll_base)) 5351 if (IS_ERR(dsi->pll_base))
5466 return PTR_ERR(dsi->pll_base); 5352 return PTR_ERR(dsi->pll_base);
5467 5353
5468 dsi->irq = platform_get_irq(dsi->pdev, 0); 5354 dsi->irq = platform_get_irq(pdev, 0);
5469 if (dsi->irq < 0) { 5355 if (dsi->irq < 0) {
5470 DSSERR("platform_get_irq failed\n"); 5356 DSSERR("platform_get_irq failed\n");
5471 return -ENODEV; 5357 return -ENODEV;
5472 } 5358 }
5473 5359
5474 r = devm_request_irq(&dsidev->dev, dsi->irq, omap_dsi_irq_handler, 5360 r = devm_request_irq(dev, dsi->irq, omap_dsi_irq_handler,
5475 IRQF_SHARED, dev_name(&dsidev->dev), dsi->pdev); 5361 IRQF_SHARED, dev_name(dev), dsi);
5476 if (r < 0) { 5362 if (r < 0) {
5477 DSSERR("request_irq failed\n"); 5363 DSSERR("request_irq failed\n");
5478 return r; 5364 return r;
@@ -5520,83 +5406,92 @@ static int dsi_bind(struct device *dev, struct device *master, void *data)
5520 dsi->vc[i].vc_id = 0; 5406 dsi->vc[i].vc_id = 0;
5521 } 5407 }
5522 5408
5523 r = dsi_get_clocks(dsidev); 5409 r = dsi_get_clocks(dsi);
5524 if (r) 5410 if (r)
5525 return r; 5411 return r;
5526 5412
5527 dsi_init_pll_data(dsidev); 5413 dsi_init_pll_data(dss, dsi);
5528 5414
5529 pm_runtime_enable(&dsidev->dev); 5415 pm_runtime_enable(dev);
5530 5416
5531 r = dsi_runtime_get(dsidev); 5417 r = dsi_runtime_get(dsi);
5532 if (r) 5418 if (r)
5533 goto err_runtime_get; 5419 goto err_runtime_get;
5534 5420
5535 rev = dsi_read_reg(dsidev, DSI_REVISION); 5421 rev = dsi_read_reg(dsi, DSI_REVISION);
5536 dev_dbg(&dsidev->dev, "OMAP DSI rev %d.%d\n", 5422 dev_dbg(dev, "OMAP DSI rev %d.%d\n",
5537 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); 5423 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
5538 5424
5539 /* DSI on OMAP3 doesn't have register DSI_GNQ, set number 5425 /* DSI on OMAP3 doesn't have register DSI_GNQ, set number
5540 * of data to 3 by default */ 5426 * of data to 3 by default */
5541 if (dsi->data->quirks & DSI_QUIRK_GNQ) 5427 if (dsi->data->quirks & DSI_QUIRK_GNQ)
5542 /* NB_DATA_LANES */ 5428 /* NB_DATA_LANES */
5543 dsi->num_lanes_supported = 1 + REG_GET(dsidev, DSI_GNQ, 11, 9); 5429 dsi->num_lanes_supported = 1 + REG_GET(dsi, DSI_GNQ, 11, 9);
5544 else 5430 else
5545 dsi->num_lanes_supported = 3; 5431 dsi->num_lanes_supported = 3;
5546 5432
5547 dsi->line_buffer_size = dsi_get_line_buf_size(dsidev); 5433 dsi->line_buffer_size = dsi_get_line_buf_size(dsi);
5548 5434
5549 dsi_init_output(dsidev); 5435 dsi_init_output(dsi);
5550 5436
5551 r = dsi_probe_of(dsidev); 5437 r = dsi_probe_of(dsi);
5552 if (r) { 5438 if (r) {
5553 DSSERR("Invalid DSI DT data\n"); 5439 DSSERR("Invalid DSI DT data\n");
5554 goto err_probe_of; 5440 goto err_probe_of;
5555 } 5441 }
5556 5442
5557 r = of_platform_populate(dsidev->dev.of_node, NULL, NULL, &dsidev->dev); 5443 r = of_platform_populate(dev->of_node, NULL, NULL, dev);
5558 if (r) 5444 if (r)
5559 DSSERR("Failed to populate DSI child devices: %d\n", r); 5445 DSSERR("Failed to populate DSI child devices: %d\n", r);
5560 5446
5561 dsi_runtime_put(dsidev); 5447 dsi_runtime_put(dsi);
5562 5448
5563 if (dsi->module_id == 0) 5449 if (dsi->module_id == 0)
5564 dss_debugfs_create_file("dsi1_regs", dsi1_dump_regs); 5450 dsi->debugfs.regs = dss_debugfs_create_file(dss, "dsi1_regs",
5565 else if (dsi->module_id == 1) 5451 dsi1_dump_regs,
5566 dss_debugfs_create_file("dsi2_regs", dsi2_dump_regs); 5452 &dsi);
5567 5453 else
5454 dsi->debugfs.regs = dss_debugfs_create_file(dss, "dsi2_regs",
5455 dsi2_dump_regs,
5456 &dsi);
5568#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS 5457#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
5569 if (dsi->module_id == 0) 5458 if (dsi->module_id == 0)
5570 dss_debugfs_create_file("dsi1_irqs", dsi1_dump_irqs); 5459 dsi->debugfs.irqs = dss_debugfs_create_file(dss, "dsi1_irqs",
5571 else if (dsi->module_id == 1) 5460 dsi1_dump_irqs,
5572 dss_debugfs_create_file("dsi2_irqs", dsi2_dump_irqs); 5461 &dsi);
5462 else
5463 dsi->debugfs.irqs = dss_debugfs_create_file(dss, "dsi2_irqs",
5464 dsi2_dump_irqs,
5465 &dsi);
5573#endif 5466#endif
5574 5467
5575 return 0; 5468 return 0;
5576 5469
5577err_probe_of: 5470err_probe_of:
5578 dsi_uninit_output(dsidev); 5471 dsi_uninit_output(dsi);
5579 dsi_runtime_put(dsidev); 5472 dsi_runtime_put(dsi);
5580 5473
5581err_runtime_get: 5474err_runtime_get:
5582 pm_runtime_disable(&dsidev->dev); 5475 pm_runtime_disable(dev);
5583 return r; 5476 return r;
5584} 5477}
5585 5478
5586static void dsi_unbind(struct device *dev, struct device *master, void *data) 5479static void dsi_unbind(struct device *dev, struct device *master, void *data)
5587{ 5480{
5588 struct platform_device *dsidev = to_platform_device(dev); 5481 struct dsi_data *dsi = dev_get_drvdata(dev);
5589 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5590 5482
5591 of_platform_depopulate(&dsidev->dev); 5483 dss_debugfs_remove_file(dsi->debugfs.irqs);
5484 dss_debugfs_remove_file(dsi->debugfs.regs);
5485
5486 of_platform_depopulate(dev);
5592 5487
5593 WARN_ON(dsi->scp_clk_refcount > 0); 5488 WARN_ON(dsi->scp_clk_refcount > 0);
5594 5489
5595 dss_pll_unregister(&dsi->pll); 5490 dss_pll_unregister(&dsi->pll);
5596 5491
5597 dsi_uninit_output(dsidev); 5492 dsi_uninit_output(dsi);
5598 5493
5599 pm_runtime_disable(&dsidev->dev); 5494 pm_runtime_disable(dev);
5600 5495
5601 if (dsi->vdds_dsi_reg != NULL && dsi->vdds_dsi_enabled) { 5496 if (dsi->vdds_dsi_reg != NULL && dsi->vdds_dsi_enabled) {
5602 regulator_disable(dsi->vdds_dsi_reg); 5497 regulator_disable(dsi->vdds_dsi_reg);
@@ -5622,8 +5517,7 @@ static int dsi_remove(struct platform_device *pdev)
5622 5517
5623static int dsi_runtime_suspend(struct device *dev) 5518static int dsi_runtime_suspend(struct device *dev)
5624{ 5519{
5625 struct platform_device *pdev = to_platform_device(dev); 5520 struct dsi_data *dsi = dev_get_drvdata(dev);
5626 struct dsi_data *dsi = dsi_get_dsidrv_data(pdev);
5627 5521
5628 dsi->is_enabled = false; 5522 dsi->is_enabled = false;
5629 /* ensure the irq handler sees the is_enabled value */ 5523 /* ensure the irq handler sees the is_enabled value */
@@ -5631,18 +5525,17 @@ static int dsi_runtime_suspend(struct device *dev)
5631 /* wait for current handler to finish before turning the DSI off */ 5525 /* wait for current handler to finish before turning the DSI off */
5632 synchronize_irq(dsi->irq); 5526 synchronize_irq(dsi->irq);
5633 5527
5634 dispc_runtime_put(); 5528 dispc_runtime_put(dsi->dss->dispc);
5635 5529
5636 return 0; 5530 return 0;
5637} 5531}
5638 5532
5639static int dsi_runtime_resume(struct device *dev) 5533static int dsi_runtime_resume(struct device *dev)
5640{ 5534{
5641 struct platform_device *pdev = to_platform_device(dev); 5535 struct dsi_data *dsi = dev_get_drvdata(dev);
5642 struct dsi_data *dsi = dsi_get_dsidrv_data(pdev);
5643 int r; 5536 int r;
5644 5537
5645 r = dispc_runtime_get(); 5538 r = dispc_runtime_get(dsi->dss->dispc);
5646 if (r) 5539 if (r)
5647 return r; 5540 return r;
5648 5541
diff --git a/drivers/gpu/drm/omapdrm/dss/dss-of.c b/drivers/gpu/drm/omapdrm/dss/dss-of.c
index 967d9e1b34e5..4602a79c6c44 100644
--- a/drivers/gpu/drm/omapdrm/dss/dss-of.c
+++ b/drivers/gpu/drm/omapdrm/dss/dss-of.c
@@ -44,7 +44,6 @@ struct device_node *dss_of_port_get_parent_device(struct device_node *port)
44 44
45 return NULL; 45 return NULL;
46} 46}
47EXPORT_SYMBOL_GPL(dss_of_port_get_parent_device);
48 47
49u32 dss_of_port_get_port_number(struct device_node *port) 48u32 dss_of_port_get_port_number(struct device_node *port)
50{ 49{
@@ -57,7 +56,6 @@ u32 dss_of_port_get_port_number(struct device_node *port)
57 56
58 return reg; 57 return reg;
59} 58}
60EXPORT_SYMBOL_GPL(dss_of_port_get_port_number);
61 59
62struct omap_dss_device * 60struct omap_dss_device *
63omapdss_of_find_source_for_first_ep(struct device_node *node) 61omapdss_of_find_source_for_first_ep(struct device_node *node)
diff --git a/drivers/gpu/drm/omapdrm/dss/dss.c b/drivers/gpu/drm/omapdrm/dss/dss.c
index 04300b2da1b1..0b908e9de792 100644
--- a/drivers/gpu/drm/omapdrm/dss/dss.c
+++ b/drivers/gpu/drm/omapdrm/dss/dss.c
@@ -48,8 +48,6 @@
48#include "omapdss.h" 48#include "omapdss.h"
49#include "dss.h" 49#include "dss.h"
50 50
51#define DSS_SZ_REGS SZ_512
52
53struct dss_reg { 51struct dss_reg {
54 u16 idx; 52 u16 idx;
55}; 53};
@@ -64,16 +62,19 @@ struct dss_reg {
64#define DSS_PLL_CONTROL DSS_REG(0x0048) 62#define DSS_PLL_CONTROL DSS_REG(0x0048)
65#define DSS_SDI_STATUS DSS_REG(0x005C) 63#define DSS_SDI_STATUS DSS_REG(0x005C)
66 64
67#define REG_GET(idx, start, end) \ 65#define REG_GET(dss, idx, start, end) \
68 FLD_GET(dss_read_reg(idx), start, end) 66 FLD_GET(dss_read_reg(dss, idx), start, end)
69 67
70#define REG_FLD_MOD(idx, val, start, end) \ 68#define REG_FLD_MOD(dss, idx, val, start, end) \
71 dss_write_reg(idx, FLD_MOD(dss_read_reg(idx), val, start, end)) 69 dss_write_reg(dss, idx, \
70 FLD_MOD(dss_read_reg(dss, idx), val, start, end))
72 71
73struct dss_ops { 72struct dss_ops {
74 int (*dpi_select_source)(int port, enum omap_channel channel); 73 int (*dpi_select_source)(struct dss_device *dss, int port,
75 int (*select_lcd_source)(enum omap_channel channel, 74 enum omap_channel channel);
76 enum dss_clk_source clk_src); 75 int (*select_lcd_source)(struct dss_device *dss,
76 enum omap_channel channel,
77 enum dss_clk_source clk_src);
77}; 78};
78 79
79struct dss_features { 80struct dss_features {
@@ -90,33 +91,6 @@ struct dss_features {
90 bool has_lcd_clk_src; 91 bool has_lcd_clk_src;
91}; 92};
92 93
93static struct {
94 struct platform_device *pdev;
95 void __iomem *base;
96 struct regmap *syscon_pll_ctrl;
97 u32 syscon_pll_ctrl_offset;
98
99 struct clk *parent_clk;
100 struct clk *dss_clk;
101 unsigned long dss_clk_rate;
102
103 unsigned long cache_req_pck;
104 unsigned long cache_prate;
105 struct dispc_clock_info cache_dispc_cinfo;
106
107 enum dss_clk_source dsi_clk_source[MAX_NUM_DSI];
108 enum dss_clk_source dispc_clk_source;
109 enum dss_clk_source lcd_clk_source[MAX_DSS_LCD_MANAGERS];
110
111 bool ctx_valid;
112 u32 ctx[DSS_SZ_REGS / sizeof(u32)];
113
114 const struct dss_features *feat;
115
116 struct dss_pll *video1_pll;
117 struct dss_pll *video2_pll;
118} dss;
119
120static const char * const dss_generic_clk_source_names[] = { 94static const char * const dss_generic_clk_source_names[] = {
121 [DSS_CLK_SRC_FCK] = "FCK", 95 [DSS_CLK_SRC_FCK] = "FCK",
122 [DSS_CLK_SRC_PLL1_1] = "PLL1:1", 96 [DSS_CLK_SRC_PLL1_1] = "PLL1:1",
@@ -128,49 +102,50 @@ static const char * const dss_generic_clk_source_names[] = {
128 [DSS_CLK_SRC_HDMI_PLL] = "HDMI PLL", 102 [DSS_CLK_SRC_HDMI_PLL] = "HDMI PLL",
129}; 103};
130 104
131static inline void dss_write_reg(const struct dss_reg idx, u32 val) 105static inline void dss_write_reg(struct dss_device *dss,
106 const struct dss_reg idx, u32 val)
132{ 107{
133 __raw_writel(val, dss.base + idx.idx); 108 __raw_writel(val, dss->base + idx.idx);
134} 109}
135 110
136static inline u32 dss_read_reg(const struct dss_reg idx) 111static inline u32 dss_read_reg(struct dss_device *dss, const struct dss_reg idx)
137{ 112{
138 return __raw_readl(dss.base + idx.idx); 113 return __raw_readl(dss->base + idx.idx);
139} 114}
140 115
141#define SR(reg) \ 116#define SR(dss, reg) \
142 dss.ctx[(DSS_##reg).idx / sizeof(u32)] = dss_read_reg(DSS_##reg) 117 dss->ctx[(DSS_##reg).idx / sizeof(u32)] = dss_read_reg(dss, DSS_##reg)
143#define RR(reg) \ 118#define RR(dss, reg) \
144 dss_write_reg(DSS_##reg, dss.ctx[(DSS_##reg).idx / sizeof(u32)]) 119 dss_write_reg(dss, DSS_##reg, dss->ctx[(DSS_##reg).idx / sizeof(u32)])
145 120
146static void dss_save_context(void) 121static void dss_save_context(struct dss_device *dss)
147{ 122{
148 DSSDBG("dss_save_context\n"); 123 DSSDBG("dss_save_context\n");
149 124
150 SR(CONTROL); 125 SR(dss, CONTROL);
151 126
152 if (dss.feat->outputs[OMAP_DSS_CHANNEL_LCD] & OMAP_DSS_OUTPUT_SDI) { 127 if (dss->feat->outputs[OMAP_DSS_CHANNEL_LCD] & OMAP_DSS_OUTPUT_SDI) {
153 SR(SDI_CONTROL); 128 SR(dss, SDI_CONTROL);
154 SR(PLL_CONTROL); 129 SR(dss, PLL_CONTROL);
155 } 130 }
156 131
157 dss.ctx_valid = true; 132 dss->ctx_valid = true;
158 133
159 DSSDBG("context saved\n"); 134 DSSDBG("context saved\n");
160} 135}
161 136
162static void dss_restore_context(void) 137static void dss_restore_context(struct dss_device *dss)
163{ 138{
164 DSSDBG("dss_restore_context\n"); 139 DSSDBG("dss_restore_context\n");
165 140
166 if (!dss.ctx_valid) 141 if (!dss->ctx_valid)
167 return; 142 return;
168 143
169 RR(CONTROL); 144 RR(dss, CONTROL);
170 145
171 if (dss.feat->outputs[OMAP_DSS_CHANNEL_LCD] & OMAP_DSS_OUTPUT_SDI) { 146 if (dss->feat->outputs[OMAP_DSS_CHANNEL_LCD] & OMAP_DSS_OUTPUT_SDI) {
172 RR(SDI_CONTROL); 147 RR(dss, SDI_CONTROL);
173 RR(PLL_CONTROL); 148 RR(dss, PLL_CONTROL);
174 } 149 }
175 150
176 DSSDBG("context restored\n"); 151 DSSDBG("context restored\n");
@@ -179,17 +154,17 @@ static void dss_restore_context(void)
179#undef SR 154#undef SR
180#undef RR 155#undef RR
181 156
182void dss_ctrl_pll_enable(enum dss_pll_id pll_id, bool enable) 157void dss_ctrl_pll_enable(struct dss_pll *pll, bool enable)
183{ 158{
184 unsigned shift; 159 unsigned int shift;
185 unsigned val; 160 unsigned int val;
186 161
187 if (!dss.syscon_pll_ctrl) 162 if (!pll->dss->syscon_pll_ctrl)
188 return; 163 return;
189 164
190 val = !enable; 165 val = !enable;
191 166
192 switch (pll_id) { 167 switch (pll->id) {
193 case DSS_PLL_VIDEO1: 168 case DSS_PLL_VIDEO1:
194 shift = 0; 169 shift = 0;
195 break; 170 break;
@@ -200,20 +175,22 @@ void dss_ctrl_pll_enable(enum dss_pll_id pll_id, bool enable)
200 shift = 2; 175 shift = 2;
201 break; 176 break;
202 default: 177 default:
203 DSSERR("illegal DSS PLL ID %d\n", pll_id); 178 DSSERR("illegal DSS PLL ID %d\n", pll->id);
204 return; 179 return;
205 } 180 }
206 181
207 regmap_update_bits(dss.syscon_pll_ctrl, dss.syscon_pll_ctrl_offset, 182 regmap_update_bits(pll->dss->syscon_pll_ctrl,
208 1 << shift, val << shift); 183 pll->dss->syscon_pll_ctrl_offset,
184 1 << shift, val << shift);
209} 185}
210 186
211static int dss_ctrl_pll_set_control_mux(enum dss_clk_source clk_src, 187static int dss_ctrl_pll_set_control_mux(struct dss_device *dss,
212 enum omap_channel channel) 188 enum dss_clk_source clk_src,
189 enum omap_channel channel)
213{ 190{
214 unsigned shift, val; 191 unsigned int shift, val;
215 192
216 if (!dss.syscon_pll_ctrl) 193 if (!dss->syscon_pll_ctrl)
217 return -EINVAL; 194 return -EINVAL;
218 195
219 switch (channel) { 196 switch (channel) {
@@ -268,47 +245,47 @@ static int dss_ctrl_pll_set_control_mux(enum dss_clk_source clk_src,
268 return -EINVAL; 245 return -EINVAL;
269 } 246 }
270 247
271 regmap_update_bits(dss.syscon_pll_ctrl, dss.syscon_pll_ctrl_offset, 248 regmap_update_bits(dss->syscon_pll_ctrl, dss->syscon_pll_ctrl_offset,
272 0x3 << shift, val << shift); 249 0x3 << shift, val << shift);
273 250
274 return 0; 251 return 0;
275} 252}
276 253
277void dss_sdi_init(int datapairs) 254void dss_sdi_init(struct dss_device *dss, int datapairs)
278{ 255{
279 u32 l; 256 u32 l;
280 257
281 BUG_ON(datapairs > 3 || datapairs < 1); 258 BUG_ON(datapairs > 3 || datapairs < 1);
282 259
283 l = dss_read_reg(DSS_SDI_CONTROL); 260 l = dss_read_reg(dss, DSS_SDI_CONTROL);
284 l = FLD_MOD(l, 0xf, 19, 15); /* SDI_PDIV */ 261 l = FLD_MOD(l, 0xf, 19, 15); /* SDI_PDIV */
285 l = FLD_MOD(l, datapairs-1, 3, 2); /* SDI_PRSEL */ 262 l = FLD_MOD(l, datapairs-1, 3, 2); /* SDI_PRSEL */
286 l = FLD_MOD(l, 2, 1, 0); /* SDI_BWSEL */ 263 l = FLD_MOD(l, 2, 1, 0); /* SDI_BWSEL */
287 dss_write_reg(DSS_SDI_CONTROL, l); 264 dss_write_reg(dss, DSS_SDI_CONTROL, l);
288 265
289 l = dss_read_reg(DSS_PLL_CONTROL); 266 l = dss_read_reg(dss, DSS_PLL_CONTROL);
290 l = FLD_MOD(l, 0x7, 25, 22); /* SDI_PLL_FREQSEL */ 267 l = FLD_MOD(l, 0x7, 25, 22); /* SDI_PLL_FREQSEL */
291 l = FLD_MOD(l, 0xb, 16, 11); /* SDI_PLL_REGN */ 268 l = FLD_MOD(l, 0xb, 16, 11); /* SDI_PLL_REGN */
292 l = FLD_MOD(l, 0xb4, 10, 1); /* SDI_PLL_REGM */ 269 l = FLD_MOD(l, 0xb4, 10, 1); /* SDI_PLL_REGM */
293 dss_write_reg(DSS_PLL_CONTROL, l); 270 dss_write_reg(dss, DSS_PLL_CONTROL, l);
294} 271}
295 272
296int dss_sdi_enable(void) 273int dss_sdi_enable(struct dss_device *dss)
297{ 274{
298 unsigned long timeout; 275 unsigned long timeout;
299 276
300 dispc_pck_free_enable(1); 277 dispc_pck_free_enable(dss->dispc, 1);
301 278
302 /* Reset SDI PLL */ 279 /* Reset SDI PLL */
303 REG_FLD_MOD(DSS_PLL_CONTROL, 1, 18, 18); /* SDI_PLL_SYSRESET */ 280 REG_FLD_MOD(dss, DSS_PLL_CONTROL, 1, 18, 18); /* SDI_PLL_SYSRESET */
304 udelay(1); /* wait 2x PCLK */ 281 udelay(1); /* wait 2x PCLK */
305 282
306 /* Lock SDI PLL */ 283 /* Lock SDI PLL */
307 REG_FLD_MOD(DSS_PLL_CONTROL, 1, 28, 28); /* SDI_PLL_GOBIT */ 284 REG_FLD_MOD(dss, DSS_PLL_CONTROL, 1, 28, 28); /* SDI_PLL_GOBIT */
308 285
309 /* Waiting for PLL lock request to complete */ 286 /* Waiting for PLL lock request to complete */
310 timeout = jiffies + msecs_to_jiffies(500); 287 timeout = jiffies + msecs_to_jiffies(500);
311 while (dss_read_reg(DSS_SDI_STATUS) & (1 << 6)) { 288 while (dss_read_reg(dss, DSS_SDI_STATUS) & (1 << 6)) {
312 if (time_after_eq(jiffies, timeout)) { 289 if (time_after_eq(jiffies, timeout)) {
313 DSSERR("PLL lock request timed out\n"); 290 DSSERR("PLL lock request timed out\n");
314 goto err1; 291 goto err1;
@@ -316,22 +293,22 @@ int dss_sdi_enable(void)
316 } 293 }
317 294
318 /* Clearing PLL_GO bit */ 295 /* Clearing PLL_GO bit */
319 REG_FLD_MOD(DSS_PLL_CONTROL, 0, 28, 28); 296 REG_FLD_MOD(dss, DSS_PLL_CONTROL, 0, 28, 28);
320 297
321 /* Waiting for PLL to lock */ 298 /* Waiting for PLL to lock */
322 timeout = jiffies + msecs_to_jiffies(500); 299 timeout = jiffies + msecs_to_jiffies(500);
323 while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 5))) { 300 while (!(dss_read_reg(dss, DSS_SDI_STATUS) & (1 << 5))) {
324 if (time_after_eq(jiffies, timeout)) { 301 if (time_after_eq(jiffies, timeout)) {
325 DSSERR("PLL lock timed out\n"); 302 DSSERR("PLL lock timed out\n");
326 goto err1; 303 goto err1;
327 } 304 }
328 } 305 }
329 306
330 dispc_lcd_enable_signal(1); 307 dispc_lcd_enable_signal(dss->dispc, 1);
331 308
332 /* Waiting for SDI reset to complete */ 309 /* Waiting for SDI reset to complete */
333 timeout = jiffies + msecs_to_jiffies(500); 310 timeout = jiffies + msecs_to_jiffies(500);
334 while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 2))) { 311 while (!(dss_read_reg(dss, DSS_SDI_STATUS) & (1 << 2))) {
335 if (time_after_eq(jiffies, timeout)) { 312 if (time_after_eq(jiffies, timeout)) {
336 DSSERR("SDI reset timed out\n"); 313 DSSERR("SDI reset timed out\n");
337 goto err2; 314 goto err2;
@@ -341,24 +318,24 @@ int dss_sdi_enable(void)
341 return 0; 318 return 0;
342 319
343 err2: 320 err2:
344 dispc_lcd_enable_signal(0); 321 dispc_lcd_enable_signal(dss->dispc, 0);
345 err1: 322 err1:
346 /* Reset SDI PLL */ 323 /* Reset SDI PLL */
347 REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */ 324 REG_FLD_MOD(dss, DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */
348 325
349 dispc_pck_free_enable(0); 326 dispc_pck_free_enable(dss->dispc, 0);
350 327
351 return -ETIMEDOUT; 328 return -ETIMEDOUT;
352} 329}
353 330
354void dss_sdi_disable(void) 331void dss_sdi_disable(struct dss_device *dss)
355{ 332{
356 dispc_lcd_enable_signal(0); 333 dispc_lcd_enable_signal(dss->dispc, 0);
357 334
358 dispc_pck_free_enable(0); 335 dispc_pck_free_enable(dss->dispc, 0);
359 336
360 /* Reset SDI PLL */ 337 /* Reset SDI PLL */
361 REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */ 338 REG_FLD_MOD(dss, DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */
362} 339}
363 340
364const char *dss_get_clk_source_name(enum dss_clk_source clk_src) 341const char *dss_get_clk_source_name(enum dss_clk_source clk_src)
@@ -366,48 +343,61 @@ const char *dss_get_clk_source_name(enum dss_clk_source clk_src)
366 return dss_generic_clk_source_names[clk_src]; 343 return dss_generic_clk_source_names[clk_src];
367} 344}
368 345
369#if defined(CONFIG_OMAP2_DSS_DEBUGFS) 346static void dss_dump_clocks(struct dss_device *dss, struct seq_file *s)
370static void dss_dump_clocks(struct seq_file *s)
371{ 347{
372 const char *fclk_name; 348 const char *fclk_name;
373 unsigned long fclk_rate; 349 unsigned long fclk_rate;
374 350
375 if (dss_runtime_get()) 351 if (dss_runtime_get(dss))
376 return; 352 return;
377 353
378 seq_printf(s, "- DSS -\n"); 354 seq_printf(s, "- DSS -\n");
379 355
380 fclk_name = dss_get_clk_source_name(DSS_CLK_SRC_FCK); 356 fclk_name = dss_get_clk_source_name(DSS_CLK_SRC_FCK);
381 fclk_rate = clk_get_rate(dss.dss_clk); 357 fclk_rate = clk_get_rate(dss->dss_clk);
382 358
383 seq_printf(s, "%s = %lu\n", 359 seq_printf(s, "%s = %lu\n",
384 fclk_name, 360 fclk_name,
385 fclk_rate); 361 fclk_rate);
386 362
387 dss_runtime_put(); 363 dss_runtime_put(dss);
388} 364}
389#endif
390 365
391static void dss_dump_regs(struct seq_file *s) 366static int dss_dump_regs(struct seq_file *s, void *p)
392{ 367{
393#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dss_read_reg(r)) 368 struct dss_device *dss = s->private;
394 369
395 if (dss_runtime_get()) 370#define DUMPREG(dss, r) seq_printf(s, "%-35s %08x\n", #r, dss_read_reg(dss, r))
396 return; 371
372 if (dss_runtime_get(dss))
373 return 0;
397 374
398 DUMPREG(DSS_REVISION); 375 DUMPREG(dss, DSS_REVISION);
399 DUMPREG(DSS_SYSCONFIG); 376 DUMPREG(dss, DSS_SYSCONFIG);
400 DUMPREG(DSS_SYSSTATUS); 377 DUMPREG(dss, DSS_SYSSTATUS);
401 DUMPREG(DSS_CONTROL); 378 DUMPREG(dss, DSS_CONTROL);
402 379
403 if (dss.feat->outputs[OMAP_DSS_CHANNEL_LCD] & OMAP_DSS_OUTPUT_SDI) { 380 if (dss->feat->outputs[OMAP_DSS_CHANNEL_LCD] & OMAP_DSS_OUTPUT_SDI) {
404 DUMPREG(DSS_SDI_CONTROL); 381 DUMPREG(dss, DSS_SDI_CONTROL);
405 DUMPREG(DSS_PLL_CONTROL); 382 DUMPREG(dss, DSS_PLL_CONTROL);
406 DUMPREG(DSS_SDI_STATUS); 383 DUMPREG(dss, DSS_SDI_STATUS);
407 } 384 }
408 385
409 dss_runtime_put(); 386 dss_runtime_put(dss);
410#undef DUMPREG 387#undef DUMPREG
388 return 0;
389}
390
391static int dss_debug_dump_clocks(struct seq_file *s, void *p)
392{
393 struct dss_device *dss = s->private;
394
395 dss_dump_clocks(dss, s);
396 dispc_dump_clocks(dss->dispc, s);
397#ifdef CONFIG_OMAP2_DSS_DSI
398 dsi_dump_clocks(s);
399#endif
400 return 0;
411} 401}
412 402
413static int dss_get_channel_index(enum omap_channel channel) 403static int dss_get_channel_index(enum omap_channel channel)
@@ -425,7 +415,8 @@ static int dss_get_channel_index(enum omap_channel channel)
425 } 415 }
426} 416}
427 417
428static void dss_select_dispc_clk_source(enum dss_clk_source clk_src) 418static void dss_select_dispc_clk_source(struct dss_device *dss,
419 enum dss_clk_source clk_src)
429{ 420{
430 int b; 421 int b;
431 422
@@ -433,7 +424,7 @@ static void dss_select_dispc_clk_source(enum dss_clk_source clk_src)
433 * We always use PRCM clock as the DISPC func clock, except on DSS3, 424 * We always use PRCM clock as the DISPC func clock, except on DSS3,
434 * where we don't have separate DISPC and LCD clock sources. 425 * where we don't have separate DISPC and LCD clock sources.
435 */ 426 */
436 if (WARN_ON(dss.feat->has_lcd_clk_src && clk_src != DSS_CLK_SRC_FCK)) 427 if (WARN_ON(dss->feat->has_lcd_clk_src && clk_src != DSS_CLK_SRC_FCK))
437 return; 428 return;
438 429
439 switch (clk_src) { 430 switch (clk_src) {
@@ -451,15 +442,15 @@ static void dss_select_dispc_clk_source(enum dss_clk_source clk_src)
451 return; 442 return;
452 } 443 }
453 444
454 REG_FLD_MOD(DSS_CONTROL, b, /* DISPC_CLK_SWITCH */ 445 REG_FLD_MOD(dss, DSS_CONTROL, b, /* DISPC_CLK_SWITCH */
455 dss.feat->dispc_clk_switch.start, 446 dss->feat->dispc_clk_switch.start,
456 dss.feat->dispc_clk_switch.end); 447 dss->feat->dispc_clk_switch.end);
457 448
458 dss.dispc_clk_source = clk_src; 449 dss->dispc_clk_source = clk_src;
459} 450}
460 451
461void dss_select_dsi_clk_source(int dsi_module, 452void dss_select_dsi_clk_source(struct dss_device *dss, int dsi_module,
462 enum dss_clk_source clk_src) 453 enum dss_clk_source clk_src)
463{ 454{
464 int b, pos; 455 int b, pos;
465 456
@@ -481,13 +472,14 @@ void dss_select_dsi_clk_source(int dsi_module,
481 } 472 }
482 473
483 pos = dsi_module == 0 ? 1 : 10; 474 pos = dsi_module == 0 ? 1 : 10;
484 REG_FLD_MOD(DSS_CONTROL, b, pos, pos); /* DSIx_CLK_SWITCH */ 475 REG_FLD_MOD(dss, DSS_CONTROL, b, pos, pos); /* DSIx_CLK_SWITCH */
485 476
486 dss.dsi_clk_source[dsi_module] = clk_src; 477 dss->dsi_clk_source[dsi_module] = clk_src;
487} 478}
488 479
489static int dss_lcd_clk_mux_dra7(enum omap_channel channel, 480static int dss_lcd_clk_mux_dra7(struct dss_device *dss,
490 enum dss_clk_source clk_src) 481 enum omap_channel channel,
482 enum dss_clk_source clk_src)
491{ 483{
492 const u8 ctrl_bits[] = { 484 const u8 ctrl_bits[] = {
493 [OMAP_DSS_CHANNEL_LCD] = 0, 485 [OMAP_DSS_CHANNEL_LCD] = 0,
@@ -500,21 +492,22 @@ static int dss_lcd_clk_mux_dra7(enum omap_channel channel,
500 492
501 if (clk_src == DSS_CLK_SRC_FCK) { 493 if (clk_src == DSS_CLK_SRC_FCK) {
502 /* LCDx_CLK_SWITCH */ 494 /* LCDx_CLK_SWITCH */
503 REG_FLD_MOD(DSS_CONTROL, 0, ctrl_bit, ctrl_bit); 495 REG_FLD_MOD(dss, DSS_CONTROL, 0, ctrl_bit, ctrl_bit);
504 return -EINVAL; 496 return -EINVAL;
505 } 497 }
506 498
507 r = dss_ctrl_pll_set_control_mux(clk_src, channel); 499 r = dss_ctrl_pll_set_control_mux(dss, clk_src, channel);
508 if (r) 500 if (r)
509 return r; 501 return r;
510 502
511 REG_FLD_MOD(DSS_CONTROL, 1, ctrl_bit, ctrl_bit); 503 REG_FLD_MOD(dss, DSS_CONTROL, 1, ctrl_bit, ctrl_bit);
512 504
513 return 0; 505 return 0;
514} 506}
515 507
516static int dss_lcd_clk_mux_omap5(enum omap_channel channel, 508static int dss_lcd_clk_mux_omap5(struct dss_device *dss,
517 enum dss_clk_source clk_src) 509 enum omap_channel channel,
510 enum dss_clk_source clk_src)
518{ 511{
519 const u8 ctrl_bits[] = { 512 const u8 ctrl_bits[] = {
520 [OMAP_DSS_CHANNEL_LCD] = 0, 513 [OMAP_DSS_CHANNEL_LCD] = 0,
@@ -531,20 +524,21 @@ static int dss_lcd_clk_mux_omap5(enum omap_channel channel,
531 524
532 if (clk_src == DSS_CLK_SRC_FCK) { 525 if (clk_src == DSS_CLK_SRC_FCK) {
533 /* LCDx_CLK_SWITCH */ 526 /* LCDx_CLK_SWITCH */
534 REG_FLD_MOD(DSS_CONTROL, 0, ctrl_bit, ctrl_bit); 527 REG_FLD_MOD(dss, DSS_CONTROL, 0, ctrl_bit, ctrl_bit);
535 return -EINVAL; 528 return -EINVAL;
536 } 529 }
537 530
538 if (WARN_ON(allowed_plls[channel] != clk_src)) 531 if (WARN_ON(allowed_plls[channel] != clk_src))
539 return -EINVAL; 532 return -EINVAL;
540 533
541 REG_FLD_MOD(DSS_CONTROL, 1, ctrl_bit, ctrl_bit); 534 REG_FLD_MOD(dss, DSS_CONTROL, 1, ctrl_bit, ctrl_bit);
542 535
543 return 0; 536 return 0;
544} 537}
545 538
546static int dss_lcd_clk_mux_omap4(enum omap_channel channel, 539static int dss_lcd_clk_mux_omap4(struct dss_device *dss,
547 enum dss_clk_source clk_src) 540 enum omap_channel channel,
541 enum dss_clk_source clk_src)
548{ 542{
549 const u8 ctrl_bits[] = { 543 const u8 ctrl_bits[] = {
550 [OMAP_DSS_CHANNEL_LCD] = 0, 544 [OMAP_DSS_CHANNEL_LCD] = 0,
@@ -559,87 +553,90 @@ static int dss_lcd_clk_mux_omap4(enum omap_channel channel,
559 553
560 if (clk_src == DSS_CLK_SRC_FCK) { 554 if (clk_src == DSS_CLK_SRC_FCK) {
561 /* LCDx_CLK_SWITCH */ 555 /* LCDx_CLK_SWITCH */
562 REG_FLD_MOD(DSS_CONTROL, 0, ctrl_bit, ctrl_bit); 556 REG_FLD_MOD(dss, DSS_CONTROL, 0, ctrl_bit, ctrl_bit);
563 return 0; 557 return 0;
564 } 558 }
565 559
566 if (WARN_ON(allowed_plls[channel] != clk_src)) 560 if (WARN_ON(allowed_plls[channel] != clk_src))
567 return -EINVAL; 561 return -EINVAL;
568 562
569 REG_FLD_MOD(DSS_CONTROL, 1, ctrl_bit, ctrl_bit); 563 REG_FLD_MOD(dss, DSS_CONTROL, 1, ctrl_bit, ctrl_bit);
570 564
571 return 0; 565 return 0;
572} 566}
573 567
574void dss_select_lcd_clk_source(enum omap_channel channel, 568void dss_select_lcd_clk_source(struct dss_device *dss,
575 enum dss_clk_source clk_src) 569 enum omap_channel channel,
570 enum dss_clk_source clk_src)
576{ 571{
577 int idx = dss_get_channel_index(channel); 572 int idx = dss_get_channel_index(channel);
578 int r; 573 int r;
579 574
580 if (!dss.feat->has_lcd_clk_src) { 575 if (!dss->feat->has_lcd_clk_src) {
581 dss_select_dispc_clk_source(clk_src); 576 dss_select_dispc_clk_source(dss, clk_src);
582 dss.lcd_clk_source[idx] = clk_src; 577 dss->lcd_clk_source[idx] = clk_src;
583 return; 578 return;
584 } 579 }
585 580
586 r = dss.feat->ops->select_lcd_source(channel, clk_src); 581 r = dss->feat->ops->select_lcd_source(dss, channel, clk_src);
587 if (r) 582 if (r)
588 return; 583 return;
589 584
590 dss.lcd_clk_source[idx] = clk_src; 585 dss->lcd_clk_source[idx] = clk_src;
591} 586}
592 587
593enum dss_clk_source dss_get_dispc_clk_source(void) 588enum dss_clk_source dss_get_dispc_clk_source(struct dss_device *dss)
594{ 589{
595 return dss.dispc_clk_source; 590 return dss->dispc_clk_source;
596} 591}
597 592
598enum dss_clk_source dss_get_dsi_clk_source(int dsi_module) 593enum dss_clk_source dss_get_dsi_clk_source(struct dss_device *dss,
594 int dsi_module)
599{ 595{
600 return dss.dsi_clk_source[dsi_module]; 596 return dss->dsi_clk_source[dsi_module];
601} 597}
602 598
603enum dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel) 599enum dss_clk_source dss_get_lcd_clk_source(struct dss_device *dss,
600 enum omap_channel channel)
604{ 601{
605 if (dss.feat->has_lcd_clk_src) { 602 if (dss->feat->has_lcd_clk_src) {
606 int idx = dss_get_channel_index(channel); 603 int idx = dss_get_channel_index(channel);
607 return dss.lcd_clk_source[idx]; 604 return dss->lcd_clk_source[idx];
608 } else { 605 } else {
609 /* LCD_CLK source is the same as DISPC_FCLK source for 606 /* LCD_CLK source is the same as DISPC_FCLK source for
610 * OMAP2 and OMAP3 */ 607 * OMAP2 and OMAP3 */
611 return dss.dispc_clk_source; 608 return dss->dispc_clk_source;
612 } 609 }
613} 610}
614 611
615bool dss_div_calc(unsigned long pck, unsigned long fck_min, 612bool dss_div_calc(struct dss_device *dss, unsigned long pck,
616 dss_div_calc_func func, void *data) 613 unsigned long fck_min, dss_div_calc_func func, void *data)
617{ 614{
618 int fckd, fckd_start, fckd_stop; 615 int fckd, fckd_start, fckd_stop;
619 unsigned long fck; 616 unsigned long fck;
620 unsigned long fck_hw_max; 617 unsigned long fck_hw_max;
621 unsigned long fckd_hw_max; 618 unsigned long fckd_hw_max;
622 unsigned long prate; 619 unsigned long prate;
623 unsigned m; 620 unsigned int m;
624 621
625 fck_hw_max = dss.feat->fck_freq_max; 622 fck_hw_max = dss->feat->fck_freq_max;
626 623
627 if (dss.parent_clk == NULL) { 624 if (dss->parent_clk == NULL) {
628 unsigned pckd; 625 unsigned int pckd;
629 626
630 pckd = fck_hw_max / pck; 627 pckd = fck_hw_max / pck;
631 628
632 fck = pck * pckd; 629 fck = pck * pckd;
633 630
634 fck = clk_round_rate(dss.dss_clk, fck); 631 fck = clk_round_rate(dss->dss_clk, fck);
635 632
636 return func(fck, data); 633 return func(fck, data);
637 } 634 }
638 635
639 fckd_hw_max = dss.feat->fck_div_max; 636 fckd_hw_max = dss->feat->fck_div_max;
640 637
641 m = dss.feat->dss_fck_multiplier; 638 m = dss->feat->dss_fck_multiplier;
642 prate = clk_get_rate(dss.parent_clk); 639 prate = clk_get_rate(dss->parent_clk);
643 640
644 fck_min = fck_min ? fck_min : 1; 641 fck_min = fck_min ? fck_min : 1;
645 642
@@ -656,67 +653,68 @@ bool dss_div_calc(unsigned long pck, unsigned long fck_min,
656 return false; 653 return false;
657} 654}
658 655
659int dss_set_fck_rate(unsigned long rate) 656int dss_set_fck_rate(struct dss_device *dss, unsigned long rate)
660{ 657{
661 int r; 658 int r;
662 659
663 DSSDBG("set fck to %lu\n", rate); 660 DSSDBG("set fck to %lu\n", rate);
664 661
665 r = clk_set_rate(dss.dss_clk, rate); 662 r = clk_set_rate(dss->dss_clk, rate);
666 if (r) 663 if (r)
667 return r; 664 return r;
668 665
669 dss.dss_clk_rate = clk_get_rate(dss.dss_clk); 666 dss->dss_clk_rate = clk_get_rate(dss->dss_clk);
670 667
671 WARN_ONCE(dss.dss_clk_rate != rate, 668 WARN_ONCE(dss->dss_clk_rate != rate, "clk rate mismatch: %lu != %lu",
672 "clk rate mismatch: %lu != %lu", dss.dss_clk_rate, 669 dss->dss_clk_rate, rate);
673 rate);
674 670
675 return 0; 671 return 0;
676} 672}
677 673
678unsigned long dss_get_dispc_clk_rate(void) 674unsigned long dss_get_dispc_clk_rate(struct dss_device *dss)
679{ 675{
680 return dss.dss_clk_rate; 676 return dss->dss_clk_rate;
681} 677}
682 678
683unsigned long dss_get_max_fck_rate(void) 679unsigned long dss_get_max_fck_rate(struct dss_device *dss)
684{ 680{
685 return dss.feat->fck_freq_max; 681 return dss->feat->fck_freq_max;
686} 682}
687 683
688enum omap_dss_output_id dss_get_supported_outputs(enum omap_channel channel) 684enum omap_dss_output_id dss_get_supported_outputs(struct dss_device *dss,
685 enum omap_channel channel)
689{ 686{
690 return dss.feat->outputs[channel]; 687 return dss->feat->outputs[channel];
691} 688}
692 689
693static int dss_setup_default_clock(void) 690static int dss_setup_default_clock(struct dss_device *dss)
694{ 691{
695 unsigned long max_dss_fck, prate; 692 unsigned long max_dss_fck, prate;
696 unsigned long fck; 693 unsigned long fck;
697 unsigned fck_div; 694 unsigned int fck_div;
698 int r; 695 int r;
699 696
700 max_dss_fck = dss.feat->fck_freq_max; 697 max_dss_fck = dss->feat->fck_freq_max;
701 698
702 if (dss.parent_clk == NULL) { 699 if (dss->parent_clk == NULL) {
703 fck = clk_round_rate(dss.dss_clk, max_dss_fck); 700 fck = clk_round_rate(dss->dss_clk, max_dss_fck);
704 } else { 701 } else {
705 prate = clk_get_rate(dss.parent_clk); 702 prate = clk_get_rate(dss->parent_clk);
706 703
707 fck_div = DIV_ROUND_UP(prate * dss.feat->dss_fck_multiplier, 704 fck_div = DIV_ROUND_UP(prate * dss->feat->dss_fck_multiplier,
708 max_dss_fck); 705 max_dss_fck);
709 fck = DIV_ROUND_UP(prate, fck_div) * dss.feat->dss_fck_multiplier; 706 fck = DIV_ROUND_UP(prate, fck_div)
707 * dss->feat->dss_fck_multiplier;
710 } 708 }
711 709
712 r = dss_set_fck_rate(fck); 710 r = dss_set_fck_rate(dss, fck);
713 if (r) 711 if (r)
714 return r; 712 return r;
715 713
716 return 0; 714 return 0;
717} 715}
718 716
719void dss_set_venc_output(enum omap_dss_venc_type type) 717void dss_set_venc_output(struct dss_device *dss, enum omap_dss_venc_type type)
720{ 718{
721 int l = 0; 719 int l = 0;
722 720
@@ -728,19 +726,21 @@ void dss_set_venc_output(enum omap_dss_venc_type type)
728 BUG(); 726 BUG();
729 727
730 /* venc out selection. 0 = comp, 1 = svideo */ 728 /* venc out selection. 0 = comp, 1 = svideo */
731 REG_FLD_MOD(DSS_CONTROL, l, 6, 6); 729 REG_FLD_MOD(dss, DSS_CONTROL, l, 6, 6);
732} 730}
733 731
734void dss_set_dac_pwrdn_bgz(bool enable) 732void dss_set_dac_pwrdn_bgz(struct dss_device *dss, bool enable)
735{ 733{
736 REG_FLD_MOD(DSS_CONTROL, enable, 5, 5); /* DAC Power-Down Control */ 734 /* DAC Power-Down Control */
735 REG_FLD_MOD(dss, DSS_CONTROL, enable, 5, 5);
737} 736}
738 737
739void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select src) 738void dss_select_hdmi_venc_clk_source(struct dss_device *dss,
739 enum dss_hdmi_venc_clk_source_select src)
740{ 740{
741 enum omap_dss_output_id outputs; 741 enum omap_dss_output_id outputs;
742 742
743 outputs = dss.feat->outputs[OMAP_DSS_CHANNEL_DIGIT]; 743 outputs = dss->feat->outputs[OMAP_DSS_CHANNEL_DIGIT];
744 744
745 /* Complain about invalid selections */ 745 /* Complain about invalid selections */
746 WARN_ON((src == DSS_VENC_TV_CLK) && !(outputs & OMAP_DSS_OUTPUT_VENC)); 746 WARN_ON((src == DSS_VENC_TV_CLK) && !(outputs & OMAP_DSS_OUTPUT_VENC));
@@ -749,24 +749,12 @@ void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select src)
749 /* Select only if we have options */ 749 /* Select only if we have options */
750 if ((outputs & OMAP_DSS_OUTPUT_VENC) && 750 if ((outputs & OMAP_DSS_OUTPUT_VENC) &&
751 (outputs & OMAP_DSS_OUTPUT_HDMI)) 751 (outputs & OMAP_DSS_OUTPUT_HDMI))
752 REG_FLD_MOD(DSS_CONTROL, src, 15, 15); /* VENC_HDMI_SWITCH */ 752 /* VENC_HDMI_SWITCH */
753} 753 REG_FLD_MOD(dss, DSS_CONTROL, src, 15, 15);
754
755enum dss_hdmi_venc_clk_source_select dss_get_hdmi_venc_clk_source(void)
756{
757 enum omap_dss_output_id outputs;
758
759 outputs = dss.feat->outputs[OMAP_DSS_CHANNEL_DIGIT];
760 if ((outputs & OMAP_DSS_OUTPUT_HDMI) == 0)
761 return DSS_VENC_TV_CLK;
762
763 if ((outputs & OMAP_DSS_OUTPUT_VENC) == 0)
764 return DSS_HDMI_M_PCLK;
765
766 return REG_GET(DSS_CONTROL, 15, 15);
767} 754}
768 755
769static int dss_dpi_select_source_omap2_omap3(int port, enum omap_channel channel) 756static int dss_dpi_select_source_omap2_omap3(struct dss_device *dss, int port,
757 enum omap_channel channel)
770{ 758{
771 if (channel != OMAP_DSS_CHANNEL_LCD) 759 if (channel != OMAP_DSS_CHANNEL_LCD)
772 return -EINVAL; 760 return -EINVAL;
@@ -774,7 +762,8 @@ static int dss_dpi_select_source_omap2_omap3(int port, enum omap_channel channel
774 return 0; 762 return 0;
775} 763}
776 764
777static int dss_dpi_select_source_omap4(int port, enum omap_channel channel) 765static int dss_dpi_select_source_omap4(struct dss_device *dss, int port,
766 enum omap_channel channel)
778{ 767{
779 int val; 768 int val;
780 769
@@ -789,12 +778,13 @@ static int dss_dpi_select_source_omap4(int port, enum omap_channel channel)
789 return -EINVAL; 778 return -EINVAL;
790 } 779 }
791 780
792 REG_FLD_MOD(DSS_CONTROL, val, 17, 17); 781 REG_FLD_MOD(dss, DSS_CONTROL, val, 17, 17);
793 782
794 return 0; 783 return 0;
795} 784}
796 785
797static int dss_dpi_select_source_omap5(int port, enum omap_channel channel) 786static int dss_dpi_select_source_omap5(struct dss_device *dss, int port,
787 enum omap_channel channel)
798{ 788{
799 int val; 789 int val;
800 790
@@ -815,16 +805,17 @@ static int dss_dpi_select_source_omap5(int port, enum omap_channel channel)
815 return -EINVAL; 805 return -EINVAL;
816 } 806 }
817 807
818 REG_FLD_MOD(DSS_CONTROL, val, 17, 16); 808 REG_FLD_MOD(dss, DSS_CONTROL, val, 17, 16);
819 809
820 return 0; 810 return 0;
821} 811}
822 812
823static int dss_dpi_select_source_dra7xx(int port, enum omap_channel channel) 813static int dss_dpi_select_source_dra7xx(struct dss_device *dss, int port,
814 enum omap_channel channel)
824{ 815{
825 switch (port) { 816 switch (port) {
826 case 0: 817 case 0:
827 return dss_dpi_select_source_omap5(port, channel); 818 return dss_dpi_select_source_omap5(dss, port, channel);
828 case 1: 819 case 1:
829 if (channel != OMAP_DSS_CHANNEL_LCD2) 820 if (channel != OMAP_DSS_CHANNEL_LCD2)
830 return -EINVAL; 821 return -EINVAL;
@@ -840,135 +831,153 @@ static int dss_dpi_select_source_dra7xx(int port, enum omap_channel channel)
840 return 0; 831 return 0;
841} 832}
842 833
843int dss_dpi_select_source(int port, enum omap_channel channel) 834int dss_dpi_select_source(struct dss_device *dss, int port,
835 enum omap_channel channel)
844{ 836{
845 return dss.feat->ops->dpi_select_source(port, channel); 837 return dss->feat->ops->dpi_select_source(dss, port, channel);
846} 838}
847 839
848static int dss_get_clocks(void) 840static int dss_get_clocks(struct dss_device *dss)
849{ 841{
850 struct clk *clk; 842 struct clk *clk;
851 843
852 clk = devm_clk_get(&dss.pdev->dev, "fck"); 844 clk = devm_clk_get(&dss->pdev->dev, "fck");
853 if (IS_ERR(clk)) { 845 if (IS_ERR(clk)) {
854 DSSERR("can't get clock fck\n"); 846 DSSERR("can't get clock fck\n");
855 return PTR_ERR(clk); 847 return PTR_ERR(clk);
856 } 848 }
857 849
858 dss.dss_clk = clk; 850 dss->dss_clk = clk;
859 851
860 if (dss.feat->parent_clk_name) { 852 if (dss->feat->parent_clk_name) {
861 clk = clk_get(NULL, dss.feat->parent_clk_name); 853 clk = clk_get(NULL, dss->feat->parent_clk_name);
862 if (IS_ERR(clk)) { 854 if (IS_ERR(clk)) {
863 DSSERR("Failed to get %s\n", dss.feat->parent_clk_name); 855 DSSERR("Failed to get %s\n",
856 dss->feat->parent_clk_name);
864 return PTR_ERR(clk); 857 return PTR_ERR(clk);
865 } 858 }
866 } else { 859 } else {
867 clk = NULL; 860 clk = NULL;
868 } 861 }
869 862
870 dss.parent_clk = clk; 863 dss->parent_clk = clk;
871 864
872 return 0; 865 return 0;
873} 866}
874 867
875static void dss_put_clocks(void) 868static void dss_put_clocks(struct dss_device *dss)
876{ 869{
877 if (dss.parent_clk) 870 if (dss->parent_clk)
878 clk_put(dss.parent_clk); 871 clk_put(dss->parent_clk);
879} 872}
880 873
881int dss_runtime_get(void) 874int dss_runtime_get(struct dss_device *dss)
882{ 875{
883 int r; 876 int r;
884 877
885 DSSDBG("dss_runtime_get\n"); 878 DSSDBG("dss_runtime_get\n");
886 879
887 r = pm_runtime_get_sync(&dss.pdev->dev); 880 r = pm_runtime_get_sync(&dss->pdev->dev);
888 WARN_ON(r < 0); 881 WARN_ON(r < 0);
889 return r < 0 ? r : 0; 882 return r < 0 ? r : 0;
890} 883}
891 884
892void dss_runtime_put(void) 885void dss_runtime_put(struct dss_device *dss)
893{ 886{
894 int r; 887 int r;
895 888
896 DSSDBG("dss_runtime_put\n"); 889 DSSDBG("dss_runtime_put\n");
897 890
898 r = pm_runtime_put_sync(&dss.pdev->dev); 891 r = pm_runtime_put_sync(&dss->pdev->dev);
899 WARN_ON(r < 0 && r != -ENOSYS && r != -EBUSY); 892 WARN_ON(r < 0 && r != -ENOSYS && r != -EBUSY);
900} 893}
901 894
902/* DEBUGFS */ 895struct dss_device *dss_get_device(struct device *dev)
903#if defined(CONFIG_OMAP2_DSS_DEBUGFS)
904static void dss_debug_dump_clocks(struct seq_file *s)
905{ 896{
906 dss_dump_clocks(s); 897 return dev_get_drvdata(dev);
907 dispc_dump_clocks(s);
908#ifdef CONFIG_OMAP2_DSS_DSI
909 dsi_dump_clocks(s);
910#endif
911} 898}
912 899
913static int dss_debug_show(struct seq_file *s, void *unused) 900/* DEBUGFS */
901#if defined(CONFIG_OMAP2_DSS_DEBUGFS)
902static int dss_initialize_debugfs(struct dss_device *dss)
914{ 903{
915 void (*func)(struct seq_file *) = s->private; 904 struct dentry *dir;
905
906 dir = debugfs_create_dir("omapdss", NULL);
907 if (IS_ERR(dir))
908 return PTR_ERR(dir);
909
910 dss->debugfs.root = dir;
916 911
917 func(s);
918 return 0; 912 return 0;
919} 913}
920 914
915static void dss_uninitialize_debugfs(struct dss_device *dss)
916{
917 debugfs_remove_recursive(dss->debugfs.root);
918}
919
920struct dss_debugfs_entry {
921 struct dentry *dentry;
922 int (*show_fn)(struct seq_file *s, void *data);
923 void *data;
924};
925
921static int dss_debug_open(struct inode *inode, struct file *file) 926static int dss_debug_open(struct inode *inode, struct file *file)
922{ 927{
923 return single_open(file, dss_debug_show, inode->i_private); 928 struct dss_debugfs_entry *entry = inode->i_private;
929
930 return single_open(file, entry->show_fn, entry->data);
924} 931}
925 932
926static const struct file_operations dss_debug_fops = { 933static const struct file_operations dss_debug_fops = {
927 .open = dss_debug_open, 934 .open = dss_debug_open,
928 .read = seq_read, 935 .read = seq_read,
929 .llseek = seq_lseek, 936 .llseek = seq_lseek,
930 .release = single_release, 937 .release = single_release,
931}; 938};
932 939
933static struct dentry *dss_debugfs_dir; 940struct dss_debugfs_entry *
934 941dss_debugfs_create_file(struct dss_device *dss, const char *name,
935static int dss_initialize_debugfs(void) 942 int (*show_fn)(struct seq_file *s, void *data),
943 void *data)
936{ 944{
937 dss_debugfs_dir = debugfs_create_dir("omapdss", NULL); 945 struct dss_debugfs_entry *entry;
938 if (IS_ERR(dss_debugfs_dir)) { 946 struct dentry *d;
939 int err = PTR_ERR(dss_debugfs_dir);
940 947
941 dss_debugfs_dir = NULL; 948 entry = kzalloc(sizeof(*entry), GFP_KERNEL);
942 return err; 949 if (!entry)
943 } 950 return ERR_PTR(-ENOMEM);
944 951
945 debugfs_create_file("clk", S_IRUGO, dss_debugfs_dir, 952 entry->show_fn = show_fn;
946 &dss_debug_dump_clocks, &dss_debug_fops); 953 entry->data = data;
947 954
948 return 0; 955 d = debugfs_create_file(name, 0444, dss->debugfs.root, entry,
949} 956 &dss_debug_fops);
957 if (IS_ERR(d)) {
958 kfree(entry);
959 return ERR_PTR(PTR_ERR(d));
960 }
950 961
951static void dss_uninitialize_debugfs(void) 962 entry->dentry = d;
952{ 963 return entry;
953 if (dss_debugfs_dir)
954 debugfs_remove_recursive(dss_debugfs_dir);
955} 964}
956 965
957int dss_debugfs_create_file(const char *name, void (*write)(struct seq_file *)) 966void dss_debugfs_remove_file(struct dss_debugfs_entry *entry)
958{ 967{
959 struct dentry *d; 968 if (IS_ERR_OR_NULL(entry))
960 969 return;
961 d = debugfs_create_file(name, S_IRUGO, dss_debugfs_dir,
962 write, &dss_debug_fops);
963 970
964 return PTR_ERR_OR_ZERO(d); 971 debugfs_remove(entry->dentry);
972 kfree(entry);
965} 973}
974
966#else /* CONFIG_OMAP2_DSS_DEBUGFS */ 975#else /* CONFIG_OMAP2_DSS_DEBUGFS */
967static inline int dss_initialize_debugfs(void) 976static inline int dss_initialize_debugfs(struct dss_device *dss)
968{ 977{
969 return 0; 978 return 0;
970} 979}
971static inline void dss_uninitialize_debugfs(void) 980static inline void dss_uninitialize_debugfs(struct dss_device *dss)
972{ 981{
973} 982}
974#endif /* CONFIG_OMAP2_DSS_DEBUGFS */ 983#endif /* CONFIG_OMAP2_DSS_DEBUGFS */
@@ -1169,23 +1178,24 @@ static const struct dss_features dra7xx_dss_feats = {
1169 .has_lcd_clk_src = true, 1178 .has_lcd_clk_src = true,
1170}; 1179};
1171 1180
1172static int dss_init_ports(struct platform_device *pdev) 1181static int dss_init_ports(struct dss_device *dss)
1173{ 1182{
1183 struct platform_device *pdev = dss->pdev;
1174 struct device_node *parent = pdev->dev.of_node; 1184 struct device_node *parent = pdev->dev.of_node;
1175 struct device_node *port; 1185 struct device_node *port;
1176 int i; 1186 int i;
1177 1187
1178 for (i = 0; i < dss.feat->num_ports; i++) { 1188 for (i = 0; i < dss->feat->num_ports; i++) {
1179 port = of_graph_get_port_by_id(parent, i); 1189 port = of_graph_get_port_by_id(parent, i);
1180 if (!port) 1190 if (!port)
1181 continue; 1191 continue;
1182 1192
1183 switch (dss.feat->ports[i]) { 1193 switch (dss->feat->ports[i]) {
1184 case OMAP_DISPLAY_TYPE_DPI: 1194 case OMAP_DISPLAY_TYPE_DPI:
1185 dpi_init_port(pdev, port, dss.feat->model); 1195 dpi_init_port(dss, pdev, port, dss->feat->model);
1186 break; 1196 break;
1187 case OMAP_DISPLAY_TYPE_SDI: 1197 case OMAP_DISPLAY_TYPE_SDI:
1188 sdi_init_port(pdev, port); 1198 sdi_init_port(dss, pdev, port);
1189 break; 1199 break;
1190 default: 1200 default:
1191 break; 1201 break;
@@ -1195,18 +1205,19 @@ static int dss_init_ports(struct platform_device *pdev)
1195 return 0; 1205 return 0;
1196} 1206}
1197 1207
1198static void dss_uninit_ports(struct platform_device *pdev) 1208static void dss_uninit_ports(struct dss_device *dss)
1199{ 1209{
1210 struct platform_device *pdev = dss->pdev;
1200 struct device_node *parent = pdev->dev.of_node; 1211 struct device_node *parent = pdev->dev.of_node;
1201 struct device_node *port; 1212 struct device_node *port;
1202 int i; 1213 int i;
1203 1214
1204 for (i = 0; i < dss.feat->num_ports; i++) { 1215 for (i = 0; i < dss->feat->num_ports; i++) {
1205 port = of_graph_get_port_by_id(parent, i); 1216 port = of_graph_get_port_by_id(parent, i);
1206 if (!port) 1217 if (!port)
1207 continue; 1218 continue;
1208 1219
1209 switch (dss.feat->ports[i]) { 1220 switch (dss->feat->ports[i]) {
1210 case OMAP_DISPLAY_TYPE_DPI: 1221 case OMAP_DISPLAY_TYPE_DPI:
1211 dpi_uninit_port(port); 1222 dpi_uninit_port(port);
1212 break; 1223 break;
@@ -1219,8 +1230,9 @@ static void dss_uninit_ports(struct platform_device *pdev)
1219 } 1230 }
1220} 1231}
1221 1232
1222static int dss_video_pll_probe(struct platform_device *pdev) 1233static int dss_video_pll_probe(struct dss_device *dss)
1223{ 1234{
1235 struct platform_device *pdev = dss->pdev;
1224 struct device_node *np = pdev->dev.of_node; 1236 struct device_node *np = pdev->dev.of_node;
1225 struct regulator *pll_regulator; 1237 struct regulator *pll_regulator;
1226 int r; 1238 int r;
@@ -1229,16 +1241,16 @@ static int dss_video_pll_probe(struct platform_device *pdev)
1229 return 0; 1241 return 0;
1230 1242
1231 if (of_property_read_bool(np, "syscon-pll-ctrl")) { 1243 if (of_property_read_bool(np, "syscon-pll-ctrl")) {
1232 dss.syscon_pll_ctrl = syscon_regmap_lookup_by_phandle(np, 1244 dss->syscon_pll_ctrl = syscon_regmap_lookup_by_phandle(np,
1233 "syscon-pll-ctrl"); 1245 "syscon-pll-ctrl");
1234 if (IS_ERR(dss.syscon_pll_ctrl)) { 1246 if (IS_ERR(dss->syscon_pll_ctrl)) {
1235 dev_err(&pdev->dev, 1247 dev_err(&pdev->dev,
1236 "failed to get syscon-pll-ctrl regmap\n"); 1248 "failed to get syscon-pll-ctrl regmap\n");
1237 return PTR_ERR(dss.syscon_pll_ctrl); 1249 return PTR_ERR(dss->syscon_pll_ctrl);
1238 } 1250 }
1239 1251
1240 if (of_property_read_u32_index(np, "syscon-pll-ctrl", 1, 1252 if (of_property_read_u32_index(np, "syscon-pll-ctrl", 1,
1241 &dss.syscon_pll_ctrl_offset)) { 1253 &dss->syscon_pll_ctrl_offset)) {
1242 dev_err(&pdev->dev, 1254 dev_err(&pdev->dev,
1243 "failed to get syscon-pll-ctrl offset\n"); 1255 "failed to get syscon-pll-ctrl offset\n");
1244 return -EINVAL; 1256 return -EINVAL;
@@ -1264,16 +1276,18 @@ static int dss_video_pll_probe(struct platform_device *pdev)
1264 } 1276 }
1265 1277
1266 if (of_property_match_string(np, "reg-names", "pll1") >= 0) { 1278 if (of_property_match_string(np, "reg-names", "pll1") >= 0) {
1267 dss.video1_pll = dss_video_pll_init(pdev, 0, pll_regulator); 1279 dss->video1_pll = dss_video_pll_init(dss, pdev, 0,
1268 if (IS_ERR(dss.video1_pll)) 1280 pll_regulator);
1269 return PTR_ERR(dss.video1_pll); 1281 if (IS_ERR(dss->video1_pll))
1282 return PTR_ERR(dss->video1_pll);
1270 } 1283 }
1271 1284
1272 if (of_property_match_string(np, "reg-names", "pll2") >= 0) { 1285 if (of_property_match_string(np, "reg-names", "pll2") >= 0) {
1273 dss.video2_pll = dss_video_pll_init(pdev, 1, pll_regulator); 1286 dss->video2_pll = dss_video_pll_init(dss, pdev, 1,
1274 if (IS_ERR(dss.video2_pll)) { 1287 pll_regulator);
1275 dss_video_pll_uninit(dss.video1_pll); 1288 if (IS_ERR(dss->video2_pll)) {
1276 return PTR_ERR(dss.video2_pll); 1289 dss_video_pll_uninit(dss->video1_pll);
1290 return PTR_ERR(dss->video2_pll);
1277 } 1291 }
1278 } 1292 }
1279 1293
@@ -1300,109 +1314,26 @@ static const struct soc_device_attribute dss_soc_devices[] = {
1300 1314
1301static int dss_bind(struct device *dev) 1315static int dss_bind(struct device *dev)
1302{ 1316{
1303 struct platform_device *pdev = to_platform_device(dev); 1317 struct dss_device *dss = dev_get_drvdata(dev);
1304 struct resource *dss_mem;
1305 u32 rev;
1306 int r; 1318 int r;
1307 1319
1308 dss_mem = platform_get_resource(dss.pdev, IORESOURCE_MEM, 0); 1320 r = component_bind_all(dev, NULL);
1309 dss.base = devm_ioremap_resource(&pdev->dev, dss_mem);
1310 if (IS_ERR(dss.base))
1311 return PTR_ERR(dss.base);
1312
1313 r = dss_get_clocks();
1314 if (r) 1321 if (r)
1315 return r; 1322 return r;
1316 1323
1317 r = dss_setup_default_clock();
1318 if (r)
1319 goto err_setup_clocks;
1320
1321 r = dss_video_pll_probe(pdev);
1322 if (r)
1323 goto err_pll_init;
1324
1325 r = dss_init_ports(pdev);
1326 if (r)
1327 goto err_init_ports;
1328
1329 pm_runtime_enable(&pdev->dev);
1330
1331 r = dss_runtime_get();
1332 if (r)
1333 goto err_runtime_get;
1334
1335 dss.dss_clk_rate = clk_get_rate(dss.dss_clk);
1336
1337 /* Select DPLL */
1338 REG_FLD_MOD(DSS_CONTROL, 0, 0, 0);
1339
1340 dss_select_dispc_clk_source(DSS_CLK_SRC_FCK);
1341
1342#ifdef CONFIG_OMAP2_DSS_VENC
1343 REG_FLD_MOD(DSS_CONTROL, 1, 4, 4); /* venc dac demen */
1344 REG_FLD_MOD(DSS_CONTROL, 1, 3, 3); /* venc clock 4x enable */
1345 REG_FLD_MOD(DSS_CONTROL, 0, 2, 2); /* venc clock mode = normal */
1346#endif
1347 dss.dsi_clk_source[0] = DSS_CLK_SRC_FCK;
1348 dss.dsi_clk_source[1] = DSS_CLK_SRC_FCK;
1349 dss.dispc_clk_source = DSS_CLK_SRC_FCK;
1350 dss.lcd_clk_source[0] = DSS_CLK_SRC_FCK;
1351 dss.lcd_clk_source[1] = DSS_CLK_SRC_FCK;
1352
1353 rev = dss_read_reg(DSS_REVISION);
1354 pr_info("OMAP DSS rev %d.%d\n", FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
1355
1356 dss_runtime_put();
1357
1358 r = component_bind_all(&pdev->dev, NULL);
1359 if (r)
1360 goto err_component;
1361
1362 dss_debugfs_create_file("dss", dss_dump_regs);
1363
1364 pm_set_vt_switch(0); 1324 pm_set_vt_switch(0);
1365 1325
1366 omapdss_gather_components(dev); 1326 omapdss_gather_components(dev);
1367 omapdss_set_is_initialized(true); 1327 omapdss_set_dss(dss);
1368 1328
1369 return 0; 1329 return 0;
1370
1371err_component:
1372err_runtime_get:
1373 pm_runtime_disable(&pdev->dev);
1374 dss_uninit_ports(pdev);
1375err_init_ports:
1376 if (dss.video1_pll)
1377 dss_video_pll_uninit(dss.video1_pll);
1378
1379 if (dss.video2_pll)
1380 dss_video_pll_uninit(dss.video2_pll);
1381err_pll_init:
1382err_setup_clocks:
1383 dss_put_clocks();
1384 return r;
1385} 1330}
1386 1331
1387static void dss_unbind(struct device *dev) 1332static void dss_unbind(struct device *dev)
1388{ 1333{
1389 struct platform_device *pdev = to_platform_device(dev); 1334 omapdss_set_dss(NULL);
1390
1391 omapdss_set_is_initialized(false);
1392 1335
1393 component_unbind_all(&pdev->dev, NULL); 1336 component_unbind_all(dev, NULL);
1394
1395 if (dss.video1_pll)
1396 dss_video_pll_uninit(dss.video1_pll);
1397
1398 if (dss.video2_pll)
1399 dss_video_pll_uninit(dss.video2_pll);
1400
1401 dss_uninit_ports(pdev);
1402
1403 pm_runtime_disable(&pdev->dev);
1404
1405 dss_put_clocks();
1406} 1337}
1407 1338
1408static const struct component_master_ops dss_component_ops = { 1339static const struct component_master_ops dss_component_ops = {
@@ -1434,18 +1365,60 @@ static int dss_add_child_component(struct device *dev, void *data)
1434 return 0; 1365 return 0;
1435} 1366}
1436 1367
1368static int dss_probe_hardware(struct dss_device *dss)
1369{
1370 u32 rev;
1371 int r;
1372
1373 r = dss_runtime_get(dss);
1374 if (r)
1375 return r;
1376
1377 dss->dss_clk_rate = clk_get_rate(dss->dss_clk);
1378
1379 /* Select DPLL */
1380 REG_FLD_MOD(dss, DSS_CONTROL, 0, 0, 0);
1381
1382 dss_select_dispc_clk_source(dss, DSS_CLK_SRC_FCK);
1383
1384#ifdef CONFIG_OMAP2_DSS_VENC
1385 REG_FLD_MOD(dss, DSS_CONTROL, 1, 4, 4); /* venc dac demen */
1386 REG_FLD_MOD(dss, DSS_CONTROL, 1, 3, 3); /* venc clock 4x enable */
1387 REG_FLD_MOD(dss, DSS_CONTROL, 0, 2, 2); /* venc clock mode = normal */
1388#endif
1389 dss->dsi_clk_source[0] = DSS_CLK_SRC_FCK;
1390 dss->dsi_clk_source[1] = DSS_CLK_SRC_FCK;
1391 dss->dispc_clk_source = DSS_CLK_SRC_FCK;
1392 dss->lcd_clk_source[0] = DSS_CLK_SRC_FCK;
1393 dss->lcd_clk_source[1] = DSS_CLK_SRC_FCK;
1394
1395 rev = dss_read_reg(dss, DSS_REVISION);
1396 pr_info("OMAP DSS rev %d.%d\n", FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
1397
1398 dss_runtime_put(dss);
1399
1400 return 0;
1401}
1402
1437static int dss_probe(struct platform_device *pdev) 1403static int dss_probe(struct platform_device *pdev)
1438{ 1404{
1439 const struct soc_device_attribute *soc; 1405 const struct soc_device_attribute *soc;
1440 struct component_match *match = NULL; 1406 struct component_match *match = NULL;
1407 struct resource *dss_mem;
1408 struct dss_device *dss;
1441 int r; 1409 int r;
1442 1410
1443 dss.pdev = pdev; 1411 dss = kzalloc(sizeof(*dss), GFP_KERNEL);
1412 if (!dss)
1413 return -ENOMEM;
1414
1415 dss->pdev = pdev;
1416 platform_set_drvdata(pdev, dss);
1444 1417
1445 r = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); 1418 r = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1446 if (r) { 1419 if (r) {
1447 dev_err(&pdev->dev, "Failed to set the DMA mask\n"); 1420 dev_err(&pdev->dev, "Failed to set the DMA mask\n");
1448 return r; 1421 goto err_free_dss;
1449 } 1422 }
1450 1423
1451 /* 1424 /*
@@ -1454,31 +1427,108 @@ static int dss_probe(struct platform_device *pdev)
1454 */ 1427 */
1455 soc = soc_device_match(dss_soc_devices); 1428 soc = soc_device_match(dss_soc_devices);
1456 if (soc) 1429 if (soc)
1457 dss.feat = soc->data; 1430 dss->feat = soc->data;
1458 else 1431 else
1459 dss.feat = of_match_device(dss_of_match, &pdev->dev)->data; 1432 dss->feat = of_match_device(dss_of_match, &pdev->dev)->data;
1433
1434 /* Map I/O registers, get and setup clocks. */
1435 dss_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1436 dss->base = devm_ioremap_resource(&pdev->dev, dss_mem);
1437 if (IS_ERR(dss->base)) {
1438 r = PTR_ERR(dss->base);
1439 goto err_free_dss;
1440 }
1460 1441
1461 r = dss_initialize_debugfs(); 1442 r = dss_get_clocks(dss);
1462 if (r) 1443 if (r)
1463 return r; 1444 goto err_free_dss;
1445
1446 r = dss_setup_default_clock(dss);
1447 if (r)
1448 goto err_put_clocks;
1464 1449
1465 /* add all the child devices as components */ 1450 /* Setup the video PLLs and the DPI and SDI ports. */
1451 r = dss_video_pll_probe(dss);
1452 if (r)
1453 goto err_put_clocks;
1454
1455 r = dss_init_ports(dss);
1456 if (r)
1457 goto err_uninit_plls;
1458
1459 /* Enable runtime PM and probe the hardware. */
1460 pm_runtime_enable(&pdev->dev);
1461
1462 r = dss_probe_hardware(dss);
1463 if (r)
1464 goto err_pm_runtime_disable;
1465
1466 /* Initialize debugfs. */
1467 r = dss_initialize_debugfs(dss);
1468 if (r)
1469 goto err_pm_runtime_disable;
1470
1471 dss->debugfs.clk = dss_debugfs_create_file(dss, "clk",
1472 dss_debug_dump_clocks, dss);
1473 dss->debugfs.dss = dss_debugfs_create_file(dss, "dss", dss_dump_regs,
1474 dss);
1475
1476 /* Add all the child devices as components. */
1466 device_for_each_child(&pdev->dev, &match, dss_add_child_component); 1477 device_for_each_child(&pdev->dev, &match, dss_add_child_component);
1467 1478
1468 r = component_master_add_with_match(&pdev->dev, &dss_component_ops, match); 1479 r = component_master_add_with_match(&pdev->dev, &dss_component_ops, match);
1469 if (r) { 1480 if (r)
1470 dss_uninitialize_debugfs(); 1481 goto err_uninit_debugfs;
1471 return r;
1472 }
1473 1482
1474 return 0; 1483 return 0;
1484
1485err_uninit_debugfs:
1486 dss_debugfs_remove_file(dss->debugfs.clk);
1487 dss_debugfs_remove_file(dss->debugfs.dss);
1488 dss_uninitialize_debugfs(dss);
1489
1490err_pm_runtime_disable:
1491 pm_runtime_disable(&pdev->dev);
1492 dss_uninit_ports(dss);
1493
1494err_uninit_plls:
1495 if (dss->video1_pll)
1496 dss_video_pll_uninit(dss->video1_pll);
1497 if (dss->video2_pll)
1498 dss_video_pll_uninit(dss->video2_pll);
1499
1500err_put_clocks:
1501 dss_put_clocks(dss);
1502
1503err_free_dss:
1504 kfree(dss);
1505
1506 return r;
1475} 1507}
1476 1508
1477static int dss_remove(struct platform_device *pdev) 1509static int dss_remove(struct platform_device *pdev)
1478{ 1510{
1511 struct dss_device *dss = platform_get_drvdata(pdev);
1512
1479 component_master_del(&pdev->dev, &dss_component_ops); 1513 component_master_del(&pdev->dev, &dss_component_ops);
1480 1514
1481 dss_uninitialize_debugfs(); 1515 dss_debugfs_remove_file(dss->debugfs.clk);
1516 dss_debugfs_remove_file(dss->debugfs.dss);
1517 dss_uninitialize_debugfs(dss);
1518
1519 pm_runtime_disable(&pdev->dev);
1520
1521 dss_uninit_ports(dss);
1522
1523 if (dss->video1_pll)
1524 dss_video_pll_uninit(dss->video1_pll);
1525
1526 if (dss->video2_pll)
1527 dss_video_pll_uninit(dss->video2_pll);
1528
1529 dss_put_clocks(dss);
1530
1531 kfree(dss);
1482 1532
1483 return 0; 1533 return 0;
1484} 1534}
@@ -1500,7 +1550,9 @@ static void dss_shutdown(struct platform_device *pdev)
1500 1550
1501static int dss_runtime_suspend(struct device *dev) 1551static int dss_runtime_suspend(struct device *dev)
1502{ 1552{
1503 dss_save_context(); 1553 struct dss_device *dss = dev_get_drvdata(dev);
1554
1555 dss_save_context(dss);
1504 dss_set_min_bus_tput(dev, 0); 1556 dss_set_min_bus_tput(dev, 0);
1505 1557
1506 pinctrl_pm_select_sleep_state(dev); 1558 pinctrl_pm_select_sleep_state(dev);
@@ -1510,6 +1562,7 @@ static int dss_runtime_suspend(struct device *dev)
1510 1562
1511static int dss_runtime_resume(struct device *dev) 1563static int dss_runtime_resume(struct device *dev)
1512{ 1564{
1565 struct dss_device *dss = dev_get_drvdata(dev);
1513 int r; 1566 int r;
1514 1567
1515 pinctrl_pm_select_default_state(dev); 1568 pinctrl_pm_select_default_state(dev);
@@ -1525,7 +1578,7 @@ static int dss_runtime_resume(struct device *dev)
1525 if (r) 1578 if (r)
1526 return r; 1579 return r;
1527 1580
1528 dss_restore_context(); 1581 dss_restore_context(dss);
1529 return 0; 1582 return 0;
1530} 1583}
1531 1584
diff --git a/drivers/gpu/drm/omapdrm/dss/dss.h b/drivers/gpu/drm/omapdrm/dss/dss.h
index 6374e57ed9da..847c78ade024 100644
--- a/drivers/gpu/drm/omapdrm/dss/dss.h
+++ b/drivers/gpu/drm/omapdrm/dss/dss.h
@@ -25,6 +25,11 @@
25 25
26#include "omapdss.h" 26#include "omapdss.h"
27 27
28struct dispc_device;
29struct dss_debugfs_entry;
30struct platform_device;
31struct seq_file;
32
28#define MAX_DSS_LCD_MANAGERS 3 33#define MAX_DSS_LCD_MANAGERS 3
29#define MAX_NUM_DSI 2 34#define MAX_NUM_DSI 2
30 35
@@ -97,17 +102,6 @@ enum dss_dsi_content_type {
97 DSS_DSI_CONTENT_GENERIC, 102 DSS_DSI_CONTENT_GENERIC,
98}; 103};
99 104
100enum dss_writeback_channel {
101 DSS_WB_LCD1_MGR = 0,
102 DSS_WB_LCD2_MGR = 1,
103 DSS_WB_TV_MGR = 2,
104 DSS_WB_OVL0 = 3,
105 DSS_WB_OVL1 = 4,
106 DSS_WB_OVL2 = 5,
107 DSS_WB_OVL3 = 6,
108 DSS_WB_LCD3_MGR = 7,
109};
110
111enum dss_clk_source { 105enum dss_clk_source {
112 DSS_CLK_SRC_FCK = 0, 106 DSS_CLK_SRC_FCK = 0,
113 107
@@ -167,10 +161,10 @@ struct dss_pll_ops {
167struct dss_pll_hw { 161struct dss_pll_hw {
168 enum dss_pll_type type; 162 enum dss_pll_type type;
169 163
170 unsigned n_max; 164 unsigned int n_max;
171 unsigned m_min; 165 unsigned int m_min;
172 unsigned m_max; 166 unsigned int m_max;
173 unsigned mX_max; 167 unsigned int mX_max;
174 168
175 unsigned long fint_min, fint_max; 169 unsigned long fint_min, fint_max;
176 unsigned long clkdco_min, clkdco_low, clkdco_max; 170 unsigned long clkdco_min, clkdco_low, clkdco_max;
@@ -191,6 +185,7 @@ struct dss_pll_hw {
191struct dss_pll { 185struct dss_pll {
192 const char *name; 186 const char *name;
193 enum dss_pll_id id; 187 enum dss_pll_id id;
188 struct dss_device *dss;
194 189
195 struct clk *clkin; 190 struct clk *clkin;
196 struct regulator *regulator; 191 struct regulator *regulator;
@@ -232,8 +227,44 @@ struct dss_lcd_mgr_config {
232 int lcden_sig_polarity; 227 int lcden_sig_polarity;
233}; 228};
234 229
235struct seq_file; 230#define DSS_SZ_REGS SZ_512
236struct platform_device; 231
232struct dss_device {
233 struct platform_device *pdev;
234 void __iomem *base;
235 struct regmap *syscon_pll_ctrl;
236 u32 syscon_pll_ctrl_offset;
237
238 struct clk *parent_clk;
239 struct clk *dss_clk;
240 unsigned long dss_clk_rate;
241
242 unsigned long cache_req_pck;
243 unsigned long cache_prate;
244 struct dispc_clock_info cache_dispc_cinfo;
245
246 enum dss_clk_source dsi_clk_source[MAX_NUM_DSI];
247 enum dss_clk_source dispc_clk_source;
248 enum dss_clk_source lcd_clk_source[MAX_DSS_LCD_MANAGERS];
249
250 bool ctx_valid;
251 u32 ctx[DSS_SZ_REGS / sizeof(u32)];
252
253 const struct dss_features *feat;
254
255 struct {
256 struct dentry *root;
257 struct dss_debugfs_entry *clk;
258 struct dss_debugfs_entry *dss;
259 } debugfs;
260
261 struct dss_pll *plls[4];
262 struct dss_pll *video1_pll;
263 struct dss_pll *video2_pll;
264
265 struct dispc_device *dispc;
266 const struct dispc_ops *dispc_ops;
267};
237 268
238/* core */ 269/* core */
239static inline int dss_set_min_bus_tput(struct device *dev, unsigned long tput) 270static inline int dss_set_min_bus_tput(struct device *dev, unsigned long tput)
@@ -253,61 +284,81 @@ static inline bool dss_mgr_is_lcd(enum omap_channel id)
253 284
254/* DSS */ 285/* DSS */
255#if defined(CONFIG_OMAP2_DSS_DEBUGFS) 286#if defined(CONFIG_OMAP2_DSS_DEBUGFS)
256int dss_debugfs_create_file(const char *name, void (*write)(struct seq_file *)); 287struct dss_debugfs_entry *
288dss_debugfs_create_file(struct dss_device *dss, const char *name,
289 int (*show_fn)(struct seq_file *s, void *data),
290 void *data);
291void dss_debugfs_remove_file(struct dss_debugfs_entry *entry);
257#else 292#else
258static inline int dss_debugfs_create_file(const char *name, 293static inline struct dss_debugfs_entry *
259 void (*write)(struct seq_file *)) 294dss_debugfs_create_file(struct dss_device *dss, const char *name,
295 int (*show_fn)(struct seq_file *s, void *data),
296 void *data)
297{
298 return NULL;
299}
300
301static inline void dss_debugfs_remove_file(struct dss_debugfs_entry *entry)
260{ 302{
261 return 0;
262} 303}
263#endif /* CONFIG_OMAP2_DSS_DEBUGFS */ 304#endif /* CONFIG_OMAP2_DSS_DEBUGFS */
264 305
265int dss_runtime_get(void); 306struct dss_device *dss_get_device(struct device *dev);
266void dss_runtime_put(void);
267 307
268unsigned long dss_get_dispc_clk_rate(void); 308int dss_runtime_get(struct dss_device *dss);
269unsigned long dss_get_max_fck_rate(void); 309void dss_runtime_put(struct dss_device *dss);
270enum omap_dss_output_id dss_get_supported_outputs(enum omap_channel channel); 310
271int dss_dpi_select_source(int port, enum omap_channel channel); 311unsigned long dss_get_dispc_clk_rate(struct dss_device *dss);
272void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select); 312unsigned long dss_get_max_fck_rate(struct dss_device *dss);
273enum dss_hdmi_venc_clk_source_select dss_get_hdmi_venc_clk_source(void); 313enum omap_dss_output_id dss_get_supported_outputs(struct dss_device *dss,
314 enum omap_channel channel);
315int dss_dpi_select_source(struct dss_device *dss, int port,
316 enum omap_channel channel);
317void dss_select_hdmi_venc_clk_source(struct dss_device *dss,
318 enum dss_hdmi_venc_clk_source_select src);
274const char *dss_get_clk_source_name(enum dss_clk_source clk_src); 319const char *dss_get_clk_source_name(enum dss_clk_source clk_src);
275 320
276/* DSS VIDEO PLL */ 321/* DSS VIDEO PLL */
277struct dss_pll *dss_video_pll_init(struct platform_device *pdev, int id, 322struct dss_pll *dss_video_pll_init(struct dss_device *dss,
278 struct regulator *regulator); 323 struct platform_device *pdev, int id,
324 struct regulator *regulator);
279void dss_video_pll_uninit(struct dss_pll *pll); 325void dss_video_pll_uninit(struct dss_pll *pll);
280 326
281void dss_ctrl_pll_enable(enum dss_pll_id pll_id, bool enable); 327void dss_ctrl_pll_enable(struct dss_pll *pll, bool enable);
282 328
283void dss_sdi_init(int datapairs); 329void dss_sdi_init(struct dss_device *dss, int datapairs);
284int dss_sdi_enable(void); 330int dss_sdi_enable(struct dss_device *dss);
285void dss_sdi_disable(void); 331void dss_sdi_disable(struct dss_device *dss);
286 332
287void dss_select_dsi_clk_source(int dsi_module, 333void dss_select_dsi_clk_source(struct dss_device *dss, int dsi_module,
288 enum dss_clk_source clk_src); 334 enum dss_clk_source clk_src);
289void dss_select_lcd_clk_source(enum omap_channel channel, 335void dss_select_lcd_clk_source(struct dss_device *dss,
290 enum dss_clk_source clk_src); 336 enum omap_channel channel,
291enum dss_clk_source dss_get_dispc_clk_source(void); 337 enum dss_clk_source clk_src);
292enum dss_clk_source dss_get_dsi_clk_source(int dsi_module); 338enum dss_clk_source dss_get_dispc_clk_source(struct dss_device *dss);
293enum dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel); 339enum dss_clk_source dss_get_dsi_clk_source(struct dss_device *dss,
340 int dsi_module);
341enum dss_clk_source dss_get_lcd_clk_source(struct dss_device *dss,
342 enum omap_channel channel);
294 343
295void dss_set_venc_output(enum omap_dss_venc_type type); 344void dss_set_venc_output(struct dss_device *dss, enum omap_dss_venc_type type);
296void dss_set_dac_pwrdn_bgz(bool enable); 345void dss_set_dac_pwrdn_bgz(struct dss_device *dss, bool enable);
297 346
298int dss_set_fck_rate(unsigned long rate); 347int dss_set_fck_rate(struct dss_device *dss, unsigned long rate);
299 348
300typedef bool (*dss_div_calc_func)(unsigned long fck, void *data); 349typedef bool (*dss_div_calc_func)(unsigned long fck, void *data);
301bool dss_div_calc(unsigned long pck, unsigned long fck_min, 350bool dss_div_calc(struct dss_device *dss, unsigned long pck,
302 dss_div_calc_func func, void *data); 351 unsigned long fck_min, dss_div_calc_func func, void *data);
303 352
304/* SDI */ 353/* SDI */
305#ifdef CONFIG_OMAP2_DSS_SDI 354#ifdef CONFIG_OMAP2_DSS_SDI
306int sdi_init_port(struct platform_device *pdev, struct device_node *port); 355int sdi_init_port(struct dss_device *dss, struct platform_device *pdev,
356 struct device_node *port);
307void sdi_uninit_port(struct device_node *port); 357void sdi_uninit_port(struct device_node *port);
308#else 358#else
309static inline int sdi_init_port(struct platform_device *pdev, 359static inline int sdi_init_port(struct dss_device *dss,
310 struct device_node *port) 360 struct platform_device *pdev,
361 struct device_node *port)
311{ 362{
312 return 0; 363 return 0;
313} 364}
@@ -320,9 +371,6 @@ static inline void sdi_uninit_port(struct device_node *port)
320 371
321#ifdef CONFIG_OMAP2_DSS_DSI 372#ifdef CONFIG_OMAP2_DSS_DSI
322 373
323struct dentry;
324struct file_operations;
325
326void dsi_dump_clocks(struct seq_file *s); 374void dsi_dump_clocks(struct seq_file *s);
327 375
328void dsi_irq_handler(void); 376void dsi_irq_handler(void);
@@ -331,12 +379,14 @@ void dsi_irq_handler(void);
331 379
332/* DPI */ 380/* DPI */
333#ifdef CONFIG_OMAP2_DSS_DPI 381#ifdef CONFIG_OMAP2_DSS_DPI
334int dpi_init_port(struct platform_device *pdev, struct device_node *port, 382int dpi_init_port(struct dss_device *dss, struct platform_device *pdev,
335 enum dss_model dss_model); 383 struct device_node *port, enum dss_model dss_model);
336void dpi_uninit_port(struct device_node *port); 384void dpi_uninit_port(struct device_node *port);
337#else 385#else
338static inline int dpi_init_port(struct platform_device *pdev, 386static inline int dpi_init_port(struct dss_device *dss,
339 struct device_node *port, enum dss_model dss_model) 387 struct platform_device *pdev,
388 struct device_node *port,
389 enum dss_model dss_model)
340{ 390{
341 return 0; 391 return 0;
342} 392}
@@ -346,51 +396,49 @@ static inline void dpi_uninit_port(struct device_node *port)
346#endif 396#endif
347 397
348/* DISPC */ 398/* DISPC */
349void dispc_dump_clocks(struct seq_file *s); 399void dispc_dump_clocks(struct dispc_device *dispc, struct seq_file *s);
350 400
351int dispc_runtime_get(void); 401int dispc_runtime_get(struct dispc_device *dispc);
352void dispc_runtime_put(void); 402void dispc_runtime_put(struct dispc_device *dispc);
353 403
354void dispc_enable_sidle(void); 404void dispc_enable_sidle(struct dispc_device *dispc);
355void dispc_disable_sidle(void); 405void dispc_disable_sidle(struct dispc_device *dispc);
356 406
357void dispc_lcd_enable_signal(bool enable); 407void dispc_lcd_enable_signal(struct dispc_device *dispc, bool enable);
358void dispc_pck_free_enable(bool enable); 408void dispc_pck_free_enable(struct dispc_device *dispc, bool enable);
359void dispc_enable_fifomerge(bool enable); 409void dispc_enable_fifomerge(struct dispc_device *dispc, bool enable);
360void dispc_enable_gamma_table(bool enable);
361 410
362typedef bool (*dispc_div_calc_func)(int lckd, int pckd, unsigned long lck, 411typedef bool (*dispc_div_calc_func)(int lckd, int pckd, unsigned long lck,
363 unsigned long pck, void *data); 412 unsigned long pck, void *data);
364bool dispc_div_calc(unsigned long dispc, 413bool dispc_div_calc(struct dispc_device *dispc, unsigned long dispc_freq,
365 unsigned long pck_min, unsigned long pck_max, 414 unsigned long pck_min, unsigned long pck_max,
366 dispc_div_calc_func func, void *data); 415 dispc_div_calc_func func, void *data);
367 416
368bool dispc_mgr_timings_ok(enum omap_channel channel, const struct videomode *vm); 417bool dispc_mgr_timings_ok(struct dispc_device *dispc,
369int dispc_calc_clock_rates(unsigned long dispc_fclk_rate, 418 enum omap_channel channel,
370 struct dispc_clock_info *cinfo); 419 const struct videomode *vm);
371 420int dispc_calc_clock_rates(struct dispc_device *dispc,
372 421 unsigned long dispc_fclk_rate,
373void dispc_ovl_set_fifo_threshold(enum omap_plane_id plane, u32 low, 422 struct dispc_clock_info *cinfo);
374 u32 high); 423
375void dispc_ovl_compute_fifo_thresholds(enum omap_plane_id plane, 424
376 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge, 425void dispc_ovl_set_fifo_threshold(struct dispc_device *dispc,
377 bool manual_update); 426 enum omap_plane_id plane, u32 low, u32 high);
378 427void dispc_ovl_compute_fifo_thresholds(struct dispc_device *dispc,
379void dispc_mgr_set_clock_div(enum omap_channel channel, 428 enum omap_plane_id plane,
380 const struct dispc_clock_info *cinfo); 429 u32 *fifo_low, u32 *fifo_high,
381int dispc_mgr_get_clock_div(enum omap_channel channel, 430 bool use_fifomerge, bool manual_update);
382 struct dispc_clock_info *cinfo); 431
383void dispc_set_tv_pclk(unsigned long pclk); 432void dispc_mgr_set_clock_div(struct dispc_device *dispc,
384 433 enum omap_channel channel,
385u32 dispc_wb_get_framedone_irq(void); 434 const struct dispc_clock_info *cinfo);
386bool dispc_wb_go_busy(void); 435int dispc_mgr_get_clock_div(struct dispc_device *dispc,
387void dispc_wb_go(void); 436 enum omap_channel channel,
388void dispc_wb_set_channel_in(enum dss_writeback_channel channel); 437 struct dispc_clock_info *cinfo);
389int dispc_wb_setup(const struct omap_dss_writeback_info *wi, 438void dispc_set_tv_pclk(struct dispc_device *dispc, unsigned long pclk);
390 bool mem_to_mem, const struct videomode *vm);
391 439
392#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS 440#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
393static inline void dss_collect_irq_stats(u32 irqstatus, unsigned *irq_arr) 441static inline void dss_collect_irq_stats(u32 irqstatus, unsigned int *irq_arr)
394{ 442{
395 int b; 443 int b;
396 for (b = 0; b < 32; ++b) { 444 for (b = 0; b < 32; ++b) {
@@ -406,11 +454,12 @@ typedef bool (*dss_pll_calc_func)(int n, int m, unsigned long fint,
406typedef bool (*dss_hsdiv_calc_func)(int m_dispc, unsigned long dispc, 454typedef bool (*dss_hsdiv_calc_func)(int m_dispc, unsigned long dispc,
407 void *data); 455 void *data);
408 456
409int dss_pll_register(struct dss_pll *pll); 457int dss_pll_register(struct dss_device *dss, struct dss_pll *pll);
410void dss_pll_unregister(struct dss_pll *pll); 458void dss_pll_unregister(struct dss_pll *pll);
411struct dss_pll *dss_pll_find(const char *name); 459struct dss_pll *dss_pll_find(struct dss_device *dss, const char *name);
412struct dss_pll *dss_pll_find_by_src(enum dss_clk_source src); 460struct dss_pll *dss_pll_find_by_src(struct dss_device *dss,
413unsigned dss_pll_get_clkout_idx_for_src(enum dss_clk_source src); 461 enum dss_clk_source src);
462unsigned int dss_pll_get_clkout_idx_for_src(enum dss_clk_source src);
414int dss_pll_enable(struct dss_pll *pll); 463int dss_pll_enable(struct dss_pll *pll);
415void dss_pll_disable(struct dss_pll *pll); 464void dss_pll_disable(struct dss_pll *pll);
416int dss_pll_set_config(struct dss_pll *pll, 465int dss_pll_set_config(struct dss_pll *pll,
diff --git a/drivers/gpu/drm/omapdrm/dss/hdmi.h b/drivers/gpu/drm/omapdrm/dss/hdmi.h
index c2609c448ddc..3aeb4cabd59f 100644
--- a/drivers/gpu/drm/omapdrm/dss/hdmi.h
+++ b/drivers/gpu/drm/omapdrm/dss/hdmi.h
@@ -29,6 +29,8 @@
29#include "omapdss.h" 29#include "omapdss.h"
30#include "dss.h" 30#include "dss.h"
31 31
32struct dss_device;
33
32/* HDMI Wrapper */ 34/* HDMI Wrapper */
33 35
34#define HDMI_WP_REVISION 0x0 36#define HDMI_WP_REVISION 0x0
@@ -324,8 +326,8 @@ phys_addr_t hdmi_wp_get_audio_dma_addr(struct hdmi_wp_data *wp);
324 326
325/* HDMI PLL funcs */ 327/* HDMI PLL funcs */
326void hdmi_pll_dump(struct hdmi_pll_data *pll, struct seq_file *s); 328void hdmi_pll_dump(struct hdmi_pll_data *pll, struct seq_file *s);
327int hdmi_pll_init(struct platform_device *pdev, struct hdmi_pll_data *pll, 329int hdmi_pll_init(struct dss_device *dss, struct platform_device *pdev,
328 struct hdmi_wp_data *wp); 330 struct hdmi_pll_data *pll, struct hdmi_wp_data *wp);
329void hdmi_pll_uninit(struct hdmi_pll_data *hpll); 331void hdmi_pll_uninit(struct hdmi_pll_data *hpll);
330 332
331/* HDMI PHY funcs */ 333/* HDMI PHY funcs */
@@ -357,6 +359,9 @@ static inline bool hdmi_mode_has_audio(struct hdmi_config *cfg)
357struct omap_hdmi { 359struct omap_hdmi {
358 struct mutex lock; 360 struct mutex lock;
359 struct platform_device *pdev; 361 struct platform_device *pdev;
362 struct dss_device *dss;
363
364 struct dss_debugfs_entry *debugfs;
360 365
361 struct hdmi_wp_data wp; 366 struct hdmi_wp_data wp;
362 struct hdmi_pll_data pll; 367 struct hdmi_pll_data pll;
@@ -384,4 +389,6 @@ struct omap_hdmi {
384 bool display_enabled; 389 bool display_enabled;
385}; 390};
386 391
392#define dssdev_to_hdmi(dssdev) container_of(dssdev, struct omap_hdmi, output)
393
387#endif 394#endif
diff --git a/drivers/gpu/drm/omapdrm/dss/hdmi4.c b/drivers/gpu/drm/omapdrm/dss/hdmi4.c
index bf914f2ac99e..97c88861d67a 100644
--- a/drivers/gpu/drm/omapdrm/dss/hdmi4.c
+++ b/drivers/gpu/drm/omapdrm/dss/hdmi4.c
@@ -45,15 +45,13 @@
45#include "dss.h" 45#include "dss.h"
46#include "hdmi.h" 46#include "hdmi.h"
47 47
48static struct omap_hdmi hdmi; 48static int hdmi_runtime_get(struct omap_hdmi *hdmi)
49
50static int hdmi_runtime_get(void)
51{ 49{
52 int r; 50 int r;
53 51
54 DSSDBG("hdmi_runtime_get\n"); 52 DSSDBG("hdmi_runtime_get\n");
55 53
56 r = pm_runtime_get_sync(&hdmi.pdev->dev); 54 r = pm_runtime_get_sync(&hdmi->pdev->dev);
57 WARN_ON(r < 0); 55 WARN_ON(r < 0);
58 if (r < 0) 56 if (r < 0)
59 return r; 57 return r;
@@ -61,13 +59,13 @@ static int hdmi_runtime_get(void)
61 return 0; 59 return 0;
62} 60}
63 61
64static void hdmi_runtime_put(void) 62static void hdmi_runtime_put(struct omap_hdmi *hdmi)
65{ 63{
66 int r; 64 int r;
67 65
68 DSSDBG("hdmi_runtime_put\n"); 66 DSSDBG("hdmi_runtime_put\n");
69 67
70 r = pm_runtime_put_sync(&hdmi.pdev->dev); 68 r = pm_runtime_put_sync(&hdmi->pdev->dev);
71 WARN_ON(r < 0 && r != -ENOSYS); 69 WARN_ON(r < 0 && r != -ENOSYS);
72} 70}
73 71
@@ -110,14 +108,14 @@ static irqreturn_t hdmi_irq_handler(int irq, void *data)
110 return IRQ_HANDLED; 108 return IRQ_HANDLED;
111} 109}
112 110
113static int hdmi_init_regulator(void) 111static int hdmi_init_regulator(struct omap_hdmi *hdmi)
114{ 112{
115 struct regulator *reg; 113 struct regulator *reg;
116 114
117 if (hdmi.vdda_reg != NULL) 115 if (hdmi->vdda_reg != NULL)
118 return 0; 116 return 0;
119 117
120 reg = devm_regulator_get(&hdmi.pdev->dev, "vdda"); 118 reg = devm_regulator_get(&hdmi->pdev->dev, "vdda");
121 119
122 if (IS_ERR(reg)) { 120 if (IS_ERR(reg)) {
123 if (PTR_ERR(reg) != -EPROBE_DEFER) 121 if (PTR_ERR(reg) != -EPROBE_DEFER)
@@ -125,64 +123,63 @@ static int hdmi_init_regulator(void)
125 return PTR_ERR(reg); 123 return PTR_ERR(reg);
126 } 124 }
127 125
128 hdmi.vdda_reg = reg; 126 hdmi->vdda_reg = reg;
129 127
130 return 0; 128 return 0;
131} 129}
132 130
133static int hdmi_power_on_core(struct omap_dss_device *dssdev) 131static int hdmi_power_on_core(struct omap_hdmi *hdmi)
134{ 132{
135 int r; 133 int r;
136 134
137 if (hdmi.core.core_pwr_cnt++) 135 if (hdmi->core.core_pwr_cnt++)
138 return 0; 136 return 0;
139 137
140 r = regulator_enable(hdmi.vdda_reg); 138 r = regulator_enable(hdmi->vdda_reg);
141 if (r) 139 if (r)
142 goto err_reg_enable; 140 goto err_reg_enable;
143 141
144 r = hdmi_runtime_get(); 142 r = hdmi_runtime_get(hdmi);
145 if (r) 143 if (r)
146 goto err_runtime_get; 144 goto err_runtime_get;
147 145
148 hdmi4_core_powerdown_disable(&hdmi.core); 146 hdmi4_core_powerdown_disable(&hdmi->core);
149 147
150 /* Make selection of HDMI in DSS */ 148 /* Make selection of HDMI in DSS */
151 dss_select_hdmi_venc_clk_source(DSS_HDMI_M_PCLK); 149 dss_select_hdmi_venc_clk_source(hdmi->dss, DSS_HDMI_M_PCLK);
152 150
153 hdmi.core_enabled = true; 151 hdmi->core_enabled = true;
154 152
155 return 0; 153 return 0;
156 154
157err_runtime_get: 155err_runtime_get:
158 regulator_disable(hdmi.vdda_reg); 156 regulator_disable(hdmi->vdda_reg);
159err_reg_enable: 157err_reg_enable:
160 hdmi.core.core_pwr_cnt--; 158 hdmi->core.core_pwr_cnt--;
161 159
162 return r; 160 return r;
163} 161}
164 162
165static void hdmi_power_off_core(struct omap_dss_device *dssdev) 163static void hdmi_power_off_core(struct omap_hdmi *hdmi)
166{ 164{
167 if (--hdmi.core.core_pwr_cnt) 165 if (--hdmi->core.core_pwr_cnt)
168 return; 166 return;
169 167
170 hdmi.core_enabled = false; 168 hdmi->core_enabled = false;
171 169
172 hdmi_runtime_put(); 170 hdmi_runtime_put(hdmi);
173 regulator_disable(hdmi.vdda_reg); 171 regulator_disable(hdmi->vdda_reg);
174} 172}
175 173
176static int hdmi_power_on_full(struct omap_dss_device *dssdev) 174static int hdmi_power_on_full(struct omap_hdmi *hdmi)
177{ 175{
178 int r; 176 int r;
179 struct videomode *vm; 177 struct videomode *vm;
180 enum omap_channel channel = dssdev->dispc_channel; 178 struct hdmi_wp_data *wp = &hdmi->wp;
181 struct hdmi_wp_data *wp = &hdmi.wp;
182 struct dss_pll_clock_info hdmi_cinfo = { 0 }; 179 struct dss_pll_clock_info hdmi_cinfo = { 0 };
183 unsigned pc; 180 unsigned int pc;
184 181
185 r = hdmi_power_on_core(dssdev); 182 r = hdmi_power_on_core(hdmi);
186 if (r) 183 if (r)
187 return r; 184 return r;
188 185
@@ -190,7 +187,7 @@ static int hdmi_power_on_full(struct omap_dss_device *dssdev)
190 hdmi_wp_clear_irqenable(wp, ~HDMI_IRQ_CORE); 187 hdmi_wp_clear_irqenable(wp, ~HDMI_IRQ_CORE);
191 hdmi_wp_set_irqstatus(wp, ~HDMI_IRQ_CORE); 188 hdmi_wp_set_irqstatus(wp, ~HDMI_IRQ_CORE);
192 189
193 vm = &hdmi.cfg.vm; 190 vm = &hdmi->cfg.vm;
194 191
195 DSSDBG("hdmi_power_on hactive= %d vactive = %d\n", vm->hactive, 192 DSSDBG("hdmi_power_on hactive= %d vactive = %d\n", vm->hactive,
196 vm->vactive); 193 vm->vactive);
@@ -202,22 +199,22 @@ static int hdmi_power_on_full(struct omap_dss_device *dssdev)
202 /* DSS_HDMI_TCLK is bitclk / 10 */ 199 /* DSS_HDMI_TCLK is bitclk / 10 */
203 pc *= 10; 200 pc *= 10;
204 201
205 dss_pll_calc_b(&hdmi.pll.pll, clk_get_rate(hdmi.pll.pll.clkin), 202 dss_pll_calc_b(&hdmi->pll.pll, clk_get_rate(hdmi->pll.pll.clkin),
206 pc, &hdmi_cinfo); 203 pc, &hdmi_cinfo);
207 204
208 r = dss_pll_enable(&hdmi.pll.pll); 205 r = dss_pll_enable(&hdmi->pll.pll);
209 if (r) { 206 if (r) {
210 DSSERR("Failed to enable PLL\n"); 207 DSSERR("Failed to enable PLL\n");
211 goto err_pll_enable; 208 goto err_pll_enable;
212 } 209 }
213 210
214 r = dss_pll_set_config(&hdmi.pll.pll, &hdmi_cinfo); 211 r = dss_pll_set_config(&hdmi->pll.pll, &hdmi_cinfo);
215 if (r) { 212 if (r) {
216 DSSERR("Failed to configure PLL\n"); 213 DSSERR("Failed to configure PLL\n");
217 goto err_pll_cfg; 214 goto err_pll_cfg;
218 } 215 }
219 216
220 r = hdmi_phy_configure(&hdmi.phy, hdmi_cinfo.clkdco, 217 r = hdmi_phy_configure(&hdmi->phy, hdmi_cinfo.clkdco,
221 hdmi_cinfo.clkout[0]); 218 hdmi_cinfo.clkout[0]);
222 if (r) { 219 if (r) {
223 DSSDBG("Failed to configure PHY\n"); 220 DSSDBG("Failed to configure PHY\n");
@@ -228,16 +225,16 @@ static int hdmi_power_on_full(struct omap_dss_device *dssdev)
228 if (r) 225 if (r)
229 goto err_phy_pwr; 226 goto err_phy_pwr;
230 227
231 hdmi4_configure(&hdmi.core, &hdmi.wp, &hdmi.cfg); 228 hdmi4_configure(&hdmi->core, &hdmi->wp, &hdmi->cfg);
232 229
233 /* tv size */ 230 /* tv size */
234 dss_mgr_set_timings(channel, vm); 231 dss_mgr_set_timings(&hdmi->output, vm);
235 232
236 r = dss_mgr_enable(channel); 233 r = dss_mgr_enable(&hdmi->output);
237 if (r) 234 if (r)
238 goto err_mgr_enable; 235 goto err_mgr_enable;
239 236
240 r = hdmi_wp_video_start(&hdmi.wp); 237 r = hdmi_wp_video_start(&hdmi->wp);
241 if (r) 238 if (r)
242 goto err_vid_enable; 239 goto err_vid_enable;
243 240
@@ -247,39 +244,39 @@ static int hdmi_power_on_full(struct omap_dss_device *dssdev)
247 return 0; 244 return 0;
248 245
249err_vid_enable: 246err_vid_enable:
250 dss_mgr_disable(channel); 247 dss_mgr_disable(&hdmi->output);
251err_mgr_enable: 248err_mgr_enable:
252 hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_OFF); 249 hdmi_wp_set_phy_pwr(&hdmi->wp, HDMI_PHYPWRCMD_OFF);
253err_phy_pwr: 250err_phy_pwr:
254err_phy_cfg: 251err_phy_cfg:
255err_pll_cfg: 252err_pll_cfg:
256 dss_pll_disable(&hdmi.pll.pll); 253 dss_pll_disable(&hdmi->pll.pll);
257err_pll_enable: 254err_pll_enable:
258 hdmi_power_off_core(dssdev); 255 hdmi_power_off_core(hdmi);
259 return -EIO; 256 return -EIO;
260} 257}
261 258
262static void hdmi_power_off_full(struct omap_dss_device *dssdev) 259static void hdmi_power_off_full(struct omap_hdmi *hdmi)
263{ 260{
264 enum omap_channel channel = dssdev->dispc_channel; 261 hdmi_wp_clear_irqenable(&hdmi->wp, ~HDMI_IRQ_CORE);
265
266 hdmi_wp_clear_irqenable(&hdmi.wp, ~HDMI_IRQ_CORE);
267 262
268 hdmi_wp_video_stop(&hdmi.wp); 263 hdmi_wp_video_stop(&hdmi->wp);
269 264
270 dss_mgr_disable(channel); 265 dss_mgr_disable(&hdmi->output);
271 266
272 hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_OFF); 267 hdmi_wp_set_phy_pwr(&hdmi->wp, HDMI_PHYPWRCMD_OFF);
273 268
274 dss_pll_disable(&hdmi.pll.pll); 269 dss_pll_disable(&hdmi->pll.pll);
275 270
276 hdmi_power_off_core(dssdev); 271 hdmi_power_off_core(hdmi);
277} 272}
278 273
279static int hdmi_display_check_timing(struct omap_dss_device *dssdev, 274static int hdmi_display_check_timing(struct omap_dss_device *dssdev,
280 struct videomode *vm) 275 struct videomode *vm)
281{ 276{
282 if (!dispc_mgr_timings_ok(dssdev->dispc_channel, vm)) 277 struct omap_hdmi *hdmi = dssdev_to_hdmi(dssdev);
278
279 if (!dispc_mgr_timings_ok(hdmi->dss->dispc, dssdev->dispc_channel, vm))
283 return -EINVAL; 280 return -EINVAL;
284 281
285 return 0; 282 return 0;
@@ -288,52 +285,59 @@ static int hdmi_display_check_timing(struct omap_dss_device *dssdev,
288static void hdmi_display_set_timing(struct omap_dss_device *dssdev, 285static void hdmi_display_set_timing(struct omap_dss_device *dssdev,
289 struct videomode *vm) 286 struct videomode *vm)
290{ 287{
291 mutex_lock(&hdmi.lock); 288 struct omap_hdmi *hdmi = dssdev_to_hdmi(dssdev);
289
290 mutex_lock(&hdmi->lock);
292 291
293 hdmi.cfg.vm = *vm; 292 hdmi->cfg.vm = *vm;
294 293
295 dispc_set_tv_pclk(vm->pixelclock); 294 dispc_set_tv_pclk(hdmi->dss->dispc, vm->pixelclock);
296 295
297 mutex_unlock(&hdmi.lock); 296 mutex_unlock(&hdmi->lock);
298} 297}
299 298
300static void hdmi_display_get_timings(struct omap_dss_device *dssdev, 299static void hdmi_display_get_timings(struct omap_dss_device *dssdev,
301 struct videomode *vm) 300 struct videomode *vm)
302{ 301{
303 *vm = hdmi.cfg.vm; 302 struct omap_hdmi *hdmi = dssdev_to_hdmi(dssdev);
303
304 *vm = hdmi->cfg.vm;
304} 305}
305 306
306static void hdmi_dump_regs(struct seq_file *s) 307static int hdmi_dump_regs(struct seq_file *s, void *p)
307{ 308{
308 mutex_lock(&hdmi.lock); 309 struct omap_hdmi *hdmi = s->private;
309 310
310 if (hdmi_runtime_get()) { 311 mutex_lock(&hdmi->lock);
311 mutex_unlock(&hdmi.lock); 312
312 return; 313 if (hdmi_runtime_get(hdmi)) {
314 mutex_unlock(&hdmi->lock);
315 return 0;
313 } 316 }
314 317
315 hdmi_wp_dump(&hdmi.wp, s); 318 hdmi_wp_dump(&hdmi->wp, s);
316 hdmi_pll_dump(&hdmi.pll, s); 319 hdmi_pll_dump(&hdmi->pll, s);
317 hdmi_phy_dump(&hdmi.phy, s); 320 hdmi_phy_dump(&hdmi->phy, s);
318 hdmi4_core_dump(&hdmi.core, s); 321 hdmi4_core_dump(&hdmi->core, s);
319 322
320 hdmi_runtime_put(); 323 hdmi_runtime_put(hdmi);
321 mutex_unlock(&hdmi.lock); 324 mutex_unlock(&hdmi->lock);
325 return 0;
322} 326}
323 327
324static int read_edid(u8 *buf, int len) 328static int read_edid(struct omap_hdmi *hdmi, u8 *buf, int len)
325{ 329{
326 int r; 330 int r;
327 331
328 mutex_lock(&hdmi.lock); 332 mutex_lock(&hdmi->lock);
329 333
330 r = hdmi_runtime_get(); 334 r = hdmi_runtime_get(hdmi);
331 BUG_ON(r); 335 BUG_ON(r);
332 336
333 r = hdmi4_read_edid(&hdmi.core, buf, len); 337 r = hdmi4_read_edid(&hdmi->core, buf, len);
334 338
335 hdmi_runtime_put(); 339 hdmi_runtime_put(hdmi);
336 mutex_unlock(&hdmi.lock); 340 mutex_unlock(&hdmi->lock);
337 341
338 return r; 342 return r;
339} 343}
@@ -352,112 +356,117 @@ static void hdmi_stop_audio_stream(struct omap_hdmi *hd)
352 356
353static int hdmi_display_enable(struct omap_dss_device *dssdev) 357static int hdmi_display_enable(struct omap_dss_device *dssdev)
354{ 358{
355 struct omap_dss_device *out = &hdmi.output; 359 struct omap_hdmi *hdmi = dssdev_to_hdmi(dssdev);
356 unsigned long flags; 360 unsigned long flags;
357 int r = 0; 361 int r = 0;
358 362
359 DSSDBG("ENTER hdmi_display_enable\n"); 363 DSSDBG("ENTER hdmi_display_enable\n");
360 364
361 mutex_lock(&hdmi.lock); 365 mutex_lock(&hdmi->lock);
362 366
363 if (!out->dispc_channel_connected) { 367 if (!dssdev->dispc_channel_connected) {
364 DSSERR("failed to enable display: no output/manager\n"); 368 DSSERR("failed to enable display: no output/manager\n");
365 r = -ENODEV; 369 r = -ENODEV;
366 goto err0; 370 goto err0;
367 } 371 }
368 372
369 r = hdmi_power_on_full(dssdev); 373 r = hdmi_power_on_full(hdmi);
370 if (r) { 374 if (r) {
371 DSSERR("failed to power on device\n"); 375 DSSERR("failed to power on device\n");
372 goto err0; 376 goto err0;
373 } 377 }
374 378
375 if (hdmi.audio_configured) { 379 if (hdmi->audio_configured) {
376 r = hdmi4_audio_config(&hdmi.core, &hdmi.wp, &hdmi.audio_config, 380 r = hdmi4_audio_config(&hdmi->core, &hdmi->wp,
377 hdmi.cfg.vm.pixelclock); 381 &hdmi->audio_config,
382 hdmi->cfg.vm.pixelclock);
378 if (r) { 383 if (r) {
379 DSSERR("Error restoring audio configuration: %d", r); 384 DSSERR("Error restoring audio configuration: %d", r);
380 hdmi.audio_abort_cb(&hdmi.pdev->dev); 385 hdmi->audio_abort_cb(&hdmi->pdev->dev);
381 hdmi.audio_configured = false; 386 hdmi->audio_configured = false;
382 } 387 }
383 } 388 }
384 389
385 spin_lock_irqsave(&hdmi.audio_playing_lock, flags); 390 spin_lock_irqsave(&hdmi->audio_playing_lock, flags);
386 if (hdmi.audio_configured && hdmi.audio_playing) 391 if (hdmi->audio_configured && hdmi->audio_playing)
387 hdmi_start_audio_stream(&hdmi); 392 hdmi_start_audio_stream(hdmi);
388 hdmi.display_enabled = true; 393 hdmi->display_enabled = true;
389 spin_unlock_irqrestore(&hdmi.audio_playing_lock, flags); 394 spin_unlock_irqrestore(&hdmi->audio_playing_lock, flags);
390 395
391 mutex_unlock(&hdmi.lock); 396 mutex_unlock(&hdmi->lock);
392 return 0; 397 return 0;
393 398
394err0: 399err0:
395 mutex_unlock(&hdmi.lock); 400 mutex_unlock(&hdmi->lock);
396 return r; 401 return r;
397} 402}
398 403
399static void hdmi_display_disable(struct omap_dss_device *dssdev) 404static void hdmi_display_disable(struct omap_dss_device *dssdev)
400{ 405{
406 struct omap_hdmi *hdmi = dssdev_to_hdmi(dssdev);
401 unsigned long flags; 407 unsigned long flags;
402 408
403 DSSDBG("Enter hdmi_display_disable\n"); 409 DSSDBG("Enter hdmi_display_disable\n");
404 410
405 mutex_lock(&hdmi.lock); 411 mutex_lock(&hdmi->lock);
406 412
407 spin_lock_irqsave(&hdmi.audio_playing_lock, flags); 413 spin_lock_irqsave(&hdmi->audio_playing_lock, flags);
408 hdmi_stop_audio_stream(&hdmi); 414 hdmi_stop_audio_stream(hdmi);
409 hdmi.display_enabled = false; 415 hdmi->display_enabled = false;
410 spin_unlock_irqrestore(&hdmi.audio_playing_lock, flags); 416 spin_unlock_irqrestore(&hdmi->audio_playing_lock, flags);
411 417
412 hdmi_power_off_full(dssdev); 418 hdmi_power_off_full(hdmi);
413 419
414 mutex_unlock(&hdmi.lock); 420 mutex_unlock(&hdmi->lock);
415} 421}
416 422
417int hdmi4_core_enable(struct omap_dss_device *dssdev) 423int hdmi4_core_enable(struct hdmi_core_data *core)
418{ 424{
425 struct omap_hdmi *hdmi = container_of(core, struct omap_hdmi, core);
419 int r = 0; 426 int r = 0;
420 427
421 DSSDBG("ENTER omapdss_hdmi4_core_enable\n"); 428 DSSDBG("ENTER omapdss_hdmi4_core_enable\n");
422 429
423 mutex_lock(&hdmi.lock); 430 mutex_lock(&hdmi->lock);
424 431
425 r = hdmi_power_on_core(dssdev); 432 r = hdmi_power_on_core(hdmi);
426 if (r) { 433 if (r) {
427 DSSERR("failed to power on device\n"); 434 DSSERR("failed to power on device\n");
428 goto err0; 435 goto err0;
429 } 436 }
430 437
431 mutex_unlock(&hdmi.lock); 438 mutex_unlock(&hdmi->lock);
432 return 0; 439 return 0;
433 440
434err0: 441err0:
435 mutex_unlock(&hdmi.lock); 442 mutex_unlock(&hdmi->lock);
436 return r; 443 return r;
437} 444}
438 445
439void hdmi4_core_disable(struct omap_dss_device *dssdev) 446void hdmi4_core_disable(struct hdmi_core_data *core)
440{ 447{
448 struct omap_hdmi *hdmi = container_of(core, struct omap_hdmi, core);
449
441 DSSDBG("Enter omapdss_hdmi4_core_disable\n"); 450 DSSDBG("Enter omapdss_hdmi4_core_disable\n");
442 451
443 mutex_lock(&hdmi.lock); 452 mutex_lock(&hdmi->lock);
444 453
445 hdmi_power_off_core(dssdev); 454 hdmi_power_off_core(hdmi);
446 455
447 mutex_unlock(&hdmi.lock); 456 mutex_unlock(&hdmi->lock);
448} 457}
449 458
450static int hdmi_connect(struct omap_dss_device *dssdev, 459static int hdmi_connect(struct omap_dss_device *dssdev,
451 struct omap_dss_device *dst) 460 struct omap_dss_device *dst)
452{ 461{
453 enum omap_channel channel = dssdev->dispc_channel; 462 struct omap_hdmi *hdmi = dssdev_to_hdmi(dssdev);
454 int r; 463 int r;
455 464
456 r = hdmi_init_regulator(); 465 r = hdmi_init_regulator(hdmi);
457 if (r) 466 if (r)
458 return r; 467 return r;
459 468
460 r = dss_mgr_connect(channel, dssdev); 469 r = dss_mgr_connect(&hdmi->output, dssdev);
461 if (r) 470 if (r)
462 return r; 471 return r;
463 472
@@ -465,7 +474,7 @@ static int hdmi_connect(struct omap_dss_device *dssdev,
465 if (r) { 474 if (r) {
466 DSSERR("failed to connect output to new device: %s\n", 475 DSSERR("failed to connect output to new device: %s\n",
467 dst->name); 476 dst->name);
468 dss_mgr_disconnect(channel, dssdev); 477 dss_mgr_disconnect(&hdmi->output, dssdev);
469 return r; 478 return r;
470 } 479 }
471 480
@@ -475,7 +484,7 @@ static int hdmi_connect(struct omap_dss_device *dssdev,
475static void hdmi_disconnect(struct omap_dss_device *dssdev, 484static void hdmi_disconnect(struct omap_dss_device *dssdev,
476 struct omap_dss_device *dst) 485 struct omap_dss_device *dst)
477{ 486{
478 enum omap_channel channel = dssdev->dispc_channel; 487 struct omap_hdmi *hdmi = dssdev_to_hdmi(dssdev);
479 488
480 WARN_ON(dst != dssdev->dst); 489 WARN_ON(dst != dssdev->dst);
481 490
@@ -484,51 +493,58 @@ static void hdmi_disconnect(struct omap_dss_device *dssdev,
484 493
485 omapdss_output_unset_device(dssdev); 494 omapdss_output_unset_device(dssdev);
486 495
487 dss_mgr_disconnect(channel, dssdev); 496 dss_mgr_disconnect(&hdmi->output, dssdev);
488} 497}
489 498
490static int hdmi_read_edid(struct omap_dss_device *dssdev, 499static int hdmi_read_edid(struct omap_dss_device *dssdev,
491 u8 *edid, int len) 500 u8 *edid, int len)
492{ 501{
502 struct omap_hdmi *hdmi = dssdev_to_hdmi(dssdev);
493 bool need_enable; 503 bool need_enable;
494 int r; 504 int r;
495 505
496 need_enable = hdmi.core_enabled == false; 506 need_enable = hdmi->core_enabled == false;
497 507
498 if (need_enable) { 508 if (need_enable) {
499 r = hdmi4_core_enable(dssdev); 509 r = hdmi4_core_enable(&hdmi->core);
500 if (r) 510 if (r)
501 return r; 511 return r;
502 } 512 }
503 513
504 r = read_edid(edid, len); 514 r = read_edid(hdmi, edid, len);
505 if (r >= 256) 515 if (r >= 256)
506 hdmi4_cec_set_phys_addr(&hdmi.core, 516 hdmi4_cec_set_phys_addr(&hdmi->core,
507 cec_get_edid_phys_addr(edid, r, NULL)); 517 cec_get_edid_phys_addr(edid, r, NULL));
508 else 518 else
509 hdmi4_cec_set_phys_addr(&hdmi.core, CEC_PHYS_ADDR_INVALID); 519 hdmi4_cec_set_phys_addr(&hdmi->core, CEC_PHYS_ADDR_INVALID);
510 if (need_enable) 520 if (need_enable)
511 hdmi4_core_disable(dssdev); 521 hdmi4_core_disable(&hdmi->core);
512 522
513 return r; 523 return r;
514} 524}
515 525
516static void hdmi_lost_hotplug(struct omap_dss_device *dssdev) 526static void hdmi_lost_hotplug(struct omap_dss_device *dssdev)
517{ 527{
518 hdmi4_cec_set_phys_addr(&hdmi.core, CEC_PHYS_ADDR_INVALID); 528 struct omap_hdmi *hdmi = dssdev_to_hdmi(dssdev);
529
530 hdmi4_cec_set_phys_addr(&hdmi->core, CEC_PHYS_ADDR_INVALID);
519} 531}
520 532
521static int hdmi_set_infoframe(struct omap_dss_device *dssdev, 533static int hdmi_set_infoframe(struct omap_dss_device *dssdev,
522 const struct hdmi_avi_infoframe *avi) 534 const struct hdmi_avi_infoframe *avi)
523{ 535{
524 hdmi.cfg.infoframe = *avi; 536 struct omap_hdmi *hdmi = dssdev_to_hdmi(dssdev);
537
538 hdmi->cfg.infoframe = *avi;
525 return 0; 539 return 0;
526} 540}
527 541
528static int hdmi_set_hdmi_mode(struct omap_dss_device *dssdev, 542static int hdmi_set_hdmi_mode(struct omap_dss_device *dssdev,
529 bool hdmi_mode) 543 bool hdmi_mode)
530{ 544{
531 hdmi.cfg.hdmi_dvi_mode = hdmi_mode ? HDMI_HDMI : HDMI_DVI; 545 struct omap_hdmi *hdmi = dssdev_to_hdmi(dssdev);
546
547 hdmi->cfg.hdmi_dvi_mode = hdmi_mode ? HDMI_HDMI : HDMI_DVI;
532 return 0; 548 return 0;
533} 549}
534 550
@@ -549,11 +565,11 @@ static const struct omapdss_hdmi_ops hdmi_ops = {
549 .set_hdmi_mode = hdmi_set_hdmi_mode, 565 .set_hdmi_mode = hdmi_set_hdmi_mode,
550}; 566};
551 567
552static void hdmi_init_output(struct platform_device *pdev) 568static void hdmi_init_output(struct omap_hdmi *hdmi)
553{ 569{
554 struct omap_dss_device *out = &hdmi.output; 570 struct omap_dss_device *out = &hdmi->output;
555 571
556 out->dev = &pdev->dev; 572 out->dev = &hdmi->pdev->dev;
557 out->id = OMAP_DSS_OUTPUT_HDMI; 573 out->id = OMAP_DSS_OUTPUT_HDMI;
558 out->output_type = OMAP_DISPLAY_TYPE_HDMI; 574 out->output_type = OMAP_DISPLAY_TYPE_HDMI;
559 out->name = "hdmi.0"; 575 out->name = "hdmi.0";
@@ -564,15 +580,16 @@ static void hdmi_init_output(struct platform_device *pdev)
564 omapdss_register_output(out); 580 omapdss_register_output(out);
565} 581}
566 582
567static void hdmi_uninit_output(struct platform_device *pdev) 583static void hdmi_uninit_output(struct omap_hdmi *hdmi)
568{ 584{
569 struct omap_dss_device *out = &hdmi.output; 585 struct omap_dss_device *out = &hdmi->output;
570 586
571 omapdss_unregister_output(out); 587 omapdss_unregister_output(out);
572} 588}
573 589
574static int hdmi_probe_of(struct platform_device *pdev) 590static int hdmi_probe_of(struct omap_hdmi *hdmi)
575{ 591{
592 struct platform_device *pdev = hdmi->pdev;
576 struct device_node *node = pdev->dev.of_node; 593 struct device_node *node = pdev->dev.of_node;
577 struct device_node *ep; 594 struct device_node *ep;
578 int r; 595 int r;
@@ -581,7 +598,7 @@ static int hdmi_probe_of(struct platform_device *pdev)
581 if (!ep) 598 if (!ep)
582 return 0; 599 return 0;
583 600
584 r = hdmi_parse_lanes_of(pdev, ep, &hdmi.phy); 601 r = hdmi_parse_lanes_of(pdev, ep, &hdmi->phy);
585 if (r) 602 if (r)
586 goto err; 603 goto err;
587 604
@@ -598,21 +615,16 @@ static int hdmi_audio_startup(struct device *dev,
598 void (*abort_cb)(struct device *dev)) 615 void (*abort_cb)(struct device *dev))
599{ 616{
600 struct omap_hdmi *hd = dev_get_drvdata(dev); 617 struct omap_hdmi *hd = dev_get_drvdata(dev);
601 int ret = 0;
602 618
603 mutex_lock(&hd->lock); 619 mutex_lock(&hd->lock);
604 620
605 if (!hdmi_mode_has_audio(&hd->cfg) || !hd->display_enabled) { 621 WARN_ON(hd->audio_abort_cb != NULL);
606 ret = -EPERM;
607 goto out;
608 }
609 622
610 hd->audio_abort_cb = abort_cb; 623 hd->audio_abort_cb = abort_cb;
611 624
612out:
613 mutex_unlock(&hd->lock); 625 mutex_unlock(&hd->lock);
614 626
615 return ret; 627 return 0;
616} 628}
617 629
618static int hdmi_audio_shutdown(struct device *dev) 630static int hdmi_audio_shutdown(struct device *dev)
@@ -633,12 +645,14 @@ static int hdmi_audio_start(struct device *dev)
633 struct omap_hdmi *hd = dev_get_drvdata(dev); 645 struct omap_hdmi *hd = dev_get_drvdata(dev);
634 unsigned long flags; 646 unsigned long flags;
635 647
636 WARN_ON(!hdmi_mode_has_audio(&hd->cfg));
637
638 spin_lock_irqsave(&hd->audio_playing_lock, flags); 648 spin_lock_irqsave(&hd->audio_playing_lock, flags);
639 649
640 if (hd->display_enabled) 650 if (hd->display_enabled) {
651 if (!hdmi_mode_has_audio(&hd->cfg))
652 DSSERR("%s: Video mode does not support audio\n",
653 __func__);
641 hdmi_start_audio_stream(hd); 654 hdmi_start_audio_stream(hd);
655 }
642 hd->audio_playing = true; 656 hd->audio_playing = true;
643 657
644 spin_unlock_irqrestore(&hd->audio_playing_lock, flags); 658 spin_unlock_irqrestore(&hd->audio_playing_lock, flags);
@@ -669,17 +683,15 @@ static int hdmi_audio_config(struct device *dev,
669 683
670 mutex_lock(&hd->lock); 684 mutex_lock(&hd->lock);
671 685
672 if (!hdmi_mode_has_audio(&hd->cfg) || !hd->display_enabled) { 686 if (hd->display_enabled) {
673 ret = -EPERM; 687 ret = hdmi4_audio_config(&hd->core, &hd->wp, dss_audio,
674 goto out; 688 hd->cfg.vm.pixelclock);
689 if (ret)
690 goto out;
675 } 691 }
676 692
677 ret = hdmi4_audio_config(&hd->core, &hd->wp, dss_audio, 693 hd->audio_configured = true;
678 hd->cfg.vm.pixelclock); 694 hd->audio_config = *dss_audio;
679 if (!ret) {
680 hd->audio_configured = true;
681 hd->audio_config = *dss_audio;
682 }
683out: 695out:
684 mutex_unlock(&hd->lock); 696 mutex_unlock(&hd->lock);
685 697
@@ -694,21 +706,21 @@ static const struct omap_hdmi_audio_ops hdmi_audio_ops = {
694 .audio_config = hdmi_audio_config, 706 .audio_config = hdmi_audio_config,
695}; 707};
696 708
697static int hdmi_audio_register(struct device *dev) 709static int hdmi_audio_register(struct omap_hdmi *hdmi)
698{ 710{
699 struct omap_hdmi_audio_pdata pdata = { 711 struct omap_hdmi_audio_pdata pdata = {
700 .dev = dev, 712 .dev = &hdmi->pdev->dev,
701 .version = 4, 713 .version = 4,
702 .audio_dma_addr = hdmi_wp_get_audio_dma_addr(&hdmi.wp), 714 .audio_dma_addr = hdmi_wp_get_audio_dma_addr(&hdmi->wp),
703 .ops = &hdmi_audio_ops, 715 .ops = &hdmi_audio_ops,
704 }; 716 };
705 717
706 hdmi.audio_pdev = platform_device_register_data( 718 hdmi->audio_pdev = platform_device_register_data(
707 dev, "omap-hdmi-audio", PLATFORM_DEVID_AUTO, 719 &hdmi->pdev->dev, "omap-hdmi-audio", PLATFORM_DEVID_AUTO,
708 &pdata, sizeof(pdata)); 720 &pdata, sizeof(pdata));
709 721
710 if (IS_ERR(hdmi.audio_pdev)) 722 if (IS_ERR(hdmi->audio_pdev))
711 return PTR_ERR(hdmi.audio_pdev); 723 return PTR_ERR(hdmi->audio_pdev);
712 724
713 return 0; 725 return 0;
714} 726}
@@ -717,88 +729,103 @@ static int hdmi_audio_register(struct device *dev)
717static int hdmi4_bind(struct device *dev, struct device *master, void *data) 729static int hdmi4_bind(struct device *dev, struct device *master, void *data)
718{ 730{
719 struct platform_device *pdev = to_platform_device(dev); 731 struct platform_device *pdev = to_platform_device(dev);
732 struct dss_device *dss = dss_get_device(master);
733 struct omap_hdmi *hdmi;
720 int r; 734 int r;
721 int irq; 735 int irq;
722 736
723 hdmi.pdev = pdev; 737 hdmi = kzalloc(sizeof(*hdmi), GFP_KERNEL);
724 dev_set_drvdata(&pdev->dev, &hdmi); 738 if (!hdmi)
739 return -ENOMEM;
740
741 hdmi->pdev = pdev;
742 hdmi->dss = dss;
743 dev_set_drvdata(&pdev->dev, hdmi);
725 744
726 mutex_init(&hdmi.lock); 745 mutex_init(&hdmi->lock);
727 spin_lock_init(&hdmi.audio_playing_lock); 746 spin_lock_init(&hdmi->audio_playing_lock);
728 747
729 r = hdmi_probe_of(pdev); 748 r = hdmi_probe_of(hdmi);
730 if (r) 749 if (r)
731 return r; 750 goto err_free;
732 751
733 r = hdmi_wp_init(pdev, &hdmi.wp, 4); 752 r = hdmi_wp_init(pdev, &hdmi->wp, 4);
734 if (r) 753 if (r)
735 return r; 754 goto err_free;
736 755
737 r = hdmi_pll_init(pdev, &hdmi.pll, &hdmi.wp); 756 r = hdmi_pll_init(dss, pdev, &hdmi->pll, &hdmi->wp);
738 if (r) 757 if (r)
739 return r; 758 goto err_free;
740 759
741 r = hdmi_phy_init(pdev, &hdmi.phy, 4); 760 r = hdmi_phy_init(pdev, &hdmi->phy, 4);
742 if (r) 761 if (r)
743 goto err; 762 goto err_pll;
744 763
745 r = hdmi4_core_init(pdev, &hdmi.core); 764 r = hdmi4_core_init(pdev, &hdmi->core);
746 if (r) 765 if (r)
747 goto err; 766 goto err_pll;
748 767
749 r = hdmi4_cec_init(pdev, &hdmi.core, &hdmi.wp); 768 r = hdmi4_cec_init(pdev, &hdmi->core, &hdmi->wp);
750 if (r) 769 if (r)
751 goto err; 770 goto err_pll;
752 771
753 irq = platform_get_irq(pdev, 0); 772 irq = platform_get_irq(pdev, 0);
754 if (irq < 0) { 773 if (irq < 0) {
755 DSSERR("platform_get_irq failed\n"); 774 DSSERR("platform_get_irq failed\n");
756 r = -ENODEV; 775 r = -ENODEV;
757 goto err; 776 goto err_pll;
758 } 777 }
759 778
760 r = devm_request_threaded_irq(&pdev->dev, irq, 779 r = devm_request_threaded_irq(&pdev->dev, irq,
761 NULL, hdmi_irq_handler, 780 NULL, hdmi_irq_handler,
762 IRQF_ONESHOT, "OMAP HDMI", &hdmi); 781 IRQF_ONESHOT, "OMAP HDMI", hdmi);
763 if (r) { 782 if (r) {
764 DSSERR("HDMI IRQ request failed\n"); 783 DSSERR("HDMI IRQ request failed\n");
765 goto err; 784 goto err_pll;
766 } 785 }
767 786
768 pm_runtime_enable(&pdev->dev); 787 pm_runtime_enable(&pdev->dev);
769 788
770 hdmi_init_output(pdev); 789 hdmi_init_output(hdmi);
771 790
772 r = hdmi_audio_register(&pdev->dev); 791 r = hdmi_audio_register(hdmi);
773 if (r) { 792 if (r) {
774 DSSERR("Registering HDMI audio failed\n"); 793 DSSERR("Registering HDMI audio failed\n");
775 hdmi_uninit_output(pdev); 794 hdmi_uninit_output(hdmi);
776 pm_runtime_disable(&pdev->dev); 795 pm_runtime_disable(&pdev->dev);
777 return r; 796 return r;
778 } 797 }
779 798
780 dss_debugfs_create_file("hdmi", hdmi_dump_regs); 799 hdmi->debugfs = dss_debugfs_create_file(dss, "hdmi", hdmi_dump_regs,
800 hdmi);
781 801
782 return 0; 802 return 0;
783err: 803
784 hdmi_pll_uninit(&hdmi.pll); 804err_pll:
805 hdmi_pll_uninit(&hdmi->pll);
806err_free:
807 kfree(hdmi);
785 return r; 808 return r;
786} 809}
787 810
788static void hdmi4_unbind(struct device *dev, struct device *master, void *data) 811static void hdmi4_unbind(struct device *dev, struct device *master, void *data)
789{ 812{
790 struct platform_device *pdev = to_platform_device(dev); 813 struct omap_hdmi *hdmi = dev_get_drvdata(dev);
814
815 dss_debugfs_remove_file(hdmi->debugfs);
791 816
792 if (hdmi.audio_pdev) 817 if (hdmi->audio_pdev)
793 platform_device_unregister(hdmi.audio_pdev); 818 platform_device_unregister(hdmi->audio_pdev);
794 819
795 hdmi_uninit_output(pdev); 820 hdmi_uninit_output(hdmi);
796 821
797 hdmi4_cec_uninit(&hdmi.core); 822 hdmi4_cec_uninit(&hdmi->core);
798 823
799 hdmi_pll_uninit(&hdmi.pll); 824 hdmi_pll_uninit(&hdmi->pll);
800 825
801 pm_runtime_disable(&pdev->dev); 826 pm_runtime_disable(dev);
827
828 kfree(hdmi);
802} 829}
803 830
804static const struct component_ops hdmi4_component_ops = { 831static const struct component_ops hdmi4_component_ops = {
@@ -819,16 +846,19 @@ static int hdmi4_remove(struct platform_device *pdev)
819 846
820static int hdmi_runtime_suspend(struct device *dev) 847static int hdmi_runtime_suspend(struct device *dev)
821{ 848{
822 dispc_runtime_put(); 849 struct omap_hdmi *hdmi = dev_get_drvdata(dev);
850
851 dispc_runtime_put(hdmi->dss->dispc);
823 852
824 return 0; 853 return 0;
825} 854}
826 855
827static int hdmi_runtime_resume(struct device *dev) 856static int hdmi_runtime_resume(struct device *dev)
828{ 857{
858 struct omap_hdmi *hdmi = dev_get_drvdata(dev);
829 int r; 859 int r;
830 860
831 r = dispc_runtime_get(); 861 r = dispc_runtime_get(hdmi->dss->dispc);
832 if (r < 0) 862 if (r < 0)
833 return r; 863 return r;
834 864
diff --git a/drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c b/drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c
index 23db74ae1826..340383150fb9 100644
--- a/drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c
+++ b/drivers/gpu/drm/omapdrm/dss/hdmi4_cec.c
@@ -175,10 +175,10 @@ static int hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable)
175 REG_FLD_MOD(core->base, HDMI_CORE_SYS_INTR_UNMASK4, 0, 3, 3); 175 REG_FLD_MOD(core->base, HDMI_CORE_SYS_INTR_UNMASK4, 0, 3, 3);
176 hdmi_wp_clear_irqenable(core->wp, HDMI_IRQ_CORE); 176 hdmi_wp_clear_irqenable(core->wp, HDMI_IRQ_CORE);
177 hdmi_wp_set_irqstatus(core->wp, HDMI_IRQ_CORE); 177 hdmi_wp_set_irqstatus(core->wp, HDMI_IRQ_CORE);
178 hdmi4_core_disable(NULL); 178 hdmi4_core_disable(core);
179 return 0; 179 return 0;
180 } 180 }
181 err = hdmi4_core_enable(NULL); 181 err = hdmi4_core_enable(core);
182 if (err) 182 if (err)
183 return err; 183 return err;
184 184
diff --git a/drivers/gpu/drm/omapdrm/dss/hdmi4_core.h b/drivers/gpu/drm/omapdrm/dss/hdmi4_core.h
index b6ab579e44d2..337a317c1a27 100644
--- a/drivers/gpu/drm/omapdrm/dss/hdmi4_core.h
+++ b/drivers/gpu/drm/omapdrm/dss/hdmi4_core.h
@@ -266,8 +266,8 @@ void hdmi4_configure(struct hdmi_core_data *core, struct hdmi_wp_data *wp,
266void hdmi4_core_dump(struct hdmi_core_data *core, struct seq_file *s); 266void hdmi4_core_dump(struct hdmi_core_data *core, struct seq_file *s);
267int hdmi4_core_init(struct platform_device *pdev, struct hdmi_core_data *core); 267int hdmi4_core_init(struct platform_device *pdev, struct hdmi_core_data *core);
268 268
269int hdmi4_core_enable(struct omap_dss_device *dssdev); 269int hdmi4_core_enable(struct hdmi_core_data *core);
270void hdmi4_core_disable(struct omap_dss_device *dssdev); 270void hdmi4_core_disable(struct hdmi_core_data *core);
271void hdmi4_core_powerdown_disable(struct hdmi_core_data *core); 271void hdmi4_core_powerdown_disable(struct hdmi_core_data *core);
272 272
273int hdmi4_audio_start(struct hdmi_core_data *core, struct hdmi_wp_data *wp); 273int hdmi4_audio_start(struct hdmi_core_data *core, struct hdmi_wp_data *wp);
diff --git a/drivers/gpu/drm/omapdrm/dss/hdmi5.c b/drivers/gpu/drm/omapdrm/dss/hdmi5.c
index 689cda41858b..d28da9ac3e90 100644
--- a/drivers/gpu/drm/omapdrm/dss/hdmi5.c
+++ b/drivers/gpu/drm/omapdrm/dss/hdmi5.c
@@ -46,15 +46,13 @@
46#include "hdmi5_core.h" 46#include "hdmi5_core.h"
47#include "dss.h" 47#include "dss.h"
48 48
49static struct omap_hdmi hdmi; 49static int hdmi_runtime_get(struct omap_hdmi *hdmi)
50
51static int hdmi_runtime_get(void)
52{ 50{
53 int r; 51 int r;
54 52
55 DSSDBG("hdmi_runtime_get\n"); 53 DSSDBG("hdmi_runtime_get\n");
56 54
57 r = pm_runtime_get_sync(&hdmi.pdev->dev); 55 r = pm_runtime_get_sync(&hdmi->pdev->dev);
58 WARN_ON(r < 0); 56 WARN_ON(r < 0);
59 if (r < 0) 57 if (r < 0)
60 return r; 58 return r;
@@ -62,19 +60,20 @@ static int hdmi_runtime_get(void)
62 return 0; 60 return 0;
63} 61}
64 62
65static void hdmi_runtime_put(void) 63static void hdmi_runtime_put(struct omap_hdmi *hdmi)
66{ 64{
67 int r; 65 int r;
68 66
69 DSSDBG("hdmi_runtime_put\n"); 67 DSSDBG("hdmi_runtime_put\n");
70 68
71 r = pm_runtime_put_sync(&hdmi.pdev->dev); 69 r = pm_runtime_put_sync(&hdmi->pdev->dev);
72 WARN_ON(r < 0 && r != -ENOSYS); 70 WARN_ON(r < 0 && r != -ENOSYS);
73} 71}
74 72
75static irqreturn_t hdmi_irq_handler(int irq, void *data) 73static irqreturn_t hdmi_irq_handler(int irq, void *data)
76{ 74{
77 struct hdmi_wp_data *wp = data; 75 struct omap_hdmi *hdmi = data;
76 struct hdmi_wp_data *wp = &hdmi->wp;
78 u32 irqstatus; 77 u32 irqstatus;
79 78
80 irqstatus = hdmi_wp_get_irqstatus(wp); 79 irqstatus = hdmi_wp_get_irqstatus(wp);
@@ -97,17 +96,17 @@ static irqreturn_t hdmi_irq_handler(int irq, void *data)
97 * setting the PHY to LDOON. To ignore those, we force the RXDET 96 * setting the PHY to LDOON. To ignore those, we force the RXDET
98 * line to 0 until the PHY power state has been changed. 97 * line to 0 until the PHY power state has been changed.
99 */ 98 */
100 v = hdmi_read_reg(hdmi.phy.base, HDMI_TXPHY_PAD_CFG_CTRL); 99 v = hdmi_read_reg(hdmi->phy.base, HDMI_TXPHY_PAD_CFG_CTRL);
101 v = FLD_MOD(v, 1, 15, 15); /* FORCE_RXDET_HIGH */ 100 v = FLD_MOD(v, 1, 15, 15); /* FORCE_RXDET_HIGH */
102 v = FLD_MOD(v, 0, 14, 7); /* RXDET_LINE */ 101 v = FLD_MOD(v, 0, 14, 7); /* RXDET_LINE */
103 hdmi_write_reg(hdmi.phy.base, HDMI_TXPHY_PAD_CFG_CTRL, v); 102 hdmi_write_reg(hdmi->phy.base, HDMI_TXPHY_PAD_CFG_CTRL, v);
104 103
105 hdmi_wp_set_irqstatus(wp, HDMI_IRQ_LINK_CONNECT | 104 hdmi_wp_set_irqstatus(wp, HDMI_IRQ_LINK_CONNECT |
106 HDMI_IRQ_LINK_DISCONNECT); 105 HDMI_IRQ_LINK_DISCONNECT);
107 106
108 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON); 107 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON);
109 108
110 REG_FLD_MOD(hdmi.phy.base, HDMI_TXPHY_PAD_CFG_CTRL, 0, 15, 15); 109 REG_FLD_MOD(hdmi->phy.base, HDMI_TXPHY_PAD_CFG_CTRL, 0, 15, 15);
111 110
112 } else if (irqstatus & HDMI_IRQ_LINK_CONNECT) { 111 } else if (irqstatus & HDMI_IRQ_LINK_CONNECT) {
113 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_TXON); 112 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_TXON);
@@ -118,70 +117,69 @@ static irqreturn_t hdmi_irq_handler(int irq, void *data)
118 return IRQ_HANDLED; 117 return IRQ_HANDLED;
119} 118}
120 119
121static int hdmi_init_regulator(void) 120static int hdmi_init_regulator(struct omap_hdmi *hdmi)
122{ 121{
123 struct regulator *reg; 122 struct regulator *reg;
124 123
125 if (hdmi.vdda_reg != NULL) 124 if (hdmi->vdda_reg != NULL)
126 return 0; 125 return 0;
127 126
128 reg = devm_regulator_get(&hdmi.pdev->dev, "vdda"); 127 reg = devm_regulator_get(&hdmi->pdev->dev, "vdda");
129 if (IS_ERR(reg)) { 128 if (IS_ERR(reg)) {
130 DSSERR("can't get VDDA regulator\n"); 129 DSSERR("can't get VDDA regulator\n");
131 return PTR_ERR(reg); 130 return PTR_ERR(reg);
132 } 131 }
133 132
134 hdmi.vdda_reg = reg; 133 hdmi->vdda_reg = reg;
135 134
136 return 0; 135 return 0;
137} 136}
138 137
139static int hdmi_power_on_core(struct omap_dss_device *dssdev) 138static int hdmi_power_on_core(struct omap_hdmi *hdmi)
140{ 139{
141 int r; 140 int r;
142 141
143 r = regulator_enable(hdmi.vdda_reg); 142 r = regulator_enable(hdmi->vdda_reg);
144 if (r) 143 if (r)
145 return r; 144 return r;
146 145
147 r = hdmi_runtime_get(); 146 r = hdmi_runtime_get(hdmi);
148 if (r) 147 if (r)
149 goto err_runtime_get; 148 goto err_runtime_get;
150 149
151 /* Make selection of HDMI in DSS */ 150 /* Make selection of HDMI in DSS */
152 dss_select_hdmi_venc_clk_source(DSS_HDMI_M_PCLK); 151 dss_select_hdmi_venc_clk_source(hdmi->dss, DSS_HDMI_M_PCLK);
153 152
154 hdmi.core_enabled = true; 153 hdmi->core_enabled = true;
155 154
156 return 0; 155 return 0;
157 156
158err_runtime_get: 157err_runtime_get:
159 regulator_disable(hdmi.vdda_reg); 158 regulator_disable(hdmi->vdda_reg);
160 159
161 return r; 160 return r;
162} 161}
163 162
164static void hdmi_power_off_core(struct omap_dss_device *dssdev) 163static void hdmi_power_off_core(struct omap_hdmi *hdmi)
165{ 164{
166 hdmi.core_enabled = false; 165 hdmi->core_enabled = false;
167 166
168 hdmi_runtime_put(); 167 hdmi_runtime_put(hdmi);
169 regulator_disable(hdmi.vdda_reg); 168 regulator_disable(hdmi->vdda_reg);
170} 169}
171 170
172static int hdmi_power_on_full(struct omap_dss_device *dssdev) 171static int hdmi_power_on_full(struct omap_hdmi *hdmi)
173{ 172{
174 int r; 173 int r;
175 struct videomode *vm; 174 struct videomode *vm;
176 enum omap_channel channel = dssdev->dispc_channel;
177 struct dss_pll_clock_info hdmi_cinfo = { 0 }; 175 struct dss_pll_clock_info hdmi_cinfo = { 0 };
178 unsigned pc; 176 unsigned int pc;
179 177
180 r = hdmi_power_on_core(dssdev); 178 r = hdmi_power_on_core(hdmi);
181 if (r) 179 if (r)
182 return r; 180 return r;
183 181
184 vm = &hdmi.cfg.vm; 182 vm = &hdmi->cfg.vm;
185 183
186 DSSDBG("hdmi_power_on hactive= %d vactive = %d\n", vm->hactive, 184 DSSDBG("hdmi_power_on hactive= %d vactive = %d\n", vm->hactive,
187 vm->vactive); 185 vm->vactive);
@@ -193,89 +191,89 @@ static int hdmi_power_on_full(struct omap_dss_device *dssdev)
193 /* DSS_HDMI_TCLK is bitclk / 10 */ 191 /* DSS_HDMI_TCLK is bitclk / 10 */
194 pc *= 10; 192 pc *= 10;
195 193
196 dss_pll_calc_b(&hdmi.pll.pll, clk_get_rate(hdmi.pll.pll.clkin), 194 dss_pll_calc_b(&hdmi->pll.pll, clk_get_rate(hdmi->pll.pll.clkin),
197 pc, &hdmi_cinfo); 195 pc, &hdmi_cinfo);
198 196
199 /* disable and clear irqs */ 197 /* disable and clear irqs */
200 hdmi_wp_clear_irqenable(&hdmi.wp, 0xffffffff); 198 hdmi_wp_clear_irqenable(&hdmi->wp, 0xffffffff);
201 hdmi_wp_set_irqstatus(&hdmi.wp, 199 hdmi_wp_set_irqstatus(&hdmi->wp,
202 hdmi_wp_get_irqstatus(&hdmi.wp)); 200 hdmi_wp_get_irqstatus(&hdmi->wp));
203 201
204 r = dss_pll_enable(&hdmi.pll.pll); 202 r = dss_pll_enable(&hdmi->pll.pll);
205 if (r) { 203 if (r) {
206 DSSERR("Failed to enable PLL\n"); 204 DSSERR("Failed to enable PLL\n");
207 goto err_pll_enable; 205 goto err_pll_enable;
208 } 206 }
209 207
210 r = dss_pll_set_config(&hdmi.pll.pll, &hdmi_cinfo); 208 r = dss_pll_set_config(&hdmi->pll.pll, &hdmi_cinfo);
211 if (r) { 209 if (r) {
212 DSSERR("Failed to configure PLL\n"); 210 DSSERR("Failed to configure PLL\n");
213 goto err_pll_cfg; 211 goto err_pll_cfg;
214 } 212 }
215 213
216 r = hdmi_phy_configure(&hdmi.phy, hdmi_cinfo.clkdco, 214 r = hdmi_phy_configure(&hdmi->phy, hdmi_cinfo.clkdco,
217 hdmi_cinfo.clkout[0]); 215 hdmi_cinfo.clkout[0]);
218 if (r) { 216 if (r) {
219 DSSDBG("Failed to start PHY\n"); 217 DSSDBG("Failed to start PHY\n");
220 goto err_phy_cfg; 218 goto err_phy_cfg;
221 } 219 }
222 220
223 r = hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_LDOON); 221 r = hdmi_wp_set_phy_pwr(&hdmi->wp, HDMI_PHYPWRCMD_LDOON);
224 if (r) 222 if (r)
225 goto err_phy_pwr; 223 goto err_phy_pwr;
226 224
227 hdmi5_configure(&hdmi.core, &hdmi.wp, &hdmi.cfg); 225 hdmi5_configure(&hdmi->core, &hdmi->wp, &hdmi->cfg);
228 226
229 /* tv size */ 227 /* tv size */
230 dss_mgr_set_timings(channel, vm); 228 dss_mgr_set_timings(&hdmi->output, vm);
231 229
232 r = dss_mgr_enable(channel); 230 r = dss_mgr_enable(&hdmi->output);
233 if (r) 231 if (r)
234 goto err_mgr_enable; 232 goto err_mgr_enable;
235 233
236 r = hdmi_wp_video_start(&hdmi.wp); 234 r = hdmi_wp_video_start(&hdmi->wp);
237 if (r) 235 if (r)
238 goto err_vid_enable; 236 goto err_vid_enable;
239 237
240 hdmi_wp_set_irqenable(&hdmi.wp, 238 hdmi_wp_set_irqenable(&hdmi->wp,
241 HDMI_IRQ_LINK_CONNECT | HDMI_IRQ_LINK_DISCONNECT); 239 HDMI_IRQ_LINK_CONNECT | HDMI_IRQ_LINK_DISCONNECT);
242 240
243 return 0; 241 return 0;
244 242
245err_vid_enable: 243err_vid_enable:
246 dss_mgr_disable(channel); 244 dss_mgr_disable(&hdmi->output);
247err_mgr_enable: 245err_mgr_enable:
248 hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_OFF); 246 hdmi_wp_set_phy_pwr(&hdmi->wp, HDMI_PHYPWRCMD_OFF);
249err_phy_pwr: 247err_phy_pwr:
250err_phy_cfg: 248err_phy_cfg:
251err_pll_cfg: 249err_pll_cfg:
252 dss_pll_disable(&hdmi.pll.pll); 250 dss_pll_disable(&hdmi->pll.pll);
253err_pll_enable: 251err_pll_enable:
254 hdmi_power_off_core(dssdev); 252 hdmi_power_off_core(hdmi);
255 return -EIO; 253 return -EIO;
256} 254}
257 255
258static void hdmi_power_off_full(struct omap_dss_device *dssdev) 256static void hdmi_power_off_full(struct omap_hdmi *hdmi)
259{ 257{
260 enum omap_channel channel = dssdev->dispc_channel; 258 hdmi_wp_clear_irqenable(&hdmi->wp, 0xffffffff);
261
262 hdmi_wp_clear_irqenable(&hdmi.wp, 0xffffffff);
263 259
264 hdmi_wp_video_stop(&hdmi.wp); 260 hdmi_wp_video_stop(&hdmi->wp);
265 261
266 dss_mgr_disable(channel); 262 dss_mgr_disable(&hdmi->output);
267 263
268 hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_OFF); 264 hdmi_wp_set_phy_pwr(&hdmi->wp, HDMI_PHYPWRCMD_OFF);
269 265
270 dss_pll_disable(&hdmi.pll.pll); 266 dss_pll_disable(&hdmi->pll.pll);
271 267
272 hdmi_power_off_core(dssdev); 268 hdmi_power_off_core(hdmi);
273} 269}
274 270
275static int hdmi_display_check_timing(struct omap_dss_device *dssdev, 271static int hdmi_display_check_timing(struct omap_dss_device *dssdev,
276 struct videomode *vm) 272 struct videomode *vm)
277{ 273{
278 if (!dispc_mgr_timings_ok(dssdev->dispc_channel, vm)) 274 struct omap_hdmi *hdmi = dssdev_to_hdmi(dssdev);
275
276 if (!dispc_mgr_timings_ok(hdmi->dss->dispc, dssdev->dispc_channel, vm))
279 return -EINVAL; 277 return -EINVAL;
280 278
281 return 0; 279 return 0;
@@ -284,66 +282,73 @@ static int hdmi_display_check_timing(struct omap_dss_device *dssdev,
284static void hdmi_display_set_timing(struct omap_dss_device *dssdev, 282static void hdmi_display_set_timing(struct omap_dss_device *dssdev,
285 struct videomode *vm) 283 struct videomode *vm)
286{ 284{
287 mutex_lock(&hdmi.lock); 285 struct omap_hdmi *hdmi = dssdev_to_hdmi(dssdev);
288 286
289 hdmi.cfg.vm = *vm; 287 mutex_lock(&hdmi->lock);
290 288
291 dispc_set_tv_pclk(vm->pixelclock); 289 hdmi->cfg.vm = *vm;
292 290
293 mutex_unlock(&hdmi.lock); 291 dispc_set_tv_pclk(hdmi->dss->dispc, vm->pixelclock);
292
293 mutex_unlock(&hdmi->lock);
294} 294}
295 295
296static void hdmi_display_get_timings(struct omap_dss_device *dssdev, 296static void hdmi_display_get_timings(struct omap_dss_device *dssdev,
297 struct videomode *vm) 297 struct videomode *vm)
298{ 298{
299 *vm = hdmi.cfg.vm; 299 struct omap_hdmi *hdmi = dssdev_to_hdmi(dssdev);
300
301 *vm = hdmi->cfg.vm;
300} 302}
301 303
302static void hdmi_dump_regs(struct seq_file *s) 304static int hdmi_dump_regs(struct seq_file *s, void *p)
303{ 305{
304 mutex_lock(&hdmi.lock); 306 struct omap_hdmi *hdmi = s->private;
305 307
306 if (hdmi_runtime_get()) { 308 mutex_lock(&hdmi->lock);
307 mutex_unlock(&hdmi.lock); 309
308 return; 310 if (hdmi_runtime_get(hdmi)) {
311 mutex_unlock(&hdmi->lock);
312 return 0;
309 } 313 }
310 314
311 hdmi_wp_dump(&hdmi.wp, s); 315 hdmi_wp_dump(&hdmi->wp, s);
312 hdmi_pll_dump(&hdmi.pll, s); 316 hdmi_pll_dump(&hdmi->pll, s);
313 hdmi_phy_dump(&hdmi.phy, s); 317 hdmi_phy_dump(&hdmi->phy, s);
314 hdmi5_core_dump(&hdmi.core, s); 318 hdmi5_core_dump(&hdmi->core, s);
315 319
316 hdmi_runtime_put(); 320 hdmi_runtime_put(hdmi);
317 mutex_unlock(&hdmi.lock); 321 mutex_unlock(&hdmi->lock);
322 return 0;
318} 323}
319 324
320static int read_edid(u8 *buf, int len) 325static int read_edid(struct omap_hdmi *hdmi, u8 *buf, int len)
321{ 326{
322 int r; 327 int r;
323 int idlemode; 328 int idlemode;
324 329
325 mutex_lock(&hdmi.lock); 330 mutex_lock(&hdmi->lock);
326 331
327 r = hdmi_runtime_get(); 332 r = hdmi_runtime_get(hdmi);
328 BUG_ON(r); 333 BUG_ON(r);
329 334
330 idlemode = REG_GET(hdmi.wp.base, HDMI_WP_SYSCONFIG, 3, 2); 335 idlemode = REG_GET(hdmi->wp.base, HDMI_WP_SYSCONFIG, 3, 2);
331 /* No-idle mode */ 336 /* No-idle mode */
332 REG_FLD_MOD(hdmi.wp.base, HDMI_WP_SYSCONFIG, 1, 3, 2); 337 REG_FLD_MOD(hdmi->wp.base, HDMI_WP_SYSCONFIG, 1, 3, 2);
333 338
334 r = hdmi5_read_edid(&hdmi.core, buf, len); 339 r = hdmi5_read_edid(&hdmi->core, buf, len);
335 340
336 REG_FLD_MOD(hdmi.wp.base, HDMI_WP_SYSCONFIG, idlemode, 3, 2); 341 REG_FLD_MOD(hdmi->wp.base, HDMI_WP_SYSCONFIG, idlemode, 3, 2);
337 342
338 hdmi_runtime_put(); 343 hdmi_runtime_put(hdmi);
339 mutex_unlock(&hdmi.lock); 344 mutex_unlock(&hdmi->lock);
340 345
341 return r; 346 return r;
342} 347}
343 348
344static void hdmi_start_audio_stream(struct omap_hdmi *hd) 349static void hdmi_start_audio_stream(struct omap_hdmi *hd)
345{ 350{
346 REG_FLD_MOD(hdmi.wp.base, HDMI_WP_SYSCONFIG, 1, 3, 2); 351 REG_FLD_MOD(hd->wp.base, HDMI_WP_SYSCONFIG, 1, 3, 2);
347 hdmi_wp_audio_enable(&hd->wp, true); 352 hdmi_wp_audio_enable(&hd->wp, true);
348 hdmi_wp_audio_core_req_enable(&hd->wp, true); 353 hdmi_wp_audio_core_req_enable(&hd->wp, true);
349} 354}
@@ -357,112 +362,114 @@ static void hdmi_stop_audio_stream(struct omap_hdmi *hd)
357 362
358static int hdmi_display_enable(struct omap_dss_device *dssdev) 363static int hdmi_display_enable(struct omap_dss_device *dssdev)
359{ 364{
360 struct omap_dss_device *out = &hdmi.output; 365 struct omap_hdmi *hdmi = dssdev_to_hdmi(dssdev);
361 unsigned long flags; 366 unsigned long flags;
362 int r = 0; 367 int r = 0;
363 368
364 DSSDBG("ENTER hdmi_display_enable\n"); 369 DSSDBG("ENTER hdmi_display_enable\n");
365 370
366 mutex_lock(&hdmi.lock); 371 mutex_lock(&hdmi->lock);
367 372
368 if (!out->dispc_channel_connected) { 373 if (!dssdev->dispc_channel_connected) {
369 DSSERR("failed to enable display: no output/manager\n"); 374 DSSERR("failed to enable display: no output/manager\n");
370 r = -ENODEV; 375 r = -ENODEV;
371 goto err0; 376 goto err0;
372 } 377 }
373 378
374 r = hdmi_power_on_full(dssdev); 379 r = hdmi_power_on_full(hdmi);
375 if (r) { 380 if (r) {
376 DSSERR("failed to power on device\n"); 381 DSSERR("failed to power on device\n");
377 goto err0; 382 goto err0;
378 } 383 }
379 384
380 if (hdmi.audio_configured) { 385 if (hdmi->audio_configured) {
381 r = hdmi5_audio_config(&hdmi.core, &hdmi.wp, &hdmi.audio_config, 386 r = hdmi5_audio_config(&hdmi->core, &hdmi->wp,
382 hdmi.cfg.vm.pixelclock); 387 &hdmi->audio_config,
388 hdmi->cfg.vm.pixelclock);
383 if (r) { 389 if (r) {
384 DSSERR("Error restoring audio configuration: %d", r); 390 DSSERR("Error restoring audio configuration: %d", r);
385 hdmi.audio_abort_cb(&hdmi.pdev->dev); 391 hdmi->audio_abort_cb(&hdmi->pdev->dev);
386 hdmi.audio_configured = false; 392 hdmi->audio_configured = false;
387 } 393 }
388 } 394 }
389 395
390 spin_lock_irqsave(&hdmi.audio_playing_lock, flags); 396 spin_lock_irqsave(&hdmi->audio_playing_lock, flags);
391 if (hdmi.audio_configured && hdmi.audio_playing) 397 if (hdmi->audio_configured && hdmi->audio_playing)
392 hdmi_start_audio_stream(&hdmi); 398 hdmi_start_audio_stream(hdmi);
393 hdmi.display_enabled = true; 399 hdmi->display_enabled = true;
394 spin_unlock_irqrestore(&hdmi.audio_playing_lock, flags); 400 spin_unlock_irqrestore(&hdmi->audio_playing_lock, flags);
395 401
396 mutex_unlock(&hdmi.lock); 402 mutex_unlock(&hdmi->lock);
397 return 0; 403 return 0;
398 404
399err0: 405err0:
400 mutex_unlock(&hdmi.lock); 406 mutex_unlock(&hdmi->lock);
401 return r; 407 return r;
402} 408}
403 409
404static void hdmi_display_disable(struct omap_dss_device *dssdev) 410static void hdmi_display_disable(struct omap_dss_device *dssdev)
405{ 411{
412 struct omap_hdmi *hdmi = dssdev_to_hdmi(dssdev);
406 unsigned long flags; 413 unsigned long flags;
407 414
408 DSSDBG("Enter hdmi_display_disable\n"); 415 DSSDBG("Enter hdmi_display_disable\n");
409 416
410 mutex_lock(&hdmi.lock); 417 mutex_lock(&hdmi->lock);
411 418
412 spin_lock_irqsave(&hdmi.audio_playing_lock, flags); 419 spin_lock_irqsave(&hdmi->audio_playing_lock, flags);
413 hdmi_stop_audio_stream(&hdmi); 420 hdmi_stop_audio_stream(hdmi);
414 hdmi.display_enabled = false; 421 hdmi->display_enabled = false;
415 spin_unlock_irqrestore(&hdmi.audio_playing_lock, flags); 422 spin_unlock_irqrestore(&hdmi->audio_playing_lock, flags);
416 423
417 hdmi_power_off_full(dssdev); 424 hdmi_power_off_full(hdmi);
418 425
419 mutex_unlock(&hdmi.lock); 426 mutex_unlock(&hdmi->lock);
420} 427}
421 428
422static int hdmi_core_enable(struct omap_dss_device *dssdev) 429static int hdmi_core_enable(struct omap_hdmi *hdmi)
423{ 430{
424 int r = 0; 431 int r = 0;
425 432
426 DSSDBG("ENTER omapdss_hdmi_core_enable\n"); 433 DSSDBG("ENTER omapdss_hdmi_core_enable\n");
427 434
428 mutex_lock(&hdmi.lock); 435 mutex_lock(&hdmi->lock);
429 436
430 r = hdmi_power_on_core(dssdev); 437 r = hdmi_power_on_core(hdmi);
431 if (r) { 438 if (r) {
432 DSSERR("failed to power on device\n"); 439 DSSERR("failed to power on device\n");
433 goto err0; 440 goto err0;
434 } 441 }
435 442
436 mutex_unlock(&hdmi.lock); 443 mutex_unlock(&hdmi->lock);
437 return 0; 444 return 0;
438 445
439err0: 446err0:
440 mutex_unlock(&hdmi.lock); 447 mutex_unlock(&hdmi->lock);
441 return r; 448 return r;
442} 449}
443 450
444static void hdmi_core_disable(struct omap_dss_device *dssdev) 451static void hdmi_core_disable(struct omap_hdmi *hdmi)
445{ 452{
446 DSSDBG("Enter omapdss_hdmi_core_disable\n"); 453 DSSDBG("Enter omapdss_hdmi_core_disable\n");
447 454
448 mutex_lock(&hdmi.lock); 455 mutex_lock(&hdmi->lock);
449 456
450 hdmi_power_off_core(dssdev); 457 hdmi_power_off_core(hdmi);
451 458
452 mutex_unlock(&hdmi.lock); 459 mutex_unlock(&hdmi->lock);
453} 460}
454 461
455static int hdmi_connect(struct omap_dss_device *dssdev, 462static int hdmi_connect(struct omap_dss_device *dssdev,
456 struct omap_dss_device *dst) 463 struct omap_dss_device *dst)
457{ 464{
458 enum omap_channel channel = dssdev->dispc_channel; 465 struct omap_hdmi *hdmi = dssdev_to_hdmi(dssdev);
459 int r; 466 int r;
460 467
461 r = hdmi_init_regulator(); 468 r = hdmi_init_regulator(hdmi);
462 if (r) 469 if (r)
463 return r; 470 return r;
464 471
465 r = dss_mgr_connect(channel, dssdev); 472 r = dss_mgr_connect(&hdmi->output, dssdev);
466 if (r) 473 if (r)
467 return r; 474 return r;
468 475
@@ -470,7 +477,7 @@ static int hdmi_connect(struct omap_dss_device *dssdev,
470 if (r) { 477 if (r) {
471 DSSERR("failed to connect output to new device: %s\n", 478 DSSERR("failed to connect output to new device: %s\n",
472 dst->name); 479 dst->name);
473 dss_mgr_disconnect(channel, dssdev); 480 dss_mgr_disconnect(&hdmi->output, dssdev);
474 return r; 481 return r;
475 } 482 }
476 483
@@ -480,7 +487,7 @@ static int hdmi_connect(struct omap_dss_device *dssdev,
480static void hdmi_disconnect(struct omap_dss_device *dssdev, 487static void hdmi_disconnect(struct omap_dss_device *dssdev,
481 struct omap_dss_device *dst) 488 struct omap_dss_device *dst)
482{ 489{
483 enum omap_channel channel = dssdev->dispc_channel; 490 struct omap_hdmi *hdmi = dssdev_to_hdmi(dssdev);
484 491
485 WARN_ON(dst != dssdev->dst); 492 WARN_ON(dst != dssdev->dst);
486 493
@@ -489,27 +496,28 @@ static void hdmi_disconnect(struct omap_dss_device *dssdev,
489 496
490 omapdss_output_unset_device(dssdev); 497 omapdss_output_unset_device(dssdev);
491 498
492 dss_mgr_disconnect(channel, dssdev); 499 dss_mgr_disconnect(&hdmi->output, dssdev);
493} 500}
494 501
495static int hdmi_read_edid(struct omap_dss_device *dssdev, 502static int hdmi_read_edid(struct omap_dss_device *dssdev,
496 u8 *edid, int len) 503 u8 *edid, int len)
497{ 504{
505 struct omap_hdmi *hdmi = dssdev_to_hdmi(dssdev);
498 bool need_enable; 506 bool need_enable;
499 int r; 507 int r;
500 508
501 need_enable = hdmi.core_enabled == false; 509 need_enable = hdmi->core_enabled == false;
502 510
503 if (need_enable) { 511 if (need_enable) {
504 r = hdmi_core_enable(dssdev); 512 r = hdmi_core_enable(hdmi);
505 if (r) 513 if (r)
506 return r; 514 return r;
507 } 515 }
508 516
509 r = read_edid(edid, len); 517 r = read_edid(hdmi, edid, len);
510 518
511 if (need_enable) 519 if (need_enable)
512 hdmi_core_disable(dssdev); 520 hdmi_core_disable(hdmi);
513 521
514 return r; 522 return r;
515} 523}
@@ -517,14 +525,18 @@ static int hdmi_read_edid(struct omap_dss_device *dssdev,
517static int hdmi_set_infoframe(struct omap_dss_device *dssdev, 525static int hdmi_set_infoframe(struct omap_dss_device *dssdev,
518 const struct hdmi_avi_infoframe *avi) 526 const struct hdmi_avi_infoframe *avi)
519{ 527{
520 hdmi.cfg.infoframe = *avi; 528 struct omap_hdmi *hdmi = dssdev_to_hdmi(dssdev);
529
530 hdmi->cfg.infoframe = *avi;
521 return 0; 531 return 0;
522} 532}
523 533
524static int hdmi_set_hdmi_mode(struct omap_dss_device *dssdev, 534static int hdmi_set_hdmi_mode(struct omap_dss_device *dssdev,
525 bool hdmi_mode) 535 bool hdmi_mode)
526{ 536{
527 hdmi.cfg.hdmi_dvi_mode = hdmi_mode ? HDMI_HDMI : HDMI_DVI; 537 struct omap_hdmi *hdmi = dssdev_to_hdmi(dssdev);
538
539 hdmi->cfg.hdmi_dvi_mode = hdmi_mode ? HDMI_HDMI : HDMI_DVI;
528 return 0; 540 return 0;
529} 541}
530 542
@@ -544,11 +556,11 @@ static const struct omapdss_hdmi_ops hdmi_ops = {
544 .set_hdmi_mode = hdmi_set_hdmi_mode, 556 .set_hdmi_mode = hdmi_set_hdmi_mode,
545}; 557};
546 558
547static void hdmi_init_output(struct platform_device *pdev) 559static void hdmi_init_output(struct omap_hdmi *hdmi)
548{ 560{
549 struct omap_dss_device *out = &hdmi.output; 561 struct omap_dss_device *out = &hdmi->output;
550 562
551 out->dev = &pdev->dev; 563 out->dev = &hdmi->pdev->dev;
552 out->id = OMAP_DSS_OUTPUT_HDMI; 564 out->id = OMAP_DSS_OUTPUT_HDMI;
553 out->output_type = OMAP_DISPLAY_TYPE_HDMI; 565 out->output_type = OMAP_DISPLAY_TYPE_HDMI;
554 out->name = "hdmi.0"; 566 out->name = "hdmi.0";
@@ -559,15 +571,16 @@ static void hdmi_init_output(struct platform_device *pdev)
559 omapdss_register_output(out); 571 omapdss_register_output(out);
560} 572}
561 573
562static void hdmi_uninit_output(struct platform_device *pdev) 574static void hdmi_uninit_output(struct omap_hdmi *hdmi)
563{ 575{
564 struct omap_dss_device *out = &hdmi.output; 576 struct omap_dss_device *out = &hdmi->output;
565 577
566 omapdss_unregister_output(out); 578 omapdss_unregister_output(out);
567} 579}
568 580
569static int hdmi_probe_of(struct platform_device *pdev) 581static int hdmi_probe_of(struct omap_hdmi *hdmi)
570{ 582{
583 struct platform_device *pdev = hdmi->pdev;
571 struct device_node *node = pdev->dev.of_node; 584 struct device_node *node = pdev->dev.of_node;
572 struct device_node *ep; 585 struct device_node *ep;
573 int r; 586 int r;
@@ -576,7 +589,7 @@ static int hdmi_probe_of(struct platform_device *pdev)
576 if (!ep) 589 if (!ep)
577 return 0; 590 return 0;
578 591
579 r = hdmi_parse_lanes_of(pdev, ep, &hdmi.phy); 592 r = hdmi_parse_lanes_of(pdev, ep, &hdmi->phy);
580 if (r) 593 if (r)
581 goto err; 594 goto err;
582 595
@@ -593,21 +606,16 @@ static int hdmi_audio_startup(struct device *dev,
593 void (*abort_cb)(struct device *dev)) 606 void (*abort_cb)(struct device *dev))
594{ 607{
595 struct omap_hdmi *hd = dev_get_drvdata(dev); 608 struct omap_hdmi *hd = dev_get_drvdata(dev);
596 int ret = 0;
597 609
598 mutex_lock(&hd->lock); 610 mutex_lock(&hd->lock);
599 611
600 if (!hdmi_mode_has_audio(&hd->cfg) || !hd->display_enabled) { 612 WARN_ON(hd->audio_abort_cb != NULL);
601 ret = -EPERM;
602 goto out;
603 }
604 613
605 hd->audio_abort_cb = abort_cb; 614 hd->audio_abort_cb = abort_cb;
606 615
607out:
608 mutex_unlock(&hd->lock); 616 mutex_unlock(&hd->lock);
609 617
610 return ret; 618 return 0;
611} 619}
612 620
613static int hdmi_audio_shutdown(struct device *dev) 621static int hdmi_audio_shutdown(struct device *dev)
@@ -628,12 +636,14 @@ static int hdmi_audio_start(struct device *dev)
628 struct omap_hdmi *hd = dev_get_drvdata(dev); 636 struct omap_hdmi *hd = dev_get_drvdata(dev);
629 unsigned long flags; 637 unsigned long flags;
630 638
631 WARN_ON(!hdmi_mode_has_audio(&hd->cfg));
632
633 spin_lock_irqsave(&hd->audio_playing_lock, flags); 639 spin_lock_irqsave(&hd->audio_playing_lock, flags);
634 640
635 if (hd->display_enabled) 641 if (hd->display_enabled) {
642 if (!hdmi_mode_has_audio(&hd->cfg))
643 DSSERR("%s: Video mode does not support audio\n",
644 __func__);
636 hdmi_start_audio_stream(hd); 645 hdmi_start_audio_stream(hd);
646 }
637 hd->audio_playing = true; 647 hd->audio_playing = true;
638 648
639 spin_unlock_irqrestore(&hd->audio_playing_lock, flags); 649 spin_unlock_irqrestore(&hd->audio_playing_lock, flags);
@@ -645,7 +655,8 @@ static void hdmi_audio_stop(struct device *dev)
645 struct omap_hdmi *hd = dev_get_drvdata(dev); 655 struct omap_hdmi *hd = dev_get_drvdata(dev);
646 unsigned long flags; 656 unsigned long flags;
647 657
648 WARN_ON(!hdmi_mode_has_audio(&hd->cfg)); 658 if (!hdmi_mode_has_audio(&hd->cfg))
659 DSSERR("%s: Video mode does not support audio\n", __func__);
649 660
650 spin_lock_irqsave(&hd->audio_playing_lock, flags); 661 spin_lock_irqsave(&hd->audio_playing_lock, flags);
651 662
@@ -664,18 +675,15 @@ static int hdmi_audio_config(struct device *dev,
664 675
665 mutex_lock(&hd->lock); 676 mutex_lock(&hd->lock);
666 677
667 if (!hdmi_mode_has_audio(&hd->cfg) || !hd->display_enabled) { 678 if (hd->display_enabled) {
668 ret = -EPERM; 679 ret = hdmi5_audio_config(&hd->core, &hd->wp, dss_audio,
669 goto out; 680 hd->cfg.vm.pixelclock);
681 if (ret)
682 goto out;
670 } 683 }
671 684
672 ret = hdmi5_audio_config(&hd->core, &hd->wp, dss_audio, 685 hd->audio_configured = true;
673 hd->cfg.vm.pixelclock); 686 hd->audio_config = *dss_audio;
674
675 if (!ret) {
676 hd->audio_configured = true;
677 hd->audio_config = *dss_audio;
678 }
679out: 687out:
680 mutex_unlock(&hd->lock); 688 mutex_unlock(&hd->lock);
681 689
@@ -690,26 +698,26 @@ static const struct omap_hdmi_audio_ops hdmi_audio_ops = {
690 .audio_config = hdmi_audio_config, 698 .audio_config = hdmi_audio_config,
691}; 699};
692 700
693static int hdmi_audio_register(struct device *dev) 701static int hdmi_audio_register(struct omap_hdmi *hdmi)
694{ 702{
695 struct omap_hdmi_audio_pdata pdata = { 703 struct omap_hdmi_audio_pdata pdata = {
696 .dev = dev, 704 .dev = &hdmi->pdev->dev,
697 .version = 5, 705 .version = 5,
698 .audio_dma_addr = hdmi_wp_get_audio_dma_addr(&hdmi.wp), 706 .audio_dma_addr = hdmi_wp_get_audio_dma_addr(&hdmi->wp),
699 .ops = &hdmi_audio_ops, 707 .ops = &hdmi_audio_ops,
700 }; 708 };
701 709
702 hdmi.audio_pdev = platform_device_register_data( 710 hdmi->audio_pdev = platform_device_register_data(
703 dev, "omap-hdmi-audio", PLATFORM_DEVID_AUTO, 711 &hdmi->pdev->dev, "omap-hdmi-audio", PLATFORM_DEVID_AUTO,
704 &pdata, sizeof(pdata)); 712 &pdata, sizeof(pdata));
705 713
706 if (IS_ERR(hdmi.audio_pdev)) 714 if (IS_ERR(hdmi->audio_pdev))
707 return PTR_ERR(hdmi.audio_pdev); 715 return PTR_ERR(hdmi->audio_pdev);
708 716
709 hdmi_runtime_get(); 717 hdmi_runtime_get(hdmi);
710 hdmi.wp_idlemode = 718 hdmi->wp_idlemode =
711 REG_GET(hdmi.wp.base, HDMI_WP_SYSCONFIG, 3, 2); 719 REG_GET(hdmi->wp.base, HDMI_WP_SYSCONFIG, 3, 2);
712 hdmi_runtime_put(); 720 hdmi_runtime_put(hdmi);
713 721
714 return 0; 722 return 0;
715} 723}
@@ -718,82 +726,97 @@ static int hdmi_audio_register(struct device *dev)
718static int hdmi5_bind(struct device *dev, struct device *master, void *data) 726static int hdmi5_bind(struct device *dev, struct device *master, void *data)
719{ 727{
720 struct platform_device *pdev = to_platform_device(dev); 728 struct platform_device *pdev = to_platform_device(dev);
729 struct dss_device *dss = dss_get_device(master);
730 struct omap_hdmi *hdmi;
721 int r; 731 int r;
722 int irq; 732 int irq;
723 733
724 hdmi.pdev = pdev; 734 hdmi = kzalloc(sizeof(*hdmi), GFP_KERNEL);
725 dev_set_drvdata(&pdev->dev, &hdmi); 735 if (!hdmi)
736 return -ENOMEM;
726 737
727 mutex_init(&hdmi.lock); 738 hdmi->pdev = pdev;
728 spin_lock_init(&hdmi.audio_playing_lock); 739 hdmi->dss = dss;
740 dev_set_drvdata(&pdev->dev, hdmi);
729 741
730 r = hdmi_probe_of(pdev); 742 mutex_init(&hdmi->lock);
743 spin_lock_init(&hdmi->audio_playing_lock);
744
745 r = hdmi_probe_of(hdmi);
731 if (r) 746 if (r)
732 return r; 747 goto err_free;
733 748
734 r = hdmi_wp_init(pdev, &hdmi.wp, 5); 749 r = hdmi_wp_init(pdev, &hdmi->wp, 5);
735 if (r) 750 if (r)
736 return r; 751 goto err_free;
737 752
738 r = hdmi_pll_init(pdev, &hdmi.pll, &hdmi.wp); 753 r = hdmi_pll_init(dss, pdev, &hdmi->pll, &hdmi->wp);
739 if (r) 754 if (r)
740 return r; 755 goto err_free;
741 756
742 r = hdmi_phy_init(pdev, &hdmi.phy, 5); 757 r = hdmi_phy_init(pdev, &hdmi->phy, 5);
743 if (r) 758 if (r)
744 goto err; 759 goto err_pll;
745 760
746 r = hdmi5_core_init(pdev, &hdmi.core); 761 r = hdmi5_core_init(pdev, &hdmi->core);
747 if (r) 762 if (r)
748 goto err; 763 goto err_pll;
749 764
750 irq = platform_get_irq(pdev, 0); 765 irq = platform_get_irq(pdev, 0);
751 if (irq < 0) { 766 if (irq < 0) {
752 DSSERR("platform_get_irq failed\n"); 767 DSSERR("platform_get_irq failed\n");
753 r = -ENODEV; 768 r = -ENODEV;
754 goto err; 769 goto err_pll;
755 } 770 }
756 771
757 r = devm_request_threaded_irq(&pdev->dev, irq, 772 r = devm_request_threaded_irq(&pdev->dev, irq,
758 NULL, hdmi_irq_handler, 773 NULL, hdmi_irq_handler,
759 IRQF_ONESHOT, "OMAP HDMI", &hdmi.wp); 774 IRQF_ONESHOT, "OMAP HDMI", hdmi);
760 if (r) { 775 if (r) {
761 DSSERR("HDMI IRQ request failed\n"); 776 DSSERR("HDMI IRQ request failed\n");
762 goto err; 777 goto err_pll;
763 } 778 }
764 779
765 pm_runtime_enable(&pdev->dev); 780 pm_runtime_enable(&pdev->dev);
766 781
767 hdmi_init_output(pdev); 782 hdmi_init_output(hdmi);
768 783
769 r = hdmi_audio_register(&pdev->dev); 784 r = hdmi_audio_register(hdmi);
770 if (r) { 785 if (r) {
771 DSSERR("Registering HDMI audio failed %d\n", r); 786 DSSERR("Registering HDMI audio failed %d\n", r);
772 hdmi_uninit_output(pdev); 787 hdmi_uninit_output(hdmi);
773 pm_runtime_disable(&pdev->dev); 788 pm_runtime_disable(&pdev->dev);
774 return r; 789 return r;
775 } 790 }
776 791
777 dss_debugfs_create_file("hdmi", hdmi_dump_regs); 792 hdmi->debugfs = dss_debugfs_create_file(dss, "hdmi", hdmi_dump_regs,
793 hdmi);
778 794
779 return 0; 795 return 0;
780err: 796
781 hdmi_pll_uninit(&hdmi.pll); 797err_pll:
798 hdmi_pll_uninit(&hdmi->pll);
799err_free:
800 kfree(hdmi);
782 return r; 801 return r;
783} 802}
784 803
785static void hdmi5_unbind(struct device *dev, struct device *master, void *data) 804static void hdmi5_unbind(struct device *dev, struct device *master, void *data)
786{ 805{
787 struct platform_device *pdev = to_platform_device(dev); 806 struct omap_hdmi *hdmi = dev_get_drvdata(dev);
807
808 dss_debugfs_remove_file(hdmi->debugfs);
788 809
789 if (hdmi.audio_pdev) 810 if (hdmi->audio_pdev)
790 platform_device_unregister(hdmi.audio_pdev); 811 platform_device_unregister(hdmi->audio_pdev);
791 812
792 hdmi_uninit_output(pdev); 813 hdmi_uninit_output(hdmi);
793 814
794 hdmi_pll_uninit(&hdmi.pll); 815 hdmi_pll_uninit(&hdmi->pll);
795 816
796 pm_runtime_disable(&pdev->dev); 817 pm_runtime_disable(dev);
818
819 kfree(hdmi);
797} 820}
798 821
799static const struct component_ops hdmi5_component_ops = { 822static const struct component_ops hdmi5_component_ops = {
@@ -814,16 +837,19 @@ static int hdmi5_remove(struct platform_device *pdev)
814 837
815static int hdmi_runtime_suspend(struct device *dev) 838static int hdmi_runtime_suspend(struct device *dev)
816{ 839{
817 dispc_runtime_put(); 840 struct omap_hdmi *hdmi = dev_get_drvdata(dev);
841
842 dispc_runtime_put(hdmi->dss->dispc);
818 843
819 return 0; 844 return 0;
820} 845}
821 846
822static int hdmi_runtime_resume(struct device *dev) 847static int hdmi_runtime_resume(struct device *dev)
823{ 848{
849 struct omap_hdmi *hdmi = dev_get_drvdata(dev);
824 int r; 850 int r;
825 851
826 r = dispc_runtime_get(); 852 r = dispc_runtime_get(hdmi->dss->dispc);
827 if (r < 0) 853 if (r < 0)
828 return r; 854 return r;
829 855
diff --git a/drivers/gpu/drm/omapdrm/dss/hdmi5_core.c b/drivers/gpu/drm/omapdrm/dss/hdmi5_core.c
index 09759f8ea7bc..2282e48574c6 100644
--- a/drivers/gpu/drm/omapdrm/dss/hdmi5_core.c
+++ b/drivers/gpu/drm/omapdrm/dss/hdmi5_core.c
@@ -50,14 +50,14 @@ static void hdmi_core_ddc_init(struct hdmi_core_data *core)
50{ 50{
51 void __iomem *base = core->base; 51 void __iomem *base = core->base;
52 const unsigned long long iclk = 266000000; /* DSS L3 ICLK */ 52 const unsigned long long iclk = 266000000; /* DSS L3 ICLK */
53 const unsigned ss_scl_high = 4600; /* ns */ 53 const unsigned int ss_scl_high = 4600; /* ns */
54 const unsigned ss_scl_low = 5400; /* ns */ 54 const unsigned int ss_scl_low = 5400; /* ns */
55 const unsigned fs_scl_high = 600; /* ns */ 55 const unsigned int fs_scl_high = 600; /* ns */
56 const unsigned fs_scl_low = 1300; /* ns */ 56 const unsigned int fs_scl_low = 1300; /* ns */
57 const unsigned sda_hold = 1000; /* ns */ 57 const unsigned int sda_hold = 1000; /* ns */
58 const unsigned sfr_div = 10; 58 const unsigned int sfr_div = 10;
59 unsigned long long sfr; 59 unsigned long long sfr;
60 unsigned v; 60 unsigned int v;
61 61
62 sfr = iclk / sfr_div; /* SFR_DIV */ 62 sfr = iclk / sfr_div; /* SFR_DIV */
63 sfr /= 1000; /* SFR clock in kHz */ 63 sfr /= 1000; /* SFR clock in kHz */
@@ -430,11 +430,11 @@ static void hdmi_core_write_avi_infoframe(struct hdmi_core_data *core,
430 void __iomem *base = core->base; 430 void __iomem *base = core->base;
431 u8 data[HDMI_INFOFRAME_SIZE(AVI)]; 431 u8 data[HDMI_INFOFRAME_SIZE(AVI)];
432 u8 *ptr; 432 u8 *ptr;
433 unsigned y, a, b, s; 433 unsigned int y, a, b, s;
434 unsigned c, m, r; 434 unsigned int c, m, r;
435 unsigned itc, ec, q, sc; 435 unsigned int itc, ec, q, sc;
436 unsigned vic; 436 unsigned int vic;
437 unsigned yq, cn, pr; 437 unsigned int yq, cn, pr;
438 438
439 hdmi_avi_infoframe_pack(frame, data, sizeof(data)); 439 hdmi_avi_infoframe_pack(frame, data, sizeof(data));
440 440
diff --git a/drivers/gpu/drm/omapdrm/dss/hdmi_phy.c b/drivers/gpu/drm/omapdrm/dss/hdmi_phy.c
index 5c14ed851609..9915923a53bd 100644
--- a/drivers/gpu/drm/omapdrm/dss/hdmi_phy.c
+++ b/drivers/gpu/drm/omapdrm/dss/hdmi_phy.c
@@ -99,7 +99,7 @@ static void hdmi_phy_configure_lanes(struct hdmi_phy_data *phy)
99 99
100 u16 lane_cfg = 0; 100 u16 lane_cfg = 0;
101 int i; 101 int i;
102 unsigned lane_cfg_val; 102 unsigned int lane_cfg_val;
103 u16 pol_val = 0; 103 u16 pol_val = 0;
104 104
105 for (i = 0; i < 4; ++i) 105 for (i = 0; i < 4; ++i)
diff --git a/drivers/gpu/drm/omapdrm/dss/hdmi_pll.c b/drivers/gpu/drm/omapdrm/dss/hdmi_pll.c
index 08885d7de1e8..e7be3707d147 100644
--- a/drivers/gpu/drm/omapdrm/dss/hdmi_pll.c
+++ b/drivers/gpu/drm/omapdrm/dss/hdmi_pll.c
@@ -48,7 +48,7 @@ static int hdmi_pll_enable(struct dss_pll *dsspll)
48 r = pm_runtime_get_sync(&pll->pdev->dev); 48 r = pm_runtime_get_sync(&pll->pdev->dev);
49 WARN_ON(r < 0); 49 WARN_ON(r < 0);
50 50
51 dss_ctrl_pll_enable(DSS_PLL_HDMI, true); 51 dss_ctrl_pll_enable(dsspll, true);
52 52
53 r = hdmi_wp_set_pll_pwr(wp, HDMI_PLLPWRCMD_BOTHON_ALLCLKS); 53 r = hdmi_wp_set_pll_pwr(wp, HDMI_PLLPWRCMD_BOTHON_ALLCLKS);
54 if (r) 54 if (r)
@@ -65,7 +65,7 @@ static void hdmi_pll_disable(struct dss_pll *dsspll)
65 65
66 hdmi_wp_set_pll_pwr(wp, HDMI_PLLPWRCMD_ALLOFF); 66 hdmi_wp_set_pll_pwr(wp, HDMI_PLLPWRCMD_ALLOFF);
67 67
68 dss_ctrl_pll_enable(DSS_PLL_HDMI, false); 68 dss_ctrl_pll_enable(dsspll, false);
69 69
70 r = pm_runtime_put_sync(&pll->pdev->dev); 70 r = pm_runtime_put_sync(&pll->pdev->dev);
71 WARN_ON(r < 0 && r != -ENOSYS); 71 WARN_ON(r < 0 && r != -ENOSYS);
@@ -128,7 +128,8 @@ static const struct dss_pll_hw dss_omap5_hdmi_pll_hw = {
128 .has_refsel = true, 128 .has_refsel = true,
129}; 129};
130 130
131static int hdmi_init_pll_data(struct platform_device *pdev, 131static int hdmi_init_pll_data(struct dss_device *dss,
132 struct platform_device *pdev,
132 struct hdmi_pll_data *hpll) 133 struct hdmi_pll_data *hpll)
133{ 134{
134 struct dss_pll *pll = &hpll->pll; 135 struct dss_pll *pll = &hpll->pll;
@@ -153,15 +154,15 @@ static int hdmi_init_pll_data(struct platform_device *pdev,
153 154
154 pll->ops = &hdmi_pll_ops; 155 pll->ops = &hdmi_pll_ops;
155 156
156 r = dss_pll_register(pll); 157 r = dss_pll_register(dss, pll);
157 if (r) 158 if (r)
158 return r; 159 return r;
159 160
160 return 0; 161 return 0;
161} 162}
162 163
163int hdmi_pll_init(struct platform_device *pdev, struct hdmi_pll_data *pll, 164int hdmi_pll_init(struct dss_device *dss, struct platform_device *pdev,
164 struct hdmi_wp_data *wp) 165 struct hdmi_pll_data *pll, struct hdmi_wp_data *wp)
165{ 166{
166 int r; 167 int r;
167 struct resource *res; 168 struct resource *res;
@@ -174,7 +175,7 @@ int hdmi_pll_init(struct platform_device *pdev, struct hdmi_pll_data *pll,
174 if (IS_ERR(pll->base)) 175 if (IS_ERR(pll->base))
175 return PTR_ERR(pll->base); 176 return PTR_ERR(pll->base);
176 177
177 r = hdmi_init_pll_data(pdev, pll); 178 r = hdmi_init_pll_data(dss, pdev, pll);
178 if (r) { 179 if (r) {
179 DSSERR("failed to init HDMI PLL\n"); 180 DSSERR("failed to init HDMI PLL\n");
180 return r; 181 return r;
diff --git a/drivers/gpu/drm/omapdrm/dss/hdmi_wp.c b/drivers/gpu/drm/omapdrm/dss/hdmi_wp.c
index 806e5fdcfe52..53bc5f78050c 100644
--- a/drivers/gpu/drm/omapdrm/dss/hdmi_wp.c
+++ b/drivers/gpu/drm/omapdrm/dss/hdmi_wp.c
@@ -168,7 +168,7 @@ void hdmi_wp_video_config_timing(struct hdmi_wp_data *wp,
168{ 168{
169 u32 timing_h = 0; 169 u32 timing_h = 0;
170 u32 timing_v = 0; 170 u32 timing_v = 0;
171 unsigned hsync_len_offset = 1; 171 unsigned int hsync_len_offset = 1;
172 172
173 DSSDBG("Enter hdmi_wp_video_config_timing\n"); 173 DSSDBG("Enter hdmi_wp_video_config_timing\n");
174 174
diff --git a/drivers/gpu/drm/omapdrm/dss/omapdss.h b/drivers/gpu/drm/omapdrm/dss/omapdss.h
index f8f83e826a56..14d74adb13fb 100644
--- a/drivers/gpu/drm/omapdrm/dss/omapdss.h
+++ b/drivers/gpu/drm/omapdrm/dss/omapdss.h
@@ -59,7 +59,11 @@
59#define DISPC_IRQ_ACBIAS_COUNT_STAT3 (1 << 29) 59#define DISPC_IRQ_ACBIAS_COUNT_STAT3 (1 << 29)
60#define DISPC_IRQ_FRAMEDONE3 (1 << 30) 60#define DISPC_IRQ_FRAMEDONE3 (1 << 30)
61 61
62struct dss_device;
63struct omap_drm_private;
62struct omap_dss_device; 64struct omap_dss_device;
65struct dispc_device;
66struct dss_device;
63struct dss_lcd_mgr_config; 67struct dss_lcd_mgr_config;
64struct snd_aes_iec958; 68struct snd_aes_iec958;
65struct snd_cea_861_aud_if; 69struct snd_cea_861_aud_if;
@@ -159,21 +163,6 @@ enum omap_overlay_caps {
159 OMAP_DSS_OVL_CAP_REPLICATION = 1 << 5, 163 OMAP_DSS_OVL_CAP_REPLICATION = 1 << 5,
160}; 164};
161 165
162enum omap_dss_clk_source {
163 OMAP_DSS_CLK_SRC_FCK = 0, /* OMAP2/3: DSS1_ALWON_FCLK
164 * OMAP4: DSS_FCLK */
165 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC, /* OMAP3: DSI1_PLL_FCLK
166 * OMAP4: PLL1_CLK1 */
167 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI, /* OMAP3: DSI2_PLL_FCLK
168 * OMAP4: PLL1_CLK2 */
169 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC, /* OMAP4: PLL2_CLK1 */
170 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI, /* OMAP4: PLL2_CLK2 */
171};
172
173enum omap_hdmi_flags {
174 OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP = 1 << 0,
175};
176
177enum omap_dss_output_id { 166enum omap_dss_output_id {
178 OMAP_DSS_OUTPUT_DPI = 1 << 0, 167 OMAP_DSS_OUTPUT_DPI = 1 << 0,
179 OMAP_DSS_OUTPUT_DBI = 1 << 1, 168 OMAP_DSS_OUTPUT_DBI = 1 << 1,
@@ -198,8 +187,8 @@ enum omap_dss_dsi_trans_mode {
198struct omap_dss_dsi_videomode_timings { 187struct omap_dss_dsi_videomode_timings {
199 unsigned long hsclk; 188 unsigned long hsclk;
200 189
201 unsigned ndl; 190 unsigned int ndl;
202 unsigned bitspp; 191 unsigned int bitspp;
203 192
204 /* pixels */ 193 /* pixels */
205 u16 hact; 194 u16 hact;
@@ -585,7 +574,12 @@ struct omap_dss_driver {
585 const struct hdmi_avi_infoframe *avi); 574 const struct hdmi_avi_infoframe *avi);
586}; 575};
587 576
588bool omapdss_is_initialized(void); 577struct dss_device *omapdss_get_dss(void);
578void omapdss_set_dss(struct dss_device *dss);
579static inline bool omapdss_is_initialized(void)
580{
581 return !!omapdss_get_dss();
582}
589 583
590int omapdss_register_display(struct omap_dss_device *dssdev); 584int omapdss_register_display(struct omap_dss_device *dssdev);
591void omapdss_unregister_display(struct omap_dss_device *dssdev); 585void omapdss_unregister_display(struct omap_dss_device *dssdev);
@@ -609,9 +603,6 @@ int omapdss_output_unset_device(struct omap_dss_device *out);
609 603
610struct omap_dss_device *omapdss_find_output_from_display(struct omap_dss_device *dssdev); 604struct omap_dss_device *omapdss_find_output_from_display(struct omap_dss_device *dssdev);
611 605
612void omapdss_default_get_timings(struct omap_dss_device *dssdev,
613 struct videomode *vm);
614
615typedef void (*omap_dispc_isr_t) (void *arg, u32 mask); 606typedef void (*omap_dispc_isr_t) (void *arg, u32 mask);
616int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask); 607int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
617int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask); 608int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
@@ -632,97 +623,139 @@ static inline bool omapdss_device_is_enabled(struct omap_dss_device *dssdev)
632struct omap_dss_device * 623struct omap_dss_device *
633omapdss_of_find_source_for_first_ep(struct device_node *node); 624omapdss_of_find_source_for_first_ep(struct device_node *node);
634 625
635void omapdss_set_is_initialized(bool set);
636
637struct device_node *dss_of_port_get_parent_device(struct device_node *port); 626struct device_node *dss_of_port_get_parent_device(struct device_node *port);
638u32 dss_of_port_get_port_number(struct device_node *port); 627u32 dss_of_port_get_port_number(struct device_node *port);
639 628
629enum dss_writeback_channel {
630 DSS_WB_LCD1_MGR = 0,
631 DSS_WB_LCD2_MGR = 1,
632 DSS_WB_TV_MGR = 2,
633 DSS_WB_OVL0 = 3,
634 DSS_WB_OVL1 = 4,
635 DSS_WB_OVL2 = 5,
636 DSS_WB_OVL3 = 6,
637 DSS_WB_LCD3_MGR = 7,
638};
639
640struct dss_mgr_ops { 640struct dss_mgr_ops {
641 int (*connect)(enum omap_channel channel, 641 int (*connect)(struct omap_drm_private *priv,
642 struct omap_dss_device *dst); 642 enum omap_channel channel,
643 void (*disconnect)(enum omap_channel channel, 643 struct omap_dss_device *dst);
644 struct omap_dss_device *dst); 644 void (*disconnect)(struct omap_drm_private *priv,
645 645 enum omap_channel channel,
646 void (*start_update)(enum omap_channel channel); 646 struct omap_dss_device *dst);
647 int (*enable)(enum omap_channel channel); 647
648 void (*disable)(enum omap_channel channel); 648 void (*start_update)(struct omap_drm_private *priv,
649 void (*set_timings)(enum omap_channel channel, 649 enum omap_channel channel);
650 const struct videomode *vm); 650 int (*enable)(struct omap_drm_private *priv,
651 void (*set_lcd_config)(enum omap_channel channel, 651 enum omap_channel channel);
652 const struct dss_lcd_mgr_config *config); 652 void (*disable)(struct omap_drm_private *priv,
653 int (*register_framedone_handler)(enum omap_channel channel, 653 enum omap_channel channel);
654 void (*set_timings)(struct omap_drm_private *priv,
655 enum omap_channel channel,
656 const struct videomode *vm);
657 void (*set_lcd_config)(struct omap_drm_private *priv,
658 enum omap_channel channel,
659 const struct dss_lcd_mgr_config *config);
660 int (*register_framedone_handler)(struct omap_drm_private *priv,
661 enum omap_channel channel,
654 void (*handler)(void *), void *data); 662 void (*handler)(void *), void *data);
655 void (*unregister_framedone_handler)(enum omap_channel channel, 663 void (*unregister_framedone_handler)(struct omap_drm_private *priv,
664 enum omap_channel channel,
656 void (*handler)(void *), void *data); 665 void (*handler)(void *), void *data);
657}; 666};
658 667
659int dss_install_mgr_ops(const struct dss_mgr_ops *mgr_ops); 668int dss_install_mgr_ops(const struct dss_mgr_ops *mgr_ops,
669 struct omap_drm_private *priv);
660void dss_uninstall_mgr_ops(void); 670void dss_uninstall_mgr_ops(void);
661 671
662int dss_mgr_connect(enum omap_channel channel, 672int dss_mgr_connect(struct omap_dss_device *dssdev,
663 struct omap_dss_device *dst); 673 struct omap_dss_device *dst);
664void dss_mgr_disconnect(enum omap_channel channel, 674void dss_mgr_disconnect(struct omap_dss_device *dssdev,
665 struct omap_dss_device *dst); 675 struct omap_dss_device *dst);
666void dss_mgr_set_timings(enum omap_channel channel, 676void dss_mgr_set_timings(struct omap_dss_device *dssdev,
667 const struct videomode *vm); 677 const struct videomode *vm);
668void dss_mgr_set_lcd_config(enum omap_channel channel, 678void dss_mgr_set_lcd_config(struct omap_dss_device *dssdev,
669 const struct dss_lcd_mgr_config *config); 679 const struct dss_lcd_mgr_config *config);
670int dss_mgr_enable(enum omap_channel channel); 680int dss_mgr_enable(struct omap_dss_device *dssdev);
671void dss_mgr_disable(enum omap_channel channel); 681void dss_mgr_disable(struct omap_dss_device *dssdev);
672void dss_mgr_start_update(enum omap_channel channel); 682void dss_mgr_start_update(struct omap_dss_device *dssdev);
673int dss_mgr_register_framedone_handler(enum omap_channel channel, 683int dss_mgr_register_framedone_handler(struct omap_dss_device *dssdev,
674 void (*handler)(void *), void *data); 684 void (*handler)(void *), void *data);
675void dss_mgr_unregister_framedone_handler(enum omap_channel channel, 685void dss_mgr_unregister_framedone_handler(struct omap_dss_device *dssdev,
676 void (*handler)(void *), void *data); 686 void (*handler)(void *), void *data);
677 687
678/* dispc ops */ 688/* dispc ops */
679 689
680struct dispc_ops { 690struct dispc_ops {
681 u32 (*read_irqstatus)(void); 691 u32 (*read_irqstatus)(struct dispc_device *dispc);
682 void (*clear_irqstatus)(u32 mask); 692 void (*clear_irqstatus)(struct dispc_device *dispc, u32 mask);
683 void (*write_irqenable)(u32 mask); 693 void (*write_irqenable)(struct dispc_device *dispc, u32 mask);
684 694
685 int (*request_irq)(irq_handler_t handler, void *dev_id); 695 int (*request_irq)(struct dispc_device *dispc, irq_handler_t handler,
686 void (*free_irq)(void *dev_id); 696 void *dev_id);
687 697 void (*free_irq)(struct dispc_device *dispc, void *dev_id);
688 int (*runtime_get)(void); 698
689 void (*runtime_put)(void); 699 int (*runtime_get)(struct dispc_device *dispc);
690 700 void (*runtime_put)(struct dispc_device *dispc);
691 int (*get_num_ovls)(void); 701
692 int (*get_num_mgrs)(void); 702 int (*get_num_ovls)(struct dispc_device *dispc);
693 703 int (*get_num_mgrs)(struct dispc_device *dispc);
694 u32 (*get_memory_bandwidth_limit)(void); 704
695 705 u32 (*get_memory_bandwidth_limit)(struct dispc_device *dispc);
696 void (*mgr_enable)(enum omap_channel channel, bool enable); 706
697 bool (*mgr_is_enabled)(enum omap_channel channel); 707 void (*mgr_enable)(struct dispc_device *dispc,
698 u32 (*mgr_get_vsync_irq)(enum omap_channel channel); 708 enum omap_channel channel, bool enable);
699 u32 (*mgr_get_framedone_irq)(enum omap_channel channel); 709 bool (*mgr_is_enabled)(struct dispc_device *dispc,
700 u32 (*mgr_get_sync_lost_irq)(enum omap_channel channel); 710 enum omap_channel channel);
701 bool (*mgr_go_busy)(enum omap_channel channel); 711 u32 (*mgr_get_vsync_irq)(struct dispc_device *dispc,
702 void (*mgr_go)(enum omap_channel channel); 712 enum omap_channel channel);
703 void (*mgr_set_lcd_config)(enum omap_channel channel, 713 u32 (*mgr_get_framedone_irq)(struct dispc_device *dispc,
704 const struct dss_lcd_mgr_config *config); 714 enum omap_channel channel);
705 void (*mgr_set_timings)(enum omap_channel channel, 715 u32 (*mgr_get_sync_lost_irq)(struct dispc_device *dispc,
706 const struct videomode *vm); 716 enum omap_channel channel);
707 void (*mgr_setup)(enum omap_channel channel, 717 bool (*mgr_go_busy)(struct dispc_device *dispc,
708 const struct omap_overlay_manager_info *info); 718 enum omap_channel channel);
709 enum omap_dss_output_id (*mgr_get_supported_outputs)(enum omap_channel channel); 719 void (*mgr_go)(struct dispc_device *dispc, enum omap_channel channel);
710 u32 (*mgr_gamma_size)(enum omap_channel channel); 720 void (*mgr_set_lcd_config)(struct dispc_device *dispc,
711 void (*mgr_set_gamma)(enum omap_channel channel, 721 enum omap_channel channel,
712 const struct drm_color_lut *lut, 722 const struct dss_lcd_mgr_config *config);
713 unsigned int length); 723 void (*mgr_set_timings)(struct dispc_device *dispc,
714 724 enum omap_channel channel,
715 int (*ovl_enable)(enum omap_plane_id plane, bool enable); 725 const struct videomode *vm);
716 int (*ovl_setup)(enum omap_plane_id plane, 726 void (*mgr_setup)(struct dispc_device *dispc, enum omap_channel channel,
727 const struct omap_overlay_manager_info *info);
728 enum omap_dss_output_id (*mgr_get_supported_outputs)(
729 struct dispc_device *dispc, enum omap_channel channel);
730 u32 (*mgr_gamma_size)(struct dispc_device *dispc,
731 enum omap_channel channel);
732 void (*mgr_set_gamma)(struct dispc_device *dispc,
733 enum omap_channel channel,
734 const struct drm_color_lut *lut,
735 unsigned int length);
736
737 int (*ovl_enable)(struct dispc_device *dispc, enum omap_plane_id plane,
738 bool enable);
739 int (*ovl_setup)(struct dispc_device *dispc, enum omap_plane_id plane,
717 const struct omap_overlay_info *oi, 740 const struct omap_overlay_info *oi,
718 const struct videomode *vm, bool mem_to_mem, 741 const struct videomode *vm, bool mem_to_mem,
719 enum omap_channel channel); 742 enum omap_channel channel);
743
744 const u32 *(*ovl_get_color_modes)(struct dispc_device *dispc,
745 enum omap_plane_id plane);
720 746
721 const u32 *(*ovl_get_color_modes)(enum omap_plane_id plane); 747 u32 (*wb_get_framedone_irq)(struct dispc_device *dispc);
748 int (*wb_setup)(struct dispc_device *dispc,
749 const struct omap_dss_writeback_info *wi,
750 bool mem_to_mem, const struct videomode *vm,
751 enum dss_writeback_channel channel_in);
752 bool (*has_writeback)(struct dispc_device *dispc);
753 bool (*wb_go_busy)(struct dispc_device *dispc);
754 void (*wb_go)(struct dispc_device *dispc);
722}; 755};
723 756
724void dispc_set_ops(const struct dispc_ops *o); 757struct dispc_device *dispc_get_dispc(struct dss_device *dss);
725const struct dispc_ops *dispc_get_ops(void); 758const struct dispc_ops *dispc_get_ops(struct dss_device *dss);
726 759
727bool omapdss_component_is_display(struct device_node *node); 760bool omapdss_component_is_display(struct device_node *node);
728bool omapdss_component_is_output(struct device_node *node); 761bool omapdss_component_is_output(struct device_node *node);
diff --git a/drivers/gpu/drm/omapdrm/dss/output.c b/drivers/gpu/drm/omapdrm/dss/output.c
index b9afd80ae385..96b9d4cd505f 100644
--- a/drivers/gpu/drm/omapdrm/dss/output.c
+++ b/drivers/gpu/drm/omapdrm/dss/output.c
@@ -156,7 +156,6 @@ struct omap_dss_device *omap_dss_find_output_by_port_node(struct device_node *po
156 156
157 return NULL; 157 return NULL;
158} 158}
159EXPORT_SYMBOL(omap_dss_find_output_by_port_node);
160 159
161struct omap_dss_device *omapdss_find_output_from_display(struct omap_dss_device *dssdev) 160struct omap_dss_device *omapdss_find_output_from_display(struct omap_dss_device *dssdev)
162{ 161{
@@ -171,13 +170,16 @@ struct omap_dss_device *omapdss_find_output_from_display(struct omap_dss_device
171EXPORT_SYMBOL(omapdss_find_output_from_display); 170EXPORT_SYMBOL(omapdss_find_output_from_display);
172 171
173static const struct dss_mgr_ops *dss_mgr_ops; 172static const struct dss_mgr_ops *dss_mgr_ops;
173static struct omap_drm_private *dss_mgr_ops_priv;
174 174
175int dss_install_mgr_ops(const struct dss_mgr_ops *mgr_ops) 175int dss_install_mgr_ops(const struct dss_mgr_ops *mgr_ops,
176 struct omap_drm_private *priv)
176{ 177{
177 if (dss_mgr_ops) 178 if (dss_mgr_ops)
178 return -EBUSY; 179 return -EBUSY;
179 180
180 dss_mgr_ops = mgr_ops; 181 dss_mgr_ops = mgr_ops;
182 dss_mgr_ops_priv = priv;
181 183
182 return 0; 184 return 0;
183} 185}
@@ -186,64 +188,71 @@ EXPORT_SYMBOL(dss_install_mgr_ops);
186void dss_uninstall_mgr_ops(void) 188void dss_uninstall_mgr_ops(void)
187{ 189{
188 dss_mgr_ops = NULL; 190 dss_mgr_ops = NULL;
191 dss_mgr_ops_priv = NULL;
189} 192}
190EXPORT_SYMBOL(dss_uninstall_mgr_ops); 193EXPORT_SYMBOL(dss_uninstall_mgr_ops);
191 194
192int dss_mgr_connect(enum omap_channel channel, 195int dss_mgr_connect(struct omap_dss_device *dssdev, struct omap_dss_device *dst)
193 struct omap_dss_device *dst)
194{ 196{
195 return dss_mgr_ops->connect(channel, dst); 197 return dss_mgr_ops->connect(dss_mgr_ops_priv,
198 dssdev->dispc_channel, dst);
196} 199}
197EXPORT_SYMBOL(dss_mgr_connect); 200EXPORT_SYMBOL(dss_mgr_connect);
198 201
199void dss_mgr_disconnect(enum omap_channel channel, 202void dss_mgr_disconnect(struct omap_dss_device *dssdev,
200 struct omap_dss_device *dst) 203 struct omap_dss_device *dst)
201{ 204{
202 dss_mgr_ops->disconnect(channel, dst); 205 dss_mgr_ops->disconnect(dss_mgr_ops_priv, dssdev->dispc_channel, dst);
203} 206}
204EXPORT_SYMBOL(dss_mgr_disconnect); 207EXPORT_SYMBOL(dss_mgr_disconnect);
205 208
206void dss_mgr_set_timings(enum omap_channel channel, const struct videomode *vm) 209void dss_mgr_set_timings(struct omap_dss_device *dssdev,
210 const struct videomode *vm)
207{ 211{
208 dss_mgr_ops->set_timings(channel, vm); 212 dss_mgr_ops->set_timings(dss_mgr_ops_priv, dssdev->dispc_channel, vm);
209} 213}
210EXPORT_SYMBOL(dss_mgr_set_timings); 214EXPORT_SYMBOL(dss_mgr_set_timings);
211 215
212void dss_mgr_set_lcd_config(enum omap_channel channel, 216void dss_mgr_set_lcd_config(struct omap_dss_device *dssdev,
213 const struct dss_lcd_mgr_config *config) 217 const struct dss_lcd_mgr_config *config)
214{ 218{
215 dss_mgr_ops->set_lcd_config(channel, config); 219 dss_mgr_ops->set_lcd_config(dss_mgr_ops_priv,
220 dssdev->dispc_channel, config);
216} 221}
217EXPORT_SYMBOL(dss_mgr_set_lcd_config); 222EXPORT_SYMBOL(dss_mgr_set_lcd_config);
218 223
219int dss_mgr_enable(enum omap_channel channel) 224int dss_mgr_enable(struct omap_dss_device *dssdev)
220{ 225{
221 return dss_mgr_ops->enable(channel); 226 return dss_mgr_ops->enable(dss_mgr_ops_priv, dssdev->dispc_channel);
222} 227}
223EXPORT_SYMBOL(dss_mgr_enable); 228EXPORT_SYMBOL(dss_mgr_enable);
224 229
225void dss_mgr_disable(enum omap_channel channel) 230void dss_mgr_disable(struct omap_dss_device *dssdev)
226{ 231{
227 dss_mgr_ops->disable(channel); 232 dss_mgr_ops->disable(dss_mgr_ops_priv, dssdev->dispc_channel);
228} 233}
229EXPORT_SYMBOL(dss_mgr_disable); 234EXPORT_SYMBOL(dss_mgr_disable);
230 235
231void dss_mgr_start_update(enum omap_channel channel) 236void dss_mgr_start_update(struct omap_dss_device *dssdev)
232{ 237{
233 dss_mgr_ops->start_update(channel); 238 dss_mgr_ops->start_update(dss_mgr_ops_priv, dssdev->dispc_channel);
234} 239}
235EXPORT_SYMBOL(dss_mgr_start_update); 240EXPORT_SYMBOL(dss_mgr_start_update);
236 241
237int dss_mgr_register_framedone_handler(enum omap_channel channel, 242int dss_mgr_register_framedone_handler(struct omap_dss_device *dssdev,
238 void (*handler)(void *), void *data) 243 void (*handler)(void *), void *data)
239{ 244{
240 return dss_mgr_ops->register_framedone_handler(channel, handler, data); 245 return dss_mgr_ops->register_framedone_handler(dss_mgr_ops_priv,
246 dssdev->dispc_channel,
247 handler, data);
241} 248}
242EXPORT_SYMBOL(dss_mgr_register_framedone_handler); 249EXPORT_SYMBOL(dss_mgr_register_framedone_handler);
243 250
244void dss_mgr_unregister_framedone_handler(enum omap_channel channel, 251void dss_mgr_unregister_framedone_handler(struct omap_dss_device *dssdev,
245 void (*handler)(void *), void *data) 252 void (*handler)(void *), void *data)
246{ 253{
247 dss_mgr_ops->unregister_framedone_handler(channel, handler, data); 254 dss_mgr_ops->unregister_framedone_handler(dss_mgr_ops_priv,
255 dssdev->dispc_channel,
256 handler, data);
248} 257}
249EXPORT_SYMBOL(dss_mgr_unregister_framedone_handler); 258EXPORT_SYMBOL(dss_mgr_unregister_framedone_handler);
diff --git a/drivers/gpu/drm/omapdrm/dss/pll.c b/drivers/gpu/drm/omapdrm/dss/pll.c
index 058714b1eb56..078b0e8216c3 100644
--- a/drivers/gpu/drm/omapdrm/dss/pll.c
+++ b/drivers/gpu/drm/omapdrm/dss/pll.c
@@ -35,15 +35,14 @@
35#define PLL_SSC_CONFIGURATION2 0x001C 35#define PLL_SSC_CONFIGURATION2 0x001C
36#define PLL_CONFIGURATION4 0x0020 36#define PLL_CONFIGURATION4 0x0020
37 37
38static struct dss_pll *dss_plls[4]; 38int dss_pll_register(struct dss_device *dss, struct dss_pll *pll)
39
40int dss_pll_register(struct dss_pll *pll)
41{ 39{
42 int i; 40 int i;
43 41
44 for (i = 0; i < ARRAY_SIZE(dss_plls); ++i) { 42 for (i = 0; i < ARRAY_SIZE(dss->plls); ++i) {
45 if (!dss_plls[i]) { 43 if (!dss->plls[i]) {
46 dss_plls[i] = pll; 44 dss->plls[i] = pll;
45 pll->dss = dss;
47 return 0; 46 return 0;
48 } 47 }
49 } 48 }
@@ -53,29 +52,32 @@ int dss_pll_register(struct dss_pll *pll)
53 52
54void dss_pll_unregister(struct dss_pll *pll) 53void dss_pll_unregister(struct dss_pll *pll)
55{ 54{
55 struct dss_device *dss = pll->dss;
56 int i; 56 int i;
57 57
58 for (i = 0; i < ARRAY_SIZE(dss_plls); ++i) { 58 for (i = 0; i < ARRAY_SIZE(dss->plls); ++i) {
59 if (dss_plls[i] == pll) { 59 if (dss->plls[i] == pll) {
60 dss_plls[i] = NULL; 60 dss->plls[i] = NULL;
61 pll->dss = NULL;
61 return; 62 return;
62 } 63 }
63 } 64 }
64} 65}
65 66
66struct dss_pll *dss_pll_find(const char *name) 67struct dss_pll *dss_pll_find(struct dss_device *dss, const char *name)
67{ 68{
68 int i; 69 int i;
69 70
70 for (i = 0; i < ARRAY_SIZE(dss_plls); ++i) { 71 for (i = 0; i < ARRAY_SIZE(dss->plls); ++i) {
71 if (dss_plls[i] && strcmp(dss_plls[i]->name, name) == 0) 72 if (dss->plls[i] && strcmp(dss->plls[i]->name, name) == 0)
72 return dss_plls[i]; 73 return dss->plls[i];
73 } 74 }
74 75
75 return NULL; 76 return NULL;
76} 77}
77 78
78struct dss_pll *dss_pll_find_by_src(enum dss_clk_source src) 79struct dss_pll *dss_pll_find_by_src(struct dss_device *dss,
80 enum dss_clk_source src)
79{ 81{
80 struct dss_pll *pll; 82 struct dss_pll *pll;
81 83
@@ -85,27 +87,27 @@ struct dss_pll *dss_pll_find_by_src(enum dss_clk_source src)
85 return NULL; 87 return NULL;
86 88
87 case DSS_CLK_SRC_HDMI_PLL: 89 case DSS_CLK_SRC_HDMI_PLL:
88 return dss_pll_find("hdmi"); 90 return dss_pll_find(dss, "hdmi");
89 91
90 case DSS_CLK_SRC_PLL1_1: 92 case DSS_CLK_SRC_PLL1_1:
91 case DSS_CLK_SRC_PLL1_2: 93 case DSS_CLK_SRC_PLL1_2:
92 case DSS_CLK_SRC_PLL1_3: 94 case DSS_CLK_SRC_PLL1_3:
93 pll = dss_pll_find("dsi0"); 95 pll = dss_pll_find(dss, "dsi0");
94 if (!pll) 96 if (!pll)
95 pll = dss_pll_find("video0"); 97 pll = dss_pll_find(dss, "video0");
96 return pll; 98 return pll;
97 99
98 case DSS_CLK_SRC_PLL2_1: 100 case DSS_CLK_SRC_PLL2_1:
99 case DSS_CLK_SRC_PLL2_2: 101 case DSS_CLK_SRC_PLL2_2:
100 case DSS_CLK_SRC_PLL2_3: 102 case DSS_CLK_SRC_PLL2_3:
101 pll = dss_pll_find("dsi1"); 103 pll = dss_pll_find(dss, "dsi1");
102 if (!pll) 104 if (!pll)
103 pll = dss_pll_find("video1"); 105 pll = dss_pll_find(dss, "video1");
104 return pll; 106 return pll;
105 } 107 }
106} 108}
107 109
108unsigned dss_pll_get_clkout_idx_for_src(enum dss_clk_source src) 110unsigned int dss_pll_get_clkout_idx_for_src(enum dss_clk_source src)
109{ 111{
110 switch (src) { 112 switch (src) {
111 case DSS_CLK_SRC_HDMI_PLL: 113 case DSS_CLK_SRC_HDMI_PLL:
@@ -277,7 +279,7 @@ bool dss_pll_calc_b(const struct dss_pll *pll, unsigned long clkin,
277 unsigned long fint, clkdco, clkout; 279 unsigned long fint, clkdco, clkout;
278 unsigned long target_clkdco; 280 unsigned long target_clkdco;
279 unsigned long min_dco; 281 unsigned long min_dco;
280 unsigned n, m, mf, m2, sd; 282 unsigned int n, m, mf, m2, sd;
281 const struct dss_pll_hw *hw = pll->hw; 283 const struct dss_pll_hw *hw = pll->hw;
282 284
283 DSSDBG("clkin %lu, target clkout %lu\n", clkin, target_clkout); 285 DSSDBG("clkin %lu, target clkout %lu\n", clkin, target_clkout);
diff --git a/drivers/gpu/drm/omapdrm/dss/sdi.c b/drivers/gpu/drm/omapdrm/dss/sdi.c
index d8ab31f3a813..68a40ae26f5b 100644
--- a/drivers/gpu/drm/omapdrm/dss/sdi.c
+++ b/drivers/gpu/drm/omapdrm/dss/sdi.c
@@ -29,8 +29,9 @@
29#include "omapdss.h" 29#include "omapdss.h"
30#include "dss.h" 30#include "dss.h"
31 31
32static struct { 32struct sdi_device {
33 struct platform_device *pdev; 33 struct platform_device *pdev;
34 struct dss_device *dss;
34 35
35 bool update_enabled; 36 bool update_enabled;
36 struct regulator *vdds_sdi_reg; 37 struct regulator *vdds_sdi_reg;
@@ -40,11 +41,12 @@ static struct {
40 int datapairs; 41 int datapairs;
41 42
42 struct omap_dss_device output; 43 struct omap_dss_device output;
44};
43 45
44 bool port_initialized; 46#define dssdev_to_sdi(dssdev) container_of(dssdev, struct sdi_device, output)
45} sdi;
46 47
47struct sdi_clk_calc_ctx { 48struct sdi_clk_calc_ctx {
49 struct sdi_device *sdi;
48 unsigned long pck_min, pck_max; 50 unsigned long pck_min, pck_max;
49 51
50 unsigned long fck; 52 unsigned long fck;
@@ -70,16 +72,17 @@ static bool dpi_calc_dss_cb(unsigned long fck, void *data)
70 72
71 ctx->fck = fck; 73 ctx->fck = fck;
72 74
73 return dispc_div_calc(fck, ctx->pck_min, ctx->pck_max, 75 return dispc_div_calc(ctx->sdi->dss->dispc, fck,
74 dpi_calc_dispc_cb, ctx); 76 ctx->pck_min, ctx->pck_max,
77 dpi_calc_dispc_cb, ctx);
75} 78}
76 79
77static int sdi_calc_clock_div(unsigned long pclk, 80static int sdi_calc_clock_div(struct sdi_device *sdi, unsigned long pclk,
78 unsigned long *fck, 81 unsigned long *fck,
79 struct dispc_clock_info *dispc_cinfo) 82 struct dispc_clock_info *dispc_cinfo)
80{ 83{
81 int i; 84 int i;
82 struct sdi_clk_calc_ctx ctx; 85 struct sdi_clk_calc_ctx ctx = { .sdi = sdi };
83 86
84 /* 87 /*
85 * DSS fclk gives us very few possibilities, so finding a good pixel 88 * DSS fclk gives us very few possibilities, so finding a good pixel
@@ -98,7 +101,8 @@ static int sdi_calc_clock_div(unsigned long pclk,
98 ctx.pck_min = 0; 101 ctx.pck_min = 0;
99 ctx.pck_max = pclk + 1000 * i * i * i; 102 ctx.pck_max = pclk + 1000 * i * i * i;
100 103
101 ok = dss_div_calc(pclk, ctx.pck_min, dpi_calc_dss_cb, &ctx); 104 ok = dss_div_calc(sdi->dss, pclk, ctx.pck_min,
105 dpi_calc_dss_cb, &ctx);
102 if (ok) { 106 if (ok) {
103 *fck = ctx.fck; 107 *fck = ctx.fck;
104 *dispc_cinfo = ctx.dispc_cinfo; 108 *dispc_cinfo = ctx.dispc_cinfo;
@@ -109,52 +113,49 @@ static int sdi_calc_clock_div(unsigned long pclk,
109 return -EINVAL; 113 return -EINVAL;
110} 114}
111 115
112static void sdi_config_lcd_manager(struct omap_dss_device *dssdev) 116static void sdi_config_lcd_manager(struct sdi_device *sdi)
113{ 117{
114 enum omap_channel channel = dssdev->dispc_channel; 118 sdi->mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS;
115 119
116 sdi.mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS; 120 sdi->mgr_config.stallmode = false;
121 sdi->mgr_config.fifohandcheck = false;
117 122
118 sdi.mgr_config.stallmode = false; 123 sdi->mgr_config.video_port_width = 24;
119 sdi.mgr_config.fifohandcheck = false; 124 sdi->mgr_config.lcden_sig_polarity = 1;
120 125
121 sdi.mgr_config.video_port_width = 24; 126 dss_mgr_set_lcd_config(&sdi->output, &sdi->mgr_config);
122 sdi.mgr_config.lcden_sig_polarity = 1;
123
124 dss_mgr_set_lcd_config(channel, &sdi.mgr_config);
125} 127}
126 128
127static int sdi_display_enable(struct omap_dss_device *dssdev) 129static int sdi_display_enable(struct omap_dss_device *dssdev)
128{ 130{
129 struct omap_dss_device *out = &sdi.output; 131 struct sdi_device *sdi = dssdev_to_sdi(dssdev);
130 enum omap_channel channel = dssdev->dispc_channel; 132 struct videomode *vm = &sdi->vm;
131 struct videomode *vm = &sdi.vm;
132 unsigned long fck; 133 unsigned long fck;
133 struct dispc_clock_info dispc_cinfo; 134 struct dispc_clock_info dispc_cinfo;
134 unsigned long pck; 135 unsigned long pck;
135 int r; 136 int r;
136 137
137 if (!out->dispc_channel_connected) { 138 if (!sdi->output.dispc_channel_connected) {
138 DSSERR("failed to enable display: no output/manager\n"); 139 DSSERR("failed to enable display: no output/manager\n");
139 return -ENODEV; 140 return -ENODEV;
140 } 141 }
141 142
142 r = regulator_enable(sdi.vdds_sdi_reg); 143 r = regulator_enable(sdi->vdds_sdi_reg);
143 if (r) 144 if (r)
144 goto err_reg_enable; 145 goto err_reg_enable;
145 146
146 r = dispc_runtime_get(); 147 r = dispc_runtime_get(sdi->dss->dispc);
147 if (r) 148 if (r)
148 goto err_get_dispc; 149 goto err_get_dispc;
149 150
150 /* 15.5.9.1.2 */ 151 /* 15.5.9.1.2 */
151 vm->flags |= DISPLAY_FLAGS_PIXDATA_POSEDGE | DISPLAY_FLAGS_SYNC_POSEDGE; 152 vm->flags |= DISPLAY_FLAGS_PIXDATA_POSEDGE | DISPLAY_FLAGS_SYNC_POSEDGE;
152 153
153 r = sdi_calc_clock_div(vm->pixelclock, &fck, &dispc_cinfo); 154 r = sdi_calc_clock_div(sdi, vm->pixelclock, &fck, &dispc_cinfo);
154 if (r) 155 if (r)
155 goto err_calc_clock_div; 156 goto err_calc_clock_div;
156 157
157 sdi.mgr_config.clock_info = dispc_cinfo; 158 sdi->mgr_config.clock_info = dispc_cinfo;
158 159
159 pck = fck / dispc_cinfo.lck_div / dispc_cinfo.pck_div; 160 pck = fck / dispc_cinfo.lck_div / dispc_cinfo.pck_div;
160 161
@@ -166,13 +167,13 @@ static int sdi_display_enable(struct omap_dss_device *dssdev)
166 } 167 }
167 168
168 169
169 dss_mgr_set_timings(channel, vm); 170 dss_mgr_set_timings(&sdi->output, vm);
170 171
171 r = dss_set_fck_rate(fck); 172 r = dss_set_fck_rate(sdi->dss, fck);
172 if (r) 173 if (r)
173 goto err_set_dss_clock_div; 174 goto err_set_dss_clock_div;
174 175
175 sdi_config_lcd_manager(dssdev); 176 sdi_config_lcd_manager(sdi);
176 177
177 /* 178 /*
178 * LCLK and PCLK divisors are located in shadow registers, and we 179 * LCLK and PCLK divisors are located in shadow registers, and we
@@ -185,63 +186,69 @@ static int sdi_display_enable(struct omap_dss_device *dssdev)
185 * need to care about the shadow register mechanism for pck-free. The 186 * need to care about the shadow register mechanism for pck-free. The
186 * exact reason for this is unknown. 187 * exact reason for this is unknown.
187 */ 188 */
188 dispc_mgr_set_clock_div(channel, &sdi.mgr_config.clock_info); 189 dispc_mgr_set_clock_div(sdi->dss->dispc, sdi->output.dispc_channel,
190 &sdi->mgr_config.clock_info);
189 191
190 dss_sdi_init(sdi.datapairs); 192 dss_sdi_init(sdi->dss, sdi->datapairs);
191 r = dss_sdi_enable(); 193 r = dss_sdi_enable(sdi->dss);
192 if (r) 194 if (r)
193 goto err_sdi_enable; 195 goto err_sdi_enable;
194 mdelay(2); 196 mdelay(2);
195 197
196 r = dss_mgr_enable(channel); 198 r = dss_mgr_enable(&sdi->output);
197 if (r) 199 if (r)
198 goto err_mgr_enable; 200 goto err_mgr_enable;
199 201
200 return 0; 202 return 0;
201 203
202err_mgr_enable: 204err_mgr_enable:
203 dss_sdi_disable(); 205 dss_sdi_disable(sdi->dss);
204err_sdi_enable: 206err_sdi_enable:
205err_set_dss_clock_div: 207err_set_dss_clock_div:
206err_calc_clock_div: 208err_calc_clock_div:
207 dispc_runtime_put(); 209 dispc_runtime_put(sdi->dss->dispc);
208err_get_dispc: 210err_get_dispc:
209 regulator_disable(sdi.vdds_sdi_reg); 211 regulator_disable(sdi->vdds_sdi_reg);
210err_reg_enable: 212err_reg_enable:
211 return r; 213 return r;
212} 214}
213 215
214static void sdi_display_disable(struct omap_dss_device *dssdev) 216static void sdi_display_disable(struct omap_dss_device *dssdev)
215{ 217{
216 enum omap_channel channel = dssdev->dispc_channel; 218 struct sdi_device *sdi = dssdev_to_sdi(dssdev);
217 219
218 dss_mgr_disable(channel); 220 dss_mgr_disable(&sdi->output);
219 221
220 dss_sdi_disable(); 222 dss_sdi_disable(sdi->dss);
221 223
222 dispc_runtime_put(); 224 dispc_runtime_put(sdi->dss->dispc);
223 225
224 regulator_disable(sdi.vdds_sdi_reg); 226 regulator_disable(sdi->vdds_sdi_reg);
225} 227}
226 228
227static void sdi_set_timings(struct omap_dss_device *dssdev, 229static void sdi_set_timings(struct omap_dss_device *dssdev,
228 struct videomode *vm) 230 struct videomode *vm)
229{ 231{
230 sdi.vm = *vm; 232 struct sdi_device *sdi = dssdev_to_sdi(dssdev);
233
234 sdi->vm = *vm;
231} 235}
232 236
233static void sdi_get_timings(struct omap_dss_device *dssdev, 237static void sdi_get_timings(struct omap_dss_device *dssdev,
234 struct videomode *vm) 238 struct videomode *vm)
235{ 239{
236 *vm = sdi.vm; 240 struct sdi_device *sdi = dssdev_to_sdi(dssdev);
241
242 *vm = sdi->vm;
237} 243}
238 244
239static int sdi_check_timings(struct omap_dss_device *dssdev, 245static int sdi_check_timings(struct omap_dss_device *dssdev,
240 struct videomode *vm) 246 struct videomode *vm)
241{ 247{
248 struct sdi_device *sdi = dssdev_to_sdi(dssdev);
242 enum omap_channel channel = dssdev->dispc_channel; 249 enum omap_channel channel = dssdev->dispc_channel;
243 250
244 if (!dispc_mgr_timings_ok(channel, vm)) 251 if (!dispc_mgr_timings_ok(sdi->dss->dispc, channel, vm))
245 return -EINVAL; 252 return -EINVAL;
246 253
247 if (vm->pixelclock == 0) 254 if (vm->pixelclock == 0)
@@ -250,21 +257,21 @@ static int sdi_check_timings(struct omap_dss_device *dssdev,
250 return 0; 257 return 0;
251} 258}
252 259
253static int sdi_init_regulator(void) 260static int sdi_init_regulator(struct sdi_device *sdi)
254{ 261{
255 struct regulator *vdds_sdi; 262 struct regulator *vdds_sdi;
256 263
257 if (sdi.vdds_sdi_reg) 264 if (sdi->vdds_sdi_reg)
258 return 0; 265 return 0;
259 266
260 vdds_sdi = devm_regulator_get(&sdi.pdev->dev, "vdds_sdi"); 267 vdds_sdi = devm_regulator_get(&sdi->pdev->dev, "vdds_sdi");
261 if (IS_ERR(vdds_sdi)) { 268 if (IS_ERR(vdds_sdi)) {
262 if (PTR_ERR(vdds_sdi) != -EPROBE_DEFER) 269 if (PTR_ERR(vdds_sdi) != -EPROBE_DEFER)
263 DSSERR("can't get VDDS_SDI regulator\n"); 270 DSSERR("can't get VDDS_SDI regulator\n");
264 return PTR_ERR(vdds_sdi); 271 return PTR_ERR(vdds_sdi);
265 } 272 }
266 273
267 sdi.vdds_sdi_reg = vdds_sdi; 274 sdi->vdds_sdi_reg = vdds_sdi;
268 275
269 return 0; 276 return 0;
270} 277}
@@ -272,14 +279,14 @@ static int sdi_init_regulator(void)
272static int sdi_connect(struct omap_dss_device *dssdev, 279static int sdi_connect(struct omap_dss_device *dssdev,
273 struct omap_dss_device *dst) 280 struct omap_dss_device *dst)
274{ 281{
275 enum omap_channel channel = dssdev->dispc_channel; 282 struct sdi_device *sdi = dssdev_to_sdi(dssdev);
276 int r; 283 int r;
277 284
278 r = sdi_init_regulator(); 285 r = sdi_init_regulator(sdi);
279 if (r) 286 if (r)
280 return r; 287 return r;
281 288
282 r = dss_mgr_connect(channel, dssdev); 289 r = dss_mgr_connect(&sdi->output, dssdev);
283 if (r) 290 if (r)
284 return r; 291 return r;
285 292
@@ -287,7 +294,7 @@ static int sdi_connect(struct omap_dss_device *dssdev,
287 if (r) { 294 if (r) {
288 DSSERR("failed to connect output to new device: %s\n", 295 DSSERR("failed to connect output to new device: %s\n",
289 dst->name); 296 dst->name);
290 dss_mgr_disconnect(channel, dssdev); 297 dss_mgr_disconnect(&sdi->output, dssdev);
291 return r; 298 return r;
292 } 299 }
293 300
@@ -297,7 +304,7 @@ static int sdi_connect(struct omap_dss_device *dssdev,
297static void sdi_disconnect(struct omap_dss_device *dssdev, 304static void sdi_disconnect(struct omap_dss_device *dssdev,
298 struct omap_dss_device *dst) 305 struct omap_dss_device *dst)
299{ 306{
300 enum omap_channel channel = dssdev->dispc_channel; 307 struct sdi_device *sdi = dssdev_to_sdi(dssdev);
301 308
302 WARN_ON(dst != dssdev->dst); 309 WARN_ON(dst != dssdev->dst);
303 310
@@ -306,7 +313,7 @@ static void sdi_disconnect(struct omap_dss_device *dssdev,
306 313
307 omapdss_output_unset_device(dssdev); 314 omapdss_output_unset_device(dssdev);
308 315
309 dss_mgr_disconnect(channel, dssdev); 316 dss_mgr_disconnect(&sdi->output, dssdev);
310} 317}
311 318
312static const struct omapdss_sdi_ops sdi_ops = { 319static const struct omapdss_sdi_ops sdi_ops = {
@@ -321,11 +328,11 @@ static const struct omapdss_sdi_ops sdi_ops = {
321 .get_timings = sdi_get_timings, 328 .get_timings = sdi_get_timings,
322}; 329};
323 330
324static void sdi_init_output(struct platform_device *pdev) 331static void sdi_init_output(struct sdi_device *sdi)
325{ 332{
326 struct omap_dss_device *out = &sdi.output; 333 struct omap_dss_device *out = &sdi->output;
327 334
328 out->dev = &pdev->dev; 335 out->dev = &sdi->pdev->dev;
329 out->id = OMAP_DSS_OUTPUT_SDI; 336 out->id = OMAP_DSS_OUTPUT_SDI;
330 out->output_type = OMAP_DISPLAY_TYPE_SDI; 337 out->output_type = OMAP_DISPLAY_TYPE_SDI;
331 out->name = "sdi.0"; 338 out->name = "sdi.0";
@@ -338,22 +345,28 @@ static void sdi_init_output(struct platform_device *pdev)
338 omapdss_register_output(out); 345 omapdss_register_output(out);
339} 346}
340 347
341static void sdi_uninit_output(struct platform_device *pdev) 348static void sdi_uninit_output(struct sdi_device *sdi)
342{ 349{
343 struct omap_dss_device *out = &sdi.output; 350 omapdss_unregister_output(&sdi->output);
344
345 omapdss_unregister_output(out);
346} 351}
347 352
348int sdi_init_port(struct platform_device *pdev, struct device_node *port) 353int sdi_init_port(struct dss_device *dss, struct platform_device *pdev,
354 struct device_node *port)
349{ 355{
356 struct sdi_device *sdi;
350 struct device_node *ep; 357 struct device_node *ep;
351 u32 datapairs; 358 u32 datapairs;
352 int r; 359 int r;
353 360
361 sdi = kzalloc(sizeof(*sdi), GFP_KERNEL);
362 if (!sdi)
363 return -ENOMEM;
364
354 ep = of_get_next_child(port, NULL); 365 ep = of_get_next_child(port, NULL);
355 if (!ep) 366 if (!ep) {
356 return 0; 367 r = 0;
368 goto err_free;
369 }
357 370
358 r = of_property_read_u32(ep, "datapairs", &datapairs); 371 r = of_property_read_u32(ep, "datapairs", &datapairs);
359 if (r) { 372 if (r) {
@@ -361,28 +374,33 @@ int sdi_init_port(struct platform_device *pdev, struct device_node *port)
361 goto err_datapairs; 374 goto err_datapairs;
362 } 375 }
363 376
364 sdi.datapairs = datapairs; 377 sdi->datapairs = datapairs;
378 sdi->dss = dss;
365 379
366 of_node_put(ep); 380 of_node_put(ep);
367 381
368 sdi.pdev = pdev; 382 sdi->pdev = pdev;
369 383 port->data = sdi;
370 sdi_init_output(pdev);
371 384
372 sdi.port_initialized = true; 385 sdi_init_output(sdi);
373 386
374 return 0; 387 return 0;
375 388
376err_datapairs: 389err_datapairs:
377 of_node_put(ep); 390 of_node_put(ep);
391err_free:
392 kfree(sdi);
378 393
379 return r; 394 return r;
380} 395}
381 396
382void sdi_uninit_port(struct device_node *port) 397void sdi_uninit_port(struct device_node *port)
383{ 398{
384 if (!sdi.port_initialized) 399 struct sdi_device *sdi = port->data;
400
401 if (!sdi)
385 return; 402 return;
386 403
387 sdi_uninit_output(sdi.pdev); 404 sdi_uninit_output(sdi);
405 kfree(sdi);
388} 406}
diff --git a/drivers/gpu/drm/omapdrm/dss/venc.c b/drivers/gpu/drm/omapdrm/dss/venc.c
index 6de9d734ddb9..24d1ced210bd 100644
--- a/drivers/gpu/drm/omapdrm/dss/venc.c
+++ b/drivers/gpu/drm/omapdrm/dss/venc.c
@@ -319,12 +319,15 @@ static enum venc_videomode venc_get_videomode(const struct videomode *vm)
319 return VENC_MODE_UNKNOWN; 319 return VENC_MODE_UNKNOWN;
320} 320}
321 321
322static struct { 322struct venc_device {
323 struct platform_device *pdev; 323 struct platform_device *pdev;
324 void __iomem *base; 324 void __iomem *base;
325 struct mutex venc_lock; 325 struct mutex venc_lock;
326 u32 wss_data; 326 u32 wss_data;
327 struct regulator *vdda_dac_reg; 327 struct regulator *vdda_dac_reg;
328 struct dss_device *dss;
329
330 struct dss_debugfs_entry *debugfs;
328 331
329 struct clk *tv_dac_clk; 332 struct clk *tv_dac_clk;
330 333
@@ -334,81 +337,87 @@ static struct {
334 bool requires_tv_dac_clk; 337 bool requires_tv_dac_clk;
335 338
336 struct omap_dss_device output; 339 struct omap_dss_device output;
337} venc; 340};
341
342#define dssdev_to_venc(dssdev) container_of(dssdev, struct venc_device, output)
338 343
339static inline void venc_write_reg(int idx, u32 val) 344static inline void venc_write_reg(struct venc_device *venc, int idx, u32 val)
340{ 345{
341 __raw_writel(val, venc.base + idx); 346 __raw_writel(val, venc->base + idx);
342} 347}
343 348
344static inline u32 venc_read_reg(int idx) 349static inline u32 venc_read_reg(struct venc_device *venc, int idx)
345{ 350{
346 u32 l = __raw_readl(venc.base + idx); 351 u32 l = __raw_readl(venc->base + idx);
347 return l; 352 return l;
348} 353}
349 354
350static void venc_write_config(const struct venc_config *config) 355static void venc_write_config(struct venc_device *venc,
356 const struct venc_config *config)
351{ 357{
352 DSSDBG("write venc conf\n"); 358 DSSDBG("write venc conf\n");
353 359
354 venc_write_reg(VENC_LLEN, config->llen); 360 venc_write_reg(venc, VENC_LLEN, config->llen);
355 venc_write_reg(VENC_FLENS, config->flens); 361 venc_write_reg(venc, VENC_FLENS, config->flens);
356 venc_write_reg(VENC_CC_CARR_WSS_CARR, config->cc_carr_wss_carr); 362 venc_write_reg(venc, VENC_CC_CARR_WSS_CARR, config->cc_carr_wss_carr);
357 venc_write_reg(VENC_C_PHASE, config->c_phase); 363 venc_write_reg(venc, VENC_C_PHASE, config->c_phase);
358 venc_write_reg(VENC_GAIN_U, config->gain_u); 364 venc_write_reg(venc, VENC_GAIN_U, config->gain_u);
359 venc_write_reg(VENC_GAIN_V, config->gain_v); 365 venc_write_reg(venc, VENC_GAIN_V, config->gain_v);
360 venc_write_reg(VENC_GAIN_Y, config->gain_y); 366 venc_write_reg(venc, VENC_GAIN_Y, config->gain_y);
361 venc_write_reg(VENC_BLACK_LEVEL, config->black_level); 367 venc_write_reg(venc, VENC_BLACK_LEVEL, config->black_level);
362 venc_write_reg(VENC_BLANK_LEVEL, config->blank_level); 368 venc_write_reg(venc, VENC_BLANK_LEVEL, config->blank_level);
363 venc_write_reg(VENC_M_CONTROL, config->m_control); 369 venc_write_reg(venc, VENC_M_CONTROL, config->m_control);
364 venc_write_reg(VENC_BSTAMP_WSS_DATA, config->bstamp_wss_data | 370 venc_write_reg(venc, VENC_BSTAMP_WSS_DATA, config->bstamp_wss_data |
365 venc.wss_data); 371 venc->wss_data);
366 venc_write_reg(VENC_S_CARR, config->s_carr); 372 venc_write_reg(venc, VENC_S_CARR, config->s_carr);
367 venc_write_reg(VENC_L21__WC_CTL, config->l21__wc_ctl); 373 venc_write_reg(venc, VENC_L21__WC_CTL, config->l21__wc_ctl);
368 venc_write_reg(VENC_SAVID__EAVID, config->savid__eavid); 374 venc_write_reg(venc, VENC_SAVID__EAVID, config->savid__eavid);
369 venc_write_reg(VENC_FLEN__FAL, config->flen__fal); 375 venc_write_reg(venc, VENC_FLEN__FAL, config->flen__fal);
370 venc_write_reg(VENC_LAL__PHASE_RESET, config->lal__phase_reset); 376 venc_write_reg(venc, VENC_LAL__PHASE_RESET, config->lal__phase_reset);
371 venc_write_reg(VENC_HS_INT_START_STOP_X, config->hs_int_start_stop_x); 377 venc_write_reg(venc, VENC_HS_INT_START_STOP_X,
372 venc_write_reg(VENC_HS_EXT_START_STOP_X, config->hs_ext_start_stop_x); 378 config->hs_int_start_stop_x);
373 venc_write_reg(VENC_VS_INT_START_X, config->vs_int_start_x); 379 venc_write_reg(venc, VENC_HS_EXT_START_STOP_X,
374 venc_write_reg(VENC_VS_INT_STOP_X__VS_INT_START_Y, 380 config->hs_ext_start_stop_x);
381 venc_write_reg(venc, VENC_VS_INT_START_X, config->vs_int_start_x);
382 venc_write_reg(venc, VENC_VS_INT_STOP_X__VS_INT_START_Y,
375 config->vs_int_stop_x__vs_int_start_y); 383 config->vs_int_stop_x__vs_int_start_y);
376 venc_write_reg(VENC_VS_INT_STOP_Y__VS_EXT_START_X, 384 venc_write_reg(venc, VENC_VS_INT_STOP_Y__VS_EXT_START_X,
377 config->vs_int_stop_y__vs_ext_start_x); 385 config->vs_int_stop_y__vs_ext_start_x);
378 venc_write_reg(VENC_VS_EXT_STOP_X__VS_EXT_START_Y, 386 venc_write_reg(venc, VENC_VS_EXT_STOP_X__VS_EXT_START_Y,
379 config->vs_ext_stop_x__vs_ext_start_y); 387 config->vs_ext_stop_x__vs_ext_start_y);
380 venc_write_reg(VENC_VS_EXT_STOP_Y, config->vs_ext_stop_y); 388 venc_write_reg(venc, VENC_VS_EXT_STOP_Y, config->vs_ext_stop_y);
381 venc_write_reg(VENC_AVID_START_STOP_X, config->avid_start_stop_x); 389 venc_write_reg(venc, VENC_AVID_START_STOP_X, config->avid_start_stop_x);
382 venc_write_reg(VENC_AVID_START_STOP_Y, config->avid_start_stop_y); 390 venc_write_reg(venc, VENC_AVID_START_STOP_Y, config->avid_start_stop_y);
383 venc_write_reg(VENC_FID_INT_START_X__FID_INT_START_Y, 391 venc_write_reg(venc, VENC_FID_INT_START_X__FID_INT_START_Y,
384 config->fid_int_start_x__fid_int_start_y); 392 config->fid_int_start_x__fid_int_start_y);
385 venc_write_reg(VENC_FID_INT_OFFSET_Y__FID_EXT_START_X, 393 venc_write_reg(venc, VENC_FID_INT_OFFSET_Y__FID_EXT_START_X,
386 config->fid_int_offset_y__fid_ext_start_x); 394 config->fid_int_offset_y__fid_ext_start_x);
387 venc_write_reg(VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y, 395 venc_write_reg(venc, VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y,
388 config->fid_ext_start_y__fid_ext_offset_y); 396 config->fid_ext_start_y__fid_ext_offset_y);
389 397
390 venc_write_reg(VENC_DAC_B__DAC_C, venc_read_reg(VENC_DAC_B__DAC_C)); 398 venc_write_reg(venc, VENC_DAC_B__DAC_C,
391 venc_write_reg(VENC_VIDOUT_CTRL, config->vidout_ctrl); 399 venc_read_reg(venc, VENC_DAC_B__DAC_C));
392 venc_write_reg(VENC_HFLTR_CTRL, config->hfltr_ctrl); 400 venc_write_reg(venc, VENC_VIDOUT_CTRL, config->vidout_ctrl);
393 venc_write_reg(VENC_X_COLOR, config->x_color); 401 venc_write_reg(venc, VENC_HFLTR_CTRL, config->hfltr_ctrl);
394 venc_write_reg(VENC_LINE21, config->line21); 402 venc_write_reg(venc, VENC_X_COLOR, config->x_color);
395 venc_write_reg(VENC_LN_SEL, config->ln_sel); 403 venc_write_reg(venc, VENC_LINE21, config->line21);
396 venc_write_reg(VENC_HTRIGGER_VTRIGGER, config->htrigger_vtrigger); 404 venc_write_reg(venc, VENC_LN_SEL, config->ln_sel);
397 venc_write_reg(VENC_TVDETGP_INT_START_STOP_X, 405 venc_write_reg(venc, VENC_HTRIGGER_VTRIGGER, config->htrigger_vtrigger);
406 venc_write_reg(venc, VENC_TVDETGP_INT_START_STOP_X,
398 config->tvdetgp_int_start_stop_x); 407 config->tvdetgp_int_start_stop_x);
399 venc_write_reg(VENC_TVDETGP_INT_START_STOP_Y, 408 venc_write_reg(venc, VENC_TVDETGP_INT_START_STOP_Y,
400 config->tvdetgp_int_start_stop_y); 409 config->tvdetgp_int_start_stop_y);
401 venc_write_reg(VENC_GEN_CTRL, config->gen_ctrl); 410 venc_write_reg(venc, VENC_GEN_CTRL, config->gen_ctrl);
402 venc_write_reg(VENC_F_CONTROL, config->f_control); 411 venc_write_reg(venc, VENC_F_CONTROL, config->f_control);
403 venc_write_reg(VENC_SYNC_CTRL, config->sync_ctrl); 412 venc_write_reg(venc, VENC_SYNC_CTRL, config->sync_ctrl);
404} 413}
405 414
406static void venc_reset(void) 415static void venc_reset(struct venc_device *venc)
407{ 416{
408 int t = 1000; 417 int t = 1000;
409 418
410 venc_write_reg(VENC_F_CONTROL, 1<<8); 419 venc_write_reg(venc, VENC_F_CONTROL, 1<<8);
411 while (venc_read_reg(VENC_F_CONTROL) & (1<<8)) { 420 while (venc_read_reg(venc, VENC_F_CONTROL) & (1<<8)) {
412 if (--t == 0) { 421 if (--t == 0) {
413 DSSERR("Failed to reset venc\n"); 422 DSSERR("Failed to reset venc\n");
414 return; 423 return;
@@ -422,24 +431,24 @@ static void venc_reset(void)
422#endif 431#endif
423} 432}
424 433
425static int venc_runtime_get(void) 434static int venc_runtime_get(struct venc_device *venc)
426{ 435{
427 int r; 436 int r;
428 437
429 DSSDBG("venc_runtime_get\n"); 438 DSSDBG("venc_runtime_get\n");
430 439
431 r = pm_runtime_get_sync(&venc.pdev->dev); 440 r = pm_runtime_get_sync(&venc->pdev->dev);
432 WARN_ON(r < 0); 441 WARN_ON(r < 0);
433 return r < 0 ? r : 0; 442 return r < 0 ? r : 0;
434} 443}
435 444
436static void venc_runtime_put(void) 445static void venc_runtime_put(struct venc_device *venc)
437{ 446{
438 int r; 447 int r;
439 448
440 DSSDBG("venc_runtime_put\n"); 449 DSSDBG("venc_runtime_put\n");
441 450
442 r = pm_runtime_put_sync(&venc.pdev->dev); 451 r = pm_runtime_put_sync(&venc->pdev->dev);
443 WARN_ON(r < 0 && r != -ENOSYS); 452 WARN_ON(r < 0 && r != -ENOSYS);
444} 453}
445 454
@@ -455,119 +464,119 @@ static const struct venc_config *venc_timings_to_config(struct videomode *vm)
455 } 464 }
456} 465}
457 466
458static int venc_power_on(struct omap_dss_device *dssdev) 467static int venc_power_on(struct venc_device *venc)
459{ 468{
460 enum omap_channel channel = dssdev->dispc_channel;
461 u32 l; 469 u32 l;
462 int r; 470 int r;
463 471
464 r = venc_runtime_get(); 472 r = venc_runtime_get(venc);
465 if (r) 473 if (r)
466 goto err0; 474 goto err0;
467 475
468 venc_reset(); 476 venc_reset(venc);
469 venc_write_config(venc_timings_to_config(&venc.vm)); 477 venc_write_config(venc, venc_timings_to_config(&venc->vm));
470 478
471 dss_set_venc_output(venc.type); 479 dss_set_venc_output(venc->dss, venc->type);
472 dss_set_dac_pwrdn_bgz(1); 480 dss_set_dac_pwrdn_bgz(venc->dss, 1);
473 481
474 l = 0; 482 l = 0;
475 483
476 if (venc.type == OMAP_DSS_VENC_TYPE_COMPOSITE) 484 if (venc->type == OMAP_DSS_VENC_TYPE_COMPOSITE)
477 l |= 1 << 1; 485 l |= 1 << 1;
478 else /* S-Video */ 486 else /* S-Video */
479 l |= (1 << 0) | (1 << 2); 487 l |= (1 << 0) | (1 << 2);
480 488
481 if (venc.invert_polarity == false) 489 if (venc->invert_polarity == false)
482 l |= 1 << 3; 490 l |= 1 << 3;
483 491
484 venc_write_reg(VENC_OUTPUT_CONTROL, l); 492 venc_write_reg(venc, VENC_OUTPUT_CONTROL, l);
485 493
486 dss_mgr_set_timings(channel, &venc.vm); 494 dss_mgr_set_timings(&venc->output, &venc->vm);
487 495
488 r = regulator_enable(venc.vdda_dac_reg); 496 r = regulator_enable(venc->vdda_dac_reg);
489 if (r) 497 if (r)
490 goto err1; 498 goto err1;
491 499
492 r = dss_mgr_enable(channel); 500 r = dss_mgr_enable(&venc->output);
493 if (r) 501 if (r)
494 goto err2; 502 goto err2;
495 503
496 return 0; 504 return 0;
497 505
498err2: 506err2:
499 regulator_disable(venc.vdda_dac_reg); 507 regulator_disable(venc->vdda_dac_reg);
500err1: 508err1:
501 venc_write_reg(VENC_OUTPUT_CONTROL, 0); 509 venc_write_reg(venc, VENC_OUTPUT_CONTROL, 0);
502 dss_set_dac_pwrdn_bgz(0); 510 dss_set_dac_pwrdn_bgz(venc->dss, 0);
503 511
504 venc_runtime_put(); 512 venc_runtime_put(venc);
505err0: 513err0:
506 return r; 514 return r;
507} 515}
508 516
509static void venc_power_off(struct omap_dss_device *dssdev) 517static void venc_power_off(struct venc_device *venc)
510{ 518{
511 enum omap_channel channel = dssdev->dispc_channel; 519 venc_write_reg(venc, VENC_OUTPUT_CONTROL, 0);
520 dss_set_dac_pwrdn_bgz(venc->dss, 0);
512 521
513 venc_write_reg(VENC_OUTPUT_CONTROL, 0); 522 dss_mgr_disable(&venc->output);
514 dss_set_dac_pwrdn_bgz(0);
515 523
516 dss_mgr_disable(channel); 524 regulator_disable(venc->vdda_dac_reg);
517 525
518 regulator_disable(venc.vdda_dac_reg); 526 venc_runtime_put(venc);
519
520 venc_runtime_put();
521} 527}
522 528
523static int venc_display_enable(struct omap_dss_device *dssdev) 529static int venc_display_enable(struct omap_dss_device *dssdev)
524{ 530{
525 struct omap_dss_device *out = &venc.output; 531 struct venc_device *venc = dssdev_to_venc(dssdev);
526 int r; 532 int r;
527 533
528 DSSDBG("venc_display_enable\n"); 534 DSSDBG("venc_display_enable\n");
529 535
530 mutex_lock(&venc.venc_lock); 536 mutex_lock(&venc->venc_lock);
531 537
532 if (!out->dispc_channel_connected) { 538 if (!dssdev->dispc_channel_connected) {
533 DSSERR("Failed to enable display: no output/manager\n"); 539 DSSERR("Failed to enable display: no output/manager\n");
534 r = -ENODEV; 540 r = -ENODEV;
535 goto err0; 541 goto err0;
536 } 542 }
537 543
538 r = venc_power_on(dssdev); 544 r = venc_power_on(venc);
539 if (r) 545 if (r)
540 goto err0; 546 goto err0;
541 547
542 venc.wss_data = 0; 548 venc->wss_data = 0;
543 549
544 mutex_unlock(&venc.venc_lock); 550 mutex_unlock(&venc->venc_lock);
545 551
546 return 0; 552 return 0;
547err0: 553err0:
548 mutex_unlock(&venc.venc_lock); 554 mutex_unlock(&venc->venc_lock);
549 return r; 555 return r;
550} 556}
551 557
552static void venc_display_disable(struct omap_dss_device *dssdev) 558static void venc_display_disable(struct omap_dss_device *dssdev)
553{ 559{
560 struct venc_device *venc = dssdev_to_venc(dssdev);
561
554 DSSDBG("venc_display_disable\n"); 562 DSSDBG("venc_display_disable\n");
555 563
556 mutex_lock(&venc.venc_lock); 564 mutex_lock(&venc->venc_lock);
557 565
558 venc_power_off(dssdev); 566 venc_power_off(venc);
559 567
560 mutex_unlock(&venc.venc_lock); 568 mutex_unlock(&venc->venc_lock);
561} 569}
562 570
563static void venc_set_timings(struct omap_dss_device *dssdev, 571static void venc_set_timings(struct omap_dss_device *dssdev,
564 struct videomode *vm) 572 struct videomode *vm)
565{ 573{
574 struct venc_device *venc = dssdev_to_venc(dssdev);
566 struct videomode actual_vm; 575 struct videomode actual_vm;
567 576
568 DSSDBG("venc_set_timings\n"); 577 DSSDBG("venc_set_timings\n");
569 578
570 mutex_lock(&venc.venc_lock); 579 mutex_lock(&venc->venc_lock);
571 580
572 switch (venc_get_videomode(vm)) { 581 switch (venc_get_videomode(vm)) {
573 default: 582 default:
@@ -581,14 +590,14 @@ static void venc_set_timings(struct omap_dss_device *dssdev,
581 } 590 }
582 591
583 /* Reset WSS data when the TV standard changes. */ 592 /* Reset WSS data when the TV standard changes. */
584 if (memcmp(&venc.vm, &actual_vm, sizeof(actual_vm))) 593 if (memcmp(&venc->vm, &actual_vm, sizeof(actual_vm)))
585 venc.wss_data = 0; 594 venc->wss_data = 0;
586 595
587 venc.vm = actual_vm; 596 venc->vm = actual_vm;
588 597
589 dispc_set_tv_pclk(13500000); 598 dispc_set_tv_pclk(venc->dss->dispc, 13500000);
590 599
591 mutex_unlock(&venc.venc_lock); 600 mutex_unlock(&venc->venc_lock);
592} 601}
593 602
594static int venc_check_timings(struct omap_dss_device *dssdev, 603static int venc_check_timings(struct omap_dss_device *dssdev,
@@ -608,127 +617,136 @@ static int venc_check_timings(struct omap_dss_device *dssdev,
608static void venc_get_timings(struct omap_dss_device *dssdev, 617static void venc_get_timings(struct omap_dss_device *dssdev,
609 struct videomode *vm) 618 struct videomode *vm)
610{ 619{
611 mutex_lock(&venc.venc_lock); 620 struct venc_device *venc = dssdev_to_venc(dssdev);
612 621
613 *vm = venc.vm; 622 mutex_lock(&venc->venc_lock);
614 623
615 mutex_unlock(&venc.venc_lock); 624 *vm = venc->vm;
625
626 mutex_unlock(&venc->venc_lock);
616} 627}
617 628
618static u32 venc_get_wss(struct omap_dss_device *dssdev) 629static u32 venc_get_wss(struct omap_dss_device *dssdev)
619{ 630{
631 struct venc_device *venc = dssdev_to_venc(dssdev);
632
620 /* Invert due to VENC_L21_WC_CTL:INV=1 */ 633 /* Invert due to VENC_L21_WC_CTL:INV=1 */
621 return (venc.wss_data >> 8) ^ 0xfffff; 634 return (venc->wss_data >> 8) ^ 0xfffff;
622} 635}
623 636
624static int venc_set_wss(struct omap_dss_device *dssdev, u32 wss) 637static int venc_set_wss(struct omap_dss_device *dssdev, u32 wss)
625{ 638{
639 struct venc_device *venc = dssdev_to_venc(dssdev);
626 const struct venc_config *config; 640 const struct venc_config *config;
627 int r; 641 int r;
628 642
629 DSSDBG("venc_set_wss\n"); 643 DSSDBG("venc_set_wss\n");
630 644
631 mutex_lock(&venc.venc_lock); 645 mutex_lock(&venc->venc_lock);
632 646
633 config = venc_timings_to_config(&venc.vm); 647 config = venc_timings_to_config(&venc->vm);
634 648
635 /* Invert due to VENC_L21_WC_CTL:INV=1 */ 649 /* Invert due to VENC_L21_WC_CTL:INV=1 */
636 venc.wss_data = (wss ^ 0xfffff) << 8; 650 venc->wss_data = (wss ^ 0xfffff) << 8;
637 651
638 r = venc_runtime_get(); 652 r = venc_runtime_get(venc);
639 if (r) 653 if (r)
640 goto err; 654 goto err;
641 655
642 venc_write_reg(VENC_BSTAMP_WSS_DATA, config->bstamp_wss_data | 656 venc_write_reg(venc, VENC_BSTAMP_WSS_DATA, config->bstamp_wss_data |
643 venc.wss_data); 657 venc->wss_data);
644 658
645 venc_runtime_put(); 659 venc_runtime_put(venc);
646 660
647err: 661err:
648 mutex_unlock(&venc.venc_lock); 662 mutex_unlock(&venc->venc_lock);
649 663
650 return r; 664 return r;
651} 665}
652 666
653static int venc_init_regulator(void) 667static int venc_init_regulator(struct venc_device *venc)
654{ 668{
655 struct regulator *vdda_dac; 669 struct regulator *vdda_dac;
656 670
657 if (venc.vdda_dac_reg != NULL) 671 if (venc->vdda_dac_reg != NULL)
658 return 0; 672 return 0;
659 673
660 vdda_dac = devm_regulator_get(&venc.pdev->dev, "vdda"); 674 vdda_dac = devm_regulator_get(&venc->pdev->dev, "vdda");
661 if (IS_ERR(vdda_dac)) { 675 if (IS_ERR(vdda_dac)) {
662 if (PTR_ERR(vdda_dac) != -EPROBE_DEFER) 676 if (PTR_ERR(vdda_dac) != -EPROBE_DEFER)
663 DSSERR("can't get VDDA_DAC regulator\n"); 677 DSSERR("can't get VDDA_DAC regulator\n");
664 return PTR_ERR(vdda_dac); 678 return PTR_ERR(vdda_dac);
665 } 679 }
666 680
667 venc.vdda_dac_reg = vdda_dac; 681 venc->vdda_dac_reg = vdda_dac;
668 682
669 return 0; 683 return 0;
670} 684}
671 685
672static void venc_dump_regs(struct seq_file *s) 686static int venc_dump_regs(struct seq_file *s, void *p)
673{ 687{
674#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, venc_read_reg(r)) 688 struct venc_device *venc = s->private;
675 689
676 if (venc_runtime_get()) 690#define DUMPREG(venc, r) \
677 return; 691 seq_printf(s, "%-35s %08x\n", #r, venc_read_reg(venc, r))
692
693 if (venc_runtime_get(venc))
694 return 0;
678 695
679 DUMPREG(VENC_F_CONTROL); 696 DUMPREG(venc, VENC_F_CONTROL);
680 DUMPREG(VENC_VIDOUT_CTRL); 697 DUMPREG(venc, VENC_VIDOUT_CTRL);
681 DUMPREG(VENC_SYNC_CTRL); 698 DUMPREG(venc, VENC_SYNC_CTRL);
682 DUMPREG(VENC_LLEN); 699 DUMPREG(venc, VENC_LLEN);
683 DUMPREG(VENC_FLENS); 700 DUMPREG(venc, VENC_FLENS);
684 DUMPREG(VENC_HFLTR_CTRL); 701 DUMPREG(venc, VENC_HFLTR_CTRL);
685 DUMPREG(VENC_CC_CARR_WSS_CARR); 702 DUMPREG(venc, VENC_CC_CARR_WSS_CARR);
686 DUMPREG(VENC_C_PHASE); 703 DUMPREG(venc, VENC_C_PHASE);
687 DUMPREG(VENC_GAIN_U); 704 DUMPREG(venc, VENC_GAIN_U);
688 DUMPREG(VENC_GAIN_V); 705 DUMPREG(venc, VENC_GAIN_V);
689 DUMPREG(VENC_GAIN_Y); 706 DUMPREG(venc, VENC_GAIN_Y);
690 DUMPREG(VENC_BLACK_LEVEL); 707 DUMPREG(venc, VENC_BLACK_LEVEL);
691 DUMPREG(VENC_BLANK_LEVEL); 708 DUMPREG(venc, VENC_BLANK_LEVEL);
692 DUMPREG(VENC_X_COLOR); 709 DUMPREG(venc, VENC_X_COLOR);
693 DUMPREG(VENC_M_CONTROL); 710 DUMPREG(venc, VENC_M_CONTROL);
694 DUMPREG(VENC_BSTAMP_WSS_DATA); 711 DUMPREG(venc, VENC_BSTAMP_WSS_DATA);
695 DUMPREG(VENC_S_CARR); 712 DUMPREG(venc, VENC_S_CARR);
696 DUMPREG(VENC_LINE21); 713 DUMPREG(venc, VENC_LINE21);
697 DUMPREG(VENC_LN_SEL); 714 DUMPREG(venc, VENC_LN_SEL);
698 DUMPREG(VENC_L21__WC_CTL); 715 DUMPREG(venc, VENC_L21__WC_CTL);
699 DUMPREG(VENC_HTRIGGER_VTRIGGER); 716 DUMPREG(venc, VENC_HTRIGGER_VTRIGGER);
700 DUMPREG(VENC_SAVID__EAVID); 717 DUMPREG(venc, VENC_SAVID__EAVID);
701 DUMPREG(VENC_FLEN__FAL); 718 DUMPREG(venc, VENC_FLEN__FAL);
702 DUMPREG(VENC_LAL__PHASE_RESET); 719 DUMPREG(venc, VENC_LAL__PHASE_RESET);
703 DUMPREG(VENC_HS_INT_START_STOP_X); 720 DUMPREG(venc, VENC_HS_INT_START_STOP_X);
704 DUMPREG(VENC_HS_EXT_START_STOP_X); 721 DUMPREG(venc, VENC_HS_EXT_START_STOP_X);
705 DUMPREG(VENC_VS_INT_START_X); 722 DUMPREG(venc, VENC_VS_INT_START_X);
706 DUMPREG(VENC_VS_INT_STOP_X__VS_INT_START_Y); 723 DUMPREG(venc, VENC_VS_INT_STOP_X__VS_INT_START_Y);
707 DUMPREG(VENC_VS_INT_STOP_Y__VS_EXT_START_X); 724 DUMPREG(venc, VENC_VS_INT_STOP_Y__VS_EXT_START_X);
708 DUMPREG(VENC_VS_EXT_STOP_X__VS_EXT_START_Y); 725 DUMPREG(venc, VENC_VS_EXT_STOP_X__VS_EXT_START_Y);
709 DUMPREG(VENC_VS_EXT_STOP_Y); 726 DUMPREG(venc, VENC_VS_EXT_STOP_Y);
710 DUMPREG(VENC_AVID_START_STOP_X); 727 DUMPREG(venc, VENC_AVID_START_STOP_X);
711 DUMPREG(VENC_AVID_START_STOP_Y); 728 DUMPREG(venc, VENC_AVID_START_STOP_Y);
712 DUMPREG(VENC_FID_INT_START_X__FID_INT_START_Y); 729 DUMPREG(venc, VENC_FID_INT_START_X__FID_INT_START_Y);
713 DUMPREG(VENC_FID_INT_OFFSET_Y__FID_EXT_START_X); 730 DUMPREG(venc, VENC_FID_INT_OFFSET_Y__FID_EXT_START_X);
714 DUMPREG(VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y); 731 DUMPREG(venc, VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y);
715 DUMPREG(VENC_TVDETGP_INT_START_STOP_X); 732 DUMPREG(venc, VENC_TVDETGP_INT_START_STOP_X);
716 DUMPREG(VENC_TVDETGP_INT_START_STOP_Y); 733 DUMPREG(venc, VENC_TVDETGP_INT_START_STOP_Y);
717 DUMPREG(VENC_GEN_CTRL); 734 DUMPREG(venc, VENC_GEN_CTRL);
718 DUMPREG(VENC_OUTPUT_CONTROL); 735 DUMPREG(venc, VENC_OUTPUT_CONTROL);
719 DUMPREG(VENC_OUTPUT_TEST); 736 DUMPREG(venc, VENC_OUTPUT_TEST);
720 737
721 venc_runtime_put(); 738 venc_runtime_put(venc);
722 739
723#undef DUMPREG 740#undef DUMPREG
741 return 0;
724} 742}
725 743
726static int venc_get_clocks(struct platform_device *pdev) 744static int venc_get_clocks(struct venc_device *venc)
727{ 745{
728 struct clk *clk; 746 struct clk *clk;
729 747
730 if (venc.requires_tv_dac_clk) { 748 if (venc->requires_tv_dac_clk) {
731 clk = devm_clk_get(&pdev->dev, "tv_dac_clk"); 749 clk = devm_clk_get(&venc->pdev->dev, "tv_dac_clk");
732 if (IS_ERR(clk)) { 750 if (IS_ERR(clk)) {
733 DSSERR("can't get tv_dac_clk\n"); 751 DSSERR("can't get tv_dac_clk\n");
734 return PTR_ERR(clk); 752 return PTR_ERR(clk);
@@ -737,7 +755,7 @@ static int venc_get_clocks(struct platform_device *pdev)
737 clk = NULL; 755 clk = NULL;
738 } 756 }
739 757
740 venc.tv_dac_clk = clk; 758 venc->tv_dac_clk = clk;
741 759
742 return 0; 760 return 0;
743} 761}
@@ -745,14 +763,14 @@ static int venc_get_clocks(struct platform_device *pdev)
745static int venc_connect(struct omap_dss_device *dssdev, 763static int venc_connect(struct omap_dss_device *dssdev,
746 struct omap_dss_device *dst) 764 struct omap_dss_device *dst)
747{ 765{
748 enum omap_channel channel = dssdev->dispc_channel; 766 struct venc_device *venc = dssdev_to_venc(dssdev);
749 int r; 767 int r;
750 768
751 r = venc_init_regulator(); 769 r = venc_init_regulator(venc);
752 if (r) 770 if (r)
753 return r; 771 return r;
754 772
755 r = dss_mgr_connect(channel, dssdev); 773 r = dss_mgr_connect(&venc->output, dssdev);
756 if (r) 774 if (r)
757 return r; 775 return r;
758 776
@@ -760,7 +778,7 @@ static int venc_connect(struct omap_dss_device *dssdev,
760 if (r) { 778 if (r) {
761 DSSERR("failed to connect output to new device: %s\n", 779 DSSERR("failed to connect output to new device: %s\n",
762 dst->name); 780 dst->name);
763 dss_mgr_disconnect(channel, dssdev); 781 dss_mgr_disconnect(&venc->output, dssdev);
764 return r; 782 return r;
765 } 783 }
766 784
@@ -770,7 +788,7 @@ static int venc_connect(struct omap_dss_device *dssdev,
770static void venc_disconnect(struct omap_dss_device *dssdev, 788static void venc_disconnect(struct omap_dss_device *dssdev,
771 struct omap_dss_device *dst) 789 struct omap_dss_device *dst)
772{ 790{
773 enum omap_channel channel = dssdev->dispc_channel; 791 struct venc_device *venc = dssdev_to_venc(dssdev);
774 792
775 WARN_ON(dst != dssdev->dst); 793 WARN_ON(dst != dssdev->dst);
776 794
@@ -779,7 +797,7 @@ static void venc_disconnect(struct omap_dss_device *dssdev,
779 797
780 omapdss_output_unset_device(dssdev); 798 omapdss_output_unset_device(dssdev);
781 799
782 dss_mgr_disconnect(channel, dssdev); 800 dss_mgr_disconnect(&venc->output, dssdev);
783} 801}
784 802
785static const struct omapdss_atv_ops venc_ops = { 803static const struct omapdss_atv_ops venc_ops = {
@@ -797,11 +815,11 @@ static const struct omapdss_atv_ops venc_ops = {
797 .get_wss = venc_get_wss, 815 .get_wss = venc_get_wss,
798}; 816};
799 817
800static void venc_init_output(struct platform_device *pdev) 818static void venc_init_output(struct venc_device *venc)
801{ 819{
802 struct omap_dss_device *out = &venc.output; 820 struct omap_dss_device *out = &venc->output;
803 821
804 out->dev = &pdev->dev; 822 out->dev = &venc->pdev->dev;
805 out->id = OMAP_DSS_OUTPUT_VENC; 823 out->id = OMAP_DSS_OUTPUT_VENC;
806 out->output_type = OMAP_DISPLAY_TYPE_VENC; 824 out->output_type = OMAP_DISPLAY_TYPE_VENC;
807 out->name = "venc.0"; 825 out->name = "venc.0";
@@ -812,16 +830,14 @@ static void venc_init_output(struct platform_device *pdev)
812 omapdss_register_output(out); 830 omapdss_register_output(out);
813} 831}
814 832
815static void venc_uninit_output(struct platform_device *pdev) 833static void venc_uninit_output(struct venc_device *venc)
816{ 834{
817 struct omap_dss_device *out = &venc.output; 835 omapdss_unregister_output(&venc->output);
818
819 omapdss_unregister_output(out);
820} 836}
821 837
822static int venc_probe_of(struct platform_device *pdev) 838static int venc_probe_of(struct venc_device *venc)
823{ 839{
824 struct device_node *node = pdev->dev.of_node; 840 struct device_node *node = venc->pdev->dev.of_node;
825 struct device_node *ep; 841 struct device_node *ep;
826 u32 channels; 842 u32 channels;
827 int r; 843 int r;
@@ -830,24 +846,25 @@ static int venc_probe_of(struct platform_device *pdev)
830 if (!ep) 846 if (!ep)
831 return 0; 847 return 0;
832 848
833 venc.invert_polarity = of_property_read_bool(ep, "ti,invert-polarity"); 849 venc->invert_polarity = of_property_read_bool(ep, "ti,invert-polarity");
834 850
835 r = of_property_read_u32(ep, "ti,channels", &channels); 851 r = of_property_read_u32(ep, "ti,channels", &channels);
836 if (r) { 852 if (r) {
837 dev_err(&pdev->dev, 853 dev_err(&venc->pdev->dev,
838 "failed to read property 'ti,channels': %d\n", r); 854 "failed to read property 'ti,channels': %d\n", r);
839 goto err; 855 goto err;
840 } 856 }
841 857
842 switch (channels) { 858 switch (channels) {
843 case 1: 859 case 1:
844 venc.type = OMAP_DSS_VENC_TYPE_COMPOSITE; 860 venc->type = OMAP_DSS_VENC_TYPE_COMPOSITE;
845 break; 861 break;
846 case 2: 862 case 2:
847 venc.type = OMAP_DSS_VENC_TYPE_SVIDEO; 863 venc->type = OMAP_DSS_VENC_TYPE_SVIDEO;
848 break; 864 break;
849 default: 865 default:
850 dev_err(&pdev->dev, "bad channel propert '%d'\n", channels); 866 dev_err(&venc->pdev->dev, "bad channel propert '%d'\n",
867 channels);
851 r = -EINVAL; 868 r = -EINVAL;
852 goto err; 869 goto err;
853 } 870 }
@@ -871,65 +888,82 @@ static const struct soc_device_attribute venc_soc_devices[] = {
871static int venc_bind(struct device *dev, struct device *master, void *data) 888static int venc_bind(struct device *dev, struct device *master, void *data)
872{ 889{
873 struct platform_device *pdev = to_platform_device(dev); 890 struct platform_device *pdev = to_platform_device(dev);
891 struct dss_device *dss = dss_get_device(master);
892 struct venc_device *venc;
874 u8 rev_id; 893 u8 rev_id;
875 struct resource *venc_mem; 894 struct resource *venc_mem;
876 int r; 895 int r;
877 896
878 venc.pdev = pdev; 897 venc = kzalloc(sizeof(*venc), GFP_KERNEL);
898 if (!venc)
899 return -ENOMEM;
900
901 venc->pdev = pdev;
902 venc->dss = dss;
903 dev_set_drvdata(dev, venc);
879 904
880 /* The OMAP34xx, OMAP35xx and AM35xx VENC require the TV DAC clock. */ 905 /* The OMAP34xx, OMAP35xx and AM35xx VENC require the TV DAC clock. */
881 if (soc_device_match(venc_soc_devices)) 906 if (soc_device_match(venc_soc_devices))
882 venc.requires_tv_dac_clk = true; 907 venc->requires_tv_dac_clk = true;
883 908
884 mutex_init(&venc.venc_lock); 909 mutex_init(&venc->venc_lock);
885 910
886 venc.wss_data = 0; 911 venc->wss_data = 0;
887 912
888 venc_mem = platform_get_resource(venc.pdev, IORESOURCE_MEM, 0); 913 venc_mem = platform_get_resource(venc->pdev, IORESOURCE_MEM, 0);
889 venc.base = devm_ioremap_resource(&pdev->dev, venc_mem); 914 venc->base = devm_ioremap_resource(&pdev->dev, venc_mem);
890 if (IS_ERR(venc.base)) 915 if (IS_ERR(venc->base)) {
891 return PTR_ERR(venc.base); 916 r = PTR_ERR(venc->base);
917 goto err_free;
918 }
892 919
893 r = venc_get_clocks(pdev); 920 r = venc_get_clocks(venc);
894 if (r) 921 if (r)
895 return r; 922 goto err_free;
896 923
897 pm_runtime_enable(&pdev->dev); 924 pm_runtime_enable(&pdev->dev);
898 925
899 r = venc_runtime_get(); 926 r = venc_runtime_get(venc);
900 if (r) 927 if (r)
901 goto err_runtime_get; 928 goto err_runtime_get;
902 929
903 rev_id = (u8)(venc_read_reg(VENC_REV_ID) & 0xff); 930 rev_id = (u8)(venc_read_reg(venc, VENC_REV_ID) & 0xff);
904 dev_dbg(&pdev->dev, "OMAP VENC rev %d\n", rev_id); 931 dev_dbg(&pdev->dev, "OMAP VENC rev %d\n", rev_id);
905 932
906 venc_runtime_put(); 933 venc_runtime_put(venc);
907 934
908 r = venc_probe_of(pdev); 935 r = venc_probe_of(venc);
909 if (r) { 936 if (r) {
910 DSSERR("Invalid DT data\n"); 937 DSSERR("Invalid DT data\n");
911 goto err_probe_of; 938 goto err_probe_of;
912 } 939 }
913 940
914 dss_debugfs_create_file("venc", venc_dump_regs); 941 venc->debugfs = dss_debugfs_create_file(dss, "venc", venc_dump_regs,
942 venc);
915 943
916 venc_init_output(pdev); 944 venc_init_output(venc);
917 945
918 return 0; 946 return 0;
919 947
920err_probe_of: 948err_probe_of:
921err_runtime_get: 949err_runtime_get:
922 pm_runtime_disable(&pdev->dev); 950 pm_runtime_disable(&pdev->dev);
951err_free:
952 kfree(venc);
923 return r; 953 return r;
924} 954}
925 955
926static void venc_unbind(struct device *dev, struct device *master, void *data) 956static void venc_unbind(struct device *dev, struct device *master, void *data)
927{ 957{
928 struct platform_device *pdev = to_platform_device(dev); 958 struct venc_device *venc = dev_get_drvdata(dev);
929 959
930 venc_uninit_output(pdev); 960 dss_debugfs_remove_file(venc->debugfs);
931 961
932 pm_runtime_disable(&pdev->dev); 962 venc_uninit_output(venc);
963
964 pm_runtime_disable(dev);
965
966 kfree(venc);
933} 967}
934 968
935static const struct component_ops venc_component_ops = { 969static const struct component_ops venc_component_ops = {
@@ -950,24 +984,27 @@ static int venc_remove(struct platform_device *pdev)
950 984
951static int venc_runtime_suspend(struct device *dev) 985static int venc_runtime_suspend(struct device *dev)
952{ 986{
953 if (venc.tv_dac_clk) 987 struct venc_device *venc = dev_get_drvdata(dev);
954 clk_disable_unprepare(venc.tv_dac_clk); 988
989 if (venc->tv_dac_clk)
990 clk_disable_unprepare(venc->tv_dac_clk);
955 991
956 dispc_runtime_put(); 992 dispc_runtime_put(venc->dss->dispc);
957 993
958 return 0; 994 return 0;
959} 995}
960 996
961static int venc_runtime_resume(struct device *dev) 997static int venc_runtime_resume(struct device *dev)
962{ 998{
999 struct venc_device *venc = dev_get_drvdata(dev);
963 int r; 1000 int r;
964 1001
965 r = dispc_runtime_get(); 1002 r = dispc_runtime_get(venc->dss->dispc);
966 if (r < 0) 1003 if (r < 0)
967 return r; 1004 return r;
968 1005
969 if (venc.tv_dac_clk) 1006 if (venc->tv_dac_clk)
970 clk_prepare_enable(venc.tv_dac_clk); 1007 clk_prepare_enable(venc->tv_dac_clk);
971 1008
972 return 0; 1009 return 0;
973} 1010}
diff --git a/drivers/gpu/drm/omapdrm/dss/video-pll.c b/drivers/gpu/drm/omapdrm/dss/video-pll.c
index bbedac797927..585ed94ccf17 100644
--- a/drivers/gpu/drm/omapdrm/dss/video-pll.c
+++ b/drivers/gpu/drm/omapdrm/dss/video-pll.c
@@ -64,11 +64,11 @@ static int dss_video_pll_enable(struct dss_pll *pll)
64 struct dss_video_pll *vpll = container_of(pll, struct dss_video_pll, pll); 64 struct dss_video_pll *vpll = container_of(pll, struct dss_video_pll, pll);
65 int r; 65 int r;
66 66
67 r = dss_runtime_get(); 67 r = dss_runtime_get(pll->dss);
68 if (r) 68 if (r)
69 return r; 69 return r;
70 70
71 dss_ctrl_pll_enable(pll->id, true); 71 dss_ctrl_pll_enable(pll, true);
72 72
73 dss_dpll_enable_scp_clk(vpll); 73 dss_dpll_enable_scp_clk(vpll);
74 74
@@ -82,8 +82,8 @@ static int dss_video_pll_enable(struct dss_pll *pll)
82 82
83err_reset: 83err_reset:
84 dss_dpll_disable_scp_clk(vpll); 84 dss_dpll_disable_scp_clk(vpll);
85 dss_ctrl_pll_enable(pll->id, false); 85 dss_ctrl_pll_enable(pll, false);
86 dss_runtime_put(); 86 dss_runtime_put(pll->dss);
87 87
88 return r; 88 return r;
89} 89}
@@ -96,9 +96,9 @@ static void dss_video_pll_disable(struct dss_pll *pll)
96 96
97 dss_dpll_disable_scp_clk(vpll); 97 dss_dpll_disable_scp_clk(vpll);
98 98
99 dss_ctrl_pll_enable(pll->id, false); 99 dss_ctrl_pll_enable(pll, false);
100 100
101 dss_runtime_put(); 101 dss_runtime_put(pll->dss);
102} 102}
103 103
104static const struct dss_pll_ops dss_pll_ops = { 104static const struct dss_pll_ops dss_pll_ops = {
@@ -136,8 +136,9 @@ static const struct dss_pll_hw dss_dra7_video_pll_hw = {
136 .errata_i886 = true, 136 .errata_i886 = true,
137}; 137};
138 138
139struct dss_pll *dss_video_pll_init(struct platform_device *pdev, int id, 139struct dss_pll *dss_video_pll_init(struct dss_device *dss,
140 struct regulator *regulator) 140 struct platform_device *pdev, int id,
141 struct regulator *regulator)
141{ 142{
142 const char * const reg_name[] = { "pll1", "pll2" }; 143 const char * const reg_name[] = { "pll1", "pll2" };
143 const char * const clkctrl_name[] = { "pll1_clkctrl", "pll2_clkctrl" }; 144 const char * const clkctrl_name[] = { "pll1_clkctrl", "pll2_clkctrl" };
@@ -190,7 +191,7 @@ struct dss_pll *dss_video_pll_init(struct platform_device *pdev, int id,
190 pll->hw = &dss_dra7_video_pll_hw; 191 pll->hw = &dss_dra7_video_pll_hw;
191 pll->ops = &dss_pll_ops; 192 pll->ops = &dss_pll_ops;
192 193
193 r = dss_pll_register(pll); 194 r = dss_pll_register(dss, pll);
194 if (r) 195 if (r)
195 return ERR_PTR(r); 196 return ERR_PTR(r);
196 197
diff --git a/drivers/gpu/drm/omapdrm/omap_crtc.c b/drivers/gpu/drm/omapdrm/omap_crtc.c
index 1b8154e58d18..6c4d40b824e4 100644
--- a/drivers/gpu/drm/omapdrm/omap_crtc.c
+++ b/drivers/gpu/drm/omapdrm/omap_crtc.c
@@ -113,15 +113,17 @@ static struct omap_crtc *omap_crtcs[8];
113static struct omap_dss_device *omap_crtc_output[8]; 113static struct omap_dss_device *omap_crtc_output[8];
114 114
115/* we can probably ignore these until we support command-mode panels: */ 115/* we can probably ignore these until we support command-mode panels: */
116static int omap_crtc_dss_connect(enum omap_channel channel, 116static int omap_crtc_dss_connect(struct omap_drm_private *priv,
117 enum omap_channel channel,
117 struct omap_dss_device *dst) 118 struct omap_dss_device *dst)
118{ 119{
119 const struct dispc_ops *dispc_ops = dispc_get_ops(); 120 const struct dispc_ops *dispc_ops = priv->dispc_ops;
121 struct dispc_device *dispc = priv->dispc;
120 122
121 if (omap_crtc_output[channel]) 123 if (omap_crtc_output[channel])
122 return -EINVAL; 124 return -EINVAL;
123 125
124 if ((dispc_ops->mgr_get_supported_outputs(channel) & dst->id) == 0) 126 if (!(dispc_ops->mgr_get_supported_outputs(dispc, channel) & dst->id))
125 return -EINVAL; 127 return -EINVAL;
126 128
127 omap_crtc_output[channel] = dst; 129 omap_crtc_output[channel] = dst;
@@ -130,14 +132,16 @@ static int omap_crtc_dss_connect(enum omap_channel channel,
130 return 0; 132 return 0;
131} 133}
132 134
133static void omap_crtc_dss_disconnect(enum omap_channel channel, 135static void omap_crtc_dss_disconnect(struct omap_drm_private *priv,
136 enum omap_channel channel,
134 struct omap_dss_device *dst) 137 struct omap_dss_device *dst)
135{ 138{
136 omap_crtc_output[channel] = NULL; 139 omap_crtc_output[channel] = NULL;
137 dst->dispc_channel_connected = false; 140 dst->dispc_channel_connected = false;
138} 141}
139 142
140static void omap_crtc_dss_start_update(enum omap_channel channel) 143static void omap_crtc_dss_start_update(struct omap_drm_private *priv,
144 enum omap_channel channel)
141{ 145{
142} 146}
143 147
@@ -156,7 +160,7 @@ static void omap_crtc_set_enabled(struct drm_crtc *crtc, bool enable)
156 return; 160 return;
157 161
158 if (omap_crtc_output[channel]->output_type == OMAP_DISPLAY_TYPE_HDMI) { 162 if (omap_crtc_output[channel]->output_type == OMAP_DISPLAY_TYPE_HDMI) {
159 priv->dispc_ops->mgr_enable(channel, enable); 163 priv->dispc_ops->mgr_enable(priv->dispc, channel, enable);
160 omap_crtc->enabled = enable; 164 omap_crtc->enabled = enable;
161 return; 165 return;
162 } 166 }
@@ -169,8 +173,9 @@ static void omap_crtc_set_enabled(struct drm_crtc *crtc, bool enable)
169 omap_crtc->ignore_digit_sync_lost = true; 173 omap_crtc->ignore_digit_sync_lost = true;
170 } 174 }
171 175
172 framedone_irq = priv->dispc_ops->mgr_get_framedone_irq(channel); 176 framedone_irq = priv->dispc_ops->mgr_get_framedone_irq(priv->dispc,
173 vsync_irq = priv->dispc_ops->mgr_get_vsync_irq(channel); 177 channel);
178 vsync_irq = priv->dispc_ops->mgr_get_vsync_irq(priv->dispc, channel);
174 179
175 if (enable) { 180 if (enable) {
176 wait = omap_irq_wait_init(dev, vsync_irq, 1); 181 wait = omap_irq_wait_init(dev, vsync_irq, 1);
@@ -190,7 +195,7 @@ static void omap_crtc_set_enabled(struct drm_crtc *crtc, bool enable)
190 wait = omap_irq_wait_init(dev, vsync_irq, 2); 195 wait = omap_irq_wait_init(dev, vsync_irq, 2);
191 } 196 }
192 197
193 priv->dispc_ops->mgr_enable(channel, enable); 198 priv->dispc_ops->mgr_enable(priv->dispc, channel, enable);
194 omap_crtc->enabled = enable; 199 omap_crtc->enabled = enable;
195 200
196 ret = omap_irq_wait(dev, wait, msecs_to_jiffies(100)); 201 ret = omap_irq_wait(dev, wait, msecs_to_jiffies(100));
@@ -207,25 +212,28 @@ static void omap_crtc_set_enabled(struct drm_crtc *crtc, bool enable)
207} 212}
208 213
209 214
210static int omap_crtc_dss_enable(enum omap_channel channel) 215static int omap_crtc_dss_enable(struct omap_drm_private *priv,
216 enum omap_channel channel)
211{ 217{
212 struct omap_crtc *omap_crtc = omap_crtcs[channel]; 218 struct omap_crtc *omap_crtc = omap_crtcs[channel];
213 struct omap_drm_private *priv = omap_crtc->base.dev->dev_private;
214 219
215 priv->dispc_ops->mgr_set_timings(omap_crtc->channel, &omap_crtc->vm); 220 priv->dispc_ops->mgr_set_timings(priv->dispc, omap_crtc->channel,
221 &omap_crtc->vm);
216 omap_crtc_set_enabled(&omap_crtc->base, true); 222 omap_crtc_set_enabled(&omap_crtc->base, true);
217 223
218 return 0; 224 return 0;
219} 225}
220 226
221static void omap_crtc_dss_disable(enum omap_channel channel) 227static void omap_crtc_dss_disable(struct omap_drm_private *priv,
228 enum omap_channel channel)
222{ 229{
223 struct omap_crtc *omap_crtc = omap_crtcs[channel]; 230 struct omap_crtc *omap_crtc = omap_crtcs[channel];
224 231
225 omap_crtc_set_enabled(&omap_crtc->base, false); 232 omap_crtc_set_enabled(&omap_crtc->base, false);
226} 233}
227 234
228static void omap_crtc_dss_set_timings(enum omap_channel channel, 235static void omap_crtc_dss_set_timings(struct omap_drm_private *priv,
236 enum omap_channel channel,
229 const struct videomode *vm) 237 const struct videomode *vm)
230{ 238{
231 struct omap_crtc *omap_crtc = omap_crtcs[channel]; 239 struct omap_crtc *omap_crtc = omap_crtcs[channel];
@@ -233,25 +241,26 @@ static void omap_crtc_dss_set_timings(enum omap_channel channel,
233 omap_crtc->vm = *vm; 241 omap_crtc->vm = *vm;
234} 242}
235 243
236static void omap_crtc_dss_set_lcd_config(enum omap_channel channel, 244static void omap_crtc_dss_set_lcd_config(struct omap_drm_private *priv,
245 enum omap_channel channel,
237 const struct dss_lcd_mgr_config *config) 246 const struct dss_lcd_mgr_config *config)
238{ 247{
239 struct omap_crtc *omap_crtc = omap_crtcs[channel]; 248 struct omap_crtc *omap_crtc = omap_crtcs[channel];
240 struct omap_drm_private *priv = omap_crtc->base.dev->dev_private;
241 249
242 DBG("%s", omap_crtc->name); 250 DBG("%s", omap_crtc->name);
243 priv->dispc_ops->mgr_set_lcd_config(omap_crtc->channel, config); 251 priv->dispc_ops->mgr_set_lcd_config(priv->dispc, omap_crtc->channel,
252 config);
244} 253}
245 254
246static int omap_crtc_dss_register_framedone( 255static int omap_crtc_dss_register_framedone(
247 enum omap_channel channel, 256 struct omap_drm_private *priv, enum omap_channel channel,
248 void (*handler)(void *), void *data) 257 void (*handler)(void *), void *data)
249{ 258{
250 return 0; 259 return 0;
251} 260}
252 261
253static void omap_crtc_dss_unregister_framedone( 262static void omap_crtc_dss_unregister_framedone(
254 enum omap_channel channel, 263 struct omap_drm_private *priv, enum omap_channel channel,
255 void (*handler)(void *), void *data) 264 void (*handler)(void *), void *data)
256{ 265{
257} 266}
@@ -272,7 +281,7 @@ static const struct dss_mgr_ops mgr_ops = {
272 * Setup, Flush and Page Flip 281 * Setup, Flush and Page Flip
273 */ 282 */
274 283
275void omap_crtc_error_irq(struct drm_crtc *crtc, uint32_t irqstatus) 284void omap_crtc_error_irq(struct drm_crtc *crtc, u32 irqstatus)
276{ 285{
277 struct omap_crtc *omap_crtc = to_omap_crtc(crtc); 286 struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
278 287
@@ -297,7 +306,7 @@ void omap_crtc_vblank_irq(struct drm_crtc *crtc)
297 * If the dispc is busy we're racing the flush operation. Try again on 306 * If the dispc is busy we're racing the flush operation. Try again on
298 * the next vblank interrupt. 307 * the next vblank interrupt.
299 */ 308 */
300 if (priv->dispc_ops->mgr_go_busy(omap_crtc->channel)) { 309 if (priv->dispc_ops->mgr_go_busy(priv->dispc, omap_crtc->channel)) {
301 spin_unlock(&crtc->dev->event_lock); 310 spin_unlock(&crtc->dev->event_lock);
302 return; 311 return;
303 } 312 }
@@ -334,7 +343,7 @@ static void omap_crtc_write_crtc_properties(struct drm_crtc *crtc)
334 info.partial_alpha_enabled = false; 343 info.partial_alpha_enabled = false;
335 info.cpr_enable = false; 344 info.cpr_enable = false;
336 345
337 priv->dispc_ops->mgr_setup(omap_crtc->channel, &info); 346 priv->dispc_ops->mgr_setup(priv->dispc, omap_crtc->channel, &info);
338} 347}
339 348
340/* ----------------------------------------------------------------------------- 349/* -----------------------------------------------------------------------------
@@ -492,7 +501,7 @@ static int omap_crtc_atomic_check(struct drm_crtc *crtc,
492 struct drm_plane_state *pri_state; 501 struct drm_plane_state *pri_state;
493 502
494 if (state->color_mgmt_changed && state->gamma_lut) { 503 if (state->color_mgmt_changed && state->gamma_lut) {
495 uint length = state->gamma_lut->length / 504 unsigned int length = state->gamma_lut->length /
496 sizeof(struct drm_color_lut); 505 sizeof(struct drm_color_lut);
497 506
498 if (length < 2) 507 if (length < 2)
@@ -526,7 +535,7 @@ static void omap_crtc_atomic_flush(struct drm_crtc *crtc,
526 535
527 if (crtc->state->color_mgmt_changed) { 536 if (crtc->state->color_mgmt_changed) {
528 struct drm_color_lut *lut = NULL; 537 struct drm_color_lut *lut = NULL;
529 uint length = 0; 538 unsigned int length = 0;
530 539
531 if (crtc->state->gamma_lut) { 540 if (crtc->state->gamma_lut) {
532 lut = (struct drm_color_lut *) 541 lut = (struct drm_color_lut *)
@@ -534,7 +543,8 @@ static void omap_crtc_atomic_flush(struct drm_crtc *crtc,
534 length = crtc->state->gamma_lut->length / 543 length = crtc->state->gamma_lut->length /
535 sizeof(*lut); 544 sizeof(*lut);
536 } 545 }
537 priv->dispc_ops->mgr_set_gamma(omap_crtc->channel, lut, length); 546 priv->dispc_ops->mgr_set_gamma(priv->dispc, omap_crtc->channel,
547 lut, length);
538 } 548 }
539 549
540 omap_crtc_write_crtc_properties(crtc); 550 omap_crtc_write_crtc_properties(crtc);
@@ -549,7 +559,7 @@ static void omap_crtc_atomic_flush(struct drm_crtc *crtc,
549 WARN_ON(ret != 0); 559 WARN_ON(ret != 0);
550 560
551 spin_lock_irq(&crtc->dev->event_lock); 561 spin_lock_irq(&crtc->dev->event_lock);
552 priv->dispc_ops->mgr_go(omap_crtc->channel); 562 priv->dispc_ops->mgr_go(priv->dispc, omap_crtc->channel);
553 omap_crtc_arm_event(crtc); 563 omap_crtc_arm_event(crtc);
554 spin_unlock_irq(&crtc->dev->event_lock); 564 spin_unlock_irq(&crtc->dev->event_lock);
555} 565}
@@ -557,7 +567,7 @@ static void omap_crtc_atomic_flush(struct drm_crtc *crtc,
557static int omap_crtc_atomic_set_property(struct drm_crtc *crtc, 567static int omap_crtc_atomic_set_property(struct drm_crtc *crtc,
558 struct drm_crtc_state *state, 568 struct drm_crtc_state *state,
559 struct drm_property *property, 569 struct drm_property *property,
560 uint64_t val) 570 u64 val)
561{ 571{
562 struct omap_drm_private *priv = crtc->dev->dev_private; 572 struct omap_drm_private *priv = crtc->dev->dev_private;
563 struct drm_plane_state *plane_state; 573 struct drm_plane_state *plane_state;
@@ -585,7 +595,7 @@ static int omap_crtc_atomic_set_property(struct drm_crtc *crtc,
585static int omap_crtc_atomic_get_property(struct drm_crtc *crtc, 595static int omap_crtc_atomic_get_property(struct drm_crtc *crtc,
586 const struct drm_crtc_state *state, 596 const struct drm_crtc_state *state,
587 struct drm_property *property, 597 struct drm_property *property,
588 uint64_t *val) 598 u64 *val)
589{ 599{
590 struct omap_drm_private *priv = crtc->dev->dev_private; 600 struct omap_drm_private *priv = crtc->dev->dev_private;
591 struct omap_crtc_state *omap_state = to_omap_crtc_state(state); 601 struct omap_crtc_state *omap_state = to_omap_crtc_state(state);
@@ -669,11 +679,11 @@ static const char *channel_names[] = {
669 [OMAP_DSS_CHANNEL_LCD3] = "lcd3", 679 [OMAP_DSS_CHANNEL_LCD3] = "lcd3",
670}; 680};
671 681
672void omap_crtc_pre_init(void) 682void omap_crtc_pre_init(struct omap_drm_private *priv)
673{ 683{
674 memset(omap_crtcs, 0, sizeof(omap_crtcs)); 684 memset(omap_crtcs, 0, sizeof(omap_crtcs));
675 685
676 dss_install_mgr_ops(&mgr_ops); 686 dss_install_mgr_ops(&mgr_ops, priv);
677} 687}
678 688
679void omap_crtc_pre_uninit(void) 689void omap_crtc_pre_uninit(void)
@@ -731,8 +741,8 @@ struct drm_crtc *omap_crtc_init(struct drm_device *dev,
731 * extracted with dispc_mgr_gamma_size(). If it returns 0 741 * extracted with dispc_mgr_gamma_size(). If it returns 0
732 * gamma table is not supprted. 742 * gamma table is not supprted.
733 */ 743 */
734 if (priv->dispc_ops->mgr_gamma_size(channel)) { 744 if (priv->dispc_ops->mgr_gamma_size(priv->dispc, channel)) {
735 uint gamma_lut_size = 256; 745 unsigned int gamma_lut_size = 256;
736 746
737 drm_crtc_enable_color_mgmt(crtc, 0, false, gamma_lut_size); 747 drm_crtc_enable_color_mgmt(crtc, 0, false, gamma_lut_size);
738 drm_mode_crtc_set_gamma_size(crtc, gamma_lut_size); 748 drm_mode_crtc_set_gamma_size(crtc, gamma_lut_size);
diff --git a/drivers/gpu/drm/omapdrm/omap_crtc.h b/drivers/gpu/drm/omapdrm/omap_crtc.h
index ad7b007c6174..eaab2d7f0324 100644
--- a/drivers/gpu/drm/omapdrm/omap_crtc.h
+++ b/drivers/gpu/drm/omapdrm/omap_crtc.h
@@ -32,12 +32,12 @@ struct videomode;
32 32
33struct videomode *omap_crtc_timings(struct drm_crtc *crtc); 33struct videomode *omap_crtc_timings(struct drm_crtc *crtc);
34enum omap_channel omap_crtc_channel(struct drm_crtc *crtc); 34enum omap_channel omap_crtc_channel(struct drm_crtc *crtc);
35void omap_crtc_pre_init(void); 35void omap_crtc_pre_init(struct omap_drm_private *priv);
36void omap_crtc_pre_uninit(void); 36void omap_crtc_pre_uninit(void);
37struct drm_crtc *omap_crtc_init(struct drm_device *dev, 37struct drm_crtc *omap_crtc_init(struct drm_device *dev,
38 struct drm_plane *plane, struct omap_dss_device *dssdev); 38 struct drm_plane *plane, struct omap_dss_device *dssdev);
39int omap_crtc_wait_pending(struct drm_crtc *crtc); 39int omap_crtc_wait_pending(struct drm_crtc *crtc);
40void omap_crtc_error_irq(struct drm_crtc *crtc, uint32_t irqstatus); 40void omap_crtc_error_irq(struct drm_crtc *crtc, u32 irqstatus);
41void omap_crtc_vblank_irq(struct drm_crtc *crtc); 41void omap_crtc_vblank_irq(struct drm_crtc *crtc);
42 42
43#endif /* __OMAPDRM_CRTC_H__ */ 43#endif /* __OMAPDRM_CRTC_H__ */
diff --git a/drivers/gpu/drm/omapdrm/omap_dmm_priv.h b/drivers/gpu/drm/omapdrm/omap_dmm_priv.h
index 600064d5c25b..c2785cc98dc9 100644
--- a/drivers/gpu/drm/omapdrm/omap_dmm_priv.h
+++ b/drivers/gpu/drm/omapdrm/omap_dmm_priv.h
@@ -102,10 +102,10 @@ struct pat_ctrl {
102}; 102};
103 103
104struct pat { 104struct pat {
105 uint32_t next_pa; 105 u32 next_pa;
106 struct pat_area area; 106 struct pat_area area;
107 struct pat_ctrl ctrl; 107 struct pat_ctrl ctrl;
108 uint32_t data_pa; 108 u32 data_pa;
109}; 109};
110 110
111#define DMM_FIXED_RETRY_COUNT 1000 111#define DMM_FIXED_RETRY_COUNT 1000
@@ -129,7 +129,7 @@ struct dmm_txn {
129 void *engine_handle; 129 void *engine_handle;
130 struct tcm *tcm; 130 struct tcm *tcm;
131 131
132 uint8_t *current_va; 132 u8 *current_va;
133 dma_addr_t current_pa; 133 dma_addr_t current_pa;
134 134
135 struct pat *last_pat; 135 struct pat *last_pat;
@@ -140,7 +140,7 @@ struct refill_engine {
140 struct dmm *dmm; 140 struct dmm *dmm;
141 struct tcm *tcm; 141 struct tcm *tcm;
142 142
143 uint8_t *refill_va; 143 u8 *refill_va;
144 dma_addr_t refill_pa; 144 dma_addr_t refill_pa;
145 145
146 /* only one trans per engine for now */ 146 /* only one trans per engine for now */
@@ -154,7 +154,7 @@ struct refill_engine {
154}; 154};
155 155
156struct dmm_platform_data { 156struct dmm_platform_data {
157 uint32_t cpu_cache_flags; 157 u32 cpu_cache_flags;
158}; 158};
159 159
160struct dmm { 160struct dmm {
diff --git a/drivers/gpu/drm/omapdrm/omap_dmm_tiler.c b/drivers/gpu/drm/omapdrm/omap_dmm_tiler.c
index 4be0c94673f5..f9fa1c90b35c 100644
--- a/drivers/gpu/drm/omapdrm/omap_dmm_tiler.c
+++ b/drivers/gpu/drm/omapdrm/omap_dmm_tiler.c
@@ -58,11 +58,11 @@ static DEFINE_SPINLOCK(list_lock);
58 } 58 }
59 59
60static const struct { 60static const struct {
61 uint32_t x_shft; /* unused X-bits (as part of bpp) */ 61 u32 x_shft; /* unused X-bits (as part of bpp) */
62 uint32_t y_shft; /* unused Y-bits (as part of bpp) */ 62 u32 y_shft; /* unused Y-bits (as part of bpp) */
63 uint32_t cpp; /* bytes/chars per pixel */ 63 u32 cpp; /* bytes/chars per pixel */
64 uint32_t slot_w; /* width of each slot (in pixels) */ 64 u32 slot_w; /* width of each slot (in pixels) */
65 uint32_t slot_h; /* height of each slot (in pixels) */ 65 u32 slot_h; /* height of each slot (in pixels) */
66} geom[TILFMT_NFORMATS] = { 66} geom[TILFMT_NFORMATS] = {
67 [TILFMT_8BIT] = GEOM(0, 0, 1), 67 [TILFMT_8BIT] = GEOM(0, 0, 1),
68 [TILFMT_16BIT] = GEOM(0, 1, 2), 68 [TILFMT_16BIT] = GEOM(0, 1, 2),
@@ -72,7 +72,7 @@ static const struct {
72 72
73 73
74/* lookup table for registers w/ per-engine instances */ 74/* lookup table for registers w/ per-engine instances */
75static const uint32_t reg[][4] = { 75static const u32 reg[][4] = {
76 [PAT_STATUS] = {DMM_PAT_STATUS__0, DMM_PAT_STATUS__1, 76 [PAT_STATUS] = {DMM_PAT_STATUS__0, DMM_PAT_STATUS__1,
77 DMM_PAT_STATUS__2, DMM_PAT_STATUS__3}, 77 DMM_PAT_STATUS__2, DMM_PAT_STATUS__3},
78 [PAT_DESCR] = {DMM_PAT_DESCR__0, DMM_PAT_DESCR__1, 78 [PAT_DESCR] = {DMM_PAT_DESCR__0, DMM_PAT_DESCR__1,
@@ -111,10 +111,10 @@ static void *alloc_dma(struct dmm_txn *txn, size_t sz, dma_addr_t *pa)
111} 111}
112 112
113/* check status and spin until wait_mask comes true */ 113/* check status and spin until wait_mask comes true */
114static int wait_status(struct refill_engine *engine, uint32_t wait_mask) 114static int wait_status(struct refill_engine *engine, u32 wait_mask)
115{ 115{
116 struct dmm *dmm = engine->dmm; 116 struct dmm *dmm = engine->dmm;
117 uint32_t r = 0, err, i; 117 u32 r = 0, err, i;
118 118
119 i = DMM_FIXED_RETRY_COUNT; 119 i = DMM_FIXED_RETRY_COUNT;
120 while (true) { 120 while (true) {
@@ -158,7 +158,7 @@ static void release_engine(struct refill_engine *engine)
158static irqreturn_t omap_dmm_irq_handler(int irq, void *arg) 158static irqreturn_t omap_dmm_irq_handler(int irq, void *arg)
159{ 159{
160 struct dmm *dmm = arg; 160 struct dmm *dmm = arg;
161 uint32_t status = dmm_read(dmm, DMM_PAT_IRQSTATUS); 161 u32 status = dmm_read(dmm, DMM_PAT_IRQSTATUS);
162 int i; 162 int i;
163 163
164 /* ack IRQ */ 164 /* ack IRQ */
@@ -226,10 +226,10 @@ static struct dmm_txn *dmm_txn_init(struct dmm *dmm, struct tcm *tcm)
226 * corresponding slot is cleared (ie. dummy_pa is programmed) 226 * corresponding slot is cleared (ie. dummy_pa is programmed)
227 */ 227 */
228static void dmm_txn_append(struct dmm_txn *txn, struct pat_area *area, 228static void dmm_txn_append(struct dmm_txn *txn, struct pat_area *area,
229 struct page **pages, uint32_t npages, uint32_t roll) 229 struct page **pages, u32 npages, u32 roll)
230{ 230{
231 dma_addr_t pat_pa = 0, data_pa = 0; 231 dma_addr_t pat_pa = 0, data_pa = 0;
232 uint32_t *data; 232 u32 *data;
233 struct pat *pat; 233 struct pat *pat;
234 struct refill_engine *engine = txn->engine_handle; 234 struct refill_engine *engine = txn->engine_handle;
235 int columns = (1 + area->x1 - area->x0); 235 int columns = (1 + area->x1 - area->x0);
@@ -239,7 +239,7 @@ static void dmm_txn_append(struct dmm_txn *txn, struct pat_area *area,
239 pat = alloc_dma(txn, sizeof(*pat), &pat_pa); 239 pat = alloc_dma(txn, sizeof(*pat), &pat_pa);
240 240
241 if (txn->last_pat) 241 if (txn->last_pat)
242 txn->last_pat->next_pa = (uint32_t)pat_pa; 242 txn->last_pat->next_pa = (u32)pat_pa;
243 243
244 pat->area = *area; 244 pat->area = *area;
245 245
@@ -330,7 +330,7 @@ cleanup:
330 * DMM programming 330 * DMM programming
331 */ 331 */
332static int fill(struct tcm_area *area, struct page **pages, 332static int fill(struct tcm_area *area, struct page **pages,
333 uint32_t npages, uint32_t roll, bool wait) 333 u32 npages, u32 roll, bool wait)
334{ 334{
335 int ret = 0; 335 int ret = 0;
336 struct tcm_area slice, area_s; 336 struct tcm_area slice, area_s;
@@ -378,7 +378,7 @@ static int fill(struct tcm_area *area, struct page **pages,
378/* note: slots for which pages[i] == NULL are filled w/ dummy page 378/* note: slots for which pages[i] == NULL are filled w/ dummy page
379 */ 379 */
380int tiler_pin(struct tiler_block *block, struct page **pages, 380int tiler_pin(struct tiler_block *block, struct page **pages,
381 uint32_t npages, uint32_t roll, bool wait) 381 u32 npages, u32 roll, bool wait)
382{ 382{
383 int ret; 383 int ret;
384 384
@@ -398,8 +398,8 @@ int tiler_unpin(struct tiler_block *block)
398/* 398/*
399 * Reserve/release 399 * Reserve/release
400 */ 400 */
401struct tiler_block *tiler_reserve_2d(enum tiler_fmt fmt, uint16_t w, 401struct tiler_block *tiler_reserve_2d(enum tiler_fmt fmt, u16 w,
402 uint16_t h, uint16_t align) 402 u16 h, u16 align)
403{ 403{
404 struct tiler_block *block = kzalloc(sizeof(*block), GFP_KERNEL); 404 struct tiler_block *block = kzalloc(sizeof(*block), GFP_KERNEL);
405 u32 min_align = 128; 405 u32 min_align = 128;
@@ -542,8 +542,8 @@ dma_addr_t tiler_ssptr(struct tiler_block *block)
542 block->area.p0.y * geom[block->fmt].slot_h); 542 block->area.p0.y * geom[block->fmt].slot_h);
543} 543}
544 544
545dma_addr_t tiler_tsptr(struct tiler_block *block, uint32_t orient, 545dma_addr_t tiler_tsptr(struct tiler_block *block, u32 orient,
546 uint32_t x, uint32_t y) 546 u32 x, u32 y)
547{ 547{
548 struct tcm_pt *p = &block->area.p0; 548 struct tcm_pt *p = &block->area.p0;
549 BUG_ON(!validfmt(block->fmt)); 549 BUG_ON(!validfmt(block->fmt));
@@ -553,14 +553,14 @@ dma_addr_t tiler_tsptr(struct tiler_block *block, uint32_t orient,
553 (p->y * geom[block->fmt].slot_h) + y); 553 (p->y * geom[block->fmt].slot_h) + y);
554} 554}
555 555
556void tiler_align(enum tiler_fmt fmt, uint16_t *w, uint16_t *h) 556void tiler_align(enum tiler_fmt fmt, u16 *w, u16 *h)
557{ 557{
558 BUG_ON(!validfmt(fmt)); 558 BUG_ON(!validfmt(fmt));
559 *w = round_up(*w, geom[fmt].slot_w); 559 *w = round_up(*w, geom[fmt].slot_w);
560 *h = round_up(*h, geom[fmt].slot_h); 560 *h = round_up(*h, geom[fmt].slot_h);
561} 561}
562 562
563uint32_t tiler_stride(enum tiler_fmt fmt, uint32_t orient) 563u32 tiler_stride(enum tiler_fmt fmt, u32 orient)
564{ 564{
565 BUG_ON(!validfmt(fmt)); 565 BUG_ON(!validfmt(fmt));
566 566
@@ -570,19 +570,19 @@ uint32_t tiler_stride(enum tiler_fmt fmt, uint32_t orient)
570 return 1 << (CONT_WIDTH_BITS + geom[fmt].y_shft); 570 return 1 << (CONT_WIDTH_BITS + geom[fmt].y_shft);
571} 571}
572 572
573size_t tiler_size(enum tiler_fmt fmt, uint16_t w, uint16_t h) 573size_t tiler_size(enum tiler_fmt fmt, u16 w, u16 h)
574{ 574{
575 tiler_align(fmt, &w, &h); 575 tiler_align(fmt, &w, &h);
576 return geom[fmt].cpp * w * h; 576 return geom[fmt].cpp * w * h;
577} 577}
578 578
579size_t tiler_vsize(enum tiler_fmt fmt, uint16_t w, uint16_t h) 579size_t tiler_vsize(enum tiler_fmt fmt, u16 w, u16 h)
580{ 580{
581 BUG_ON(!validfmt(fmt)); 581 BUG_ON(!validfmt(fmt));
582 return round_up(geom[fmt].cpp * w, PAGE_SIZE) * h; 582 return round_up(geom[fmt].cpp * w, PAGE_SIZE) * h;
583} 583}
584 584
585uint32_t tiler_get_cpu_cache_flags(void) 585u32 tiler_get_cpu_cache_flags(void)
586{ 586{
587 return omap_dmm->plat_data->cpu_cache_flags; 587 return omap_dmm->plat_data->cpu_cache_flags;
588} 588}
diff --git a/drivers/gpu/drm/omapdrm/omap_dmm_tiler.h b/drivers/gpu/drm/omapdrm/omap_dmm_tiler.h
index cc78ba4fe6ab..835e6654fa82 100644
--- a/drivers/gpu/drm/omapdrm/omap_dmm_tiler.h
+++ b/drivers/gpu/drm/omapdrm/omap_dmm_tiler.h
@@ -88,30 +88,30 @@ int tiler_map_show(struct seq_file *s, void *arg);
88 88
89/* pin/unpin */ 89/* pin/unpin */
90int tiler_pin(struct tiler_block *block, struct page **pages, 90int tiler_pin(struct tiler_block *block, struct page **pages,
91 uint32_t npages, uint32_t roll, bool wait); 91 u32 npages, u32 roll, bool wait);
92int tiler_unpin(struct tiler_block *block); 92int tiler_unpin(struct tiler_block *block);
93 93
94/* reserve/release */ 94/* reserve/release */
95struct tiler_block *tiler_reserve_2d(enum tiler_fmt fmt, uint16_t w, uint16_t h, 95struct tiler_block *tiler_reserve_2d(enum tiler_fmt fmt, u16 w, u16 h,
96 uint16_t align); 96 u16 align);
97struct tiler_block *tiler_reserve_1d(size_t size); 97struct tiler_block *tiler_reserve_1d(size_t size);
98int tiler_release(struct tiler_block *block); 98int tiler_release(struct tiler_block *block);
99 99
100/* utilities */ 100/* utilities */
101dma_addr_t tiler_ssptr(struct tiler_block *block); 101dma_addr_t tiler_ssptr(struct tiler_block *block);
102dma_addr_t tiler_tsptr(struct tiler_block *block, uint32_t orient, 102dma_addr_t tiler_tsptr(struct tiler_block *block, u32 orient,
103 uint32_t x, uint32_t y); 103 u32 x, u32 y);
104uint32_t tiler_stride(enum tiler_fmt fmt, uint32_t orient); 104u32 tiler_stride(enum tiler_fmt fmt, u32 orient);
105size_t tiler_size(enum tiler_fmt fmt, uint16_t w, uint16_t h); 105size_t tiler_size(enum tiler_fmt fmt, u16 w, u16 h);
106size_t tiler_vsize(enum tiler_fmt fmt, uint16_t w, uint16_t h); 106size_t tiler_vsize(enum tiler_fmt fmt, u16 w, u16 h);
107void tiler_align(enum tiler_fmt fmt, uint16_t *w, uint16_t *h); 107void tiler_align(enum tiler_fmt fmt, u16 *w, u16 *h);
108uint32_t tiler_get_cpu_cache_flags(void); 108u32 tiler_get_cpu_cache_flags(void);
109bool dmm_is_available(void); 109bool dmm_is_available(void);
110 110
111extern struct platform_driver omap_dmm_driver; 111extern struct platform_driver omap_dmm_driver;
112 112
113/* GEM bo flags -> tiler fmt */ 113/* GEM bo flags -> tiler fmt */
114static inline enum tiler_fmt gem2fmt(uint32_t flags) 114static inline enum tiler_fmt gem2fmt(u32 flags)
115{ 115{
116 switch (flags & OMAP_BO_TILED) { 116 switch (flags & OMAP_BO_TILED) {
117 case OMAP_BO_TILED_8: 117 case OMAP_BO_TILED_8:
diff --git a/drivers/gpu/drm/omapdrm/omap_drv.c b/drivers/gpu/drm/omapdrm/omap_drv.c
index dd68b2556f5b..3632854c2b91 100644
--- a/drivers/gpu/drm/omapdrm/omap_drv.c
+++ b/drivers/gpu/drm/omapdrm/omap_drv.c
@@ -69,7 +69,7 @@ static void omap_atomic_commit_tail(struct drm_atomic_state *old_state)
69 struct drm_device *dev = old_state->dev; 69 struct drm_device *dev = old_state->dev;
70 struct omap_drm_private *priv = dev->dev_private; 70 struct omap_drm_private *priv = dev->dev_private;
71 71
72 priv->dispc_ops->runtime_get(); 72 priv->dispc_ops->runtime_get(priv->dispc);
73 73
74 /* Apply the atomic update. */ 74 /* Apply the atomic update. */
75 drm_atomic_helper_commit_modeset_disables(dev, old_state); 75 drm_atomic_helper_commit_modeset_disables(dev, old_state);
@@ -113,7 +113,7 @@ static void omap_atomic_commit_tail(struct drm_atomic_state *old_state)
113 113
114 drm_atomic_helper_cleanup_planes(dev, old_state); 114 drm_atomic_helper_cleanup_planes(dev, old_state);
115 115
116 priv->dispc_ops->runtime_put(); 116 priv->dispc_ops->runtime_put(priv->dispc);
117} 117}
118 118
119static const struct drm_mode_config_helper_funcs omap_mode_config_helper_funcs = { 119static const struct drm_mode_config_helper_funcs omap_mode_config_helper_funcs = {
@@ -191,7 +191,7 @@ cleanup:
191static int omap_modeset_init_properties(struct drm_device *dev) 191static int omap_modeset_init_properties(struct drm_device *dev)
192{ 192{
193 struct omap_drm_private *priv = dev->dev_private; 193 struct omap_drm_private *priv = dev->dev_private;
194 unsigned int num_planes = priv->dispc_ops->get_num_ovls(); 194 unsigned int num_planes = priv->dispc_ops->get_num_ovls(priv->dispc);
195 195
196 priv->zorder_prop = drm_property_create_range(dev, 0, "zorder", 0, 196 priv->zorder_prop = drm_property_create_range(dev, 0, "zorder", 0,
197 num_planes - 1); 197 num_planes - 1);
@@ -205,8 +205,8 @@ static int omap_modeset_init(struct drm_device *dev)
205{ 205{
206 struct omap_drm_private *priv = dev->dev_private; 206 struct omap_drm_private *priv = dev->dev_private;
207 struct omap_dss_device *dssdev = NULL; 207 struct omap_dss_device *dssdev = NULL;
208 int num_ovls = priv->dispc_ops->get_num_ovls(); 208 int num_ovls = priv->dispc_ops->get_num_ovls(priv->dispc);
209 int num_mgrs = priv->dispc_ops->get_num_mgrs(); 209 int num_mgrs = priv->dispc_ops->get_num_mgrs(priv->dispc);
210 int num_crtcs, crtc_idx, plane_idx; 210 int num_crtcs, crtc_idx, plane_idx;
211 int ret; 211 int ret;
212 u32 plane_crtc_mask; 212 u32 plane_crtc_mask;
@@ -310,11 +310,14 @@ static int omap_modeset_init(struct drm_device *dev)
310 dev->mode_config.min_width = 8; 310 dev->mode_config.min_width = 8;
311 dev->mode_config.min_height = 2; 311 dev->mode_config.min_height = 2;
312 312
313 /* note: eventually will need some cpu_is_omapXYZ() type stuff here 313 /*
314 * to fill in these limits properly on different OMAP generations.. 314 * Note: these values are used for multiple independent things:
315 * connector mode filtering, buffer sizes, crtc sizes...
316 * Use big enough values here to cover all use cases, and do more
317 * specific checking in the respective code paths.
315 */ 318 */
316 dev->mode_config.max_width = 2048; 319 dev->mode_config.max_width = 8192;
317 dev->mode_config.max_height = 2048; 320 dev->mode_config.max_height = 8192;
318 321
319 dev->mode_config.funcs = &omap_mode_config_funcs; 322 dev->mode_config.funcs = &omap_mode_config_funcs;
320 dev->mode_config.helper_private = &omap_mode_config_helper_funcs; 323 dev->mode_config.helper_private = &omap_mode_config_helper_funcs;
@@ -510,40 +513,26 @@ static const struct soc_device_attribute omapdrm_soc_devices[] = {
510 { /* sentinel */ } 513 { /* sentinel */ }
511}; 514};
512 515
513static int pdev_probe(struct platform_device *pdev) 516static int omapdrm_init(struct omap_drm_private *priv, struct device *dev)
514{ 517{
515 const struct soc_device_attribute *soc; 518 const struct soc_device_attribute *soc;
516 struct omap_drm_private *priv;
517 struct drm_device *ddev; 519 struct drm_device *ddev;
518 unsigned int i; 520 unsigned int i;
519 int ret; 521 int ret;
520 522
521 DBG("%s", pdev->name); 523 DBG("%s", dev_name(dev));
522 524
523 if (omapdss_is_initialized() == false) 525 priv->dev = dev;
524 return -EPROBE_DEFER; 526 priv->dss = omapdss_get_dss();
527 priv->dispc = dispc_get_dispc(priv->dss);
528 priv->dispc_ops = dispc_get_ops(priv->dss);
525 529
526 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); 530 omap_crtc_pre_init(priv);
527 if (ret) {
528 dev_err(&pdev->dev, "Failed to set the DMA mask\n");
529 return ret;
530 }
531
532 omap_crtc_pre_init();
533 531
534 ret = omap_connect_dssdevs(); 532 ret = omap_connect_dssdevs();
535 if (ret) 533 if (ret)
536 goto err_crtc_uninit; 534 goto err_crtc_uninit;
537 535
538 /* Allocate and initialize the driver private structure. */
539 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
540 if (!priv) {
541 ret = -ENOMEM;
542 goto err_disconnect_dssdevs;
543 }
544
545 priv->dispc_ops = dispc_get_ops();
546
547 soc = soc_device_match(omapdrm_soc_devices); 536 soc = soc_device_match(omapdrm_soc_devices);
548 priv->omaprev = soc ? (unsigned int)soc->data : 0; 537 priv->omaprev = soc ? (unsigned int)soc->data : 0;
549 priv->wq = alloc_ordered_workqueue("omapdrm", 0); 538 priv->wq = alloc_ordered_workqueue("omapdrm", 0);
@@ -552,39 +541,39 @@ static int pdev_probe(struct platform_device *pdev)
552 INIT_LIST_HEAD(&priv->obj_list); 541 INIT_LIST_HEAD(&priv->obj_list);
553 542
554 /* Allocate and initialize the DRM device. */ 543 /* Allocate and initialize the DRM device. */
555 ddev = drm_dev_alloc(&omap_drm_driver, &pdev->dev); 544 ddev = drm_dev_alloc(&omap_drm_driver, priv->dev);
556 if (IS_ERR(ddev)) { 545 if (IS_ERR(ddev)) {
557 ret = PTR_ERR(ddev); 546 ret = PTR_ERR(ddev);
558 goto err_free_priv; 547 goto err_destroy_wq;
559 } 548 }
560 549
550 priv->ddev = ddev;
561 ddev->dev_private = priv; 551 ddev->dev_private = priv;
562 platform_set_drvdata(pdev, ddev);
563 552
564 /* Get memory bandwidth limits */ 553 /* Get memory bandwidth limits */
565 if (priv->dispc_ops->get_memory_bandwidth_limit) 554 if (priv->dispc_ops->get_memory_bandwidth_limit)
566 priv->max_bandwidth = 555 priv->max_bandwidth =
567 priv->dispc_ops->get_memory_bandwidth_limit(); 556 priv->dispc_ops->get_memory_bandwidth_limit(priv->dispc);
568 557
569 omap_gem_init(ddev); 558 omap_gem_init(ddev);
570 559
571 ret = omap_modeset_init(ddev); 560 ret = omap_modeset_init(ddev);
572 if (ret) { 561 if (ret) {
573 dev_err(&pdev->dev, "omap_modeset_init failed: ret=%d\n", ret); 562 dev_err(priv->dev, "omap_modeset_init failed: ret=%d\n", ret);
574 goto err_free_drm_dev; 563 goto err_free_drm_dev;
575 } 564 }
576 565
577 /* Initialize vblank handling, start with all CRTCs disabled. */ 566 /* Initialize vblank handling, start with all CRTCs disabled. */
578 ret = drm_vblank_init(ddev, priv->num_crtcs); 567 ret = drm_vblank_init(ddev, priv->num_crtcs);
579 if (ret) { 568 if (ret) {
580 dev_err(&pdev->dev, "could not init vblank\n"); 569 dev_err(priv->dev, "could not init vblank\n");
581 goto err_cleanup_modeset; 570 goto err_cleanup_modeset;
582 } 571 }
583 572
584 for (i = 0; i < priv->num_crtcs; i++) 573 for (i = 0; i < priv->num_crtcs; i++)
585 drm_crtc_vblank_off(priv->crtcs[i]); 574 drm_crtc_vblank_off(priv->crtcs[i]);
586 575
587 priv->fbdev = omap_fbdev_init(ddev); 576 omap_fbdev_init(ddev);
588 577
589 drm_kms_helper_poll_init(ddev); 578 drm_kms_helper_poll_init(ddev);
590 omap_modeset_enable_external_hpd(); 579 omap_modeset_enable_external_hpd();
@@ -602,28 +591,25 @@ static int pdev_probe(struct platform_device *pdev)
602err_cleanup_helpers: 591err_cleanup_helpers:
603 omap_modeset_disable_external_hpd(); 592 omap_modeset_disable_external_hpd();
604 drm_kms_helper_poll_fini(ddev); 593 drm_kms_helper_poll_fini(ddev);
605 if (priv->fbdev) 594
606 omap_fbdev_free(ddev); 595 omap_fbdev_fini(ddev);
607err_cleanup_modeset: 596err_cleanup_modeset:
608 drm_mode_config_cleanup(ddev); 597 drm_mode_config_cleanup(ddev);
609 omap_drm_irq_uninstall(ddev); 598 omap_drm_irq_uninstall(ddev);
610err_free_drm_dev: 599err_free_drm_dev:
611 omap_gem_deinit(ddev); 600 omap_gem_deinit(ddev);
612 drm_dev_unref(ddev); 601 drm_dev_unref(ddev);
613err_free_priv: 602err_destroy_wq:
614 destroy_workqueue(priv->wq); 603 destroy_workqueue(priv->wq);
615 kfree(priv);
616err_disconnect_dssdevs:
617 omap_disconnect_dssdevs(); 604 omap_disconnect_dssdevs();
618err_crtc_uninit: 605err_crtc_uninit:
619 omap_crtc_pre_uninit(); 606 omap_crtc_pre_uninit();
620 return ret; 607 return ret;
621} 608}
622 609
623static int pdev_remove(struct platform_device *pdev) 610static void omapdrm_cleanup(struct omap_drm_private *priv)
624{ 611{
625 struct drm_device *ddev = platform_get_drvdata(pdev); 612 struct drm_device *ddev = priv->ddev;
626 struct omap_drm_private *priv = ddev->dev_private;
627 613
628 DBG(""); 614 DBG("");
629 615
@@ -632,8 +618,7 @@ static int pdev_remove(struct platform_device *pdev)
632 omap_modeset_disable_external_hpd(); 618 omap_modeset_disable_external_hpd();
633 drm_kms_helper_poll_fini(ddev); 619 drm_kms_helper_poll_fini(ddev);
634 620
635 if (priv->fbdev) 621 omap_fbdev_fini(ddev);
636 omap_fbdev_free(ddev);
637 622
638 drm_atomic_helper_shutdown(ddev); 623 drm_atomic_helper_shutdown(ddev);
639 624
@@ -645,10 +630,45 @@ static int pdev_remove(struct platform_device *pdev)
645 drm_dev_unref(ddev); 630 drm_dev_unref(ddev);
646 631
647 destroy_workqueue(priv->wq); 632 destroy_workqueue(priv->wq);
648 kfree(priv);
649 633
650 omap_disconnect_dssdevs(); 634 omap_disconnect_dssdevs();
651 omap_crtc_pre_uninit(); 635 omap_crtc_pre_uninit();
636}
637
638static int pdev_probe(struct platform_device *pdev)
639{
640 struct omap_drm_private *priv;
641 int ret;
642
643 if (omapdss_is_initialized() == false)
644 return -EPROBE_DEFER;
645
646 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
647 if (ret) {
648 dev_err(&pdev->dev, "Failed to set the DMA mask\n");
649 return ret;
650 }
651
652 /* Allocate and initialize the driver private structure. */
653 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
654 if (!priv)
655 return -ENOMEM;
656
657 platform_set_drvdata(pdev, priv);
658
659 ret = omapdrm_init(priv, &pdev->dev);
660 if (ret < 0)
661 kfree(priv);
662
663 return ret;
664}
665
666static int pdev_remove(struct platform_device *pdev)
667{
668 struct omap_drm_private *priv = platform_get_drvdata(pdev);
669
670 omapdrm_cleanup(priv);
671 kfree(priv);
652 672
653 return 0; 673 return 0;
654} 674}
@@ -692,7 +712,8 @@ static int omap_drm_resume_all_displays(void)
692 712
693static int omap_drm_suspend(struct device *dev) 713static int omap_drm_suspend(struct device *dev)
694{ 714{
695 struct drm_device *drm_dev = dev_get_drvdata(dev); 715 struct omap_drm_private *priv = dev_get_drvdata(dev);
716 struct drm_device *drm_dev = priv->ddev;
696 717
697 drm_kms_helper_poll_disable(drm_dev); 718 drm_kms_helper_poll_disable(drm_dev);
698 719
@@ -705,7 +726,8 @@ static int omap_drm_suspend(struct device *dev)
705 726
706static int omap_drm_resume(struct device *dev) 727static int omap_drm_resume(struct device *dev)
707{ 728{
708 struct drm_device *drm_dev = dev_get_drvdata(dev); 729 struct omap_drm_private *priv = dev_get_drvdata(dev);
730 struct drm_device *drm_dev = priv->ddev;
709 731
710 drm_modeset_lock_all(drm_dev); 732 drm_modeset_lock_all(drm_dev);
711 omap_drm_resume_all_displays(); 733 omap_drm_resume_all_displays();
diff --git a/drivers/gpu/drm/omapdrm/omap_drv.h b/drivers/gpu/drm/omapdrm/omap_drv.h
index 0ac97fe09f9b..6eaee4df4559 100644
--- a/drivers/gpu/drm/omapdrm/omap_drv.h
+++ b/drivers/gpu/drm/omapdrm/omap_drv.h
@@ -46,8 +46,12 @@
46struct omap_drm_usergart; 46struct omap_drm_usergart;
47 47
48struct omap_drm_private { 48struct omap_drm_private {
49 uint32_t omaprev; 49 struct drm_device *ddev;
50 struct device *dev;
51 u32 omaprev;
50 52
53 struct dss_device *dss;
54 struct dispc_device *dispc;
51 const struct dispc_ops *dispc_ops; 55 const struct dispc_ops *dispc_ops;
52 56
53 unsigned int num_crtcs; 57 unsigned int num_crtcs;
@@ -81,7 +85,7 @@ struct omap_drm_private {
81 /* irq handling: */ 85 /* irq handling: */
82 spinlock_t wait_lock; /* protects the wait_list */ 86 spinlock_t wait_lock; /* protects the wait_list */
83 struct list_head wait_list; /* list of omap_irq_wait */ 87 struct list_head wait_list; /* list of omap_irq_wait */
84 uint32_t irq_mask; /* enabled irqs in addition to wait_list */ 88 u32 irq_mask; /* enabled irqs in addition to wait_list */
85 89
86 /* memory bandwidth limit if it is needed on the platform */ 90 /* memory bandwidth limit if it is needed on the platform */
87 unsigned int max_bandwidth; 91 unsigned int max_bandwidth;
diff --git a/drivers/gpu/drm/omapdrm/omap_fb.c b/drivers/gpu/drm/omapdrm/omap_fb.c
index b2539a90e1a4..5fd22ca73913 100644
--- a/drivers/gpu/drm/omapdrm/omap_fb.c
+++ b/drivers/gpu/drm/omapdrm/omap_fb.c
@@ -52,8 +52,8 @@ static const u32 formats[] = {
52/* per-plane info for the fb: */ 52/* per-plane info for the fb: */
53struct plane { 53struct plane {
54 struct drm_gem_object *bo; 54 struct drm_gem_object *bo;
55 uint32_t pitch; 55 u32 pitch;
56 uint32_t offset; 56 u32 offset;
57 dma_addr_t dma_addr; 57 dma_addr_t dma_addr;
58}; 58};
59 59
@@ -100,10 +100,10 @@ static const struct drm_framebuffer_funcs omap_framebuffer_funcs = {
100 .destroy = omap_framebuffer_destroy, 100 .destroy = omap_framebuffer_destroy,
101}; 101};
102 102
103static uint32_t get_linear_addr(struct plane *plane, 103static u32 get_linear_addr(struct plane *plane,
104 const struct drm_format_info *format, int n, int x, int y) 104 const struct drm_format_info *format, int n, int x, int y)
105{ 105{
106 uint32_t offset; 106 u32 offset;
107 107
108 offset = plane->offset 108 offset = plane->offset
109 + (x * format->cpp[n] / (n == 0 ? 1 : format->hsub)) 109 + (x * format->cpp[n] / (n == 0 ? 1 : format->hsub))
@@ -121,9 +121,9 @@ bool omap_framebuffer_supports_rotation(struct drm_framebuffer *fb)
121} 121}
122 122
123/* Note: DRM rotates counter-clockwise, TILER & DSS rotates clockwise */ 123/* Note: DRM rotates counter-clockwise, TILER & DSS rotates clockwise */
124static uint32_t drm_rotation_to_tiler(unsigned int drm_rot) 124static u32 drm_rotation_to_tiler(unsigned int drm_rot)
125{ 125{
126 uint32_t orient; 126 u32 orient;
127 127
128 switch (drm_rot & DRM_MODE_ROTATE_MASK) { 128 switch (drm_rot & DRM_MODE_ROTATE_MASK) {
129 default: 129 default:
@@ -158,7 +158,7 @@ void omap_framebuffer_update_scanout(struct drm_framebuffer *fb,
158 struct omap_framebuffer *omap_fb = to_omap_framebuffer(fb); 158 struct omap_framebuffer *omap_fb = to_omap_framebuffer(fb);
159 const struct drm_format_info *format = omap_fb->format; 159 const struct drm_format_info *format = omap_fb->format;
160 struct plane *plane = &omap_fb->planes[0]; 160 struct plane *plane = &omap_fb->planes[0];
161 uint32_t x, y, orient = 0; 161 u32 x, y, orient = 0;
162 162
163 info->fourcc = fb->format->format; 163 info->fourcc = fb->format->format;
164 164
@@ -177,8 +177,8 @@ void omap_framebuffer_update_scanout(struct drm_framebuffer *fb,
177 y = state->src_y >> 16; 177 y = state->src_y >> 16;
178 178
179 if (omap_gem_flags(plane->bo) & OMAP_BO_TILED) { 179 if (omap_gem_flags(plane->bo) & OMAP_BO_TILED) {
180 uint32_t w = state->src_w >> 16; 180 u32 w = state->src_w >> 16;
181 uint32_t h = state->src_h >> 16; 181 u32 h = state->src_h >> 16;
182 182
183 orient = drm_rotation_to_tiler(state->rotation); 183 orient = drm_rotation_to_tiler(state->rotation);
184 184
diff --git a/drivers/gpu/drm/omapdrm/omap_fbdev.c b/drivers/gpu/drm/omapdrm/omap_fbdev.c
index fb309d19ca1b..0f66c74a54b0 100644
--- a/drivers/gpu/drm/omapdrm/omap_fbdev.c
+++ b/drivers/gpu/drm/omapdrm/omap_fbdev.c
@@ -80,15 +80,21 @@ fallback:
80 80
81static struct fb_ops omap_fb_ops = { 81static struct fb_ops omap_fb_ops = {
82 .owner = THIS_MODULE, 82 .owner = THIS_MODULE,
83 DRM_FB_HELPER_DEFAULT_OPS, 83
84 .fb_check_var = drm_fb_helper_check_var,
85 .fb_set_par = drm_fb_helper_set_par,
86 .fb_setcmap = drm_fb_helper_setcmap,
87 .fb_blank = drm_fb_helper_blank,
88 .fb_pan_display = omap_fbdev_pan_display,
89 .fb_debug_enter = drm_fb_helper_debug_enter,
90 .fb_debug_leave = drm_fb_helper_debug_leave,
91 .fb_ioctl = drm_fb_helper_ioctl,
84 92
85 .fb_read = drm_fb_helper_sys_read, 93 .fb_read = drm_fb_helper_sys_read,
86 .fb_write = drm_fb_helper_sys_write, 94 .fb_write = drm_fb_helper_sys_write,
87 .fb_fillrect = drm_fb_helper_sys_fillrect, 95 .fb_fillrect = drm_fb_helper_sys_fillrect,
88 .fb_copyarea = drm_fb_helper_sys_copyarea, 96 .fb_copyarea = drm_fb_helper_sys_copyarea,
89 .fb_imageblit = drm_fb_helper_sys_imageblit, 97 .fb_imageblit = drm_fb_helper_sys_imageblit,
90
91 .fb_pan_display = omap_fbdev_pan_display,
92}; 98};
93 99
94static int omap_fbdev_create(struct drm_fb_helper *helper, 100static int omap_fbdev_create(struct drm_fb_helper *helper,
@@ -188,7 +194,7 @@ static int omap_fbdev_create(struct drm_fb_helper *helper,
188 194
189 dev->mode_config.fb_base = dma_addr; 195 dev->mode_config.fb_base = dma_addr;
190 196
191 fbi->screen_base = omap_gem_vaddr(fbdev->bo); 197 fbi->screen_buffer = omap_gem_vaddr(fbdev->bo);
192 fbi->screen_size = fbdev->bo->size; 198 fbi->screen_size = fbdev->bo->size;
193 fbi->fix.smem_start = dma_addr; 199 fbi->fix.smem_start = dma_addr;
194 fbi->fix.smem_len = fbdev->bo->size; 200 fbi->fix.smem_len = fbdev->bo->size;
@@ -236,13 +242,16 @@ static struct drm_fb_helper *get_fb(struct fb_info *fbi)
236} 242}
237 243
238/* initialize fbdev helper */ 244/* initialize fbdev helper */
239struct drm_fb_helper *omap_fbdev_init(struct drm_device *dev) 245void omap_fbdev_init(struct drm_device *dev)
240{ 246{
241 struct omap_drm_private *priv = dev->dev_private; 247 struct omap_drm_private *priv = dev->dev_private;
242 struct omap_fbdev *fbdev = NULL; 248 struct omap_fbdev *fbdev = NULL;
243 struct drm_fb_helper *helper; 249 struct drm_fb_helper *helper;
244 int ret = 0; 250 int ret = 0;
245 251
252 if (!priv->num_crtcs || !priv->num_connectors)
253 return;
254
246 fbdev = kzalloc(sizeof(*fbdev), GFP_KERNEL); 255 fbdev = kzalloc(sizeof(*fbdev), GFP_KERNEL);
247 if (!fbdev) 256 if (!fbdev)
248 goto fail; 257 goto fail;
@@ -254,10 +263,8 @@ struct drm_fb_helper *omap_fbdev_init(struct drm_device *dev)
254 drm_fb_helper_prepare(dev, helper, &omap_fb_helper_funcs); 263 drm_fb_helper_prepare(dev, helper, &omap_fb_helper_funcs);
255 264
256 ret = drm_fb_helper_init(dev, helper, priv->num_connectors); 265 ret = drm_fb_helper_init(dev, helper, priv->num_connectors);
257 if (ret) { 266 if (ret)
258 dev_err(dev->dev, "could not init fbdev: ret=%d\n", ret);
259 goto fail; 267 goto fail;
260 }
261 268
262 ret = drm_fb_helper_single_add_all_connectors(helper); 269 ret = drm_fb_helper_single_add_all_connectors(helper);
263 if (ret) 270 if (ret)
@@ -269,7 +276,7 @@ struct drm_fb_helper *omap_fbdev_init(struct drm_device *dev)
269 276
270 priv->fbdev = helper; 277 priv->fbdev = helper;
271 278
272 return helper; 279 return;
273 280
274fini: 281fini:
275 drm_fb_helper_fini(helper); 282 drm_fb_helper_fini(helper);
@@ -277,12 +284,9 @@ fail:
277 kfree(fbdev); 284 kfree(fbdev);
278 285
279 dev_warn(dev->dev, "omap_fbdev_init failed\n"); 286 dev_warn(dev->dev, "omap_fbdev_init failed\n");
280 /* well, limp along without an fbdev.. maybe X11 will work? */
281
282 return NULL;
283} 287}
284 288
285void omap_fbdev_free(struct drm_device *dev) 289void omap_fbdev_fini(struct drm_device *dev)
286{ 290{
287 struct omap_drm_private *priv = dev->dev_private; 291 struct omap_drm_private *priv = dev->dev_private;
288 struct drm_fb_helper *helper = priv->fbdev; 292 struct drm_fb_helper *helper = priv->fbdev;
@@ -290,14 +294,18 @@ void omap_fbdev_free(struct drm_device *dev)
290 294
291 DBG(); 295 DBG();
292 296
297 if (!helper)
298 return;
299
293 drm_fb_helper_unregister_fbi(helper); 300 drm_fb_helper_unregister_fbi(helper);
294 301
295 drm_fb_helper_fini(helper); 302 drm_fb_helper_fini(helper);
296 303
297 fbdev = to_omap_fbdev(priv->fbdev); 304 fbdev = to_omap_fbdev(helper);
298 305
299 /* unpin the GEM object pinned in omap_fbdev_create() */ 306 /* unpin the GEM object pinned in omap_fbdev_create() */
300 omap_gem_unpin(fbdev->bo); 307 if (fbdev->bo)
308 omap_gem_unpin(fbdev->bo);
301 309
302 /* this will free the backing object */ 310 /* this will free the backing object */
303 if (fbdev->fb) 311 if (fbdev->fb)
diff --git a/drivers/gpu/drm/omapdrm/omap_fbdev.h b/drivers/gpu/drm/omapdrm/omap_fbdev.h
index 1f5ba0996a1a..7dfd843f73f1 100644
--- a/drivers/gpu/drm/omapdrm/omap_fbdev.h
+++ b/drivers/gpu/drm/omapdrm/omap_fbdev.h
@@ -24,14 +24,13 @@ struct drm_device;
24struct drm_fb_helper; 24struct drm_fb_helper;
25 25
26#ifdef CONFIG_DRM_FBDEV_EMULATION 26#ifdef CONFIG_DRM_FBDEV_EMULATION
27struct drm_fb_helper *omap_fbdev_init(struct drm_device *dev); 27void omap_fbdev_init(struct drm_device *dev);
28void omap_fbdev_free(struct drm_device *dev); 28void omap_fbdev_fini(struct drm_device *dev);
29#else 29#else
30static inline struct drm_fb_helper *omap_fbdev_init(struct drm_device *dev) 30static inline void omap_fbdev_init(struct drm_device *dev)
31{ 31{
32 return NULL;
33} 32}
34static inline void omap_fbdev_free(struct drm_device *dev) 33static inline void omap_fbdev_fini(struct drm_device *dev)
35{ 34{
36} 35}
37#endif 36#endif
diff --git a/drivers/gpu/drm/omapdrm/omap_gem.c b/drivers/gpu/drm/omapdrm/omap_gem.c
index 443469d4fa46..0faf042b82e1 100644
--- a/drivers/gpu/drm/omapdrm/omap_gem.c
+++ b/drivers/gpu/drm/omapdrm/omap_gem.c
@@ -39,13 +39,13 @@ struct omap_gem_object {
39 39
40 struct list_head mm_list; 40 struct list_head mm_list;
41 41
42 uint32_t flags; 42 u32 flags;
43 43
44 /** width/height for tiled formats (rounded up to slot boundaries) */ 44 /** width/height for tiled formats (rounded up to slot boundaries) */
45 uint16_t width, height; 45 u16 width, height;
46 46
47 /** roll applied when mapping to DMM */ 47 /** roll applied when mapping to DMM */
48 uint32_t roll; 48 u32 roll;
49 49
50 /** 50 /**
51 * dma_addr contains the buffer DMA address. It is valid for 51 * dma_addr contains the buffer DMA address. It is valid for
@@ -73,7 +73,7 @@ struct omap_gem_object {
73 /** 73 /**
74 * # of users of dma_addr 74 * # of users of dma_addr
75 */ 75 */
76 uint32_t dma_addr_cnt; 76 u32 dma_addr_cnt;
77 77
78 /** 78 /**
79 * If the buffer has been imported from a dmabuf the OMAP_DB_DMABUF flag 79 * If the buffer has been imported from a dmabuf the OMAP_DB_DMABUF flag
@@ -137,7 +137,7 @@ struct omap_drm_usergart {
137 */ 137 */
138 138
139/** get mmap offset */ 139/** get mmap offset */
140static uint64_t mmap_offset(struct drm_gem_object *obj) 140static u64 mmap_offset(struct drm_gem_object *obj)
141{ 141{
142 struct drm_device *dev = obj->dev; 142 struct drm_device *dev = obj->dev;
143 int ret; 143 int ret;
@@ -331,14 +331,15 @@ static void omap_gem_detach_pages(struct drm_gem_object *obj)
331} 331}
332 332
333/* get buffer flags */ 333/* get buffer flags */
334uint32_t omap_gem_flags(struct drm_gem_object *obj) 334u32 omap_gem_flags(struct drm_gem_object *obj)
335{ 335{
336 return to_omap_bo(obj)->flags; 336 return to_omap_bo(obj)->flags;
337} 337}
338 338
339uint64_t omap_gem_mmap_offset(struct drm_gem_object *obj) 339u64 omap_gem_mmap_offset(struct drm_gem_object *obj)
340{ 340{
341 uint64_t offset; 341 u64 offset;
342
342 mutex_lock(&obj->dev->struct_mutex); 343 mutex_lock(&obj->dev->struct_mutex);
343 offset = mmap_offset(obj); 344 offset = mmap_offset(obj);
344 mutex_unlock(&obj->dev->struct_mutex); 345 mutex_unlock(&obj->dev->struct_mutex);
@@ -649,7 +650,7 @@ int omap_gem_dumb_create(struct drm_file *file, struct drm_device *dev,
649 * into user memory. We don't have to do much here at the moment. 650 * into user memory. We don't have to do much here at the moment.
650 */ 651 */
651int omap_gem_dumb_map_offset(struct drm_file *file, struct drm_device *dev, 652int omap_gem_dumb_map_offset(struct drm_file *file, struct drm_device *dev,
652 uint32_t handle, uint64_t *offset) 653 u32 handle, u64 *offset)
653{ 654{
654 struct drm_gem_object *obj; 655 struct drm_gem_object *obj;
655 int ret = 0; 656 int ret = 0;
@@ -675,10 +676,10 @@ fail:
675 * 676 *
676 * Call only from non-atomic contexts. 677 * Call only from non-atomic contexts.
677 */ 678 */
678int omap_gem_roll(struct drm_gem_object *obj, uint32_t roll) 679int omap_gem_roll(struct drm_gem_object *obj, u32 roll)
679{ 680{
680 struct omap_gem_object *omap_obj = to_omap_bo(obj); 681 struct omap_gem_object *omap_obj = to_omap_bo(obj);
681 uint32_t npages = obj->size >> PAGE_SHIFT; 682 u32 npages = obj->size >> PAGE_SHIFT;
682 int ret = 0; 683 int ret = 0;
683 684
684 if (roll > npages) { 685 if (roll > npages) {
@@ -808,7 +809,7 @@ int omap_gem_pin(struct drm_gem_object *obj, dma_addr_t *dma_addr)
808 if (!is_contiguous(omap_obj) && priv->has_dmm) { 809 if (!is_contiguous(omap_obj) && priv->has_dmm) {
809 if (omap_obj->dma_addr_cnt == 0) { 810 if (omap_obj->dma_addr_cnt == 0) {
810 struct page **pages; 811 struct page **pages;
811 uint32_t npages = obj->size >> PAGE_SHIFT; 812 u32 npages = obj->size >> PAGE_SHIFT;
812 enum tiler_fmt fmt = gem2fmt(omap_obj->flags); 813 enum tiler_fmt fmt = gem2fmt(omap_obj->flags);
813 struct tiler_block *block; 814 struct tiler_block *block;
814 815
@@ -904,7 +905,7 @@ void omap_gem_unpin(struct drm_gem_object *obj)
904 * specified orientation and x,y offset from top-left corner of buffer 905 * specified orientation and x,y offset from top-left corner of buffer
905 * (only valid for tiled 2d buffers) 906 * (only valid for tiled 2d buffers)
906 */ 907 */
907int omap_gem_rotated_dma_addr(struct drm_gem_object *obj, uint32_t orient, 908int omap_gem_rotated_dma_addr(struct drm_gem_object *obj, u32 orient,
908 int x, int y, dma_addr_t *dma_addr) 909 int x, int y, dma_addr_t *dma_addr)
909{ 910{
910 struct omap_gem_object *omap_obj = to_omap_bo(obj); 911 struct omap_gem_object *omap_obj = to_omap_bo(obj);
@@ -921,7 +922,7 @@ int omap_gem_rotated_dma_addr(struct drm_gem_object *obj, uint32_t orient,
921} 922}
922 923
923/* Get tiler stride for the buffer (only valid for 2d tiled buffers) */ 924/* Get tiler stride for the buffer (only valid for 2d tiled buffers) */
924int omap_gem_tiled_stride(struct drm_gem_object *obj, uint32_t orient) 925int omap_gem_tiled_stride(struct drm_gem_object *obj, u32 orient)
925{ 926{
926 struct omap_gem_object *omap_obj = to_omap_bo(obj); 927 struct omap_gem_object *omap_obj = to_omap_bo(obj);
927 int ret = -EINVAL; 928 int ret = -EINVAL;
@@ -1003,7 +1004,8 @@ int omap_gem_resume(struct drm_device *dev)
1003 list_for_each_entry(omap_obj, &priv->obj_list, mm_list) { 1004 list_for_each_entry(omap_obj, &priv->obj_list, mm_list) {
1004 if (omap_obj->block) { 1005 if (omap_obj->block) {
1005 struct drm_gem_object *obj = &omap_obj->base; 1006 struct drm_gem_object *obj = &omap_obj->base;
1006 uint32_t npages = obj->size >> PAGE_SHIFT; 1007 u32 npages = obj->size >> PAGE_SHIFT;
1008
1007 WARN_ON(!omap_obj->pages); /* this can't happen */ 1009 WARN_ON(!omap_obj->pages); /* this can't happen */
1008 ret = tiler_pin(omap_obj->block, 1010 ret = tiler_pin(omap_obj->block,
1009 omap_obj->pages, npages, 1011 omap_obj->pages, npages,
@@ -1027,7 +1029,7 @@ int omap_gem_resume(struct drm_device *dev)
1027void omap_gem_describe(struct drm_gem_object *obj, struct seq_file *m) 1029void omap_gem_describe(struct drm_gem_object *obj, struct seq_file *m)
1028{ 1030{
1029 struct omap_gem_object *omap_obj = to_omap_bo(obj); 1031 struct omap_gem_object *omap_obj = to_omap_bo(obj);
1030 uint64_t off; 1032 u64 off;
1031 1033
1032 off = drm_vma_node_start(&obj->vma_node); 1034 off = drm_vma_node_start(&obj->vma_node);
1033 1035
@@ -1115,7 +1117,7 @@ void omap_gem_free_object(struct drm_gem_object *obj)
1115 1117
1116/* GEM buffer object constructor */ 1118/* GEM buffer object constructor */
1117struct drm_gem_object *omap_gem_new(struct drm_device *dev, 1119struct drm_gem_object *omap_gem_new(struct drm_device *dev,
1118 union omap_gem_size gsize, uint32_t flags) 1120 union omap_gem_size gsize, u32 flags)
1119{ 1121{
1120 struct omap_drm_private *priv = dev->dev_private; 1122 struct omap_drm_private *priv = dev->dev_private;
1121 struct omap_gem_object *omap_obj; 1123 struct omap_gem_object *omap_obj;
@@ -1280,7 +1282,7 @@ done:
1280 1282
1281/* convenience method to construct a GEM buffer object, and userspace handle */ 1283/* convenience method to construct a GEM buffer object, and userspace handle */
1282int omap_gem_new_handle(struct drm_device *dev, struct drm_file *file, 1284int omap_gem_new_handle(struct drm_device *dev, struct drm_file *file,
1283 union omap_gem_size gsize, uint32_t flags, uint32_t *handle) 1285 union omap_gem_size gsize, u32 flags, u32 *handle)
1284{ 1286{
1285 struct drm_gem_object *obj; 1287 struct drm_gem_object *obj;
1286 int ret; 1288 int ret;
@@ -1327,7 +1329,8 @@ void omap_gem_init(struct drm_device *dev)
1327 1329
1328 /* reserve 4k aligned/wide regions for userspace mappings: */ 1330 /* reserve 4k aligned/wide regions for userspace mappings: */
1329 for (i = 0; i < ARRAY_SIZE(fmts); i++) { 1331 for (i = 0; i < ARRAY_SIZE(fmts); i++) {
1330 uint16_t h = 1, w = PAGE_SIZE >> i; 1332 u16 h = 1, w = PAGE_SIZE >> i;
1333
1331 tiler_align(fmts[i], &w, &h); 1334 tiler_align(fmts[i], &w, &h);
1332 /* note: since each region is 1 4kb page wide, and minimum 1335 /* note: since each region is 1 4kb page wide, and minimum
1333 * number of rows, the height ends up being the same as the 1336 * number of rows, the height ends up being the same as the
diff --git a/drivers/gpu/drm/omapdrm/omap_gem.h b/drivers/gpu/drm/omapdrm/omap_gem.h
index 35fa690b3d90..a78bde05193a 100644
--- a/drivers/gpu/drm/omapdrm/omap_gem.h
+++ b/drivers/gpu/drm/omapdrm/omap_gem.h
@@ -53,17 +53,17 @@ void omap_gem_describe_objects(struct list_head *list, struct seq_file *m);
53 53
54/* GEM Object Creation and Deletion */ 54/* GEM Object Creation and Deletion */
55struct drm_gem_object *omap_gem_new(struct drm_device *dev, 55struct drm_gem_object *omap_gem_new(struct drm_device *dev,
56 union omap_gem_size gsize, uint32_t flags); 56 union omap_gem_size gsize, u32 flags);
57struct drm_gem_object *omap_gem_new_dmabuf(struct drm_device *dev, size_t size, 57struct drm_gem_object *omap_gem_new_dmabuf(struct drm_device *dev, size_t size,
58 struct sg_table *sgt); 58 struct sg_table *sgt);
59int omap_gem_new_handle(struct drm_device *dev, struct drm_file *file, 59int omap_gem_new_handle(struct drm_device *dev, struct drm_file *file,
60 union omap_gem_size gsize, uint32_t flags, uint32_t *handle); 60 union omap_gem_size gsize, u32 flags, u32 *handle);
61void omap_gem_free_object(struct drm_gem_object *obj); 61void omap_gem_free_object(struct drm_gem_object *obj);
62void *omap_gem_vaddr(struct drm_gem_object *obj); 62void *omap_gem_vaddr(struct drm_gem_object *obj);
63 63
64/* Dumb Buffers Interface */ 64/* Dumb Buffers Interface */
65int omap_gem_dumb_map_offset(struct drm_file *file, struct drm_device *dev, 65int omap_gem_dumb_map_offset(struct drm_file *file, struct drm_device *dev,
66 uint32_t handle, uint64_t *offset); 66 u32 handle, u64 *offset);
67int omap_gem_dumb_create(struct drm_file *file, struct drm_device *dev, 67int omap_gem_dumb_create(struct drm_file *file, struct drm_device *dev,
68 struct drm_mode_create_dumb *args); 68 struct drm_mode_create_dumb *args);
69 69
@@ -71,7 +71,7 @@ int omap_gem_dumb_create(struct drm_file *file, struct drm_device *dev,
71int omap_gem_mmap(struct file *filp, struct vm_area_struct *vma); 71int omap_gem_mmap(struct file *filp, struct vm_area_struct *vma);
72int omap_gem_mmap_obj(struct drm_gem_object *obj, 72int omap_gem_mmap_obj(struct drm_gem_object *obj,
73 struct vm_area_struct *vma); 73 struct vm_area_struct *vma);
74uint64_t omap_gem_mmap_offset(struct drm_gem_object *obj); 74u64 omap_gem_mmap_offset(struct drm_gem_object *obj);
75size_t omap_gem_mmap_size(struct drm_gem_object *obj); 75size_t omap_gem_mmap_size(struct drm_gem_object *obj);
76 76
77/* PRIME Interface */ 77/* PRIME Interface */
@@ -81,7 +81,7 @@ struct drm_gem_object *omap_gem_prime_import(struct drm_device *dev,
81 struct dma_buf *buffer); 81 struct dma_buf *buffer);
82 82
83int omap_gem_fault(struct vm_fault *vmf); 83int omap_gem_fault(struct vm_fault *vmf);
84int omap_gem_roll(struct drm_gem_object *obj, uint32_t roll); 84int omap_gem_roll(struct drm_gem_object *obj, u32 roll);
85void omap_gem_cpu_sync_page(struct drm_gem_object *obj, int pgoff); 85void omap_gem_cpu_sync_page(struct drm_gem_object *obj, int pgoff);
86void omap_gem_dma_sync_buffer(struct drm_gem_object *obj, 86void omap_gem_dma_sync_buffer(struct drm_gem_object *obj,
87 enum dma_data_direction dir); 87 enum dma_data_direction dir);
@@ -91,9 +91,9 @@ int omap_gem_get_pages(struct drm_gem_object *obj, struct page ***pages,
91 bool remap); 91 bool remap);
92int omap_gem_put_pages(struct drm_gem_object *obj); 92int omap_gem_put_pages(struct drm_gem_object *obj);
93 93
94uint32_t omap_gem_flags(struct drm_gem_object *obj); 94u32 omap_gem_flags(struct drm_gem_object *obj);
95int omap_gem_rotated_dma_addr(struct drm_gem_object *obj, uint32_t orient, 95int omap_gem_rotated_dma_addr(struct drm_gem_object *obj, u32 orient,
96 int x, int y, dma_addr_t *dma_addr); 96 int x, int y, dma_addr_t *dma_addr);
97int omap_gem_tiled_stride(struct drm_gem_object *obj, uint32_t orient); 97int omap_gem_tiled_stride(struct drm_gem_object *obj, u32 orient);
98 98
99#endif /* __OMAPDRM_GEM_H__ */ 99#endif /* __OMAPDRM_GEM_H__ */
diff --git a/drivers/gpu/drm/omapdrm/omap_irq.c b/drivers/gpu/drm/omapdrm/omap_irq.c
index 53ba424823b2..c85115049f86 100644
--- a/drivers/gpu/drm/omapdrm/omap_irq.c
+++ b/drivers/gpu/drm/omapdrm/omap_irq.c
@@ -20,7 +20,7 @@
20struct omap_irq_wait { 20struct omap_irq_wait {
21 struct list_head node; 21 struct list_head node;
22 wait_queue_head_t wq; 22 wait_queue_head_t wq;
23 uint32_t irqmask; 23 u32 irqmask;
24 int count; 24 int count;
25}; 25};
26 26
@@ -29,7 +29,7 @@ static void omap_irq_update(struct drm_device *dev)
29{ 29{
30 struct omap_drm_private *priv = dev->dev_private; 30 struct omap_drm_private *priv = dev->dev_private;
31 struct omap_irq_wait *wait; 31 struct omap_irq_wait *wait;
32 uint32_t irqmask = priv->irq_mask; 32 u32 irqmask = priv->irq_mask;
33 33
34 assert_spin_locked(&priv->wait_lock); 34 assert_spin_locked(&priv->wait_lock);
35 35
@@ -38,7 +38,7 @@ static void omap_irq_update(struct drm_device *dev)
38 38
39 DBG("irqmask=%08x", irqmask); 39 DBG("irqmask=%08x", irqmask);
40 40
41 priv->dispc_ops->write_irqenable(irqmask); 41 priv->dispc_ops->write_irqenable(priv->dispc, irqmask);
42} 42}
43 43
44static void omap_irq_wait_handler(struct omap_irq_wait *wait) 44static void omap_irq_wait_handler(struct omap_irq_wait *wait)
@@ -48,7 +48,7 @@ static void omap_irq_wait_handler(struct omap_irq_wait *wait)
48} 48}
49 49
50struct omap_irq_wait * omap_irq_wait_init(struct drm_device *dev, 50struct omap_irq_wait * omap_irq_wait_init(struct drm_device *dev,
51 uint32_t irqmask, int count) 51 u32 irqmask, int count)
52{ 52{
53 struct omap_drm_private *priv = dev->dev_private; 53 struct omap_drm_private *priv = dev->dev_private;
54 struct omap_irq_wait *wait = kzalloc(sizeof(*wait), GFP_KERNEL); 54 struct omap_irq_wait *wait = kzalloc(sizeof(*wait), GFP_KERNEL);
@@ -108,7 +108,8 @@ int omap_irq_enable_vblank(struct drm_crtc *crtc)
108 DBG("dev=%p, crtc=%u", dev, channel); 108 DBG("dev=%p, crtc=%u", dev, channel);
109 109
110 spin_lock_irqsave(&priv->wait_lock, flags); 110 spin_lock_irqsave(&priv->wait_lock, flags);
111 priv->irq_mask |= priv->dispc_ops->mgr_get_vsync_irq(channel); 111 priv->irq_mask |= priv->dispc_ops->mgr_get_vsync_irq(priv->dispc,
112 channel);
112 omap_irq_update(dev); 113 omap_irq_update(dev);
113 spin_unlock_irqrestore(&priv->wait_lock, flags); 114 spin_unlock_irqrestore(&priv->wait_lock, flags);
114 115
@@ -134,7 +135,8 @@ void omap_irq_disable_vblank(struct drm_crtc *crtc)
134 DBG("dev=%p, crtc=%u", dev, channel); 135 DBG("dev=%p, crtc=%u", dev, channel);
135 136
136 spin_lock_irqsave(&priv->wait_lock, flags); 137 spin_lock_irqsave(&priv->wait_lock, flags);
137 priv->irq_mask &= ~priv->dispc_ops->mgr_get_vsync_irq(channel); 138 priv->irq_mask &= ~priv->dispc_ops->mgr_get_vsync_irq(priv->dispc,
139 channel);
138 omap_irq_update(dev); 140 omap_irq_update(dev);
139 spin_unlock_irqrestore(&priv->wait_lock, flags); 141 spin_unlock_irqrestore(&priv->wait_lock, flags);
140} 142}
@@ -198,9 +200,9 @@ static irqreturn_t omap_irq_handler(int irq, void *arg)
198 unsigned int id; 200 unsigned int id;
199 u32 irqstatus; 201 u32 irqstatus;
200 202
201 irqstatus = priv->dispc_ops->read_irqstatus(); 203 irqstatus = priv->dispc_ops->read_irqstatus(priv->dispc);
202 priv->dispc_ops->clear_irqstatus(irqstatus); 204 priv->dispc_ops->clear_irqstatus(priv->dispc, irqstatus);
203 priv->dispc_ops->read_irqstatus(); /* flush posted write */ 205 priv->dispc_ops->read_irqstatus(priv->dispc); /* flush posted write */
204 206
205 VERB("irqs: %08x", irqstatus); 207 VERB("irqs: %08x", irqstatus);
206 208
@@ -208,12 +210,12 @@ static irqreturn_t omap_irq_handler(int irq, void *arg)
208 struct drm_crtc *crtc = priv->crtcs[id]; 210 struct drm_crtc *crtc = priv->crtcs[id];
209 enum omap_channel channel = omap_crtc_channel(crtc); 211 enum omap_channel channel = omap_crtc_channel(crtc);
210 212
211 if (irqstatus & priv->dispc_ops->mgr_get_vsync_irq(channel)) { 213 if (irqstatus & priv->dispc_ops->mgr_get_vsync_irq(priv->dispc, channel)) {
212 drm_handle_vblank(dev, id); 214 drm_handle_vblank(dev, id);
213 omap_crtc_vblank_irq(crtc); 215 omap_crtc_vblank_irq(crtc);
214 } 216 }
215 217
216 if (irqstatus & priv->dispc_ops->mgr_get_sync_lost_irq(channel)) 218 if (irqstatus & priv->dispc_ops->mgr_get_sync_lost_irq(priv->dispc, channel))
217 omap_crtc_error_irq(crtc, irqstatus); 219 omap_crtc_error_irq(crtc, irqstatus);
218 } 220 }
219 221
@@ -247,7 +249,7 @@ static const u32 omap_underflow_irqs[] = {
247int omap_drm_irq_install(struct drm_device *dev) 249int omap_drm_irq_install(struct drm_device *dev)
248{ 250{
249 struct omap_drm_private *priv = dev->dev_private; 251 struct omap_drm_private *priv = dev->dev_private;
250 unsigned int num_mgrs = priv->dispc_ops->get_num_mgrs(); 252 unsigned int num_mgrs = priv->dispc_ops->get_num_mgrs(priv->dispc);
251 unsigned int max_planes; 253 unsigned int max_planes;
252 unsigned int i; 254 unsigned int i;
253 int ret; 255 int ret;
@@ -265,13 +267,13 @@ int omap_drm_irq_install(struct drm_device *dev)
265 } 267 }
266 268
267 for (i = 0; i < num_mgrs; ++i) 269 for (i = 0; i < num_mgrs; ++i)
268 priv->irq_mask |= priv->dispc_ops->mgr_get_sync_lost_irq(i); 270 priv->irq_mask |= priv->dispc_ops->mgr_get_sync_lost_irq(priv->dispc, i);
269 271
270 priv->dispc_ops->runtime_get(); 272 priv->dispc_ops->runtime_get(priv->dispc);
271 priv->dispc_ops->clear_irqstatus(0xffffffff); 273 priv->dispc_ops->clear_irqstatus(priv->dispc, 0xffffffff);
272 priv->dispc_ops->runtime_put(); 274 priv->dispc_ops->runtime_put(priv->dispc);
273 275
274 ret = priv->dispc_ops->request_irq(omap_irq_handler, dev); 276 ret = priv->dispc_ops->request_irq(priv->dispc, omap_irq_handler, dev);
275 if (ret < 0) 277 if (ret < 0)
276 return ret; 278 return ret;
277 279
@@ -289,5 +291,5 @@ void omap_drm_irq_uninstall(struct drm_device *dev)
289 291
290 dev->irq_enabled = false; 292 dev->irq_enabled = false;
291 293
292 priv->dispc_ops->free_irq(dev); 294 priv->dispc_ops->free_irq(priv->dispc, dev);
293} 295}
diff --git a/drivers/gpu/drm/omapdrm/omap_irq.h b/drivers/gpu/drm/omapdrm/omap_irq.h
index 606c09932bc0..9d5441468eca 100644
--- a/drivers/gpu/drm/omapdrm/omap_irq.h
+++ b/drivers/gpu/drm/omapdrm/omap_irq.h
@@ -32,7 +32,7 @@ void omap_drm_irq_uninstall(struct drm_device *dev);
32int omap_drm_irq_install(struct drm_device *dev); 32int omap_drm_irq_install(struct drm_device *dev);
33 33
34struct omap_irq_wait *omap_irq_wait_init(struct drm_device *dev, 34struct omap_irq_wait *omap_irq_wait_init(struct drm_device *dev,
35 uint32_t irqmask, int count); 35 u32 irqmask, int count);
36int omap_irq_wait(struct drm_device *dev, struct omap_irq_wait *wait, 36int omap_irq_wait(struct drm_device *dev, struct omap_irq_wait *wait,
37 unsigned long timeout); 37 unsigned long timeout);
38 38
diff --git a/drivers/gpu/drm/omapdrm/omap_plane.c b/drivers/gpu/drm/omapdrm/omap_plane.c
index 7d789d1551a1..2899435cad6e 100644
--- a/drivers/gpu/drm/omapdrm/omap_plane.c
+++ b/drivers/gpu/drm/omapdrm/omap_plane.c
@@ -77,17 +77,17 @@ static void omap_plane_atomic_update(struct drm_plane *plane,
77 &info.paddr, &info.p_uv_addr); 77 &info.paddr, &info.p_uv_addr);
78 78
79 /* and finally, update omapdss: */ 79 /* and finally, update omapdss: */
80 ret = priv->dispc_ops->ovl_setup(omap_plane->id, &info, 80 ret = priv->dispc_ops->ovl_setup(priv->dispc, omap_plane->id, &info,
81 omap_crtc_timings(state->crtc), false, 81 omap_crtc_timings(state->crtc), false,
82 omap_crtc_channel(state->crtc)); 82 omap_crtc_channel(state->crtc));
83 if (ret) { 83 if (ret) {
84 dev_err(plane->dev->dev, "Failed to setup plane %s\n", 84 dev_err(plane->dev->dev, "Failed to setup plane %s\n",
85 omap_plane->name); 85 omap_plane->name);
86 priv->dispc_ops->ovl_enable(omap_plane->id, false); 86 priv->dispc_ops->ovl_enable(priv->dispc, omap_plane->id, false);
87 return; 87 return;
88 } 88 }
89 89
90 priv->dispc_ops->ovl_enable(omap_plane->id, true); 90 priv->dispc_ops->ovl_enable(priv->dispc, omap_plane->id, true);
91} 91}
92 92
93static void omap_plane_atomic_disable(struct drm_plane *plane, 93static void omap_plane_atomic_disable(struct drm_plane *plane,
@@ -100,7 +100,7 @@ static void omap_plane_atomic_disable(struct drm_plane *plane,
100 plane->state->zpos = plane->type == DRM_PLANE_TYPE_PRIMARY 100 plane->state->zpos = plane->type == DRM_PLANE_TYPE_PRIMARY
101 ? 0 : omap_plane->id; 101 ? 0 : omap_plane->id;
102 102
103 priv->dispc_ops->ovl_enable(omap_plane->id, false); 103 priv->dispc_ops->ovl_enable(priv->dispc, omap_plane->id, false);
104} 104}
105 105
106static int omap_plane_atomic_check(struct drm_plane *plane, 106static int omap_plane_atomic_check(struct drm_plane *plane,
@@ -201,7 +201,7 @@ static void omap_plane_reset(struct drm_plane *plane)
201static int omap_plane_atomic_set_property(struct drm_plane *plane, 201static int omap_plane_atomic_set_property(struct drm_plane *plane,
202 struct drm_plane_state *state, 202 struct drm_plane_state *state,
203 struct drm_property *property, 203 struct drm_property *property,
204 uint64_t val) 204 u64 val)
205{ 205{
206 struct omap_drm_private *priv = plane->dev->dev_private; 206 struct omap_drm_private *priv = plane->dev->dev_private;
207 207
@@ -216,7 +216,7 @@ static int omap_plane_atomic_set_property(struct drm_plane *plane,
216static int omap_plane_atomic_get_property(struct drm_plane *plane, 216static int omap_plane_atomic_get_property(struct drm_plane *plane,
217 const struct drm_plane_state *state, 217 const struct drm_plane_state *state,
218 struct drm_property *property, 218 struct drm_property *property,
219 uint64_t *val) 219 u64 *val)
220{ 220{
221 struct omap_drm_private *priv = plane->dev->dev_private; 221 struct omap_drm_private *priv = plane->dev->dev_private;
222 222
@@ -259,7 +259,7 @@ struct drm_plane *omap_plane_init(struct drm_device *dev,
259 u32 possible_crtcs) 259 u32 possible_crtcs)
260{ 260{
261 struct omap_drm_private *priv = dev->dev_private; 261 struct omap_drm_private *priv = dev->dev_private;
262 unsigned int num_planes = priv->dispc_ops->get_num_ovls(); 262 unsigned int num_planes = priv->dispc_ops->get_num_ovls(priv->dispc);
263 struct drm_plane *plane; 263 struct drm_plane *plane;
264 struct omap_plane *omap_plane; 264 struct omap_plane *omap_plane;
265 enum omap_plane_id id; 265 enum omap_plane_id id;
@@ -278,7 +278,7 @@ struct drm_plane *omap_plane_init(struct drm_device *dev,
278 if (!omap_plane) 278 if (!omap_plane)
279 return ERR_PTR(-ENOMEM); 279 return ERR_PTR(-ENOMEM);
280 280
281 formats = priv->dispc_ops->ovl_get_color_modes(id); 281 formats = priv->dispc_ops->ovl_get_color_modes(priv->dispc, id);
282 for (nformats = 0; formats[nformats]; ++nformats) 282 for (nformats = 0; formats[nformats]; ++nformats)
283 ; 283 ;
284 omap_plane->id = id; 284 omap_plane->id = id;
diff --git a/drivers/gpu/drm/omapdrm/tcm-sita.c b/drivers/gpu/drm/omapdrm/tcm-sita.c
index 661362d072f7..d7f7bc9f061a 100644
--- a/drivers/gpu/drm/omapdrm/tcm-sita.c
+++ b/drivers/gpu/drm/omapdrm/tcm-sita.c
@@ -33,8 +33,8 @@ static unsigned long mask[8];
33 * map ptr to bitmap 33 * map ptr to bitmap
34 * stride slots in a row 34 * stride slots in a row
35 */ 35 */
36static void free_slots(unsigned long pos, uint16_t w, uint16_t h, 36static void free_slots(unsigned long pos, u16 w, u16 h,
37 unsigned long *map, uint16_t stride) 37 unsigned long *map, u16 stride)
38{ 38{
39 int i; 39 int i;
40 40
@@ -48,7 +48,7 @@ static void free_slots(unsigned long pos, uint16_t w, uint16_t h,
48 * map ptr to bitmap 48 * map ptr to bitmap
49 * num_bits number of bits in bitmap 49 * num_bits number of bits in bitmap
50 */ 50 */
51static int r2l_b2t_1d(uint16_t w, unsigned long *pos, unsigned long *map, 51static int r2l_b2t_1d(u16 w, unsigned long *pos, unsigned long *map,
52 size_t num_bits) 52 size_t num_bits)
53{ 53{
54 unsigned long search_count = 0; 54 unsigned long search_count = 0;
@@ -84,7 +84,7 @@ static int r2l_b2t_1d(uint16_t w, unsigned long *pos, unsigned long *map,
84 * num_bits = size of bitmap 84 * num_bits = size of bitmap
85 * stride = bits in one row of container 85 * stride = bits in one row of container
86 */ 86 */
87static int l2r_t2b(uint16_t w, uint16_t h, uint16_t a, int16_t offset, 87static int l2r_t2b(u16 w, u16 h, u16 a, s16 offset,
88 unsigned long *pos, unsigned long slot_bytes, 88 unsigned long *pos, unsigned long slot_bytes,
89 unsigned long *map, size_t num_bits, size_t slot_stride) 89 unsigned long *map, size_t num_bits, size_t slot_stride)
90{ 90{
@@ -179,7 +179,7 @@ static s32 sita_reserve_1d(struct tcm *tcm, u32 num_slots,
179} 179}
180 180
181static s32 sita_reserve_2d(struct tcm *tcm, u16 h, u16 w, u16 align, 181static s32 sita_reserve_2d(struct tcm *tcm, u16 h, u16 w, u16 align,
182 int16_t offset, uint16_t slot_bytes, 182 s16 offset, u16 slot_bytes,
183 struct tcm_area *area) 183 struct tcm_area *area)
184{ 184{
185 unsigned long pos; 185 unsigned long pos;
@@ -208,7 +208,7 @@ static void sita_deinit(struct tcm *tcm)
208static s32 sita_free(struct tcm *tcm, struct tcm_area *area) 208static s32 sita_free(struct tcm *tcm, struct tcm_area *area)
209{ 209{
210 unsigned long pos; 210 unsigned long pos;
211 uint16_t w, h; 211 u16 w, h;
212 212
213 pos = area->p0.x + area->p0.y * tcm->width; 213 pos = area->p0.x + area->p0.y * tcm->width;
214 if (area->is2d) { 214 if (area->is2d) {
diff --git a/drivers/gpu/drm/omapdrm/tcm.h b/drivers/gpu/drm/omapdrm/tcm.h
index d8a369a4f269..8efcda93c50d 100644
--- a/drivers/gpu/drm/omapdrm/tcm.h
+++ b/drivers/gpu/drm/omapdrm/tcm.h
@@ -65,7 +65,7 @@ struct tcm {
65 65
66 /* function table */ 66 /* function table */
67 s32 (*reserve_2d)(struct tcm *tcm, u16 height, u16 width, u16 align, 67 s32 (*reserve_2d)(struct tcm *tcm, u16 height, u16 width, u16 align,
68 int16_t offset, uint16_t slot_bytes, 68 s16 offset, u16 slot_bytes,
69 struct tcm_area *area); 69 struct tcm_area *area);
70 s32 (*reserve_1d)(struct tcm *tcm, u32 slots, struct tcm_area *area); 70 s32 (*reserve_1d)(struct tcm *tcm, u32 slots, struct tcm_area *area);
71 s32 (*free)(struct tcm *tcm, struct tcm_area *area); 71 s32 (*free)(struct tcm *tcm, struct tcm_area *area);
@@ -129,7 +129,7 @@ static inline void tcm_deinit(struct tcm *tcm)
129 * allocation. 129 * allocation.
130 */ 130 */
131static inline s32 tcm_reserve_2d(struct tcm *tcm, u16 width, u16 height, 131static inline s32 tcm_reserve_2d(struct tcm *tcm, u16 width, u16 height,
132 u16 align, int16_t offset, uint16_t slot_bytes, 132 u16 align, s16 offset, u16 slot_bytes,
133 struct tcm_area *area) 133 struct tcm_area *area)
134{ 134{
135 /* perform rudimentary error checking */ 135 /* perform rudimentary error checking */
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-30 12:34:28 -0400