PCI: rockchip: Remove the pointer to L1 substate cap

Per the errata of TRM, the RC can't support L1 substate, so remove the L1
substate cap as well as operation for PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2.

Tested-by: Brian Norris <briannorris@chromium.org>
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

1 files changed, 8 insertions, 9 deletions

diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
index 13e0dd6097a4..17df584742ff 100644
--- a/drivers/pci/host/pcie-rockchip.c
+++ b/drivers/pci/host/pcie-rockchip.c
@@ -148,6 +148,8 @@
 #define   PCIE_RC_CONFIG_LCS_LBMS               BIT(30)
 #define   PCIE_RC_CONFIG_LCS_LAMS               BIT(31)
 #define PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2 (PCIE_RC_CONFIG_BASE + 0x90c)
+#define PCIE_RC_CONFIG_THP_CAP          (PCIE_RC_CONFIG_BASE + 0x274)
+#define   PCIE_RC_CONFIG_THP_CAP_NEXT_MASK      GENMASK(31, 20)
 
 #define PCIE_CORE_AXI_CONF_BASE         0xc00000
 #define PCIE_CORE_OB_REGION_ADDR0       (PCIE_CORE_AXI_CONF_BASE + 0x0)
@@ -569,15 +571,6 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
                 return err;
         }
 
-        /*
-         * We need to read/write PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2 before
-         * enabling ASPM.  Otherwise L1PwrOnSc and L1PwrOnVal isn't
-         * reliable and enabling ASPM doesn't work.  This is a controller
-         * bug we need to work around.
-         */
-        status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2);
-        rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2);
-
         /* Fix the transmitted FTS count desired to exit from L0s. */
         status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL_PLC1);
         status = (status & PCIE_CORE_CTRL_PLC1_FTS_MASK) |
@@ -655,6 +648,12 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
         rockchip_pcie_write(rockchip,
                             PCI_CLASS_BRIDGE_PCI << PCIE_RC_CONFIG_SCC_SHIFT,
                             PCIE_RC_CONFIG_RID_CCR);
+
+        /* Clear THP cap's next cap pointer to remove L1 substate cap */
+        status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_THP_CAP);
+        status &= ~PCIE_RC_CONFIG_THP_CAP_NEXT_MASK;
+        rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_THP_CAP);
+
         rockchip_pcie_write(rockchip, 0x0, PCIE_RC_BAR_CONF);
 
         rockchip_pcie_write(rockchip,