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authorChristian König <christian.koenig@amd.com>2018-09-14 10:06:31 -0400
committerAlex Deucher <alexander.deucher@amd.com>2018-09-19 13:38:48 -0400
commit77a2faa55c1a497f4e7e89eabd11830f0e3cb3dd (patch)
tree6c0eb5f3977246e97ae34339b72b45bd1a65ac21
parent403009bfba45163887398652762ed1fc6645181c (diff)
drm/amdgpu: fix up GDS/GWS/OA shifting
That only worked by pure coincident. Completely remove the shifting and always apply correct PAGE_SHIFT. Signed-off-by: Christian König <christian.koenig@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c12
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h7
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c12
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c14
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_object.c6
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c15
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c9
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c9
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c12
9 files changed, 25 insertions, 71 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index d762d78e5102..8836186eb5ef 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -721,16 +721,16 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p,
721 e->bo_va = amdgpu_vm_bo_find(vm, ttm_to_amdgpu_bo(e->tv.bo)); 721 e->bo_va = amdgpu_vm_bo_find(vm, ttm_to_amdgpu_bo(e->tv.bo));
722 722
723 if (gds) { 723 if (gds) {
724 p->job->gds_base = amdgpu_bo_gpu_offset(gds); 724 p->job->gds_base = amdgpu_bo_gpu_offset(gds) >> PAGE_SHIFT;
725 p->job->gds_size = amdgpu_bo_size(gds); 725 p->job->gds_size = amdgpu_bo_size(gds) >> PAGE_SHIFT;
726 } 726 }
727 if (gws) { 727 if (gws) {
728 p->job->gws_base = amdgpu_bo_gpu_offset(gws); 728 p->job->gws_base = amdgpu_bo_gpu_offset(gws) >> PAGE_SHIFT;
729 p->job->gws_size = amdgpu_bo_size(gws); 729 p->job->gws_size = amdgpu_bo_size(gws) >> PAGE_SHIFT;
730 } 730 }
731 if (oa) { 731 if (oa) {
732 p->job->oa_base = amdgpu_bo_gpu_offset(oa); 732 p->job->oa_base = amdgpu_bo_gpu_offset(oa) >> PAGE_SHIFT;
733 p->job->oa_size = amdgpu_bo_size(oa); 733 p->job->oa_size = amdgpu_bo_size(oa) >> PAGE_SHIFT;
734 } 734 }
735 735
736 if (!r && p->uf_entry.tv.bo) { 736 if (!r && p->uf_entry.tv.bo) {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h
index e73728d90388..ecbcefe49a98 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gds.h
@@ -24,13 +24,6 @@
24#ifndef __AMDGPU_GDS_H__ 24#ifndef __AMDGPU_GDS_H__
25#define __AMDGPU_GDS_H__ 25#define __AMDGPU_GDS_H__
26 26
27/* Because TTM request that alloacted buffer should be PAGE_SIZE aligned,
28 * we should report GDS/GWS/OA size as PAGE_SIZE aligned
29 * */
30#define AMDGPU_GDS_SHIFT 2
31#define AMDGPU_GWS_SHIFT PAGE_SHIFT
32#define AMDGPU_OA_SHIFT PAGE_SHIFT
33
34struct amdgpu_ring; 27struct amdgpu_ring;
35struct amdgpu_bo; 28struct amdgpu_bo;
36 29
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index d30a0838851b..7b3d1ebda9df 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -244,16 +244,10 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
244 return -EINVAL; 244 return -EINVAL;
245 } 245 }
246 flags |= AMDGPU_GEM_CREATE_NO_CPU_ACCESS; 246 flags |= AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
247 if (args->in.domains == AMDGPU_GEM_DOMAIN_GDS) 247 /* GDS allocations must be DW aligned */
248 size = size << AMDGPU_GDS_SHIFT; 248 if (args->in.domains & AMDGPU_GEM_DOMAIN_GDS)
249 else if (args->in.domains == AMDGPU_GEM_DOMAIN_GWS) 249 size = ALIGN(size, 4);
250 size = size << AMDGPU_GWS_SHIFT;
251 else if (args->in.domains == AMDGPU_GEM_DOMAIN_OA)
252 size = size << AMDGPU_OA_SHIFT;
253 else
254 return -EINVAL;
255 } 250 }
256 size = roundup(size, PAGE_SIZE);
257 251
258 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) { 252 if (flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) {
259 r = amdgpu_bo_reserve(vm->root.base.bo, false); 253 r = amdgpu_bo_reserve(vm->root.base.bo, false);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index dc4b2f34e3ea..a64056dadc58 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -528,13 +528,13 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
528 struct drm_amdgpu_info_gds gds_info; 528 struct drm_amdgpu_info_gds gds_info;
529 529
530 memset(&gds_info, 0, sizeof(gds_info)); 530 memset(&gds_info, 0, sizeof(gds_info));
531 gds_info.gds_gfx_partition_size = adev->gds.mem.gfx_partition_size >> AMDGPU_GDS_SHIFT; 531 gds_info.gds_gfx_partition_size = adev->gds.mem.gfx_partition_size;
532 gds_info.compute_partition_size = adev->gds.mem.cs_partition_size >> AMDGPU_GDS_SHIFT; 532 gds_info.compute_partition_size = adev->gds.mem.cs_partition_size;
533 gds_info.gds_total_size = adev->gds.mem.total_size >> AMDGPU_GDS_SHIFT; 533 gds_info.gds_total_size = adev->gds.mem.total_size;
534 gds_info.gws_per_gfx_partition = adev->gds.gws.gfx_partition_size >> AMDGPU_GWS_SHIFT; 534 gds_info.gws_per_gfx_partition = adev->gds.gws.gfx_partition_size;
535 gds_info.gws_per_compute_partition = adev->gds.gws.cs_partition_size >> AMDGPU_GWS_SHIFT; 535 gds_info.gws_per_compute_partition = adev->gds.gws.cs_partition_size;
536 gds_info.oa_per_gfx_partition = adev->gds.oa.gfx_partition_size >> AMDGPU_OA_SHIFT; 536 gds_info.oa_per_gfx_partition = adev->gds.oa.gfx_partition_size;
537 gds_info.oa_per_compute_partition = adev->gds.oa.cs_partition_size >> AMDGPU_OA_SHIFT; 537 gds_info.oa_per_compute_partition = adev->gds.oa.cs_partition_size;
538 return copy_to_user(out, &gds_info, 538 return copy_to_user(out, &gds_info,
539 min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0; 539 min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0;
540 } 540 }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 113738cbb32c..904014dc5915 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -427,7 +427,11 @@ static int amdgpu_bo_do_create(struct amdgpu_device *adev,
427 int r; 427 int r;
428 428
429 page_align = roundup(bp->byte_align, PAGE_SIZE) >> PAGE_SHIFT; 429 page_align = roundup(bp->byte_align, PAGE_SIZE) >> PAGE_SHIFT;
430 size = ALIGN(size, PAGE_SIZE); 430 if (bp->domain & (AMDGPU_GEM_DOMAIN_GDS | AMDGPU_GEM_DOMAIN_GWS |
431 AMDGPU_GEM_DOMAIN_OA))
432 size <<= PAGE_SHIFT;
433 else
434 size = ALIGN(size, PAGE_SIZE);
431 435
432 if (!amdgpu_bo_validate_size(adev, size, bp->domain)) 436 if (!amdgpu_bo_validate_size(adev, size, bp->domain))
433 return -ENOMEM; 437 return -ENOMEM;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index d61910873627..0c4ab72474e4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1845,19 +1845,10 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
1845 (unsigned)(gtt_size / (1024 * 1024))); 1845 (unsigned)(gtt_size / (1024 * 1024)));
1846 1846
1847 /* Initialize various on-chip memory pools */ 1847 /* Initialize various on-chip memory pools */
1848 adev->gds.mem.total_size = adev->gds.mem.total_size << AMDGPU_GDS_SHIFT;
1849 adev->gds.mem.gfx_partition_size = adev->gds.mem.gfx_partition_size << AMDGPU_GDS_SHIFT;
1850 adev->gds.mem.cs_partition_size = adev->gds.mem.cs_partition_size << AMDGPU_GDS_SHIFT;
1851 adev->gds.gws.total_size = adev->gds.gws.total_size << AMDGPU_GWS_SHIFT;
1852 adev->gds.gws.gfx_partition_size = adev->gds.gws.gfx_partition_size << AMDGPU_GWS_SHIFT;
1853 adev->gds.gws.cs_partition_size = adev->gds.gws.cs_partition_size << AMDGPU_GWS_SHIFT;
1854 adev->gds.oa.total_size = adev->gds.oa.total_size << AMDGPU_OA_SHIFT;
1855 adev->gds.oa.gfx_partition_size = adev->gds.oa.gfx_partition_size << AMDGPU_OA_SHIFT;
1856 adev->gds.oa.cs_partition_size = adev->gds.oa.cs_partition_size << AMDGPU_OA_SHIFT;
1857 /* GDS Memory */ 1848 /* GDS Memory */
1858 if (adev->gds.mem.total_size) { 1849 if (adev->gds.mem.total_size) {
1859 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GDS, 1850 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GDS,
1860 adev->gds.mem.total_size >> PAGE_SHIFT); 1851 adev->gds.mem.total_size);
1861 if (r) { 1852 if (r) {
1862 DRM_ERROR("Failed initializing GDS heap.\n"); 1853 DRM_ERROR("Failed initializing GDS heap.\n");
1863 return r; 1854 return r;
@@ -1867,7 +1858,7 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
1867 /* GWS */ 1858 /* GWS */
1868 if (adev->gds.gws.total_size) { 1859 if (adev->gds.gws.total_size) {
1869 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GWS, 1860 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GWS,
1870 adev->gds.gws.total_size >> PAGE_SHIFT); 1861 adev->gds.gws.total_size);
1871 if (r) { 1862 if (r) {
1872 DRM_ERROR("Failed initializing gws heap.\n"); 1863 DRM_ERROR("Failed initializing gws heap.\n");
1873 return r; 1864 return r;
@@ -1877,7 +1868,7 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
1877 /* OA */ 1868 /* OA */
1878 if (adev->gds.oa.total_size) { 1869 if (adev->gds.oa.total_size) {
1879 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_OA, 1870 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_OA,
1880 adev->gds.oa.total_size >> PAGE_SHIFT); 1871 adev->gds.oa.total_size);
1881 if (r) { 1872 if (r) {
1882 DRM_ERROR("Failed initializing oa heap.\n"); 1873 DRM_ERROR("Failed initializing oa heap.\n");
1883 return r; 1874 return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index a15d9c0f233b..c0f9732cbaf7 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -4170,15 +4170,6 @@ static void gfx_v7_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
4170 uint32_t gws_base, uint32_t gws_size, 4170 uint32_t gws_base, uint32_t gws_size,
4171 uint32_t oa_base, uint32_t oa_size) 4171 uint32_t oa_base, uint32_t oa_size)
4172{ 4172{
4173 gds_base = gds_base >> AMDGPU_GDS_SHIFT;
4174 gds_size = gds_size >> AMDGPU_GDS_SHIFT;
4175
4176 gws_base = gws_base >> AMDGPU_GWS_SHIFT;
4177 gws_size = gws_size >> AMDGPU_GWS_SHIFT;
4178
4179 oa_base = oa_base >> AMDGPU_OA_SHIFT;
4180 oa_size = oa_size >> AMDGPU_OA_SHIFT;
4181
4182 /* GDS Base */ 4173 /* GDS Base */
4183 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4174 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4184 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4175 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 11e6ccdfc3d1..96df23c99cfb 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -5396,15 +5396,6 @@ static void gfx_v8_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
5396 uint32_t gws_base, uint32_t gws_size, 5396 uint32_t gws_base, uint32_t gws_size,
5397 uint32_t oa_base, uint32_t oa_size) 5397 uint32_t oa_base, uint32_t oa_size)
5398{ 5398{
5399 gds_base = gds_base >> AMDGPU_GDS_SHIFT;
5400 gds_size = gds_size >> AMDGPU_GDS_SHIFT;
5401
5402 gws_base = gws_base >> AMDGPU_GWS_SHIFT;
5403 gws_size = gws_size >> AMDGPU_GWS_SHIFT;
5404
5405 oa_base = oa_base >> AMDGPU_OA_SHIFT;
5406 oa_size = oa_size >> AMDGPU_OA_SHIFT;
5407
5408 /* GDS Base */ 5399 /* GDS Base */
5409 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 5400 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5410 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 5401 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 1a298f17b7dc..528a8a567633 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -1527,8 +1527,7 @@ static int gfx_v9_0_ngg_en(struct amdgpu_device *adev)
1527 gfx_v9_0_write_data_to_reg(ring, 0, false, 1527 gfx_v9_0_write_data_to_reg(ring, 0, false,
1528 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE), 1528 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE),
1529 (adev->gds.mem.total_size + 1529 (adev->gds.mem.total_size +
1530 adev->gfx.ngg.gds_reserve_size) >> 1530 adev->gfx.ngg.gds_reserve_size));
1531 AMDGPU_GDS_SHIFT);
1532 1531
1533 amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5)); 1532 amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5));
1534 amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC | 1533 amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC |
@@ -3472,15 +3471,6 @@ static void gfx_v9_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
3472{ 3471{
3473 struct amdgpu_device *adev = ring->adev; 3472 struct amdgpu_device *adev = ring->adev;
3474 3473
3475 gds_base = gds_base >> AMDGPU_GDS_SHIFT;
3476 gds_size = gds_size >> AMDGPU_GDS_SHIFT;
3477
3478 gws_base = gws_base >> AMDGPU_GWS_SHIFT;
3479 gws_size = gws_size >> AMDGPU_GWS_SHIFT;
3480
3481 oa_base = oa_base >> AMDGPU_OA_SHIFT;
3482 oa_size = oa_size >> AMDGPU_OA_SHIFT;
3483
3484 /* GDS Base */ 3474 /* GDS Base */
3485 gfx_v9_0_write_data_to_reg(ring, 0, false, 3475 gfx_v9_0_write_data_to_reg(ring, 0, false,
3486 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid, 3476 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid,