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authorYijing Wang <wangyijing@huawei.com>2015-05-21 03:05:04 -0400
committerBjorn Helgaas <bhelgaas@google.com>2015-05-29 16:35:26 -0400
commit777e61ea40e4a94081b3123c76ea3fe977c368a2 (patch)
tree69f6230aa9f5a8213f3bd0445d6c33251c906aec
parentc8fc9339409df88693742d323819ab8415cd2e9d (diff)
PCI: Use dev->has_secondary_link to find downstream PCIe links
Previously we assumed that PCIe Root Ports and Downstream Ports had Links on their secondary side. That is true in most systems, but it is possible to connect a switch with either an Upstream or a Downstream Port leading downstream. Instead of relying on the component type to identify devices that have links leading downstream, use the "dev->has_secondary_link" field. [bhelgaas: changelog] Signed-off-by: Yijing Wang <wangyijing@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
-rw-r--r--drivers/pci/pcie/aer/aerdrv_core.c3
-rw-r--r--drivers/pci/probe.c2
-rw-r--r--drivers/pci/vc.c3
3 files changed, 3 insertions, 5 deletions
diff --git a/drivers/pci/pcie/aer/aerdrv_core.c b/drivers/pci/pcie/aer/aerdrv_core.c
index 5653ea94547f..9803e3d039fe 100644
--- a/drivers/pci/pcie/aer/aerdrv_core.c
+++ b/drivers/pci/pcie/aer/aerdrv_core.c
@@ -425,8 +425,7 @@ static pci_ers_result_t reset_link(struct pci_dev *dev)
425 425
426 if (driver && driver->reset_link) { 426 if (driver && driver->reset_link) {
427 status = driver->reset_link(udev); 427 status = driver->reset_link(udev);
428 } else if (pci_pcie_type(udev) == PCI_EXP_TYPE_DOWNSTREAM || 428 } else if (udev->has_secondary_link) {
429 pci_pcie_type(udev) == PCI_EXP_TYPE_ROOT_PORT) {
430 status = default_reset_link(udev); 429 status = default_reset_link(udev);
431 } else { 430 } else {
432 dev_printk(KERN_DEBUG, &dev->dev, 431 dev_printk(KERN_DEBUG, &dev->dev,
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index 96dcd7b8303b..d405d27a92cd 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -1629,7 +1629,7 @@ static int only_one_child(struct pci_bus *bus)
1629 return 0; 1629 return 0;
1630 if (pci_pcie_type(parent) == PCI_EXP_TYPE_ROOT_PORT) 1630 if (pci_pcie_type(parent) == PCI_EXP_TYPE_ROOT_PORT)
1631 return 1; 1631 return 1;
1632 if (pci_pcie_type(parent) == PCI_EXP_TYPE_DOWNSTREAM && 1632 if (parent->has_secondary_link &&
1633 !pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS)) 1633 !pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS))
1634 return 1; 1634 return 1;
1635 return 0; 1635 return 0;
diff --git a/drivers/pci/vc.c b/drivers/pci/vc.c
index 7e1304d2e389..dfbab61a1b47 100644
--- a/drivers/pci/vc.c
+++ b/drivers/pci/vc.c
@@ -108,8 +108,7 @@ static void pci_vc_enable(struct pci_dev *dev, int pos, int res)
108 struct pci_dev *link = NULL; 108 struct pci_dev *link = NULL;
109 109
110 /* Enable VCs from the downstream device */ 110 /* Enable VCs from the downstream device */
111 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT || 111 if (!dev->has_secondary_link)
112 pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM)
113 return; 112 return;
114 113
115 ctrl_pos = pos + PCI_VC_RES_CTRL + (res * PCI_CAP_VC_PER_VC_SIZEOF); 114 ctrl_pos = pos + PCI_VC_RES_CTRL + (res * PCI_CAP_VC_PER_VC_SIZEOF);