aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorNishanth Menon <nm@ti.com>2014-06-12 07:45:22 -0400
committerTony Lindgren <tony@atomide.com>2014-07-22 02:32:51 -0400
commit76be4a54157ab0059fb29d8d516db46d239812e2 (patch)
tree434db5329e5a6facbc1ca84bfac6c20daf9c7972
parent3db53918e306d3960bf9e12eea8b2fd3f7d0fd62 (diff)
ARM: OMAP2+: DMA: remove requirement of irq for platform-dma driver
we have currently 2 DMA drivers that try to co-exist. drivers/dma/omap-dma.c which registers it's own IRQ and is device tree aware and uses arch/arm/plat-omap/dma.c instance created by arch/arm/mach-omap2/dma.c to maintain channel usage (omap_request_dma). Currently both try to register interrupts and mach-omap2/plat-omap dma.c attempts to use the IRQ number registered by hwmod to register it's own interrupt handler. Now, there is no reasonable way of static allocating DMA irq in GIC SPI when we use crossbar. However, since the dma_chan structure is freed as a result of IRQ not being present due to devm allocation, maintaining information of channel by platform code fails at a later point in time when that region of memory is reused. So, if hwmod does not indicate an IRQ number, then, assume that dma-engine will take care of the interrupt handling. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
-rw-r--r--arch/arm/mach-omap2/dma.c3
-rw-r--r--arch/arm/plat-omap/dma.c5
-rw-r--r--include/linux/omap-dma.h1
3 files changed, 7 insertions, 2 deletions
diff --git a/arch/arm/mach-omap2/dma.c b/arch/arm/mach-omap2/dma.c
index a6d2cf1f8d02..e1a56d87599e 100644
--- a/arch/arm/mach-omap2/dma.c
+++ b/arch/arm/mach-omap2/dma.c
@@ -259,6 +259,9 @@ static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused)
259 if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP)) 259 if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
260 d->dev_caps |= HS_CHANNELS_RESERVED; 260 d->dev_caps |= HS_CHANNELS_RESERVED;
261 261
262 if (platform_get_irq_byname(pdev, "0") < 0)
263 d->dev_caps |= DMA_ENGINE_HANDLE_IRQ;
264
262 /* Check the capabilities register for descriptor loading feature */ 265 /* Check the capabilities register for descriptor loading feature */
263 if (dma_read(CAPS_0, 0) & DMA_HAS_DESCRIPTOR_CAPS) 266 if (dma_read(CAPS_0, 0) & DMA_HAS_DESCRIPTOR_CAPS)
264 dma_common_ch_end = CCDN; 267 dma_common_ch_end = CCDN;
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index b5608b1f9fbd..7aae0e5b188c 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -2100,7 +2100,7 @@ static int omap_system_dma_probe(struct platform_device *pdev)
2100 omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE, 2100 omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE,
2101 DMA_DEFAULT_FIFO_DEPTH, 0); 2101 DMA_DEFAULT_FIFO_DEPTH, 0);
2102 2102
2103 if (dma_omap2plus()) { 2103 if (dma_omap2plus() && !(d->dev_caps & DMA_ENGINE_HANDLE_IRQ)) {
2104 strcpy(irq_name, "0"); 2104 strcpy(irq_name, "0");
2105 dma_irq = platform_get_irq_byname(pdev, irq_name); 2105 dma_irq = platform_get_irq_byname(pdev, irq_name);
2106 if (dma_irq < 0) { 2106 if (dma_irq < 0) {
@@ -2145,7 +2145,8 @@ static int omap_system_dma_remove(struct platform_device *pdev)
2145 char irq_name[4]; 2145 char irq_name[4];
2146 strcpy(irq_name, "0"); 2146 strcpy(irq_name, "0");
2147 dma_irq = platform_get_irq_byname(pdev, irq_name); 2147 dma_irq = platform_get_irq_byname(pdev, irq_name);
2148 remove_irq(dma_irq, &omap24xx_dma_irq); 2148 if (dma_irq >= 0)
2149 remove_irq(dma_irq, &omap24xx_dma_irq);
2149 } else { 2150 } else {
2150 int irq_rel = 0; 2151 int irq_rel = 0;
2151 for ( ; irq_rel < dma_chan_count; irq_rel++) { 2152 for ( ; irq_rel < dma_chan_count; irq_rel++) {
diff --git a/include/linux/omap-dma.h b/include/linux/omap-dma.h
index 88e6ea4a5d36..6f06f8bc612c 100644
--- a/include/linux/omap-dma.h
+++ b/include/linux/omap-dma.h
@@ -130,6 +130,7 @@
130#define IS_WORD_16 BIT(0xd) 130#define IS_WORD_16 BIT(0xd)
131#define ENABLE_16XX_MODE BIT(0xe) 131#define ENABLE_16XX_MODE BIT(0xe)
132#define HS_CHANNELS_RESERVED BIT(0xf) 132#define HS_CHANNELS_RESERVED BIT(0xf)
133#define DMA_ENGINE_HANDLE_IRQ BIT(0x10)
133 134
134/* Defines for DMA Capabilities */ 135/* Defines for DMA Capabilities */
135#define DMA_HAS_TRANSPARENT_CAPS (0x1 << 18) 136#define DMA_HAS_TRANSPARENT_CAPS (0x1 << 18)