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authorLinus Torvalds <torvalds@linux-foundation.org>2018-07-28 15:32:28 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2018-07-28 15:32:28 -0400
commit7648c44680de90a0b656a55813fed5f6621512c5 (patch)
tree1a85cd823efc5d11bf4714949125f89ef4549991
parentdd63bf22fccd68913e3088c5ed5de3bf406a7546 (diff)
parentd5ea019f8a381f88545bb26993b62ec24a2796b7 (diff)
Merge tag 'mips_fixes_4.18_5' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux
Pull MIPS fix from Paul Burton: "Here's one more MIPS fix, reverting an errata workaround that was merged for v4.18-rc2 but has since been found to cause system hangs on some BCM4718A1-based systems by the OpenWRT project" * tag 'mips_fixes_4.18_5' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: Revert "MIPS: BCM47XX: Enable 74K Core ExternalSync for PCIe erratum"
-rw-r--r--arch/mips/bcm47xx/setup.c6
-rw-r--r--arch/mips/include/asm/mipsregs.h3
2 files changed, 0 insertions, 9 deletions
diff --git a/arch/mips/bcm47xx/setup.c b/arch/mips/bcm47xx/setup.c
index 8c9cbf13d32a..6054d49e608e 100644
--- a/arch/mips/bcm47xx/setup.c
+++ b/arch/mips/bcm47xx/setup.c
@@ -212,12 +212,6 @@ static int __init bcm47xx_cpu_fixes(void)
212 */ 212 */
213 if (bcm47xx_bus.bcma.bus.chipinfo.id == BCMA_CHIP_ID_BCM4706) 213 if (bcm47xx_bus.bcma.bus.chipinfo.id == BCMA_CHIP_ID_BCM4706)
214 cpu_wait = NULL; 214 cpu_wait = NULL;
215
216 /*
217 * BCM47XX Erratum "R10: PCIe Transactions Periodically Fail"
218 * Enable ExternalSync for sync instruction to take effect
219 */
220 set_c0_config7(MIPS_CONF7_ES);
221 break; 215 break;
222#endif 216#endif
223 } 217 }
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 0bc270806ec5..ae461d91cd1f 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -681,8 +681,6 @@
681#define MIPS_CONF7_WII (_ULCAST_(1) << 31) 681#define MIPS_CONF7_WII (_ULCAST_(1) << 31)
682 682
683#define MIPS_CONF7_RPS (_ULCAST_(1) << 2) 683#define MIPS_CONF7_RPS (_ULCAST_(1) << 2)
684/* ExternalSync */
685#define MIPS_CONF7_ES (_ULCAST_(1) << 8)
686 684
687#define MIPS_CONF7_IAR (_ULCAST_(1) << 10) 685#define MIPS_CONF7_IAR (_ULCAST_(1) << 10)
688#define MIPS_CONF7_AR (_ULCAST_(1) << 16) 686#define MIPS_CONF7_AR (_ULCAST_(1) << 16)
@@ -2767,7 +2765,6 @@ __BUILD_SET_C0(status)
2767__BUILD_SET_C0(cause) 2765__BUILD_SET_C0(cause)
2768__BUILD_SET_C0(config) 2766__BUILD_SET_C0(config)
2769__BUILD_SET_C0(config5) 2767__BUILD_SET_C0(config5)
2770__BUILD_SET_C0(config7)
2771__BUILD_SET_C0(intcontrol) 2768__BUILD_SET_C0(intcontrol)
2772__BUILD_SET_C0(intctl) 2769__BUILD_SET_C0(intctl)
2773__BUILD_SET_C0(srsmap) 2770__BUILD_SET_C0(srsmap)