drm/radeon: allow unaligned shader loads on CIK

Set alignment mode to unaligned on CIK to align with amdgpu.  This is
needed for unaligned loads to work properly in mesa.  The current setting
requires dword alignment.

Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

2 files changed, 7 insertions, 3 deletions

diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index f6ff41a0eed6..ac0d93936d77 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -35,6 +35,9 @@
 #include "clearstate_ci.h"
 #include "radeon_kfd.h"
 
+#define SH_MEM_CONFIG_GFX_DEFAULT \
+        ALIGNMENT_MODE(SH_MEM_ALIGNMENT_MODE_UNALIGNED)
+
 MODULE_FIRMWARE("radeon/BONAIRE_pfp.bin");
 MODULE_FIRMWARE("radeon/BONAIRE_me.bin");
 MODULE_FIRMWARE("radeon/BONAIRE_ce.bin");
@@ -5587,7 +5590,7 @@ static int cik_pcie_gart_enable(struct radeon_device *rdev)
         for (i = 0; i < 16; i++) {
                 cik_srbm_select(rdev, 0, 0, 0, i);
                 /* CP and shaders */
-                WREG32(SH_MEM_CONFIG, 0);
+                WREG32(SH_MEM_CONFIG, SH_MEM_CONFIG_GFX_DEFAULT);
                 WREG32(SH_MEM_APE1_BASE, 1);
                 WREG32(SH_MEM_APE1_LIMIT, 0);
                 WREG32(SH_MEM_BASES, 0);
@@ -5794,7 +5797,7 @@ void cik_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring,
         radeon_ring_write(ring, 0);
 
         radeon_ring_write(ring, 0); /* SH_MEM_BASES */
-        radeon_ring_write(ring, 0); /* SH_MEM_CONFIG */
+        radeon_ring_write(ring, SH_MEM_CONFIG_GFX_DEFAULT); /* SH_MEM_CONFIG */
         radeon_ring_write(ring, 1); /* SH_MEM_APE1_BASE */
         radeon_ring_write(ring, 0); /* SH_MEM_APE1_LIMIT */
 
diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c
index 956c425e639e..1ecd6930c452 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.c
+++ b/drivers/gpu/drm/radeon/radeon_drv.c
@@ -98,9 +98,10 @@
  *   2.47.0 - Add UVD_NO_OP register support
  *   2.48.0 - TA_CS_BC_BASE_ADDR allowed on SI
  *   2.49.0 - DRM_RADEON_GEM_INFO ioctl returns correct vram_size/visible values
+ *   2.50.0 - Allows unaligned shader loads on CIK. (needed by OpenGL)
  */
 #define KMS_DRIVER_MAJOR        2
-#define KMS_DRIVER_MINOR        49
+#define KMS_DRIVER_MINOR        50
 #define KMS_DRIVER_PATCHLEVEL   0
 int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
 void radeon_driver_unload_kms(struct drm_device *dev);