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authorLinus Walleij <linus.walleij@linaro.org>2017-11-06 15:27:34 -0500
committerLinus Walleij <linus.walleij@linaro.org>2017-11-08 07:53:50 -0500
commit756a024f3983093d26a8756fe4677e34b38bd519 (patch)
tree9cc81644baf76fce679bc107faf20fdd68351656
parent8d6cfb14088e340acd56264f52a60c8f8f735854 (diff)
pinctrl: gemini: Fix GMAC groups
The GMII groups need to be split across GMAC0 and GMAC1 since GMAC0 is always available but GMAC1 masks GPIO2 lines 0-7 so we might want just one interface out. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
-rw-r--r--drivers/pinctrl/pinctrl-gemini.c79
1 files changed, 54 insertions, 25 deletions
diff --git a/drivers/pinctrl/pinctrl-gemini.c b/drivers/pinctrl/pinctrl-gemini.c
index bd6133f06759..ecfc9733db7e 100644
--- a/drivers/pinctrl/pinctrl-gemini.c
+++ b/drivers/pinctrl/pinctrl-gemini.c
@@ -96,6 +96,13 @@ struct gemini_pin_group {
96 * you are stuck with it. 96 * you are stuck with it.
97 */ 97 */
98#define GLOBAL_MISC_CTRL 0x30 98#define GLOBAL_MISC_CTRL 0x30
99#define GEMINI_GMAC_IOSEL_MASK GENMASK(28, 27)
100/* Not really used */
101#define GEMINI_GMAC_IOSEL_GMAC0_GMII BIT(28)
102/* Activated with GMAC1 */
103#define GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII BIT(27)
104/* This will be the default */
105#define GEMINI_GMAC_IOSEL_GMAC0_RGMII_GMAC1_GPIO2 0
99#define TVC_CLK_PAD_ENABLE BIT(20) 106#define TVC_CLK_PAD_ENABLE BIT(20)
100#define PCI_CLK_PAD_ENABLE BIT(17) 107#define PCI_CLK_PAD_ENABLE BIT(17)
101#define LPC_CLK_PAD_ENABLE BIT(16) 108#define LPC_CLK_PAD_ENABLE BIT(16)
@@ -109,8 +116,8 @@ struct gemini_pin_group {
109#define NAND_PADS_DISABLE BIT(2) 116#define NAND_PADS_DISABLE BIT(2)
110#define PFLASH_PADS_DISABLE BIT(1) 117#define PFLASH_PADS_DISABLE BIT(1)
111#define SFLASH_PADS_DISABLE BIT(0) 118#define SFLASH_PADS_DISABLE BIT(0)
112#define PADS_MASK (GENMASK(9, 0) | BIT(16) | BIT(17) | BIT(20)) 119#define PADS_MASK (GENMASK(9, 0) | BIT(16) | BIT(17) | BIT(20) | BIT(27))
113#define PADS_MAXBIT 20 120#define PADS_MAXBIT 27
114 121
115/* Ordered by bit index */ 122/* Ordered by bit index */
116static const char * const gemini_padgroups[] = { 123static const char * const gemini_padgroups[] = {
@@ -516,9 +523,12 @@ static const unsigned int usb_3512_pins[] = {
516}; 523};
517 524
518/* GMII, ethernet pins */ 525/* GMII, ethernet pins */
519static const unsigned int gmii_3512_pins[] = { 526static const unsigned int gmii_gmac0_3512_pins[] = {
520 311, 240, 258, 276, 294, 312, 241, 259, 277, 295, 313, 242, 260, 278, 296, 527 240, 241, 242, 258, 259, 260, 276, 277, 278, 294, 295, 311, 312, 313
521 315, 297, 279, 261, 243, 316, 298, 280, 262, 244, 317, 299, 281 528};
529
530static const unsigned int gmii_gmac1_3512_pins[] = {
531 243, 244, 261, 262, 279, 280, 281, 296, 297, 298, 299, 315, 316, 317
522}; 532};
523 533
524static const unsigned int pci_3512_pins[] = { 534static const unsigned int pci_3512_pins[] = {
@@ -668,10 +678,10 @@ static const unsigned int gpio1c_3512_pins[] = {
668/* The GPIO1D (28-31) pins overlap with LCD and TVC */ 678/* The GPIO1D (28-31) pins overlap with LCD and TVC */
669static const unsigned int gpio1d_3512_pins[] = { 246, 319, 301, 283 }; 679static const unsigned int gpio1d_3512_pins[] = { 246, 319, 301, 283 };
670 680
671/* The GPIO2A (0-3) pins overlap with GMII and extended parallel flash */ 681/* The GPIO2A (0-3) pins overlap with GMII GMAC1 and extended parallel flash */
672static const unsigned int gpio2a_3512_pins[] = { 315, 297, 279, 261 }; 682static const unsigned int gpio2a_3512_pins[] = { 315, 297, 279, 261 };
673 683
674/* The GPIO2B (4-7) pins overlap with GMII, extended parallel flash and LCD */ 684/* The GPIO2B (4-7) pins overlap with GMII GMAC1, extended parallel flash and LCD */
675static const unsigned int gpio2b_3512_pins[] = { 262, 244, 317, 299 }; 685static const unsigned int gpio2b_3512_pins[] = { 262, 244, 317, 299 };
676 686
677/* The GPIO2C (8-31) pins overlap with PCI */ 687/* The GPIO2C (8-31) pins overlap with PCI */
@@ -738,9 +748,16 @@ static const struct gemini_pin_group gemini_3512_pin_groups[] = {
738 .num_pins = ARRAY_SIZE(usb_3512_pins), 748 .num_pins = ARRAY_SIZE(usb_3512_pins),
739 }, 749 },
740 { 750 {
741 .name = "gmiigrp", 751 .name = "gmii_gmac0_grp",
742 .pins = gmii_3512_pins, 752 .pins = gmii_gmac0_3512_pins,
743 .num_pins = ARRAY_SIZE(gmii_3512_pins), 753 .num_pins = ARRAY_SIZE(gmii_gmac0_3512_pins),
754 },
755 {
756 .name = "gmii_gmac1_grp",
757 .pins = gmii_gmac1_3512_pins,
758 .num_pins = ARRAY_SIZE(gmii_gmac1_3512_pins),
759 /* Bring out RGMII on the GMAC1 pins */
760 .value = GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII,
744 }, 761 },
745 { 762 {
746 .name = "pcigrp", 763 .name = "pcigrp",
@@ -954,14 +971,15 @@ static const struct gemini_pin_group gemini_3512_pin_groups[] = {
954 .name = "gpio2agrp", 971 .name = "gpio2agrp",
955 .pins = gpio2a_3512_pins, 972 .pins = gpio2a_3512_pins,
956 .num_pins = ARRAY_SIZE(gpio2a_3512_pins), 973 .num_pins = ARRAY_SIZE(gpio2a_3512_pins),
957 /* Conflict with GMII and extended parallel flash */ 974 .mask = GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII,
975 /* Conflict with GMII GMAC1 and extended parallel flash */
958 }, 976 },
959 { 977 {
960 .name = "gpio2bgrp", 978 .name = "gpio2bgrp",
961 .pins = gpio2b_3512_pins, 979 .pins = gpio2b_3512_pins,
962 .num_pins = ARRAY_SIZE(gpio2b_3512_pins), 980 .num_pins = ARRAY_SIZE(gpio2b_3512_pins),
963 /* Conflict with GMII, extended parallel flash and LCD */ 981 /* Conflict with GMII GMAC1, extended parallel flash and LCD */
964 .mask = LCD_PADS_ENABLE, 982 .mask = LCD_PADS_ENABLE | GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII,
965 }, 983 },
966 { 984 {
967 .name = "gpio2cgrp", 985 .name = "gpio2cgrp",
@@ -1441,9 +1459,12 @@ static const unsigned int usb_3516_pins[] = {
1441}; 1459};
1442 1460
1443/* GMII, ethernet pins */ 1461/* GMII, ethernet pins */
1444static const unsigned int gmii_3516_pins[] = { 1462static const unsigned int gmii_gmac0_3516_pins[] = {
1445 306, 307, 308, 309, 310, 325, 326, 327, 328, 329, 330, 345, 346, 347, 1463 306, 307, 325, 326, 327, 328, 345, 346, 347, 348, 367, 368, 386, 387
1446 348, 349, 350, 351, 367, 368, 369, 370, 371, 386, 387, 389, 390, 391 1464};
1465
1466static const unsigned int gmii_gmac1_3516_pins[] = {
1467 308, 309, 310, 329, 330, 349, 350, 351, 369, 370, 371, 389, 390, 391
1447}; 1468};
1448 1469
1449static const unsigned int pci_3516_pins[] = { 1470static const unsigned int pci_3516_pins[] = {
@@ -1585,10 +1606,10 @@ static const unsigned int gpio1c_3516_pins[] = {
1585/* The GPIO1D (28-31) pins overlap with TVC */ 1606/* The GPIO1D (28-31) pins overlap with TVC */
1586static const unsigned int gpio1d_3516_pins[] = { 353, 311, 394, 374 }; 1607static const unsigned int gpio1d_3516_pins[] = { 353, 311, 394, 374 };
1587 1608
1588/* The GPIO2A (0-3) pins overlap with GMII and extended parallel flash */ 1609/* The GPIO2A (0-3) pins overlap with GMII GMAC1 and extended parallel flash */
1589static const unsigned int gpio2a_3516_pins[] = { 308, 369, 389, 329 }; 1610static const unsigned int gpio2a_3516_pins[] = { 308, 369, 389, 329 };
1590 1611
1591/* The GPIO2B (4-7) pins overlap with GMII, extended parallel flash and LCD */ 1612/* The GPIO2B (4-7) pins overlap with GMII GMAC1, extended parallel flash and LCD */
1592static const unsigned int gpio2b_3516_pins[] = { 391, 351, 310, 371 }; 1613static const unsigned int gpio2b_3516_pins[] = { 391, 351, 310, 371 };
1593 1614
1594/* The GPIO2C (8-31) pins overlap with PCI */ 1615/* The GPIO2C (8-31) pins overlap with PCI */
@@ -1660,9 +1681,16 @@ static const struct gemini_pin_group gemini_3516_pin_groups[] = {
1660 .num_pins = ARRAY_SIZE(usb_3516_pins), 1681 .num_pins = ARRAY_SIZE(usb_3516_pins),
1661 }, 1682 },
1662 { 1683 {
1663 .name = "gmiigrp", 1684 .name = "gmii_gmac0_grp",
1664 .pins = gmii_3516_pins, 1685 .pins = gmii_gmac0_3516_pins,
1665 .num_pins = ARRAY_SIZE(gmii_3516_pins), 1686 .num_pins = ARRAY_SIZE(gmii_gmac0_3516_pins),
1687 },
1688 {
1689 .name = "gmii_gmac1_grp",
1690 .pins = gmii_gmac1_3516_pins,
1691 .num_pins = ARRAY_SIZE(gmii_gmac1_3516_pins),
1692 /* Bring out RGMII on the GMAC1 pins */
1693 .value = GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII,
1666 }, 1694 },
1667 { 1695 {
1668 .name = "pcigrp", 1696 .name = "pcigrp",
@@ -1861,14 +1889,15 @@ static const struct gemini_pin_group gemini_3516_pin_groups[] = {
1861 .name = "gpio2agrp", 1889 .name = "gpio2agrp",
1862 .pins = gpio2a_3516_pins, 1890 .pins = gpio2a_3516_pins,
1863 .num_pins = ARRAY_SIZE(gpio2a_3516_pins), 1891 .num_pins = ARRAY_SIZE(gpio2a_3516_pins),
1864 /* Conflict with GMII and extended parallel flash */ 1892 .mask = GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII,
1893 /* Conflict with GMII GMAC1 and extended parallel flash */
1865 }, 1894 },
1866 { 1895 {
1867 .name = "gpio2bgrp", 1896 .name = "gpio2bgrp",
1868 .pins = gpio2b_3516_pins, 1897 .pins = gpio2b_3516_pins,
1869 .num_pins = ARRAY_SIZE(gpio2b_3516_pins), 1898 .num_pins = ARRAY_SIZE(gpio2b_3516_pins),
1870 /* Conflict with GMII, extended parallel flash and LCD */ 1899 /* Conflict with GMII GMAC1, extended parallel flash and LCD */
1871 .mask = LCD_PADS_ENABLE, 1900 .mask = LCD_PADS_ENABLE | GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII,
1872 }, 1901 },
1873 { 1902 {
1874 .name = "gpio2cgrp", 1903 .name = "gpio2cgrp",
@@ -1971,7 +2000,7 @@ static const char * const icegrps[] = { "icegrp" };
1971static const char * const idegrps[] = { "idegrp" }; 2000static const char * const idegrps[] = { "idegrp" };
1972static const char * const satagrps[] = { "satagrp" }; 2001static const char * const satagrps[] = { "satagrp" };
1973static const char * const usbgrps[] = { "usbgrp" }; 2002static const char * const usbgrps[] = { "usbgrp" };
1974static const char * const gmiigrps[] = { "gmiigrp" }; 2003static const char * const gmiigrps[] = { "gmii_gmac0_grp", "gmii_gmac1_grp" };
1975static const char * const pcigrps[] = { "pcigrp" }; 2004static const char * const pcigrps[] = { "pcigrp" };
1976static const char * const lpcgrps[] = { "lpcgrp" }; 2005static const char * const lpcgrps[] = { "lpcgrp" };
1977static const char * const lcdgrps[] = { "lcdgrp" }; 2006static const char * const lcdgrps[] = { "lcdgrp" };