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authorOlof Johansson <olof@lixom.net>2015-08-05 04:47:18 -0400
committerOlof Johansson <olof@lixom.net>2015-08-05 04:47:18 -0400
commit754d5c784fde1d8649e237b46e9ceb234fb17de0 (patch)
treef76bf67630d057d9abcdfcc2164d9594975d173d
parent70d334ca71b0e35ef21493d86799cec83f452d94 (diff)
parent9943230c8860178a6f6409f0ba19167c0a46a71b (diff)
Merge tag 'qcom-arm64-for-4.3' of git://codeaurora.org/quic/kernel/agross-msm into next/arm64
Qualcomm ARM64 Updates for v4.3 * Add BLSP and required pinctrl info for MSM8916 * Add SDHC aliases and nodes for MSM8916 * Add USB nodes for MSM8916 * Add APQ8016 SBC specific USB configuration * Add APQ8016 LED configuration * tag 'qcom-arm64-for-4.3' of git://codeaurora.org/quic/kernel/agross-msm: arm64: dts: qcom: Add apq8016-sbc board LED's related device nodes arm64: dts: qcom: Fix apq8016-sbc board USB related pin definitions arm64: dts: qcom: apq8016-sbc: Don't hog client driver pins arm64: dts: qcom: Add msm8916 USB configuration nodes arm64: dts: qcom: Add msm8916 sdhci configuration nodes arm64: dts: qcom: Add msm8916 BLSP device nodes arm64: dts: qcom: Extend msm8916 pinctrl device coverage Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat
-rw-r--r--arch/arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi34
-rw-r--r--arch/arm64/boot/dts/qcom/apq8016-sbc-soc-pins.dtsi14
-rw-r--r--arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi51
-rw-r--r--arch/arm64/boot/dts/qcom/msm8916-pins.dtsi430
-rw-r--r--arch/arm64/boot/dts/qcom/msm8916.dtsi227
5 files changed, 708 insertions, 48 deletions
diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi b/arch/arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi
index 535532b9287f..e03c11d9d834 100644
--- a/arch/arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi
+++ b/arch/arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi
@@ -2,27 +2,37 @@
2 2
3&pm8916_gpios { 3&pm8916_gpios {
4 4
5 pinctrl-names = "default"; 5 usb_hub_reset_pm: usb_hub_reset_pm {
6 pinctrl-0 = <&pm8916_gpios_default>; 6 pinconf {
7 7 pins = "gpio3";
8 pm8916_gpios_default: default {
9 usb_hub_reset_pm {
10 pins = "gpio1";
11 function = PMIC_GPIO_FUNC_NORMAL; 8 function = PMIC_GPIO_FUNC_NORMAL;
12 output-low; 9 output-low;
13 }; 10 };
14 usb_sw_sel_pm { 11 };
15 pins = "gpio2"; 12
13 usb_sw_sel_pm: usb_sw_sel_pm {
14 pinconf {
15 pins = "gpio4";
16 function = PMIC_GPIO_FUNC_NORMAL; 16 function = PMIC_GPIO_FUNC_NORMAL;
17 power-source = <PM8916_GPIO_VPH>;
17 input-disable; 18 input-disable;
18 }; 19 };
19 usr_led_3_ctrl { 20 };
20 pins = "gpio3"; 21
22 pm8916_gpios_leds: pm8916_gpios_leds {
23 pinconf {
24 pins = "gpio1", "gpio2";
21 function = PMIC_GPIO_FUNC_NORMAL; 25 function = PMIC_GPIO_FUNC_NORMAL;
22 output-low; 26 output-low;
23 }; 27 };
24 usr_led_4_ctrl { 28 };
25 pins = "gpio4"; 29};
30
31&pm8916_mpps {
32
33 pm8916_mpps_leds: pm8916_mpps_leds {
34 pinconf {
35 pins = "mpp2", "mpp3";
26 function = PMIC_GPIO_FUNC_NORMAL; 36 function = PMIC_GPIO_FUNC_NORMAL;
27 output-low; 37 output-low;
28 }; 38 };
diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc-soc-pins.dtsi b/arch/arm64/boot/dts/qcom/apq8016-sbc-soc-pins.dtsi
index 5f7023f90df7..cbeee0bcdf52 100644
--- a/arch/arm64/boot/dts/qcom/apq8016-sbc-soc-pins.dtsi
+++ b/arch/arm64/boot/dts/qcom/apq8016-sbc-soc-pins.dtsi
@@ -3,17 +3,9 @@
3 3
4&msmgpio { 4&msmgpio {
5 5
6 pinctrl-names = "default"; 6 msmgpio_leds: msmgpio_leds {
7 pinctrl-0 = <&soc_gpios_default>; 7 pinconf {
8 8 pins = "gpio21", "gpio120";
9 soc_gpios_default: default {
10 usr_led_1_ctrl_default: usr_led_1_ctrl_default {
11 pins = "gpio21";
12 function = "gpio";
13 output-low;
14 };
15 usr_led_2_ctrl_default: usr_led_2_ctrl_default {
16 pins = "gpio120";
17 function = "gpio"; 9 function = "gpio";
18 output-low; 10 output-low;
19 }; 11 };
diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
index 98abece6b233..66804ffbc6d2 100644
--- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
+++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
@@ -32,5 +32,56 @@
32 pinctrl-0 = <&blsp1_uart2_default>; 32 pinctrl-0 = <&blsp1_uart2_default>;
33 pinctrl-1 = <&blsp1_uart2_sleep>; 33 pinctrl-1 = <&blsp1_uart2_sleep>;
34 }; 34 };
35
36 leds {
37 pinctrl-names = "default";
38 pinctrl-0 = <&msmgpio_leds>,
39 <&pm8916_gpios_leds>,
40 <&pm8916_mpps_leds>;
41
42 compatible = "gpio-leds";
43
44 led@1 {
45 label = "apq8016-sbc:green:user1";
46 gpios = <&msmgpio 21 GPIO_ACTIVE_HIGH>;
47 linux,default-trigger = "heartbeat";
48 default-state = "off";
49 };
50
51 led@2 {
52 label = "apq8016-sbc:green:user2";
53 gpios = <&msmgpio 120 GPIO_ACTIVE_HIGH>;
54 linux,default-trigger = "mmc0";
55 default-state = "off";
56 };
57
58 led@3 {
59 label = "apq8016-sbc:green:user3";
60 gpios = <&pm8916_gpios 1 GPIO_ACTIVE_HIGH>;
61 linux,default-trigger = "mmc1";
62 default-state = "off";
63 };
64
65 led@4 {
66 label = "apq8016-sbc:green:user4";
67 gpios = <&pm8916_gpios 2 GPIO_ACTIVE_HIGH>;
68 linux,default-trigger = "none";
69 default-state = "off";
70 };
71
72 led@5 {
73 label = "apq8016-sbc:yellow:wlan";
74 gpios = <&pm8916_mpps 2 GPIO_ACTIVE_HIGH>;
75 linux,default-trigger = "wlan";
76 default-state = "off";
77 };
78
79 led@6 {
80 label = "apq8016-sbc:blue:bt";
81 gpios = <&pm8916_mpps 3 GPIO_ACTIVE_HIGH>;
82 linux,default-trigger = "bt";
83 default-state = "off";
84 };
85 };
35 }; 86 };
36}; 87};
diff --git a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi
new file mode 100644
index 000000000000..568956859088
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi
@@ -0,0 +1,430 @@
1/*
2 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14&msmgpio {
15
16 blsp1_uart2_default: blsp1_uart2_default {
17 pinmux {
18 function = "blsp_uart2";
19 pins = "gpio4", "gpio5";
20 };
21 pinconf {
22 pins = "gpio4", "gpio5";
23 drive-strength = <16>;
24 bias-disable;
25 };
26 };
27
28 blsp1_uart2_sleep: blsp1_uart2_sleep {
29 pinmux {
30 function = "blsp_uart2";
31 pins = "gpio4", "gpio5";
32 };
33 pinconf {
34 pins = "gpio4", "gpio5";
35 drive-strength = <2>;
36 bias-pull-down;
37 };
38 };
39
40 spi1_default: spi1_default {
41 pinmux {
42 function = "blsp_spi1";
43 pins = "gpio0", "gpio1", "gpio3";
44 };
45 pinmux_cs {
46 function = "gpio";
47 pins = "gpio2";
48 };
49 pinconf {
50 pins = "gpio0", "gpio1", "gpio3";
51 drive-strength = <12>;
52 bias-disable;
53 };
54 pinconf_cs {
55 pins = "gpio2";
56 drive-strength = <2>;
57 bias-disable;
58 output-high;
59 };
60 };
61
62 spi1_sleep: spi1_sleep {
63 pinmux {
64 function = "gpio";
65 pins = "gpio0", "gpio1", "gpio2", "gpio3";
66 };
67 pinconf {
68 pins = "gpio0", "gpio1", "gpio2", "gpio3";
69 drive-strength = <2>;
70 bias-pull-down;
71 };
72 };
73
74 spi2_default: spi2_default {
75 pinmux {
76 function = "blsp_spi2";
77 pins = "gpio4", "gpio5", "gpio7";
78 };
79 pinmux_cs {
80 function = "gpio";
81 pins = "gpio6";
82 };
83 pinconf {
84 pins = "gpio4", "gpio5", "gpio6", "gpio7";
85 drive-strength = <12>;
86 bias-disable;
87 };
88 pinconf_cs {
89 pins = "gpio6";
90 drive-strength = <2>;
91 bias-disable;
92 output-high;
93 };
94 };
95
96 spi2_sleep: spi2_sleep {
97 pinmux {
98 function = "gpio";
99 pins = "gpio4", "gpio5", "gpio6", "gpio7";
100 };
101 pinconf {
102 pins = "gpio4", "gpio5", "gpio6", "gpio7";
103 drive-strength = <2>;
104 bias-pull-down;
105 };
106 };
107
108 spi3_default: spi3_default {
109 pinmux {
110 function = "blsp_spi3";
111 pins = "gpio8", "gpio9", "gpio11";
112 };
113 pinmux_cs {
114 function = "gpio";
115 pins = "gpio10";
116 };
117 pinconf {
118 pins = "gpio8", "gpio9", "gpio10", "gpio11";
119 drive-strength = <12>;
120 bias-disable;
121 };
122 pinconf_cs {
123 pins = "gpio10";
124 drive-strength = <2>;
125 bias-disable;
126 output-high;
127 };
128 };
129
130 spi3_sleep: spi3_sleep {
131 pinmux {
132 function = "gpio";
133 pins = "gpio8", "gpio9", "gpio10", "gpio11";
134 };
135 pinconf {
136 pins = "gpio8", "gpio9", "gpio10", "gpio11";
137 drive-strength = <2>;
138 bias-pull-down;
139 };
140 };
141
142 spi4_default: spi4_default {
143 pinmux {
144 function = "blsp_spi4";
145 pins = "gpio12", "gpio13", "gpio15";
146 };
147 pinmux_cs {
148 function = "gpio";
149 pins = "gpio14";
150 };
151 pinconf {
152 pins = "gpio12", "gpio13", "gpio14", "gpio15";
153 drive-strength = <12>;
154 bias-disable;
155 };
156 pinconf_cs {
157 pins = "gpio14";
158 drive-strength = <2>;
159 bias-disable;
160 output-high;
161 };
162 };
163
164 spi4_sleep: spi4_sleep {
165 pinmux {
166 function = "gpio";
167 pins = "gpio12", "gpio13", "gpio14", "gpio15";
168 };
169 pinconf {
170 pins = "gpio12", "gpio13", "gpio14", "gpio15";
171 drive-strength = <2>;
172 bias-pull-down;
173 };
174 };
175
176 spi5_default: spi5_default {
177 pinmux {
178 function = "blsp_spi5";
179 pins = "gpio16", "gpio17", "gpio19";
180 };
181 pinmux_cs {
182 function = "gpio";
183 pins = "gpio18";
184 };
185 pinconf {
186 pins = "gpio16", "gpio17", "gpio18", "gpio19";
187 drive-strength = <12>;
188 bias-disable;
189 };
190 pinconf_cs {
191 pins = "gpio18";
192 drive-strength = <2>;
193 bias-disable;
194 output-high;
195 };
196 };
197
198 spi5_sleep: spi5_sleep {
199 pinmux {
200 function = "gpio";
201 pins = "gpio16", "gpio17", "gpio18", "gpio19";
202 };
203 pinconf {
204 pins = "gpio16", "gpio17", "gpio18", "gpio19";
205 drive-strength = <2>;
206 bias-pull-down;
207 };
208 };
209
210 spi6_default: spi6_default {
211 pinmux {
212 function = "blsp_spi6";
213 pins = "gpio20", "gpio21", "gpio23";
214 };
215 pinmux_cs {
216 function = "gpio";
217 pins = "gpio22";
218 };
219 pinconf {
220 pins = "gpio20", "gpio21", "gpio22", "gpio23";
221 drive-strength = <12>;
222 bias-disable;
223 };
224 pinconf_cs {
225 pins = "gpio22";
226 drive-strength = <2>;
227 bias-disable;
228 output-high;
229 };
230 };
231
232 spi6_sleep: spi6_sleep {
233 pinmux {
234 function = "gpio";
235 pins = "gpio20", "gpio21", "gpio22", "gpio23";
236 };
237 pinconf {
238 pins = "gpio20", "gpio21", "gpio22", "gpio23";
239 drive-strength = <2>;
240 bias-pull-down;
241 };
242 };
243
244 i2c4_default: i2c4_default {
245 pinmux {
246 function = "blsp_i2c4";
247 pins = "gpio14", "gpio15";
248 };
249 pinconf {
250 pins = "gpio14", "gpio15";
251 drive-strength = <2>;
252 bias-disable = <0>;
253 };
254 };
255
256 i2c4_sleep: i2c4_sleep {
257 pinmux {
258 function = "blsp_i2c4";
259 pins = "gpio14", "gpio15";
260 };
261 pinconf {
262 pins = "gpio14", "gpio15";
263 drive-strength = <2>;
264 bias-disable = <0>;
265 };
266 };
267
268 sdhc2_cd_pin {
269 sdc2_cd_on: cd_on {
270 pinmux {
271 function = "gpio";
272 pins = "gpio38";
273 };
274 pinconf {
275 pins = "gpio38";
276 drive-strength = <2>;
277 bias-pull-up;
278 };
279 };
280 sdc2_cd_off: cd_off {
281 pinmux {
282 function = "gpio";
283 pins = "gpio38";
284 };
285 pinconf {
286 pins = "gpio38";
287 drive-strength = <2>;
288 bias-disable;
289 };
290 };
291 };
292
293 pmx_sdc1_clk {
294 sdc1_clk_on: clk_on {
295 pinmux {
296 pins = "sdc1_clk";
297 };
298 pinconf {
299 pins = "sdc1_clk";
300 bias-disable;
301 drive-strength = <16>;
302 };
303 };
304 sdc1_clk_off: clk_off {
305 pinmux {
306 pins = "sdc1_clk";
307 };
308 pinconf {
309 pins = "sdc1_clk";
310 bias-disable;
311 drive-strength = <2>;
312 };
313 };
314 };
315
316 pmx_sdc1_cmd {
317 sdc1_cmd_on: cmd_on {
318 pinmux {
319 pins = "sdc1_cmd";
320 };
321 pinconf {
322 pins = "sdc1_cmd";
323 bias-pull-up;
324 drive-strength = <10>;
325 };
326 };
327 sdc1_cmd_off: cmd_off {
328 pinmux {
329 pins = "sdc1_cmd";
330 };
331 pinconf {
332 pins = "sdc1_cmd";
333 bias-pull-up;
334 drive-strength = <2>;
335 };
336 };
337 };
338
339 pmx_sdc1_data {
340 sdc1_data_on: data_on {
341 pinmux {
342 pins = "sdc1_data";
343 };
344 pinconf {
345 pins = "sdc1_data";
346 bias-pull-up;
347 drive-strength = <10>;
348 };
349 };
350 sdc1_data_off: data_off {
351 pinmux {
352 pins = "sdc1_data";
353 };
354 pinconf {
355 pins = "sdc1_data";
356 bias-pull-up;
357 drive-strength = <2>;
358 };
359 };
360 };
361
362 pmx_sdc2_clk {
363 sdc2_clk_on: clk_on {
364 pinmux {
365 pins = "sdc2_clk";
366 };
367 pinconf {
368 pins = "sdc2_clk";
369 bias-disable;
370 drive-strength = <16>;
371 };
372 };
373 sdc2_clk_off: clk_off {
374 pinmux {
375 pins = "sdc2_clk";
376 };
377 pinconf {
378 pins = "sdc2_clk";
379 bias-disable;
380 drive-strength = <2>;
381 };
382 };
383 };
384
385 pmx_sdc2_cmd {
386 sdc2_cmd_on: cmd_on {
387 pinmux {
388 pins = "sdc2_cmd";
389 };
390 pinconf {
391 pins = "sdc2_cmd";
392 bias-pull-up;
393 drive-strength = <10>;
394 };
395 };
396 sdc2_cmd_off: cmd_off {
397 pinmux {
398 pins = "sdc2_cmd";
399 };
400 pinconf {
401 pins = "sdc2_cmd";
402 bias-pull-up;
403 drive-strength = <2>;
404 };
405 };
406 };
407
408 pmx_sdc2_data {
409 sdc2_data_on: data_on {
410 pinmux {
411 pins = "sdc2_data";
412 };
413 pinconf {
414 pins = "sdc2_data";
415 bias-pull-up;
416 drive-strength = <10>;
417 };
418 };
419 sdc2_data_off: data_off {
420 pinmux {
421 pins = "sdc2_data";
422 };
423 pinconf {
424 pins = "sdc2_data";
425 bias-pull-up;
426 drive-strength = <2>;
427 };
428 };
429 };
430};
diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index 0f49ebd0aa8b..5911de008dd5 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -24,7 +24,10 @@
24 #address-cells = <2>; 24 #address-cells = <2>;
25 #size-cells = <2>; 25 #size-cells = <2>;
26 26
27 aliases { }; 27 aliases {
28 sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
29 sdhc2 = &sdhc_2; /* SDC2 SD card slot */
30 };
28 31
29 chosen { }; 32 chosen { };
30 33
@@ -90,30 +93,6 @@
90 #gpio-cells = <2>; 93 #gpio-cells = <2>;
91 interrupt-controller; 94 interrupt-controller;
92 #interrupt-cells = <2>; 95 #interrupt-cells = <2>;
93
94 blsp1_uart2_default: blsp1_uart2_default {
95 pinmux {
96 function = "blsp_uart2";
97 pins = "gpio4", "gpio5";
98 };
99 pinconf {
100 pins = "gpio4", "gpio5";
101 drive-strength = <16>;
102 bias-disable;
103 };
104 };
105
106 blsp1_uart2_sleep: blsp1_uart2_sleep {
107 pinmux {
108 function = "blsp_uart2";
109 pins = "gpio4", "gpio5";
110 };
111 pinconf {
112 pins = "gpio4", "gpio5";
113 drive-strength = <2>;
114 bias-pull-down;
115 };
116 };
117 }; 96 };
118 97
119 gcc: qcom,gcc@1800000 { 98 gcc: qcom,gcc@1800000 {
@@ -132,6 +111,202 @@
132 status = "disabled"; 111 status = "disabled";
133 }; 112 };
134 113
114 blsp_dma: dma@7884000 {
115 compatible = "qcom,bam-v1.7.0";
116 reg = <0x07884000 0x23000>;
117 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
118 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
119 clock-names = "bam_clk";
120 #dma-cells = <1>;
121 qcom,ee = <0>;
122 status = "disabled";
123 };
124
125 blsp_spi1: spi@78b5000 {
126 compatible = "qcom,spi-qup-v2.2.1";
127 reg = <0x078b5000 0x600>;
128 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
129 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
130 <&gcc GCC_BLSP1_AHB_CLK>;
131 clock-names = "core", "iface";
132 dmas = <&blsp_dma 5>, <&blsp_dma 4>;
133 dma-names = "rx", "tx";
134 pinctrl-names = "default", "sleep";
135 pinctrl-0 = <&spi1_default>;
136 pinctrl-1 = <&spi1_sleep>;
137 #address-cells = <1>;
138 #size-cells = <0>;
139 status = "disabled";
140 };
141
142 blsp_spi2: spi@78b6000 {
143 compatible = "qcom,spi-qup-v2.2.1";
144 reg = <0x078b6000 0x600>;
145 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
146 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
147 <&gcc GCC_BLSP1_AHB_CLK>;
148 clock-names = "core", "iface";
149 dmas = <&blsp_dma 7>, <&blsp_dma 6>;
150 dma-names = "rx", "tx";
151 pinctrl-names = "default", "sleep";
152 pinctrl-0 = <&spi2_default>;
153 pinctrl-1 = <&spi2_sleep>;
154 #address-cells = <1>;
155 #size-cells = <0>;
156 status = "disabled";
157 };
158
159 blsp_spi3: spi@78b7000 {
160 compatible = "qcom,spi-qup-v2.2.1";
161 reg = <0x078b7000 0x600>;
162 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
163 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
164 <&gcc GCC_BLSP1_AHB_CLK>;
165 clock-names = "core", "iface";
166 dmas = <&blsp_dma 9>, <&blsp_dma 8>;
167 dma-names = "rx", "tx";
168 pinctrl-names = "default", "sleep";
169 pinctrl-0 = <&spi3_default>;
170 pinctrl-1 = <&spi3_sleep>;
171 #address-cells = <1>;
172 #size-cells = <0>;
173 status = "disabled";
174 };
175
176 blsp_spi4: spi@78b8000 {
177 compatible = "qcom,spi-qup-v2.2.1";
178 reg = <0x078b8000 0x600>;
179 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
180 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
181 <&gcc GCC_BLSP1_AHB_CLK>;
182 clock-names = "core", "iface";
183 dmas = <&blsp_dma 11>, <&blsp_dma 10>;
184 dma-names = "rx", "tx";
185 pinctrl-names = "default", "sleep";
186 pinctrl-0 = <&spi4_default>;
187 pinctrl-1 = <&spi4_sleep>;
188 #address-cells = <1>;
189 #size-cells = <0>;
190 status = "disabled";
191 };
192
193 blsp_spi5: spi@78b9000 {
194 compatible = "qcom,spi-qup-v2.2.1";
195 reg = <0x078b9000 0x600>;
196 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
197 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
198 <&gcc GCC_BLSP1_AHB_CLK>;
199 clock-names = "core", "iface";
200 dmas = <&blsp_dma 13>, <&blsp_dma 12>;
201 dma-names = "rx", "tx";
202 pinctrl-names = "default", "sleep";
203 pinctrl-0 = <&spi5_default>;
204 pinctrl-1 = <&spi5_sleep>;
205 #address-cells = <1>;
206 #size-cells = <0>;
207 status = "disabled";
208 };
209
210 blsp_spi6: spi@78ba000 {
211 compatible = "qcom,spi-qup-v2.2.1";
212 reg = <0x078ba000 0x600>;
213 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
214 clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>,
215 <&gcc GCC_BLSP1_AHB_CLK>;
216 clock-names = "core", "iface";
217 dmas = <&blsp_dma 15>, <&blsp_dma 14>;
218 dma-names = "rx", "tx";
219 pinctrl-names = "default", "sleep";
220 pinctrl-0 = <&spi6_default>;
221 pinctrl-1 = <&spi6_sleep>;
222 #address-cells = <1>;
223 #size-cells = <0>;
224 status = "disabled";
225 };
226
227 blsp_i2c4: i2c@78b8000 {
228 compatible = "qcom,i2c-qup-v2.2.1";
229 reg = <0x78b8000 0x1000>;
230 interrupts = <GIC_SPI 98 0>;
231 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
232 <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
233 clock-names = "iface", "core";
234 pinctrl-names = "default", "sleep";
235 pinctrl-0 = <&i2c4_default>;
236 pinctrl-1 = <&i2c4_sleep>;
237 #address-cells = <1>;
238 #size-cells = <0>;
239 status = "disabled";
240 };
241
242 sdhc_1: sdhci@07824000 {
243 compatible = "qcom,sdhci-msm-v4";
244 reg = <0x07824900 0x11c>, <0x07824000 0x800>;
245 reg-names = "hc_mem", "core_mem";
246
247 interrupts = <0 123 0>, <0 138 0>;
248 interrupt-names = "hc_irq", "pwr_irq";
249 clocks = <&gcc GCC_SDCC1_APPS_CLK>,
250 <&gcc GCC_SDCC1_AHB_CLK>;
251 clock-names = "core", "iface";
252 bus-width = <8>;
253 non-removable;
254 status = "disabled";
255 };
256
257 sdhc_2: sdhci@07864000 {
258 compatible = "qcom,sdhci-msm-v4";
259 reg = <0x07864900 0x11c>, <0x07864000 0x800>;
260 reg-names = "hc_mem", "core_mem";
261
262 interrupts = <0 125 0>, <0 221 0>;
263 interrupt-names = "hc_irq", "pwr_irq";
264 clocks = <&gcc GCC_SDCC2_APPS_CLK>,
265 <&gcc GCC_SDCC2_AHB_CLK>;
266 clock-names = "core", "iface";
267 bus-width = <4>;
268 status = "disabled";
269 };
270
271 usb_dev: usb@78d9000 {
272 compatible = "qcom,ci-hdrc";
273 reg = <0x78d9000 0x400>;
274 dr_mode = "peripheral";
275 interrupts = <GIC_SPI 134 IRQ_TYPE_NONE>;
276 usb-phy = <&usb_otg>;
277 status = "disabled";
278 };
279
280 usb_host: ehci@78d9000 {
281 compatible = "qcom,ehci-host";
282 reg = <0x78d9000 0x400>;
283 interrupts = <GIC_SPI 134 IRQ_TYPE_NONE>;
284 usb-phy = <&usb_otg>;
285 status = "disabled";
286 };
287
288 usb_otg: phy@78d9000 {
289 compatible = "qcom,usb-otg-snps";
290 reg = <0x78d9000 0x400>;
291 interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_BOTH>,
292 <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>;
293
294 qcom,vdd-levels = <1 5 7>;
295 qcom,phy-init-sequence = <0x44 0x6B 0x24 0x13>;
296 dr_mode = "peripheral";
297 qcom,otg-control = <2>; // PMIC
298
299 clocks = <&gcc GCC_USB_HS_AHB_CLK>,
300 <&gcc GCC_USB_HS_SYSTEM_CLK>,
301 <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
302 clock-names = "iface", "core", "sleep";
303
304 resets = <&gcc GCC_USB2A_PHY_BCR>,
305 <&gcc GCC_USB_HS_BCR>;
306 reset-names = "phy", "link";
307 status = "disabled";
308 };
309
135 intc: interrupt-controller@b000000 { 310 intc: interrupt-controller@b000000 {
136 compatible = "qcom,msm-qgic2"; 311 compatible = "qcom,msm-qgic2";
137 interrupt-controller; 312 interrupt-controller;
@@ -217,3 +392,5 @@
217 }; 392 };
218 }; 393 };
219}; 394};
395
396#include "msm8916-pins.dtsi"
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-15 10:04:46 -0400