diff options
| author | Arvind Yadav <arvind.yadav.cs@gmail.com> | 2017-03-14 05:54:51 -0400 |
|---|---|---|
| committer | Helge Deller <deller@gmx.de> | 2017-03-18 12:24:43 -0400 |
| commit | 74e3f6e63da6c8e8246fba1689e040bc926b4a1a (patch) | |
| tree | cff57cc4ed624b1a1bebb8c7341ab7ba7c5e988d | |
| parent | 186ecf14e58befba434f0774eea89e35f64d3c6a (diff) | |
parisc: perf: Fix potential NULL pointer dereference
Fix potential NULL pointer dereference and clean up
coding style errors (code indent, trailing whitespaces).
Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com>
Signed-off-by: Helge Deller <deller@gmx.de>
| -rw-r--r-- | arch/parisc/kernel/perf.c | 94 |
1 files changed, 49 insertions, 45 deletions
diff --git a/arch/parisc/kernel/perf.c b/arch/parisc/kernel/perf.c index e282a5131d77..6017a5af2e6e 100644 --- a/arch/parisc/kernel/perf.c +++ b/arch/parisc/kernel/perf.c | |||
| @@ -39,7 +39,7 @@ | |||
| 39 | * the PDC INTRIGUE calls. This is done to eliminate bugs introduced | 39 | * the PDC INTRIGUE calls. This is done to eliminate bugs introduced |
| 40 | * in various PDC revisions. The code is much more maintainable | 40 | * in various PDC revisions. The code is much more maintainable |
| 41 | * and reliable this way vs having to debug on every version of PDC | 41 | * and reliable this way vs having to debug on every version of PDC |
| 42 | * on every box. | 42 | * on every box. |
| 43 | */ | 43 | */ |
| 44 | 44 | ||
| 45 | #include <linux/capability.h> | 45 | #include <linux/capability.h> |
| @@ -195,8 +195,8 @@ static int perf_config(uint32_t *image_ptr); | |||
| 195 | static int perf_release(struct inode *inode, struct file *file); | 195 | static int perf_release(struct inode *inode, struct file *file); |
| 196 | static int perf_open(struct inode *inode, struct file *file); | 196 | static int perf_open(struct inode *inode, struct file *file); |
| 197 | static ssize_t perf_read(struct file *file, char __user *buf, size_t cnt, loff_t *ppos); | 197 | static ssize_t perf_read(struct file *file, char __user *buf, size_t cnt, loff_t *ppos); |
| 198 | static ssize_t perf_write(struct file *file, const char __user *buf, size_t count, | 198 | static ssize_t perf_write(struct file *file, const char __user *buf, |
| 199 | loff_t *ppos); | 199 | size_t count, loff_t *ppos); |
| 200 | static long perf_ioctl(struct file *file, unsigned int cmd, unsigned long arg); | 200 | static long perf_ioctl(struct file *file, unsigned int cmd, unsigned long arg); |
| 201 | static void perf_start_counters(void); | 201 | static void perf_start_counters(void); |
| 202 | static int perf_stop_counters(uint32_t *raddr); | 202 | static int perf_stop_counters(uint32_t *raddr); |
| @@ -222,7 +222,7 @@ extern void perf_intrigue_disable_perf_counters (void); | |||
| 222 | /* | 222 | /* |
| 223 | * configure: | 223 | * configure: |
| 224 | * | 224 | * |
| 225 | * Configure the cpu with a given data image. First turn off the counters, | 225 | * Configure the cpu with a given data image. First turn off the counters, |
| 226 | * then download the image, then turn the counters back on. | 226 | * then download the image, then turn the counters back on. |
| 227 | */ | 227 | */ |
| 228 | static int perf_config(uint32_t *image_ptr) | 228 | static int perf_config(uint32_t *image_ptr) |
| @@ -234,7 +234,7 @@ static int perf_config(uint32_t *image_ptr) | |||
| 234 | error = perf_stop_counters(raddr); | 234 | error = perf_stop_counters(raddr); |
| 235 | if (error != 0) { | 235 | if (error != 0) { |
| 236 | printk("perf_config: perf_stop_counters = %ld\n", error); | 236 | printk("perf_config: perf_stop_counters = %ld\n", error); |
| 237 | return -EINVAL; | 237 | return -EINVAL; |
| 238 | } | 238 | } |
| 239 | 239 | ||
| 240 | printk("Preparing to write image\n"); | 240 | printk("Preparing to write image\n"); |
| @@ -242,7 +242,7 @@ printk("Preparing to write image\n"); | |||
| 242 | error = perf_write_image((uint64_t *)image_ptr); | 242 | error = perf_write_image((uint64_t *)image_ptr); |
| 243 | if (error != 0) { | 243 | if (error != 0) { |
| 244 | printk("perf_config: DOWNLOAD = %ld\n", error); | 244 | printk("perf_config: DOWNLOAD = %ld\n", error); |
| 245 | return -EINVAL; | 245 | return -EINVAL; |
| 246 | } | 246 | } |
| 247 | 247 | ||
| 248 | printk("Preparing to start counters\n"); | 248 | printk("Preparing to start counters\n"); |
| @@ -254,7 +254,7 @@ printk("Preparing to start counters\n"); | |||
| 254 | } | 254 | } |
| 255 | 255 | ||
| 256 | /* | 256 | /* |
| 257 | * Open the device and initialize all of its memory. The device is only | 257 | * Open the device and initialize all of its memory. The device is only |
| 258 | * opened once, but can be "queried" by multiple processes that know its | 258 | * opened once, but can be "queried" by multiple processes that know its |
| 259 | * file descriptor. | 259 | * file descriptor. |
| 260 | */ | 260 | */ |
| @@ -298,19 +298,19 @@ static ssize_t perf_read(struct file *file, char __user *buf, size_t cnt, loff_t | |||
| 298 | * called on the processor that the download should happen | 298 | * called on the processor that the download should happen |
| 299 | * on. | 299 | * on. |
| 300 | */ | 300 | */ |
| 301 | static ssize_t perf_write(struct file *file, const char __user *buf, size_t count, | 301 | static ssize_t perf_write(struct file *file, const char __user *buf, |
| 302 | loff_t *ppos) | 302 | size_t count, loff_t *ppos) |
| 303 | { | 303 | { |
| 304 | size_t image_size; | 304 | size_t image_size; |
| 305 | uint32_t image_type; | 305 | uint32_t image_type; |
| 306 | uint32_t interface_type; | 306 | uint32_t interface_type; |
| 307 | uint32_t test; | 307 | uint32_t test; |
| 308 | 308 | ||
| 309 | if (perf_processor_interface == ONYX_INTF) | 309 | if (perf_processor_interface == ONYX_INTF) |
| 310 | image_size = PCXU_IMAGE_SIZE; | 310 | image_size = PCXU_IMAGE_SIZE; |
| 311 | else if (perf_processor_interface == CUDA_INTF) | 311 | else if (perf_processor_interface == CUDA_INTF) |
| 312 | image_size = PCXW_IMAGE_SIZE; | 312 | image_size = PCXW_IMAGE_SIZE; |
| 313 | else | 313 | else |
| 314 | return -EFAULT; | 314 | return -EFAULT; |
| 315 | 315 | ||
| 316 | if (!capable(CAP_SYS_ADMIN)) | 316 | if (!capable(CAP_SYS_ADMIN)) |
| @@ -330,22 +330,22 @@ static ssize_t perf_write(struct file *file, const char __user *buf, size_t coun | |||
| 330 | 330 | ||
| 331 | /* First check the machine type is correct for | 331 | /* First check the machine type is correct for |
| 332 | the requested image */ | 332 | the requested image */ |
| 333 | if (((perf_processor_interface == CUDA_INTF) && | 333 | if (((perf_processor_interface == CUDA_INTF) && |
| 334 | (interface_type != CUDA_INTF)) || | 334 | (interface_type != CUDA_INTF)) || |
| 335 | ((perf_processor_interface == ONYX_INTF) && | 335 | ((perf_processor_interface == ONYX_INTF) && |
| 336 | (interface_type != ONYX_INTF))) | 336 | (interface_type != ONYX_INTF))) |
| 337 | return -EINVAL; | 337 | return -EINVAL; |
| 338 | 338 | ||
| 339 | /* Next check to make sure the requested image | 339 | /* Next check to make sure the requested image |
| 340 | is valid */ | 340 | is valid */ |
| 341 | if (((interface_type == CUDA_INTF) && | 341 | if (((interface_type == CUDA_INTF) && |
| 342 | (test >= MAX_CUDA_IMAGES)) || | 342 | (test >= MAX_CUDA_IMAGES)) || |
| 343 | ((interface_type == ONYX_INTF) && | 343 | ((interface_type == ONYX_INTF) && |
| 344 | (test >= MAX_ONYX_IMAGES))) | 344 | (test >= MAX_ONYX_IMAGES))) |
| 345 | return -EINVAL; | 345 | return -EINVAL; |
| 346 | 346 | ||
| 347 | /* Copy the image into the processor */ | 347 | /* Copy the image into the processor */ |
| 348 | if (interface_type == CUDA_INTF) | 348 | if (interface_type == CUDA_INTF) |
| 349 | return perf_config(cuda_images[test]); | 349 | return perf_config(cuda_images[test]); |
| 350 | else | 350 | else |
| 351 | return perf_config(onyx_images[test]); | 351 | return perf_config(onyx_images[test]); |
| @@ -359,7 +359,7 @@ static ssize_t perf_write(struct file *file, const char __user *buf, size_t coun | |||
| 359 | static void perf_patch_images(void) | 359 | static void perf_patch_images(void) |
| 360 | { | 360 | { |
| 361 | #if 0 /* FIXME!! */ | 361 | #if 0 /* FIXME!! */ |
| 362 | /* | 362 | /* |
| 363 | * NOTE: this routine is VERY specific to the current TLB image. | 363 | * NOTE: this routine is VERY specific to the current TLB image. |
| 364 | * If the image is changed, this routine might also need to be changed. | 364 | * If the image is changed, this routine might also need to be changed. |
| 365 | */ | 365 | */ |
| @@ -367,9 +367,9 @@ static void perf_patch_images(void) | |||
| 367 | extern void $i_dtlb_miss_2_0(); | 367 | extern void $i_dtlb_miss_2_0(); |
| 368 | extern void PA2_0_iva(); | 368 | extern void PA2_0_iva(); |
| 369 | 369 | ||
| 370 | /* | 370 | /* |
| 371 | * We can only use the lower 32-bits, the upper 32-bits should be 0 | 371 | * We can only use the lower 32-bits, the upper 32-bits should be 0 |
| 372 | * anyway given this is in the kernel | 372 | * anyway given this is in the kernel |
| 373 | */ | 373 | */ |
| 374 | uint32_t itlb_addr = (uint32_t)&($i_itlb_miss_2_0); | 374 | uint32_t itlb_addr = (uint32_t)&($i_itlb_miss_2_0); |
| 375 | uint32_t dtlb_addr = (uint32_t)&($i_dtlb_miss_2_0); | 375 | uint32_t dtlb_addr = (uint32_t)&($i_dtlb_miss_2_0); |
| @@ -377,21 +377,21 @@ static void perf_patch_images(void) | |||
| 377 | 377 | ||
| 378 | if (perf_processor_interface == ONYX_INTF) { | 378 | if (perf_processor_interface == ONYX_INTF) { |
| 379 | /* clear last 2 bytes */ | 379 | /* clear last 2 bytes */ |
| 380 | onyx_images[TLBMISS][15] &= 0xffffff00; | 380 | onyx_images[TLBMISS][15] &= 0xffffff00; |
| 381 | /* set 2 bytes */ | 381 | /* set 2 bytes */ |
| 382 | onyx_images[TLBMISS][15] |= (0x000000ff&((dtlb_addr) >> 24)); | 382 | onyx_images[TLBMISS][15] |= (0x000000ff&((dtlb_addr) >> 24)); |
| 383 | onyx_images[TLBMISS][16] = (dtlb_addr << 8)&0xffffff00; | 383 | onyx_images[TLBMISS][16] = (dtlb_addr << 8)&0xffffff00; |
| 384 | onyx_images[TLBMISS][17] = itlb_addr; | 384 | onyx_images[TLBMISS][17] = itlb_addr; |
| 385 | 385 | ||
| 386 | /* clear last 2 bytes */ | 386 | /* clear last 2 bytes */ |
| 387 | onyx_images[TLBHANDMISS][15] &= 0xffffff00; | 387 | onyx_images[TLBHANDMISS][15] &= 0xffffff00; |
| 388 | /* set 2 bytes */ | 388 | /* set 2 bytes */ |
| 389 | onyx_images[TLBHANDMISS][15] |= (0x000000ff&((dtlb_addr) >> 24)); | 389 | onyx_images[TLBHANDMISS][15] |= (0x000000ff&((dtlb_addr) >> 24)); |
| 390 | onyx_images[TLBHANDMISS][16] = (dtlb_addr << 8)&0xffffff00; | 390 | onyx_images[TLBHANDMISS][16] = (dtlb_addr << 8)&0xffffff00; |
| 391 | onyx_images[TLBHANDMISS][17] = itlb_addr; | 391 | onyx_images[TLBHANDMISS][17] = itlb_addr; |
| 392 | 392 | ||
| 393 | /* clear last 2 bytes */ | 393 | /* clear last 2 bytes */ |
| 394 | onyx_images[BIG_CPI][15] &= 0xffffff00; | 394 | onyx_images[BIG_CPI][15] &= 0xffffff00; |
| 395 | /* set 2 bytes */ | 395 | /* set 2 bytes */ |
| 396 | onyx_images[BIG_CPI][15] |= (0x000000ff&((dtlb_addr) >> 24)); | 396 | onyx_images[BIG_CPI][15] |= (0x000000ff&((dtlb_addr) >> 24)); |
| 397 | onyx_images[BIG_CPI][16] = (dtlb_addr << 8)&0xffffff00; | 397 | onyx_images[BIG_CPI][16] = (dtlb_addr << 8)&0xffffff00; |
| @@ -404,24 +404,24 @@ static void perf_patch_images(void) | |||
| 404 | 404 | ||
| 405 | } else if (perf_processor_interface == CUDA_INTF) { | 405 | } else if (perf_processor_interface == CUDA_INTF) { |
| 406 | /* Cuda interface */ | 406 | /* Cuda interface */ |
| 407 | cuda_images[TLBMISS][16] = | 407 | cuda_images[TLBMISS][16] = |
| 408 | (cuda_images[TLBMISS][16]&0xffff0000) | | 408 | (cuda_images[TLBMISS][16]&0xffff0000) | |
| 409 | ((dtlb_addr >> 8)&0x0000ffff); | 409 | ((dtlb_addr >> 8)&0x0000ffff); |
| 410 | cuda_images[TLBMISS][17] = | 410 | cuda_images[TLBMISS][17] = |
| 411 | ((dtlb_addr << 24)&0xff000000) | ((itlb_addr >> 16)&0x000000ff); | 411 | ((dtlb_addr << 24)&0xff000000) | ((itlb_addr >> 16)&0x000000ff); |
| 412 | cuda_images[TLBMISS][18] = (itlb_addr << 16)&0xffff0000; | 412 | cuda_images[TLBMISS][18] = (itlb_addr << 16)&0xffff0000; |
| 413 | 413 | ||
| 414 | cuda_images[TLBHANDMISS][16] = | 414 | cuda_images[TLBHANDMISS][16] = |
| 415 | (cuda_images[TLBHANDMISS][16]&0xffff0000) | | 415 | (cuda_images[TLBHANDMISS][16]&0xffff0000) | |
| 416 | ((dtlb_addr >> 8)&0x0000ffff); | 416 | ((dtlb_addr >> 8)&0x0000ffff); |
| 417 | cuda_images[TLBHANDMISS][17] = | 417 | cuda_images[TLBHANDMISS][17] = |
| 418 | ((dtlb_addr << 24)&0xff000000) | ((itlb_addr >> 16)&0x000000ff); | 418 | ((dtlb_addr << 24)&0xff000000) | ((itlb_addr >> 16)&0x000000ff); |
| 419 | cuda_images[TLBHANDMISS][18] = (itlb_addr << 16)&0xffff0000; | 419 | cuda_images[TLBHANDMISS][18] = (itlb_addr << 16)&0xffff0000; |
| 420 | 420 | ||
| 421 | cuda_images[BIG_CPI][16] = | 421 | cuda_images[BIG_CPI][16] = |
| 422 | (cuda_images[BIG_CPI][16]&0xffff0000) | | 422 | (cuda_images[BIG_CPI][16]&0xffff0000) | |
| 423 | ((dtlb_addr >> 8)&0x0000ffff); | 423 | ((dtlb_addr >> 8)&0x0000ffff); |
| 424 | cuda_images[BIG_CPI][17] = | 424 | cuda_images[BIG_CPI][17] = |
| 425 | ((dtlb_addr << 24)&0xff000000) | ((itlb_addr >> 16)&0x000000ff); | 425 | ((dtlb_addr << 24)&0xff000000) | ((itlb_addr >> 16)&0x000000ff); |
| 426 | cuda_images[BIG_CPI][18] = (itlb_addr << 16)&0xffff0000; | 426 | cuda_images[BIG_CPI][18] = (itlb_addr << 16)&0xffff0000; |
| 427 | } else { | 427 | } else { |
| @@ -433,7 +433,7 @@ static void perf_patch_images(void) | |||
| 433 | 433 | ||
| 434 | /* | 434 | /* |
| 435 | * ioctl routine | 435 | * ioctl routine |
| 436 | * All routines effect the processor that they are executed on. Thus you | 436 | * All routines effect the processor that they are executed on. Thus you |
| 437 | * must be running on the processor that you wish to change. | 437 | * must be running on the processor that you wish to change. |
| 438 | */ | 438 | */ |
| 439 | 439 | ||
| @@ -459,7 +459,7 @@ static long perf_ioctl(struct file *file, unsigned int cmd, unsigned long arg) | |||
| 459 | } | 459 | } |
| 460 | 460 | ||
| 461 | /* copy out the Counters */ | 461 | /* copy out the Counters */ |
| 462 | if (copy_to_user((void __user *)arg, raddr, | 462 | if (copy_to_user((void __user *)arg, raddr, |
| 463 | sizeof (raddr)) != 0) { | 463 | sizeof (raddr)) != 0) { |
| 464 | error = -EFAULT; | 464 | error = -EFAULT; |
| 465 | break; | 465 | break; |
| @@ -487,7 +487,7 @@ static const struct file_operations perf_fops = { | |||
| 487 | .open = perf_open, | 487 | .open = perf_open, |
| 488 | .release = perf_release | 488 | .release = perf_release |
| 489 | }; | 489 | }; |
| 490 | 490 | ||
| 491 | static struct miscdevice perf_dev = { | 491 | static struct miscdevice perf_dev = { |
| 492 | MISC_DYNAMIC_MINOR, | 492 | MISC_DYNAMIC_MINOR, |
| 493 | PA_PERF_DEV, | 493 | PA_PERF_DEV, |
| @@ -595,7 +595,7 @@ static int perf_stop_counters(uint32_t *raddr) | |||
| 595 | /* OR sticky2 (bit 1496) to counter2 bit 32 */ | 595 | /* OR sticky2 (bit 1496) to counter2 bit 32 */ |
| 596 | tmp64 |= (userbuf[23] >> 8) & 0x0000000080000000; | 596 | tmp64 |= (userbuf[23] >> 8) & 0x0000000080000000; |
| 597 | raddr[2] = (uint32_t)tmp64; | 597 | raddr[2] = (uint32_t)tmp64; |
| 598 | 598 | ||
| 599 | /* Counter3 is bits 1497 to 1528 */ | 599 | /* Counter3 is bits 1497 to 1528 */ |
| 600 | tmp64 = (userbuf[23] >> 7) & 0x00000000ffffffff; | 600 | tmp64 = (userbuf[23] >> 7) & 0x00000000ffffffff; |
| 601 | /* OR sticky3 (bit 1529) to counter3 bit 32 */ | 601 | /* OR sticky3 (bit 1529) to counter3 bit 32 */ |
| @@ -617,7 +617,7 @@ static int perf_stop_counters(uint32_t *raddr) | |||
| 617 | userbuf[22] = 0; | 617 | userbuf[22] = 0; |
| 618 | userbuf[23] = 0; | 618 | userbuf[23] = 0; |
| 619 | 619 | ||
| 620 | /* | 620 | /* |
| 621 | * Write back the zeroed bytes + the image given | 621 | * Write back the zeroed bytes + the image given |
| 622 | * the read was destructive. | 622 | * the read was destructive. |
| 623 | */ | 623 | */ |
| @@ -625,13 +625,13 @@ static int perf_stop_counters(uint32_t *raddr) | |||
| 625 | } else { | 625 | } else { |
| 626 | 626 | ||
| 627 | /* | 627 | /* |
| 628 | * Read RDR-15 which contains the counters and sticky bits | 628 | * Read RDR-15 which contains the counters and sticky bits |
| 629 | */ | 629 | */ |
| 630 | if (!perf_rdr_read_ubuf(15, userbuf)) { | 630 | if (!perf_rdr_read_ubuf(15, userbuf)) { |
| 631 | return -13; | 631 | return -13; |
| 632 | } | 632 | } |
| 633 | 633 | ||
| 634 | /* | 634 | /* |
| 635 | * Clear out the counters | 635 | * Clear out the counters |
| 636 | */ | 636 | */ |
| 637 | perf_rdr_clear(15); | 637 | perf_rdr_clear(15); |
| @@ -644,7 +644,7 @@ static int perf_stop_counters(uint32_t *raddr) | |||
| 644 | raddr[2] = (uint32_t)((userbuf[1] >> 32) & 0x00000000ffffffffUL); | 644 | raddr[2] = (uint32_t)((userbuf[1] >> 32) & 0x00000000ffffffffUL); |
| 645 | raddr[3] = (uint32_t)(userbuf[1] & 0x00000000ffffffffUL); | 645 | raddr[3] = (uint32_t)(userbuf[1] & 0x00000000ffffffffUL); |
| 646 | } | 646 | } |
| 647 | 647 | ||
| 648 | return 0; | 648 | return 0; |
| 649 | } | 649 | } |
| 650 | 650 | ||
| @@ -682,7 +682,7 @@ static int perf_rdr_read_ubuf(uint32_t rdr_num, uint64_t *buffer) | |||
| 682 | i = tentry->num_words; | 682 | i = tentry->num_words; |
| 683 | while (i--) { | 683 | while (i--) { |
| 684 | buffer[i] = 0; | 684 | buffer[i] = 0; |
| 685 | } | 685 | } |
| 686 | 686 | ||
| 687 | /* Check for bits an even number of 64 */ | 687 | /* Check for bits an even number of 64 */ |
| 688 | if ((xbits = width & 0x03f) != 0) { | 688 | if ((xbits = width & 0x03f) != 0) { |
| @@ -808,18 +808,22 @@ static int perf_write_image(uint64_t *memaddr) | |||
| 808 | } | 808 | } |
| 809 | 809 | ||
| 810 | runway = ioremap_nocache(cpu_device->hpa.start, 4096); | 810 | runway = ioremap_nocache(cpu_device->hpa.start, 4096); |
| 811 | if (!runway) { | ||
| 812 | pr_err("perf_write_image: ioremap failed!\n"); | ||
| 813 | return -ENOMEM; | ||
| 814 | } | ||
| 811 | 815 | ||
| 812 | /* Merge intrigue bits into Runway STATUS 0 */ | 816 | /* Merge intrigue bits into Runway STATUS 0 */ |
| 813 | tmp64 = __raw_readq(runway + RUNWAY_STATUS) & 0xffecfffffffffffful; | 817 | tmp64 = __raw_readq(runway + RUNWAY_STATUS) & 0xffecfffffffffffful; |
| 814 | __raw_writeq(tmp64 | (*memaddr++ & 0x0013000000000000ul), | 818 | __raw_writeq(tmp64 | (*memaddr++ & 0x0013000000000000ul), |
| 815 | runway + RUNWAY_STATUS); | 819 | runway + RUNWAY_STATUS); |
| 816 | 820 | ||
| 817 | /* Write RUNWAY DEBUG registers */ | 821 | /* Write RUNWAY DEBUG registers */ |
| 818 | for (i = 0; i < 8; i++) { | 822 | for (i = 0; i < 8; i++) { |
| 819 | __raw_writeq(*memaddr++, runway + RUNWAY_DEBUG); | 823 | __raw_writeq(*memaddr++, runway + RUNWAY_DEBUG); |
| 820 | } | 824 | } |
| 821 | 825 | ||
| 822 | return 0; | 826 | return 0; |
| 823 | } | 827 | } |
| 824 | 828 | ||
| 825 | /* | 829 | /* |
| @@ -843,7 +847,7 @@ printk("perf_rdr_write\n"); | |||
| 843 | perf_rdr_shift_out_U(rdr_num, buffer[i]); | 847 | perf_rdr_shift_out_U(rdr_num, buffer[i]); |
| 844 | } else { | 848 | } else { |
| 845 | perf_rdr_shift_out_W(rdr_num, buffer[i]); | 849 | perf_rdr_shift_out_W(rdr_num, buffer[i]); |
| 846 | } | 850 | } |
| 847 | } | 851 | } |
| 848 | printk("perf_rdr_write done\n"); | 852 | printk("perf_rdr_write done\n"); |
| 849 | } | 853 | } |
