drm/i915/bxt: reserve space for RC6 in the the GuC WOPCM

This patch resizes the GuC WOPCM (specifically on BXT)
so that the GuC and RC6 memory spaces do not overlap.

v2:
    Made calculation of WOPCM size into a separate function,
    so that it's consistent between the firmware size-check
    and the register-programming operations [Dave Gordon].

Issue: https://jira01.devtools.intel.com/browse/VIZ-6638
Signed-off-by: Peter Antoine <peter.antoine@intel.com>
Signed-off-by: Dave Gordon <david.s.gordon@intel.com>
Reviewed-by: Nick Hoath <nicholas.hoath@intel.com>
Tested-by: Nick Hoath <nicholas.hoath@intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1463494365-26330-1-git-send-email-david.s.gordon@intel.com

2 files changed, 16 insertions, 7 deletions

diff --git a/drivers/gpu/drm/i915/i915_guc_reg.h b/drivers/gpu/drm/i915/i915_guc_reg.h
index 80786d9f9ad3..cf5a65be4fe0 100644
--- a/drivers/gpu/drm/i915/i915_guc_reg.h
+++ b/drivers/gpu/drm/i915/i915_guc_reg.h
@@ -67,11 +67,11 @@
 #define   GUC_WOPCM_OFFSET_VALUE          0x80000       /* 512KB */
 #define GUC_MAX_IDLE_COUNT              _MMIO(0xC3E4)
 
+/* Defines WOPCM space available to GuC firmware */
 #define GUC_WOPCM_SIZE                  _MMIO(0xc050)
-#define   GUC_WOPCM_SIZE_VALUE            (0x80 << 12)  /* 512KB */
-
 /* GuC addresses below GUC_WOPCM_TOP don't map through the GTT */
-#define GUC_WOPCM_TOP                   (GUC_WOPCM_SIZE_VALUE)
+#define   GUC_WOPCM_TOP                   (0x80 << 12)  /* 512KB */
+#define   BXT_GUC_WOPCM_RC6_RESERVED      (0x10 << 12)  /* 64KB  */
 
 #define GEN8_GT_PM_CONFIG               _MMIO(0x138140)
 #define GEN9LP_GT_PM_CONFIG             _MMIO(0x138140)
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 23345e15bffc..34405de72dfa 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -284,6 +284,17 @@ static int guc_ucode_xfer_dma(struct drm_i915_private *dev_priv)
         return ret;
 }
 
+static u32 guc_wopcm_size(struct drm_i915_private *dev_priv)
+{
+        u32 wopcm_size = GUC_WOPCM_TOP;
+
+        /* On BXT, the top of WOPCM is reserved for RC6 context */
+        if (IS_BROXTON(dev_priv))
+                wopcm_size -= BXT_GUC_WOPCM_RC6_RESERVED;
+
+        return wopcm_size;
+}
+
 /*
  * Load the GuC firmware blob into the MinuteIA.
  */
@@ -311,7 +322,7 @@ static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
 
         /* init WOPCM */
-        I915_WRITE(GUC_WOPCM_SIZE, GUC_WOPCM_SIZE_VALUE);
+        I915_WRITE(GUC_WOPCM_SIZE, guc_wopcm_size(dev_priv));
         I915_WRITE(DMA_GUC_WOPCM_OFFSET, GUC_WOPCM_OFFSET_VALUE);
 
         /* Enable MIA caching. GuC clock gating is disabled. */
@@ -555,9 +566,7 @@ static void guc_fw_fetch(struct drm_device *dev, struct intel_guc_fw *guc_fw)
 
         /* Header and uCode will be loaded to WOPCM. Size of the two. */
         size = guc_fw->header_size + guc_fw->ucode_size;
-
-        /* Top 32k of WOPCM is reserved (8K stack + 24k RC6 context). */
-        if (size > GUC_WOPCM_SIZE_VALUE - 0x8000) {
+        if (size > guc_wopcm_size(dev->dev_private)) {
                 DRM_ERROR("Firmware is too large to fit in WOPCM\n");
                 goto fail;
         }