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authorLinus Torvalds <torvalds@linux-foundation.org>2016-04-07 18:53:19 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2016-04-07 18:53:19 -0400
commit741f37b8ccf10b3f9976f7e55b703af8087f182a (patch)
tree2c9db58d7cc32aab3204beb35b82115622c8dd4e
parentc4004b02f8e5b9ce357a0bb1641756cc86962664 (diff)
parentfd8c61ebd4265ff1c5fa80ba351e8e1dd710fac0 (diff)
Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux
Pull drm fixes from Dave Airlie: "This is mostly amdgpu/radeon fixes, and imx related fixes. There is also one one TTM fix, one nouveau fix, and one hdlcd fix. The AMD ones are some fixes for power management after suspend/resume one some GPUs, and some vblank fixes. The IMX ones are for more stricter plane checks and some cleanups. I'm off until Monday, so therre might be some fixes early next week if anyone missed me" * 'drm-fixes' of git://people.freedesktop.org/~airlied/linux: (34 commits) drm/nouveau/tegra: acquire and enable reference clock if needed drm/amdgpu: total vram size also reduces pin size drm/amd/powerplay: add uvd/vce dpm enabling flag default. drm/amd/powerplay: fix issue that resume back, dpm can't work on FIJI. drm/amdgpu: save and restore the firwmware cache part when suspend resume drm/amdgpu: save and restore UVD context with suspend and resume drm/ttm: use phys_addr_t for ttm_bus_placement drm: ARM HDLCD - fix an error code drm: ARM HDLCD - get rid of devm_clk_put() drm/radeon: Only call drm_vblank_on/off between drm_vblank_init/cleanup drm/amdgpu: fence wait old rcu slot drm/amdgpu: fix leaking fence in the pageflip code drm/amdgpu: print vram type rather than just DDR drm/amdgpu/gmc: use proper register for vram type on Fiji drm/amdgpu/gmc: move vram type fetching into sw_init drm/amdgpu: Set vblank_disable_allowed = true drm/radeon: Set vblank_disable_allowed = true drm/amd/powerplay: Need to change boot to performance state in resume. drm/amd/powerplay: add new Fiji function for not setting same ps. drm/amdgpu: check dpm state before pm system fs initialized. ...
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu.h1
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c24
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_display.c2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c8
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c1
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_object.c15
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c10
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c58
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c16
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c23
-rw-r--r--drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c4
-rw-r--r--drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c4
-rw-r--r--drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c7
-rw-r--r--drivers/gpu/drm/amd/include/cgs_common.h8
-rw-r--r--drivers/gpu/drm/amd/powerplay/eventmgr/eventactionchains.c4
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c69
-rw-r--r--drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c16
-rw-r--r--drivers/gpu/drm/arm/hdlcd_drv.c14
-rw-r--r--drivers/gpu/drm/imx/dw_hdmi-imx.c13
-rw-r--r--drivers/gpu/drm/imx/imx-drm-core.c10
-rw-r--r--drivers/gpu/drm/imx/ipuv3-plane.c123
-rw-r--r--drivers/gpu/drm/imx/ipuv3-plane.h4
-rw-r--r--drivers/gpu/drm/nouveau/include/nvkm/core/tegra.h5
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_platform.c7
-rw-r--r--drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c17
-rw-r--r--drivers/gpu/drm/radeon/atombios_crtc.c6
-rw-r--r--drivers/gpu/drm/radeon/radeon_irq_kms.c2
-rw-r--r--drivers/gpu/drm/radeon/radeon_legacy_crtc.c6
-rw-r--r--drivers/gpu/ipu-v3/ipu-cpmem.c79
-rw-r--r--drivers/gpu/ipu-v3/ipu-dmfc.c8
-rw-r--r--include/drm/ttm/ttm_bo_api.h2
-rw-r--r--include/video/imx-ipu-v3.h7
33 files changed, 405 insertions, 170 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index c4a21c6428f5..62a778012fe0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1591,6 +1591,7 @@ struct amdgpu_uvd {
1591 struct amdgpu_bo *vcpu_bo; 1591 struct amdgpu_bo *vcpu_bo;
1592 void *cpu_addr; 1592 void *cpu_addr;
1593 uint64_t gpu_addr; 1593 uint64_t gpu_addr;
1594 void *saved_bo;
1594 atomic_t handles[AMDGPU_MAX_UVD_HANDLES]; 1595 atomic_t handles[AMDGPU_MAX_UVD_HANDLES];
1595 struct drm_file *filp[AMDGPU_MAX_UVD_HANDLES]; 1596 struct drm_file *filp[AMDGPU_MAX_UVD_HANDLES];
1596 struct delayed_work idle_work; 1597 struct delayed_work idle_work;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
index 7a4b101e10c6..6043dc7c3a94 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
@@ -816,10 +816,13 @@ static int amdgpu_cgs_get_active_displays_info(void *cgs_device,
816 struct drm_device *ddev = adev->ddev; 816 struct drm_device *ddev = adev->ddev;
817 struct drm_crtc *crtc; 817 struct drm_crtc *crtc;
818 uint32_t line_time_us, vblank_lines; 818 uint32_t line_time_us, vblank_lines;
819 struct cgs_mode_info *mode_info;
819 820
820 if (info == NULL) 821 if (info == NULL)
821 return -EINVAL; 822 return -EINVAL;
822 823
824 mode_info = info->mode_info;
825
823 if (adev->mode_info.num_crtc && adev->mode_info.mode_config_initialized) { 826 if (adev->mode_info.num_crtc && adev->mode_info.mode_config_initialized) {
824 list_for_each_entry(crtc, 827 list_for_each_entry(crtc,
825 &ddev->mode_config.crtc_list, head) { 828 &ddev->mode_config.crtc_list, head) {
@@ -828,7 +831,7 @@ static int amdgpu_cgs_get_active_displays_info(void *cgs_device,
828 info->active_display_mask |= (1 << amdgpu_crtc->crtc_id); 831 info->active_display_mask |= (1 << amdgpu_crtc->crtc_id);
829 info->display_count++; 832 info->display_count++;
830 } 833 }
831 if (info->mode_info != NULL && 834 if (mode_info != NULL &&
832 crtc->enabled && amdgpu_crtc->enabled && 835 crtc->enabled && amdgpu_crtc->enabled &&
833 amdgpu_crtc->hw_mode.clock) { 836 amdgpu_crtc->hw_mode.clock) {
834 line_time_us = (amdgpu_crtc->hw_mode.crtc_htotal * 1000) / 837 line_time_us = (amdgpu_crtc->hw_mode.crtc_htotal * 1000) /
@@ -836,10 +839,10 @@ static int amdgpu_cgs_get_active_displays_info(void *cgs_device,
836 vblank_lines = amdgpu_crtc->hw_mode.crtc_vblank_end - 839 vblank_lines = amdgpu_crtc->hw_mode.crtc_vblank_end -
837 amdgpu_crtc->hw_mode.crtc_vdisplay + 840 amdgpu_crtc->hw_mode.crtc_vdisplay +
838 (amdgpu_crtc->v_border * 2); 841 (amdgpu_crtc->v_border * 2);
839 info->mode_info->vblank_time_us = vblank_lines * line_time_us; 842 mode_info->vblank_time_us = vblank_lines * line_time_us;
840 info->mode_info->refresh_rate = drm_mode_vrefresh(&amdgpu_crtc->hw_mode); 843 mode_info->refresh_rate = drm_mode_vrefresh(&amdgpu_crtc->hw_mode);
841 info->mode_info->ref_clock = adev->clock.spll.reference_freq; 844 mode_info->ref_clock = adev->clock.spll.reference_freq;
842 info->mode_info++; 845 mode_info = NULL;
843 } 846 }
844 } 847 }
845 } 848 }
@@ -847,6 +850,16 @@ static int amdgpu_cgs_get_active_displays_info(void *cgs_device,
847 return 0; 850 return 0;
848} 851}
849 852
853
854static int amdgpu_cgs_notify_dpm_enabled(void *cgs_device, bool enabled)
855{
856 CGS_FUNC_ADEV;
857
858 adev->pm.dpm_enabled = enabled;
859
860 return 0;
861}
862
850/** \brief evaluate acpi namespace object, handle or pathname must be valid 863/** \brief evaluate acpi namespace object, handle or pathname must be valid
851 * \param cgs_device 864 * \param cgs_device
852 * \param info input/output arguments for the control method 865 * \param info input/output arguments for the control method
@@ -1097,6 +1110,7 @@ static const struct cgs_ops amdgpu_cgs_ops = {
1097 amdgpu_cgs_set_powergating_state, 1110 amdgpu_cgs_set_powergating_state,
1098 amdgpu_cgs_set_clockgating_state, 1111 amdgpu_cgs_set_clockgating_state,
1099 amdgpu_cgs_get_active_displays_info, 1112 amdgpu_cgs_get_active_displays_info,
1113 amdgpu_cgs_notify_dpm_enabled,
1100 amdgpu_cgs_call_acpi_method, 1114 amdgpu_cgs_call_acpi_method,
1101 amdgpu_cgs_query_system_info, 1115 amdgpu_cgs_query_system_info,
1102}; 1116};
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
index f0ed974bd4e0..3fb405b3a614 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
@@ -57,7 +57,7 @@ static bool amdgpu_flip_handle_fence(struct amdgpu_flip_work *work,
57 if (!fence_add_callback(fence, &work->cb, amdgpu_flip_callback)) 57 if (!fence_add_callback(fence, &work->cb, amdgpu_flip_callback))
58 return true; 58 return true;
59 59
60 fence_put(*f); 60 fence_put(fence);
61 return false; 61 return false;
62} 62}
63 63
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
index 4303b447efe8..d81f1f4883a6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
@@ -121,7 +121,7 @@ int amdgpu_fence_emit(struct amdgpu_ring *ring, struct fence **f)
121{ 121{
122 struct amdgpu_device *adev = ring->adev; 122 struct amdgpu_device *adev = ring->adev;
123 struct amdgpu_fence *fence; 123 struct amdgpu_fence *fence;
124 struct fence **ptr; 124 struct fence *old, **ptr;
125 uint32_t seq; 125 uint32_t seq;
126 126
127 fence = kmem_cache_alloc(amdgpu_fence_slab, GFP_KERNEL); 127 fence = kmem_cache_alloc(amdgpu_fence_slab, GFP_KERNEL);
@@ -141,7 +141,11 @@ int amdgpu_fence_emit(struct amdgpu_ring *ring, struct fence **f)
141 /* This function can't be called concurrently anyway, otherwise 141 /* This function can't be called concurrently anyway, otherwise
142 * emitting the fence would mess up the hardware ring buffer. 142 * emitting the fence would mess up the hardware ring buffer.
143 */ 143 */
144 BUG_ON(rcu_dereference_protected(*ptr, 1)); 144 old = rcu_dereference_protected(*ptr, 1);
145 if (old && !fence_is_signaled(old)) {
146 DRM_INFO("rcu slot is busy\n");
147 fence_wait(old, false);
148 }
145 149
146 rcu_assign_pointer(*ptr, fence_get(&fence->base)); 150 rcu_assign_pointer(*ptr, fence_get(&fence->base));
147 151
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
index f594cfaa97e5..762cfdb85147 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
@@ -219,6 +219,8 @@ int amdgpu_irq_init(struct amdgpu_device *adev)
219 if (r) { 219 if (r) {
220 return r; 220 return r;
221 } 221 }
222 adev->ddev->vblank_disable_allowed = true;
223
222 /* enable msi */ 224 /* enable msi */
223 adev->irq.msi_enabled = false; 225 adev->irq.msi_enabled = false;
224 226
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 7805a8706af7..598eb0cd5aab 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -382,6 +382,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
382 struct drm_amdgpu_info_vram_gtt vram_gtt; 382 struct drm_amdgpu_info_vram_gtt vram_gtt;
383 383
384 vram_gtt.vram_size = adev->mc.real_vram_size; 384 vram_gtt.vram_size = adev->mc.real_vram_size;
385 vram_gtt.vram_size -= adev->vram_pin_size;
385 vram_gtt.vram_cpu_accessible_size = adev->mc.visible_vram_size; 386 vram_gtt.vram_cpu_accessible_size = adev->mc.visible_vram_size;
386 vram_gtt.vram_cpu_accessible_size -= adev->vram_pin_size; 387 vram_gtt.vram_cpu_accessible_size -= adev->vram_pin_size;
387 vram_gtt.gtt_size = adev->mc.gtt_size; 388 vram_gtt.gtt_size = adev->mc.gtt_size;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 56d1458393cc..5b6639faa731 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -476,6 +476,17 @@ int amdgpu_bo_evict_vram(struct amdgpu_device *adev)
476 return ttm_bo_evict_mm(&adev->mman.bdev, TTM_PL_VRAM); 476 return ttm_bo_evict_mm(&adev->mman.bdev, TTM_PL_VRAM);
477} 477}
478 478
479static const char *amdgpu_vram_names[] = {
480 "UNKNOWN",
481 "GDDR1",
482 "DDR2",
483 "GDDR3",
484 "GDDR4",
485 "GDDR5",
486 "HBM",
487 "DDR3"
488};
489
479int amdgpu_bo_init(struct amdgpu_device *adev) 490int amdgpu_bo_init(struct amdgpu_device *adev)
480{ 491{
481 /* Add an MTRR for the VRAM */ 492 /* Add an MTRR for the VRAM */
@@ -484,8 +495,8 @@ int amdgpu_bo_init(struct amdgpu_device *adev)
484 DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n", 495 DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
485 adev->mc.mc_vram_size >> 20, 496 adev->mc.mc_vram_size >> 20,
486 (unsigned long long)adev->mc.aper_size >> 20); 497 (unsigned long long)adev->mc.aper_size >> 20);
487 DRM_INFO("RAM width %dbits DDR\n", 498 DRM_INFO("RAM width %dbits %s\n",
488 adev->mc.vram_width); 499 adev->mc.vram_width, amdgpu_vram_names[adev->mc.vram_type]);
489 return amdgpu_ttm_init(adev); 500 return amdgpu_ttm_init(adev);
490} 501}
491 502
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
index 3cb6d6c413c7..e9c6ae6ed2f7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
@@ -143,7 +143,7 @@ static int amdgpu_pp_late_init(void *handle)
143 adev->powerplay.pp_handle); 143 adev->powerplay.pp_handle);
144 144
145#ifdef CONFIG_DRM_AMD_POWERPLAY 145#ifdef CONFIG_DRM_AMD_POWERPLAY
146 if (adev->pp_enabled) { 146 if (adev->pp_enabled && adev->pm.dpm_enabled) {
147 amdgpu_pm_sysfs_init(adev); 147 amdgpu_pm_sysfs_init(adev);
148 amdgpu_dpm_dispatch_task(adev, AMD_PP_EVENT_COMPLETE_INIT, NULL, NULL); 148 amdgpu_dpm_dispatch_task(adev, AMD_PP_EVENT_COMPLETE_INIT, NULL, NULL);
149 } 149 }
@@ -161,12 +161,8 @@ static int amdgpu_pp_sw_init(void *handle)
161 adev->powerplay.pp_handle); 161 adev->powerplay.pp_handle);
162 162
163#ifdef CONFIG_DRM_AMD_POWERPLAY 163#ifdef CONFIG_DRM_AMD_POWERPLAY
164 if (adev->pp_enabled) { 164 if (adev->pp_enabled)
165 if (amdgpu_dpm == 0) 165 adev->pm.dpm_enabled = true;
166 adev->pm.dpm_enabled = false;
167 else
168 adev->pm.dpm_enabled = true;
169 }
170#endif 166#endif
171 167
172 return ret; 168 return ret;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
index c1a581044417..338da80006b6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
@@ -241,32 +241,28 @@ int amdgpu_uvd_sw_fini(struct amdgpu_device *adev)
241 241
242int amdgpu_uvd_suspend(struct amdgpu_device *adev) 242int amdgpu_uvd_suspend(struct amdgpu_device *adev)
243{ 243{
244 struct amdgpu_ring *ring = &adev->uvd.ring; 244 unsigned size;
245 int i, r; 245 void *ptr;
246 int i;
246 247
247 if (adev->uvd.vcpu_bo == NULL) 248 if (adev->uvd.vcpu_bo == NULL)
248 return 0; 249 return 0;
249 250
250 for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i) { 251 for (i = 0; i < AMDGPU_MAX_UVD_HANDLES; ++i)
251 uint32_t handle = atomic_read(&adev->uvd.handles[i]); 252 if (atomic_read(&adev->uvd.handles[i]))
252 if (handle != 0) { 253 break;
253 struct fence *fence;
254 254
255 amdgpu_uvd_note_usage(adev); 255 if (i == AMDGPU_MAX_UVD_HANDLES)
256 return 0;
256 257
257 r = amdgpu_uvd_get_destroy_msg(ring, handle, false, &fence); 258 size = amdgpu_bo_size(adev->uvd.vcpu_bo);
258 if (r) { 259 ptr = adev->uvd.cpu_addr;
259 DRM_ERROR("Error destroying UVD (%d)!\n", r);
260 continue;
261 }
262 260
263 fence_wait(fence, false); 261 adev->uvd.saved_bo = kmalloc(size, GFP_KERNEL);
264 fence_put(fence); 262 if (!adev->uvd.saved_bo)
263 return -ENOMEM;
265 264
266 adev->uvd.filp[i] = NULL; 265 memcpy(adev->uvd.saved_bo, ptr, size);
267 atomic_set(&adev->uvd.handles[i], 0);
268 }
269 }
270 266
271 return 0; 267 return 0;
272} 268}
@@ -275,23 +271,29 @@ int amdgpu_uvd_resume(struct amdgpu_device *adev)
275{ 271{
276 unsigned size; 272 unsigned size;
277 void *ptr; 273 void *ptr;
278 const struct common_firmware_header *hdr;
279 unsigned offset;
280 274
281 if (adev->uvd.vcpu_bo == NULL) 275 if (adev->uvd.vcpu_bo == NULL)
282 return -EINVAL; 276 return -EINVAL;
283 277
284 hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
285 offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
286 memcpy(adev->uvd.cpu_addr, (adev->uvd.fw->data) + offset,
287 (adev->uvd.fw->size) - offset);
288
289 size = amdgpu_bo_size(adev->uvd.vcpu_bo); 278 size = amdgpu_bo_size(adev->uvd.vcpu_bo);
290 size -= le32_to_cpu(hdr->ucode_size_bytes);
291 ptr = adev->uvd.cpu_addr; 279 ptr = adev->uvd.cpu_addr;
292 ptr += le32_to_cpu(hdr->ucode_size_bytes);
293 280
294 memset(ptr, 0, size); 281 if (adev->uvd.saved_bo != NULL) {
282 memcpy(ptr, adev->uvd.saved_bo, size);
283 kfree(adev->uvd.saved_bo);
284 adev->uvd.saved_bo = NULL;
285 } else {
286 const struct common_firmware_header *hdr;
287 unsigned offset;
288
289 hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
290 offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
291 memcpy(adev->uvd.cpu_addr, (adev->uvd.fw->data) + offset,
292 (adev->uvd.fw->size) - offset);
293 size -= le32_to_cpu(hdr->ucode_size_bytes);
294 ptr += le32_to_cpu(hdr->ucode_size_bytes);
295 memset(ptr, 0, size);
296 }
295 297
296 return 0; 298 return 0;
297} 299}
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index 82ce7d943884..05b0353d3880 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -903,14 +903,6 @@ static int gmc_v7_0_early_init(void *handle)
903 gmc_v7_0_set_gart_funcs(adev); 903 gmc_v7_0_set_gart_funcs(adev);
904 gmc_v7_0_set_irq_funcs(adev); 904 gmc_v7_0_set_irq_funcs(adev);
905 905
906 if (adev->flags & AMD_IS_APU) {
907 adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
908 } else {
909 u32 tmp = RREG32(mmMC_SEQ_MISC0);
910 tmp &= MC_SEQ_MISC0__MT__MASK;
911 adev->mc.vram_type = gmc_v7_0_convert_vram_type(tmp);
912 }
913
914 return 0; 906 return 0;
915} 907}
916 908
@@ -927,6 +919,14 @@ static int gmc_v7_0_sw_init(void *handle)
927 int dma_bits; 919 int dma_bits;
928 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 920 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
929 921
922 if (adev->flags & AMD_IS_APU) {
923 adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
924 } else {
925 u32 tmp = RREG32(mmMC_SEQ_MISC0);
926 tmp &= MC_SEQ_MISC0__MT__MASK;
927 adev->mc.vram_type = gmc_v7_0_convert_vram_type(tmp);
928 }
929
930 r = amdgpu_irq_add_id(adev, 146, &adev->mc.vm_fault); 930 r = amdgpu_irq_add_id(adev, 146, &adev->mc.vm_fault);
931 if (r) 931 if (r)
932 return r; 932 return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index 29bd7b57dc91..02deb3229405 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -863,14 +863,6 @@ static int gmc_v8_0_early_init(void *handle)
863 gmc_v8_0_set_gart_funcs(adev); 863 gmc_v8_0_set_gart_funcs(adev);
864 gmc_v8_0_set_irq_funcs(adev); 864 gmc_v8_0_set_irq_funcs(adev);
865 865
866 if (adev->flags & AMD_IS_APU) {
867 adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
868 } else {
869 u32 tmp = RREG32(mmMC_SEQ_MISC0);
870 tmp &= MC_SEQ_MISC0__MT__MASK;
871 adev->mc.vram_type = gmc_v8_0_convert_vram_type(tmp);
872 }
873
874 return 0; 866 return 0;
875} 867}
876 868
@@ -881,12 +873,27 @@ static int gmc_v8_0_late_init(void *handle)
881 return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0); 873 return amdgpu_irq_get(adev, &adev->mc.vm_fault, 0);
882} 874}
883 875
876#define mmMC_SEQ_MISC0_FIJI 0xA71
877
884static int gmc_v8_0_sw_init(void *handle) 878static int gmc_v8_0_sw_init(void *handle)
885{ 879{
886 int r; 880 int r;
887 int dma_bits; 881 int dma_bits;
888 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 882 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
889 883
884 if (adev->flags & AMD_IS_APU) {
885 adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
886 } else {
887 u32 tmp;
888
889 if (adev->asic_type == CHIP_FIJI)
890 tmp = RREG32(mmMC_SEQ_MISC0_FIJI);
891 else
892 tmp = RREG32(mmMC_SEQ_MISC0);
893 tmp &= MC_SEQ_MISC0__MT__MASK;
894 adev->mc.vram_type = gmc_v8_0_convert_vram_type(tmp);
895 }
896
890 r = amdgpu_irq_add_id(adev, 146, &adev->mc.vm_fault); 897 r = amdgpu_irq_add_id(adev, 146, &adev->mc.vm_fault);
891 if (r) 898 if (r)
892 return r; 899 return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
index c606ccb38d8b..cb463753115b 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
@@ -224,11 +224,11 @@ static int uvd_v4_2_suspend(void *handle)
224 int r; 224 int r;
225 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 225 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
226 226
227 r = amdgpu_uvd_suspend(adev); 227 r = uvd_v4_2_hw_fini(adev);
228 if (r) 228 if (r)
229 return r; 229 return r;
230 230
231 r = uvd_v4_2_hw_fini(adev); 231 r = amdgpu_uvd_suspend(adev);
232 if (r) 232 if (r)
233 return r; 233 return r;
234 234
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
index e3c852d9d79a..16476d80f475 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
@@ -220,11 +220,11 @@ static int uvd_v5_0_suspend(void *handle)
220 int r; 220 int r;
221 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 221 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
222 222
223 r = amdgpu_uvd_suspend(adev); 223 r = uvd_v5_0_hw_fini(adev);
224 if (r) 224 if (r)
225 return r; 225 return r;
226 226
227 r = uvd_v5_0_hw_fini(adev); 227 r = amdgpu_uvd_suspend(adev);
228 if (r) 228 if (r)
229 return r; 229 return r;
230 230
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
index 3375e614ac67..d49379145ef2 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
@@ -214,15 +214,16 @@ static int uvd_v6_0_suspend(void *handle)
214 int r; 214 int r;
215 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 215 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
216 216
217 r = uvd_v6_0_hw_fini(adev);
218 if (r)
219 return r;
220
217 /* Skip this for APU for now */ 221 /* Skip this for APU for now */
218 if (!(adev->flags & AMD_IS_APU)) { 222 if (!(adev->flags & AMD_IS_APU)) {
219 r = amdgpu_uvd_suspend(adev); 223 r = amdgpu_uvd_suspend(adev);
220 if (r) 224 if (r)
221 return r; 225 return r;
222 } 226 }
223 r = uvd_v6_0_hw_fini(adev);
224 if (r)
225 return r;
226 227
227 return r; 228 return r;
228} 229}
diff --git a/drivers/gpu/drm/amd/include/cgs_common.h b/drivers/gpu/drm/amd/include/cgs_common.h
index aec38fc3834f..ab84d4947247 100644
--- a/drivers/gpu/drm/amd/include/cgs_common.h
+++ b/drivers/gpu/drm/amd/include/cgs_common.h
@@ -589,6 +589,8 @@ typedef int(*cgs_get_active_displays_info)(
589 void *cgs_device, 589 void *cgs_device,
590 struct cgs_display_info *info); 590 struct cgs_display_info *info);
591 591
592typedef int (*cgs_notify_dpm_enabled)(void *cgs_device, bool enabled);
593
592typedef int (*cgs_call_acpi_method)(void *cgs_device, 594typedef int (*cgs_call_acpi_method)(void *cgs_device,
593 uint32_t acpi_method, 595 uint32_t acpi_method,
594 uint32_t acpi_function, 596 uint32_t acpi_function,
@@ -644,6 +646,8 @@ struct cgs_ops {
644 cgs_set_clockgating_state set_clockgating_state; 646 cgs_set_clockgating_state set_clockgating_state;
645 /* display manager */ 647 /* display manager */
646 cgs_get_active_displays_info get_active_displays_info; 648 cgs_get_active_displays_info get_active_displays_info;
649 /* notify dpm enabled */
650 cgs_notify_dpm_enabled notify_dpm_enabled;
647 /* ACPI */ 651 /* ACPI */
648 cgs_call_acpi_method call_acpi_method; 652 cgs_call_acpi_method call_acpi_method;
649 /* get system info */ 653 /* get system info */
@@ -734,8 +738,12 @@ struct cgs_device
734 CGS_CALL(set_powergating_state, dev, block_type, state) 738 CGS_CALL(set_powergating_state, dev, block_type, state)
735#define cgs_set_clockgating_state(dev, block_type, state) \ 739#define cgs_set_clockgating_state(dev, block_type, state) \
736 CGS_CALL(set_clockgating_state, dev, block_type, state) 740 CGS_CALL(set_clockgating_state, dev, block_type, state)
741#define cgs_notify_dpm_enabled(dev, enabled) \
742 CGS_CALL(notify_dpm_enabled, dev, enabled)
743
737#define cgs_get_active_displays_info(dev, info) \ 744#define cgs_get_active_displays_info(dev, info) \
738 CGS_CALL(get_active_displays_info, dev, info) 745 CGS_CALL(get_active_displays_info, dev, info)
746
739#define cgs_call_acpi_method(dev, acpi_method, acpi_function, pintput, poutput, output_count, input_size, output_size) \ 747#define cgs_call_acpi_method(dev, acpi_method, acpi_function, pintput, poutput, output_count, input_size, output_size) \
740 CGS_CALL(call_acpi_method, dev, acpi_method, acpi_function, pintput, poutput, output_count, input_size, output_size) 748 CGS_CALL(call_acpi_method, dev, acpi_method, acpi_function, pintput, poutput, output_count, input_size, output_size)
741#define cgs_query_system_info(dev, sys_info) \ 749#define cgs_query_system_info(dev, sys_info) \
diff --git a/drivers/gpu/drm/amd/powerplay/eventmgr/eventactionchains.c b/drivers/gpu/drm/amd/powerplay/eventmgr/eventactionchains.c
index 6b52c78cb404..56856a2864d1 100644
--- a/drivers/gpu/drm/amd/powerplay/eventmgr/eventactionchains.c
+++ b/drivers/gpu/drm/amd/powerplay/eventmgr/eventactionchains.c
@@ -137,14 +137,14 @@ static const pem_event_action *resume_event[] = {
137 reset_display_configCounter_tasks, 137 reset_display_configCounter_tasks,
138 update_dal_configuration_tasks, 138 update_dal_configuration_tasks,
139 vari_bright_resume_tasks, 139 vari_bright_resume_tasks,
140 block_adjust_power_state_tasks,
141 setup_asic_tasks, 140 setup_asic_tasks,
142 enable_stutter_mode_tasks, /*must do this in boot state and before SMC is started */ 141 enable_stutter_mode_tasks, /*must do this in boot state and before SMC is started */
143 enable_dynamic_state_management_tasks, 142 enable_dynamic_state_management_tasks,
144 enable_clock_power_gatings_tasks, 143 enable_clock_power_gatings_tasks,
145 enable_disable_bapm_tasks, 144 enable_disable_bapm_tasks,
146 initialize_thermal_controller_tasks, 145 initialize_thermal_controller_tasks,
147 reset_boot_state_tasks, 146 get_2d_performance_state_tasks,
147 set_performance_state_tasks,
148 adjust_power_state_tasks, 148 adjust_power_state_tasks,
149 enable_disable_fps_tasks, 149 enable_disable_fps_tasks,
150 notify_hw_power_source_tasks, 150 notify_hw_power_source_tasks,
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
index 51dedf84623c..89f31bc5b68b 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
@@ -2389,6 +2389,7 @@ static int fiji_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
2389 2389
2390 for(count = 0; count < table->VceLevelCount; count++) { 2390 for(count = 0; count < table->VceLevelCount; count++) {
2391 table->VceLevel[count].Frequency = mm_table->entries[count].eclk; 2391 table->VceLevel[count].Frequency = mm_table->entries[count].eclk;
2392 table->VceLevel[count].MinVoltage = 0;
2392 table->VceLevel[count].MinVoltage |= 2393 table->VceLevel[count].MinVoltage |=
2393 (mm_table->entries[count].vddc * VOLTAGE_SCALE) << VDDC_SHIFT; 2394 (mm_table->entries[count].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
2394 table->VceLevel[count].MinVoltage |= 2395 table->VceLevel[count].MinVoltage |=
@@ -2465,6 +2466,7 @@ static int fiji_populate_smc_samu_level(struct pp_hwmgr *hwmgr,
2465 2466
2466 for (count = 0; count < table->SamuLevelCount; count++) { 2467 for (count = 0; count < table->SamuLevelCount; count++) {
2467 /* not sure whether we need evclk or not */ 2468 /* not sure whether we need evclk or not */
2469 table->SamuLevel[count].MinVoltage = 0;
2468 table->SamuLevel[count].Frequency = mm_table->entries[count].samclock; 2470 table->SamuLevel[count].Frequency = mm_table->entries[count].samclock;
2469 table->SamuLevel[count].MinVoltage |= (mm_table->entries[count].vddc * 2471 table->SamuLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
2470 VOLTAGE_SCALE) << VDDC_SHIFT; 2472 VOLTAGE_SCALE) << VDDC_SHIFT;
@@ -2562,6 +2564,7 @@ static int fiji_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
2562 table->UvdBootLevel = 0; 2564 table->UvdBootLevel = 0;
2563 2565
2564 for (count = 0; count < table->UvdLevelCount; count++) { 2566 for (count = 0; count < table->UvdLevelCount; count++) {
2567 table->UvdLevel[count].MinVoltage = 0;
2565 table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk; 2568 table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk;
2566 table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk; 2569 table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk;
2567 table->UvdLevel[count].MinVoltage |= (mm_table->entries[count].vddc * 2570 table->UvdLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
@@ -2900,6 +2903,8 @@ static int fiji_init_smc_table(struct pp_hwmgr *hwmgr)
2900 if(FIJI_VOLTAGE_CONTROL_NONE != data->voltage_control) 2903 if(FIJI_VOLTAGE_CONTROL_NONE != data->voltage_control)
2901 fiji_populate_smc_voltage_tables(hwmgr, table); 2904 fiji_populate_smc_voltage_tables(hwmgr, table);
2902 2905
2906 table->SystemFlags = 0;
2907
2903 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 2908 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2904 PHM_PlatformCaps_AutomaticDCTransition)) 2909 PHM_PlatformCaps_AutomaticDCTransition))
2905 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC; 2910 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
@@ -2997,6 +3002,7 @@ static int fiji_init_smc_table(struct pp_hwmgr *hwmgr)
2997 table->MemoryThermThrottleEnable = 1; 3002 table->MemoryThermThrottleEnable = 1;
2998 table->PCIeBootLinkLevel = 0; /* 0:Gen1 1:Gen2 2:Gen3*/ 3003 table->PCIeBootLinkLevel = 0; /* 0:Gen1 1:Gen2 2:Gen3*/
2999 table->PCIeGenInterval = 1; 3004 table->PCIeGenInterval = 1;
3005 table->VRConfig = 0;
3000 3006
3001 result = fiji_populate_vr_config(hwmgr, table); 3007 result = fiji_populate_vr_config(hwmgr, table);
3002 PP_ASSERT_WITH_CODE(0 == result, 3008 PP_ASSERT_WITH_CODE(0 == result,
@@ -5195,6 +5201,67 @@ static int fiji_print_clock_levels(struct pp_hwmgr *hwmgr,
5195 return size; 5201 return size;
5196} 5202}
5197 5203
5204static inline bool fiji_are_power_levels_equal(const struct fiji_performance_level *pl1,
5205 const struct fiji_performance_level *pl2)
5206{
5207 return ((pl1->memory_clock == pl2->memory_clock) &&
5208 (pl1->engine_clock == pl2->engine_clock) &&
5209 (pl1->pcie_gen == pl2->pcie_gen) &&
5210 (pl1->pcie_lane == pl2->pcie_lane));
5211}
5212
5213int fiji_check_states_equal(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *pstate1, const struct pp_hw_power_state *pstate2, bool *equal)
5214{
5215 const struct fiji_power_state *psa = cast_const_phw_fiji_power_state(pstate1);
5216 const struct fiji_power_state *psb = cast_const_phw_fiji_power_state(pstate2);
5217 int i;
5218
5219 if (equal == NULL || psa == NULL || psb == NULL)
5220 return -EINVAL;
5221
5222 /* If the two states don't even have the same number of performance levels they cannot be the same state. */
5223 if (psa->performance_level_count != psb->performance_level_count) {
5224 *equal = false;
5225 return 0;
5226 }
5227
5228 for (i = 0; i < psa->performance_level_count; i++) {
5229 if (!fiji_are_power_levels_equal(&(psa->performance_levels[i]), &(psb->performance_levels[i]))) {
5230 /* If we have found even one performance level pair that is different the states are different. */
5231 *equal = false;
5232 return 0;
5233 }
5234 }
5235
5236 /* If all performance levels are the same try to use the UVD clocks to break the tie.*/
5237 *equal = ((psa->uvd_clks.vclk == psb->uvd_clks.vclk) && (psa->uvd_clks.dclk == psb->uvd_clks.dclk));
5238 *equal &= ((psa->vce_clks.evclk == psb->vce_clks.evclk) && (psa->vce_clks.ecclk == psb->vce_clks.ecclk));
5239 *equal &= (psa->sclk_threshold == psb->sclk_threshold);
5240 *equal &= (psa->acp_clk == psb->acp_clk);
5241
5242 return 0;
5243}
5244
5245bool fiji_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
5246{
5247 struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
5248 bool is_update_required = false;
5249 struct cgs_display_info info = {0,0,NULL};
5250
5251 cgs_get_active_displays_info(hwmgr->device, &info);
5252
5253 if (data->display_timing.num_existing_displays != info.display_count)
5254 is_update_required = true;
5255/* TO DO NEED TO GET DEEP SLEEP CLOCK FROM DAL
5256 if (phm_cap_enabled(hwmgr->hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
5257 cgs_get_min_clock_settings(hwmgr->device, &min_clocks);
5258 if(min_clocks.engineClockInSR != data->display_timing.minClockInSR)
5259 is_update_required = true;
5260*/
5261 return is_update_required;
5262}
5263
5264
5198static const struct pp_hwmgr_func fiji_hwmgr_funcs = { 5265static const struct pp_hwmgr_func fiji_hwmgr_funcs = {
5199 .backend_init = &fiji_hwmgr_backend_init, 5266 .backend_init = &fiji_hwmgr_backend_init,
5200 .backend_fini = &tonga_hwmgr_backend_fini, 5267 .backend_fini = &tonga_hwmgr_backend_fini,
@@ -5230,6 +5297,8 @@ static const struct pp_hwmgr_func fiji_hwmgr_funcs = {
5230 .register_internal_thermal_interrupt = fiji_register_internal_thermal_interrupt, 5297 .register_internal_thermal_interrupt = fiji_register_internal_thermal_interrupt,
5231 .set_fan_control_mode = fiji_set_fan_control_mode, 5298 .set_fan_control_mode = fiji_set_fan_control_mode,
5232 .get_fan_control_mode = fiji_get_fan_control_mode, 5299 .get_fan_control_mode = fiji_get_fan_control_mode,
5300 .check_states_equal = fiji_check_states_equal,
5301 .check_smc_update_required_for_display_configuration = fiji_check_smc_update_required_for_display_configuration,
5233 .get_pp_table = fiji_get_pp_table, 5302 .get_pp_table = fiji_get_pp_table,
5234 .set_pp_table = fiji_set_pp_table, 5303 .set_pp_table = fiji_set_pp_table,
5235 .force_clock_level = fiji_force_clock_level, 5304 .force_clock_level = fiji_force_clock_level,
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
index be31bed2538a..fa208ada6892 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
@@ -58,6 +58,9 @@ void phm_init_dynamic_caps(struct pp_hwmgr *hwmgr)
58 58
59 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_VpuRecoveryInProgress); 59 phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_VpuRecoveryInProgress);
60 60
61 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_UVDDPM);
62 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_VCEDPM);
63
61 if (acpi_atcs_functions_supported(hwmgr->device, ATCS_FUNCTION_PCIE_PERFORMANCE_REQUEST) && 64 if (acpi_atcs_functions_supported(hwmgr->device, ATCS_FUNCTION_PCIE_PERFORMANCE_REQUEST) &&
62 acpi_atcs_functions_supported(hwmgr->device, ATCS_FUNCTION_PCIE_DEVICE_READY_NOTIFICATION)) 65 acpi_atcs_functions_supported(hwmgr->device, ATCS_FUNCTION_PCIE_DEVICE_READY_NOTIFICATION))
63 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest); 66 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest);
@@ -130,18 +133,25 @@ int phm_set_power_state(struct pp_hwmgr *hwmgr,
130 133
131int phm_enable_dynamic_state_management(struct pp_hwmgr *hwmgr) 134int phm_enable_dynamic_state_management(struct pp_hwmgr *hwmgr)
132{ 135{
136 int ret = 1;
137 bool enabled;
133 PHM_FUNC_CHECK(hwmgr); 138 PHM_FUNC_CHECK(hwmgr);
134 139
135 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 140 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
136 PHM_PlatformCaps_TablelessHardwareInterface)) { 141 PHM_PlatformCaps_TablelessHardwareInterface)) {
137 if (NULL != hwmgr->hwmgr_func->dynamic_state_management_enable) 142 if (NULL != hwmgr->hwmgr_func->dynamic_state_management_enable)
138 return hwmgr->hwmgr_func->dynamic_state_management_enable(hwmgr); 143 ret = hwmgr->hwmgr_func->dynamic_state_management_enable(hwmgr);
139 } else { 144 } else {
140 return phm_dispatch_table(hwmgr, 145 ret = phm_dispatch_table(hwmgr,
141 &(hwmgr->enable_dynamic_state_management), 146 &(hwmgr->enable_dynamic_state_management),
142 NULL, NULL); 147 NULL, NULL);
143 } 148 }
144 return 0; 149
150 enabled = ret == 0 ? true : false;
151
152 cgs_notify_dpm_enabled(hwmgr->device, enabled);
153
154 return ret;
145} 155}
146 156
147int phm_force_dpm_levels(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level) 157int phm_force_dpm_levels(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level)
diff --git a/drivers/gpu/drm/arm/hdlcd_drv.c b/drivers/gpu/drm/arm/hdlcd_drv.c
index 56b829f97699..3ac1ae4d8caf 100644
--- a/drivers/gpu/drm/arm/hdlcd_drv.c
+++ b/drivers/gpu/drm/arm/hdlcd_drv.c
@@ -57,14 +57,13 @@ static int hdlcd_load(struct drm_device *drm, unsigned long flags)
57 DRM_ERROR("failed to map control registers area\n"); 57 DRM_ERROR("failed to map control registers area\n");
58 ret = PTR_ERR(hdlcd->mmio); 58 ret = PTR_ERR(hdlcd->mmio);
59 hdlcd->mmio = NULL; 59 hdlcd->mmio = NULL;
60 goto fail; 60 return ret;
61 } 61 }
62 62
63 version = hdlcd_read(hdlcd, HDLCD_REG_VERSION); 63 version = hdlcd_read(hdlcd, HDLCD_REG_VERSION);
64 if ((version & HDLCD_PRODUCT_MASK) != HDLCD_PRODUCT_ID) { 64 if ((version & HDLCD_PRODUCT_MASK) != HDLCD_PRODUCT_ID) {
65 DRM_ERROR("unknown product id: 0x%x\n", version); 65 DRM_ERROR("unknown product id: 0x%x\n", version);
66 ret = -EINVAL; 66 return -EINVAL;
67 goto fail;
68 } 67 }
69 DRM_INFO("found ARM HDLCD version r%dp%d\n", 68 DRM_INFO("found ARM HDLCD version r%dp%d\n",
70 (version & HDLCD_VERSION_MAJOR_MASK) >> 8, 69 (version & HDLCD_VERSION_MAJOR_MASK) >> 8,
@@ -73,7 +72,7 @@ static int hdlcd_load(struct drm_device *drm, unsigned long flags)
73 /* Get the optional framebuffer memory resource */ 72 /* Get the optional framebuffer memory resource */
74 ret = of_reserved_mem_device_init(drm->dev); 73 ret = of_reserved_mem_device_init(drm->dev);
75 if (ret && ret != -ENODEV) 74 if (ret && ret != -ENODEV)
76 goto fail; 75 return ret;
77 76
78 ret = dma_set_mask_and_coherent(drm->dev, DMA_BIT_MASK(32)); 77 ret = dma_set_mask_and_coherent(drm->dev, DMA_BIT_MASK(32));
79 if (ret) 78 if (ret)
@@ -101,8 +100,6 @@ irq_fail:
101 drm_crtc_cleanup(&hdlcd->crtc); 100 drm_crtc_cleanup(&hdlcd->crtc);
102setup_fail: 101setup_fail:
103 of_reserved_mem_device_release(drm->dev); 102 of_reserved_mem_device_release(drm->dev);
104fail:
105 devm_clk_put(drm->dev, hdlcd->clk);
106 103
107 return ret; 104 return ret;
108} 105}
@@ -412,7 +409,6 @@ err_unload:
412 pm_runtime_put_sync(drm->dev); 409 pm_runtime_put_sync(drm->dev);
413 pm_runtime_disable(drm->dev); 410 pm_runtime_disable(drm->dev);
414 of_reserved_mem_device_release(drm->dev); 411 of_reserved_mem_device_release(drm->dev);
415 devm_clk_put(dev, hdlcd->clk);
416err_free: 412err_free:
417 drm_dev_unref(drm); 413 drm_dev_unref(drm);
418 414
@@ -436,10 +432,6 @@ static void hdlcd_drm_unbind(struct device *dev)
436 pm_runtime_put_sync(drm->dev); 432 pm_runtime_put_sync(drm->dev);
437 pm_runtime_disable(drm->dev); 433 pm_runtime_disable(drm->dev);
438 of_reserved_mem_device_release(drm->dev); 434 of_reserved_mem_device_release(drm->dev);
439 if (!IS_ERR(hdlcd->clk)) {
440 devm_clk_put(drm->dev, hdlcd->clk);
441 hdlcd->clk = NULL;
442 }
443 drm_mode_config_cleanup(drm); 435 drm_mode_config_cleanup(drm);
444 drm_dev_unregister(drm); 436 drm_dev_unregister(drm);
445 drm_dev_unref(drm); 437 drm_dev_unref(drm);
diff --git a/drivers/gpu/drm/imx/dw_hdmi-imx.c b/drivers/gpu/drm/imx/dw_hdmi-imx.c
index 2a95d10e9d92..a24631fdf4ad 100644
--- a/drivers/gpu/drm/imx/dw_hdmi-imx.c
+++ b/drivers/gpu/drm/imx/dw_hdmi-imx.c
@@ -225,8 +225,6 @@ static int dw_hdmi_imx_bind(struct device *dev, struct device *master,
225 if (!iores) 225 if (!iores)
226 return -ENXIO; 226 return -ENXIO;
227 227
228 platform_set_drvdata(pdev, hdmi);
229
230 encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node); 228 encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
231 /* 229 /*
232 * If we failed to find the CRTC(s) which this encoder is 230 * If we failed to find the CRTC(s) which this encoder is
@@ -245,7 +243,16 @@ static int dw_hdmi_imx_bind(struct device *dev, struct device *master,
245 drm_encoder_init(drm, encoder, &dw_hdmi_imx_encoder_funcs, 243 drm_encoder_init(drm, encoder, &dw_hdmi_imx_encoder_funcs,
246 DRM_MODE_ENCODER_TMDS, NULL); 244 DRM_MODE_ENCODER_TMDS, NULL);
247 245
248 return dw_hdmi_bind(dev, master, data, encoder, iores, irq, plat_data); 246 ret = dw_hdmi_bind(dev, master, data, encoder, iores, irq, plat_data);
247
248 /*
249 * If dw_hdmi_bind() fails we'll never call dw_hdmi_unbind(),
250 * which would have called the encoder cleanup. Do it manually.
251 */
252 if (ret)
253 drm_encoder_cleanup(encoder);
254
255 return ret;
249} 256}
250 257
251static void dw_hdmi_imx_unbind(struct device *dev, struct device *master, 258static void dw_hdmi_imx_unbind(struct device *dev, struct device *master,
diff --git a/drivers/gpu/drm/imx/imx-drm-core.c b/drivers/gpu/drm/imx/imx-drm-core.c
index 9876e0f0c3e1..e26dcdec2aba 100644
--- a/drivers/gpu/drm/imx/imx-drm-core.c
+++ b/drivers/gpu/drm/imx/imx-drm-core.c
@@ -326,7 +326,6 @@ int imx_drm_add_crtc(struct drm_device *drm, struct drm_crtc *crtc,
326{ 326{
327 struct imx_drm_device *imxdrm = drm->dev_private; 327 struct imx_drm_device *imxdrm = drm->dev_private;
328 struct imx_drm_crtc *imx_drm_crtc; 328 struct imx_drm_crtc *imx_drm_crtc;
329 int ret;
330 329
331 /* 330 /*
332 * The vblank arrays are dimensioned by MAX_CRTC - we can't 331 * The vblank arrays are dimensioned by MAX_CRTC - we can't
@@ -351,10 +350,6 @@ int imx_drm_add_crtc(struct drm_device *drm, struct drm_crtc *crtc,
351 350
352 *new_crtc = imx_drm_crtc; 351 *new_crtc = imx_drm_crtc;
353 352
354 ret = drm_mode_crtc_set_gamma_size(imx_drm_crtc->crtc, 256);
355 if (ret)
356 goto err_register;
357
358 drm_crtc_helper_add(crtc, 353 drm_crtc_helper_add(crtc,
359 imx_drm_crtc->imx_drm_helper_funcs.crtc_helper_funcs); 354 imx_drm_crtc->imx_drm_helper_funcs.crtc_helper_funcs);
360 355
@@ -362,11 +357,6 @@ int imx_drm_add_crtc(struct drm_device *drm, struct drm_crtc *crtc,
362 imx_drm_crtc->imx_drm_helper_funcs.crtc_funcs, NULL); 357 imx_drm_crtc->imx_drm_helper_funcs.crtc_funcs, NULL);
363 358
364 return 0; 359 return 0;
365
366err_register:
367 imxdrm->crtc[--imxdrm->pipes] = NULL;
368 kfree(imx_drm_crtc);
369 return ret;
370} 360}
371EXPORT_SYMBOL_GPL(imx_drm_add_crtc); 361EXPORT_SYMBOL_GPL(imx_drm_add_crtc);
372 362
diff --git a/drivers/gpu/drm/imx/ipuv3-plane.c b/drivers/gpu/drm/imx/ipuv3-plane.c
index 588827844f30..681ec6eb77d9 100644
--- a/drivers/gpu/drm/imx/ipuv3-plane.c
+++ b/drivers/gpu/drm/imx/ipuv3-plane.c
@@ -72,22 +72,101 @@ static inline int calc_bandwidth(int width, int height, unsigned int vref)
72int ipu_plane_set_base(struct ipu_plane *ipu_plane, struct drm_framebuffer *fb, 72int ipu_plane_set_base(struct ipu_plane *ipu_plane, struct drm_framebuffer *fb,
73 int x, int y) 73 int x, int y)
74{ 74{
75 struct drm_gem_cma_object *cma_obj; 75 struct drm_gem_cma_object *cma_obj[3];
76 unsigned long eba; 76 unsigned long eba, ubo, vbo;
77 int active; 77 int active, i;
78 78
79 cma_obj = drm_fb_cma_get_gem_obj(fb, 0); 79 for (i = 0; i < drm_format_num_planes(fb->pixel_format); i++) {
80 if (!cma_obj) { 80 cma_obj[i] = drm_fb_cma_get_gem_obj(fb, i);
81 DRM_DEBUG_KMS("entry is null.\n"); 81 if (!cma_obj[i]) {
82 return -EFAULT; 82 DRM_DEBUG_KMS("plane %d entry is null.\n", i);
83 return -EFAULT;
84 }
83 } 85 }
84 86
85 dev_dbg(ipu_plane->base.dev->dev, "phys = %pad, x = %d, y = %d", 87 eba = cma_obj[0]->paddr + fb->offsets[0] +
86 &cma_obj->paddr, x, y);
87
88 eba = cma_obj->paddr + fb->offsets[0] +
89 fb->pitches[0] * y + (fb->bits_per_pixel >> 3) * x; 88 fb->pitches[0] * y + (fb->bits_per_pixel >> 3) * x;
90 89
90 if (eba & 0x7) {
91 DRM_DEBUG_KMS("base address must be a multiple of 8.\n");
92 return -EINVAL;
93 }
94
95 if (fb->pitches[0] < 1 || fb->pitches[0] > 16384) {
96 DRM_DEBUG_KMS("pitches out of range.\n");
97 return -EINVAL;
98 }
99
100 if (ipu_plane->enabled && fb->pitches[0] != ipu_plane->stride[0]) {
101 DRM_DEBUG_KMS("pitches must not change while plane is enabled.\n");
102 return -EINVAL;
103 }
104
105 ipu_plane->stride[0] = fb->pitches[0];
106
107 switch (fb->pixel_format) {
108 case DRM_FORMAT_YUV420:
109 case DRM_FORMAT_YVU420:
110 /*
111 * Multiplanar formats have to meet the following restrictions:
112 * - The (up to) three plane addresses are EBA, EBA+UBO, EBA+VBO
113 * - EBA, UBO and VBO are a multiple of 8
114 * - UBO and VBO are unsigned and not larger than 0xfffff8
115 * - Only EBA may be changed while scanout is active
116 * - The strides of U and V planes must be identical.
117 */
118 ubo = cma_obj[1]->paddr + fb->offsets[1] +
119 fb->pitches[1] * y / 2 + x / 2 - eba;
120 vbo = cma_obj[2]->paddr + fb->offsets[2] +
121 fb->pitches[2] * y / 2 + x / 2 - eba;
122
123 if ((ubo & 0x7) || (vbo & 0x7)) {
124 DRM_DEBUG_KMS("U/V buffer offsets must be a multiple of 8.\n");
125 return -EINVAL;
126 }
127
128 if ((ubo > 0xfffff8) || (vbo > 0xfffff8)) {
129 DRM_DEBUG_KMS("U/V buffer offsets must be positive and not larger than 0xfffff8.\n");
130 return -EINVAL;
131 }
132
133 if (ipu_plane->enabled && ((ipu_plane->u_offset != ubo) ||
134 (ipu_plane->v_offset != vbo))) {
135 DRM_DEBUG_KMS("U/V buffer offsets must not change while plane is enabled.\n");
136 return -EINVAL;
137 }
138
139 if (fb->pitches[1] != fb->pitches[2]) {
140 DRM_DEBUG_KMS("U/V pitches must be identical.\n");
141 return -EINVAL;
142 }
143
144 if (fb->pitches[1] < 1 || fb->pitches[1] > 16384) {
145 DRM_DEBUG_KMS("U/V pitches out of range.\n");
146 return -EINVAL;
147 }
148
149 if (ipu_plane->enabled &&
150 (ipu_plane->stride[1] != fb->pitches[1])) {
151 DRM_DEBUG_KMS("U/V pitches must not change while plane is enabled.\n");
152 return -EINVAL;
153 }
154
155 ipu_plane->u_offset = ubo;
156 ipu_plane->v_offset = vbo;
157 ipu_plane->stride[1] = fb->pitches[1];
158
159 dev_dbg(ipu_plane->base.dev->dev,
160 "phys = %pad %pad %pad, x = %d, y = %d",
161 &cma_obj[0]->paddr, &cma_obj[1]->paddr,
162 &cma_obj[2]->paddr, x, y);
163 break;
164 default:
165 dev_dbg(ipu_plane->base.dev->dev, "phys = %pad, x = %d, y = %d",
166 &cma_obj[0]->paddr, x, y);
167 break;
168 }
169
91 if (ipu_plane->enabled) { 170 if (ipu_plane->enabled) {
92 active = ipu_idmac_get_current_buffer(ipu_plane->ipu_ch); 171 active = ipu_idmac_get_current_buffer(ipu_plane->ipu_ch);
93 ipu_cpmem_set_buffer(ipu_plane->ipu_ch, !active, eba); 172 ipu_cpmem_set_buffer(ipu_plane->ipu_ch, !active, eba);
@@ -201,12 +280,6 @@ int ipu_plane_mode_set(struct ipu_plane *ipu_plane, struct drm_crtc *crtc,
201 } 280 }
202 } 281 }
203 282
204 ret = ipu_dmfc_init_channel(ipu_plane->dmfc, crtc_w);
205 if (ret) {
206 dev_err(dev, "initializing dmfc channel failed with %d\n", ret);
207 return ret;
208 }
209
210 ret = ipu_dmfc_alloc_bandwidth(ipu_plane->dmfc, 283 ret = ipu_dmfc_alloc_bandwidth(ipu_plane->dmfc,
211 calc_bandwidth(crtc_w, crtc_h, 284 calc_bandwidth(crtc_w, crtc_h,
212 calc_vref(mode)), 64); 285 calc_vref(mode)), 64);
@@ -215,6 +288,8 @@ int ipu_plane_mode_set(struct ipu_plane *ipu_plane, struct drm_crtc *crtc,
215 return ret; 288 return ret;
216 } 289 }
217 290
291 ipu_dmfc_config_wait4eot(ipu_plane->dmfc, crtc_w);
292
218 ipu_cpmem_zero(ipu_plane->ipu_ch); 293 ipu_cpmem_zero(ipu_plane->ipu_ch);
219 ipu_cpmem_set_resolution(ipu_plane->ipu_ch, src_w, src_h); 294 ipu_cpmem_set_resolution(ipu_plane->ipu_ch, src_w, src_h);
220 ret = ipu_cpmem_set_fmt(ipu_plane->ipu_ch, fb->pixel_format); 295 ret = ipu_cpmem_set_fmt(ipu_plane->ipu_ch, fb->pixel_format);
@@ -233,6 +308,18 @@ int ipu_plane_mode_set(struct ipu_plane *ipu_plane, struct drm_crtc *crtc,
233 if (interlaced) 308 if (interlaced)
234 ipu_cpmem_interlaced_scan(ipu_plane->ipu_ch, fb->pitches[0]); 309 ipu_cpmem_interlaced_scan(ipu_plane->ipu_ch, fb->pitches[0]);
235 310
311 if (fb->pixel_format == DRM_FORMAT_YUV420) {
312 ipu_cpmem_set_yuv_planar_full(ipu_plane->ipu_ch,
313 ipu_plane->stride[1],
314 ipu_plane->u_offset,
315 ipu_plane->v_offset);
316 } else if (fb->pixel_format == DRM_FORMAT_YVU420) {
317 ipu_cpmem_set_yuv_planar_full(ipu_plane->ipu_ch,
318 ipu_plane->stride[1],
319 ipu_plane->v_offset,
320 ipu_plane->u_offset);
321 }
322
236 ipu_plane->w = src_w; 323 ipu_plane->w = src_w;
237 ipu_plane->h = src_h; 324 ipu_plane->h = src_h;
238 325
diff --git a/drivers/gpu/drm/imx/ipuv3-plane.h b/drivers/gpu/drm/imx/ipuv3-plane.h
index 3a443b413c60..4448fd4ad4eb 100644
--- a/drivers/gpu/drm/imx/ipuv3-plane.h
+++ b/drivers/gpu/drm/imx/ipuv3-plane.h
@@ -29,6 +29,10 @@ struct ipu_plane {
29 int w; 29 int w;
30 int h; 30 int h;
31 31
32 unsigned int u_offset;
33 unsigned int v_offset;
34 unsigned int stride[2];
35
32 bool enabled; 36 bool enabled;
33}; 37};
34 38
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/tegra.h b/drivers/gpu/drm/nouveau/include/nvkm/core/tegra.h
index 16641cec18a2..b5370cb56e3c 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/core/tegra.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/core/tegra.h
@@ -11,6 +11,7 @@ struct nvkm_device_tegra {
11 11
12 struct reset_control *rst; 12 struct reset_control *rst;
13 struct clk *clk; 13 struct clk *clk;
14 struct clk *clk_ref;
14 struct clk *clk_pwr; 15 struct clk *clk_pwr;
15 16
16 struct regulator *vdd; 17 struct regulator *vdd;
@@ -36,6 +37,10 @@ struct nvkm_device_tegra_func {
36 * bypassed). A value of 0 means an IOMMU is never used. 37 * bypassed). A value of 0 means an IOMMU is never used.
37 */ 38 */
38 u8 iommu_bit; 39 u8 iommu_bit;
40 /*
41 * Whether the chip requires a reference clock
42 */
43 bool require_ref_clk;
39}; 44};
40 45
41int nvkm_device_tegra_new(const struct nvkm_device_tegra_func *, 46int nvkm_device_tegra_new(const struct nvkm_device_tegra_func *,
diff --git a/drivers/gpu/drm/nouveau/nouveau_platform.c b/drivers/gpu/drm/nouveau/nouveau_platform.c
index 2dfe58af12e4..4c4cc2260257 100644
--- a/drivers/gpu/drm/nouveau/nouveau_platform.c
+++ b/drivers/gpu/drm/nouveau/nouveau_platform.c
@@ -55,6 +55,11 @@ static const struct nvkm_device_tegra_func gk20a_platform_data = {
55 .iommu_bit = 34, 55 .iommu_bit = 34,
56}; 56};
57 57
58static const struct nvkm_device_tegra_func gm20b_platform_data = {
59 .iommu_bit = 34,
60 .require_ref_clk = true,
61};
62
58static const struct of_device_id nouveau_platform_match[] = { 63static const struct of_device_id nouveau_platform_match[] = {
59 { 64 {
60 .compatible = "nvidia,gk20a", 65 .compatible = "nvidia,gk20a",
@@ -62,7 +67,7 @@ static const struct of_device_id nouveau_platform_match[] = {
62 }, 67 },
63 { 68 {
64 .compatible = "nvidia,gm20b", 69 .compatible = "nvidia,gm20b",
65 .data = &gk20a_platform_data, 70 .data = &gm20b_platform_data,
66 }, 71 },
67 { } 72 { }
68}; 73};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c
index 9afa5f3e3c1c..ec12efb4689a 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c
@@ -35,6 +35,11 @@ nvkm_device_tegra_power_up(struct nvkm_device_tegra *tdev)
35 ret = clk_prepare_enable(tdev->clk); 35 ret = clk_prepare_enable(tdev->clk);
36 if (ret) 36 if (ret)
37 goto err_clk; 37 goto err_clk;
38 if (tdev->clk_ref) {
39 ret = clk_prepare_enable(tdev->clk_ref);
40 if (ret)
41 goto err_clk_ref;
42 }
38 ret = clk_prepare_enable(tdev->clk_pwr); 43 ret = clk_prepare_enable(tdev->clk_pwr);
39 if (ret) 44 if (ret)
40 goto err_clk_pwr; 45 goto err_clk_pwr;
@@ -57,6 +62,9 @@ nvkm_device_tegra_power_up(struct nvkm_device_tegra *tdev)
57err_clamp: 62err_clamp:
58 clk_disable_unprepare(tdev->clk_pwr); 63 clk_disable_unprepare(tdev->clk_pwr);
59err_clk_pwr: 64err_clk_pwr:
65 if (tdev->clk_ref)
66 clk_disable_unprepare(tdev->clk_ref);
67err_clk_ref:
60 clk_disable_unprepare(tdev->clk); 68 clk_disable_unprepare(tdev->clk);
61err_clk: 69err_clk:
62 regulator_disable(tdev->vdd); 70 regulator_disable(tdev->vdd);
@@ -71,6 +79,8 @@ nvkm_device_tegra_power_down(struct nvkm_device_tegra *tdev)
71 udelay(10); 79 udelay(10);
72 80
73 clk_disable_unprepare(tdev->clk_pwr); 81 clk_disable_unprepare(tdev->clk_pwr);
82 if (tdev->clk_ref)
83 clk_disable_unprepare(tdev->clk_ref);
74 clk_disable_unprepare(tdev->clk); 84 clk_disable_unprepare(tdev->clk);
75 udelay(10); 85 udelay(10);
76 86
@@ -274,6 +284,13 @@ nvkm_device_tegra_new(const struct nvkm_device_tegra_func *func,
274 goto free; 284 goto free;
275 } 285 }
276 286
287 if (func->require_ref_clk)
288 tdev->clk_ref = devm_clk_get(&pdev->dev, "ref");
289 if (IS_ERR(tdev->clk_ref)) {
290 ret = PTR_ERR(tdev->clk_ref);
291 goto free;
292 }
293
277 tdev->clk_pwr = devm_clk_get(&pdev->dev, "pwr"); 294 tdev->clk_pwr = devm_clk_get(&pdev->dev, "pwr");
278 if (IS_ERR(tdev->clk_pwr)) { 295 if (IS_ERR(tdev->clk_pwr)) {
279 ret = PTR_ERR(tdev->clk_pwr); 296 ret = PTR_ERR(tdev->clk_pwr);
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index cf61e0856f4a..b80b08f71cb4 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -275,13 +275,15 @@ void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
275 if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev)) 275 if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev))
276 atombios_enable_crtc_memreq(crtc, ATOM_ENABLE); 276 atombios_enable_crtc_memreq(crtc, ATOM_ENABLE);
277 atombios_blank_crtc(crtc, ATOM_DISABLE); 277 atombios_blank_crtc(crtc, ATOM_DISABLE);
278 drm_vblank_on(dev, radeon_crtc->crtc_id); 278 if (dev->num_crtcs > radeon_crtc->crtc_id)
279 drm_vblank_on(dev, radeon_crtc->crtc_id);
279 radeon_crtc_load_lut(crtc); 280 radeon_crtc_load_lut(crtc);
280 break; 281 break;
281 case DRM_MODE_DPMS_STANDBY: 282 case DRM_MODE_DPMS_STANDBY:
282 case DRM_MODE_DPMS_SUSPEND: 283 case DRM_MODE_DPMS_SUSPEND:
283 case DRM_MODE_DPMS_OFF: 284 case DRM_MODE_DPMS_OFF:
284 drm_vblank_off(dev, radeon_crtc->crtc_id); 285 if (dev->num_crtcs > radeon_crtc->crtc_id)
286 drm_vblank_off(dev, radeon_crtc->crtc_id);
285 if (radeon_crtc->enabled) 287 if (radeon_crtc->enabled)
286 atombios_blank_crtc(crtc, ATOM_ENABLE); 288 atombios_blank_crtc(crtc, ATOM_ENABLE);
287 if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev)) 289 if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev))
diff --git a/drivers/gpu/drm/radeon/radeon_irq_kms.c b/drivers/gpu/drm/radeon/radeon_irq_kms.c
index 979f3bf65f2c..1e9304d1c88f 100644
--- a/drivers/gpu/drm/radeon/radeon_irq_kms.c
+++ b/drivers/gpu/drm/radeon/radeon_irq_kms.c
@@ -291,6 +291,8 @@ int radeon_irq_kms_init(struct radeon_device *rdev)
291 if (r) { 291 if (r) {
292 return r; 292 return r;
293 } 293 }
294 rdev->ddev->vblank_disable_allowed = true;
295
294 /* enable msi */ 296 /* enable msi */
295 rdev->msi_enabled = 0; 297 rdev->msi_enabled = 0;
296 298
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
index 24152dfef199..478d4099b0d0 100644
--- a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
+++ b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
@@ -331,13 +331,15 @@ static void radeon_crtc_dpms(struct drm_crtc *crtc, int mode)
331 RADEON_CRTC_DISP_REQ_EN_B)); 331 RADEON_CRTC_DISP_REQ_EN_B));
332 WREG32_P(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl, ~(mask | crtc_ext_cntl)); 332 WREG32_P(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl, ~(mask | crtc_ext_cntl));
333 } 333 }
334 drm_vblank_on(dev, radeon_crtc->crtc_id); 334 if (dev->num_crtcs > radeon_crtc->crtc_id)
335 drm_vblank_on(dev, radeon_crtc->crtc_id);
335 radeon_crtc_load_lut(crtc); 336 radeon_crtc_load_lut(crtc);
336 break; 337 break;
337 case DRM_MODE_DPMS_STANDBY: 338 case DRM_MODE_DPMS_STANDBY:
338 case DRM_MODE_DPMS_SUSPEND: 339 case DRM_MODE_DPMS_SUSPEND:
339 case DRM_MODE_DPMS_OFF: 340 case DRM_MODE_DPMS_OFF:
340 drm_vblank_off(dev, radeon_crtc->crtc_id); 341 if (dev->num_crtcs > radeon_crtc->crtc_id)
342 drm_vblank_off(dev, radeon_crtc->crtc_id);
341 if (radeon_crtc->crtc_id) 343 if (radeon_crtc->crtc_id)
342 WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~(RADEON_CRTC2_EN | mask)); 344 WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~(RADEON_CRTC2_EN | mask));
343 else { 345 else {
diff --git a/drivers/gpu/ipu-v3/ipu-cpmem.c b/drivers/gpu/ipu-v3/ipu-cpmem.c
index 883a314cd83a..6494a4d28171 100644
--- a/drivers/gpu/ipu-v3/ipu-cpmem.c
+++ b/drivers/gpu/ipu-v3/ipu-cpmem.c
@@ -395,60 +395,48 @@ void ipu_cpmem_set_yuv_interleaved(struct ipuv3_channel *ch, u32 pixel_format)
395EXPORT_SYMBOL_GPL(ipu_cpmem_set_yuv_interleaved); 395EXPORT_SYMBOL_GPL(ipu_cpmem_set_yuv_interleaved);
396 396
397void ipu_cpmem_set_yuv_planar_full(struct ipuv3_channel *ch, 397void ipu_cpmem_set_yuv_planar_full(struct ipuv3_channel *ch,
398 u32 pixel_format, int stride, 398 unsigned int uv_stride,
399 int u_offset, int v_offset) 399 unsigned int u_offset, unsigned int v_offset)
400{ 400{
401 switch (pixel_format) { 401 ipu_ch_param_write_field(ch, IPU_FIELD_SLUV, uv_stride - 1);
402 case V4L2_PIX_FMT_YUV420: 402 ipu_ch_param_write_field(ch, IPU_FIELD_UBO, u_offset / 8);
403 case V4L2_PIX_FMT_YUV422P: 403 ipu_ch_param_write_field(ch, IPU_FIELD_VBO, v_offset / 8);
404 ipu_ch_param_write_field(ch, IPU_FIELD_SLUV, (stride / 2) - 1);
405 ipu_ch_param_write_field(ch, IPU_FIELD_UBO, u_offset / 8);
406 ipu_ch_param_write_field(ch, IPU_FIELD_VBO, v_offset / 8);
407 break;
408 case V4L2_PIX_FMT_YVU420:
409 ipu_ch_param_write_field(ch, IPU_FIELD_SLUV, (stride / 2) - 1);
410 ipu_ch_param_write_field(ch, IPU_FIELD_UBO, v_offset / 8);
411 ipu_ch_param_write_field(ch, IPU_FIELD_VBO, u_offset / 8);
412 break;
413 case V4L2_PIX_FMT_NV12:
414 case V4L2_PIX_FMT_NV16:
415 ipu_ch_param_write_field(ch, IPU_FIELD_SLUV, stride - 1);
416 ipu_ch_param_write_field(ch, IPU_FIELD_UBO, u_offset / 8);
417 ipu_ch_param_write_field(ch, IPU_FIELD_VBO, u_offset / 8);
418 break;
419 }
420} 404}
421EXPORT_SYMBOL_GPL(ipu_cpmem_set_yuv_planar_full); 405EXPORT_SYMBOL_GPL(ipu_cpmem_set_yuv_planar_full);
422 406
423void ipu_cpmem_set_yuv_planar(struct ipuv3_channel *ch, 407void ipu_cpmem_set_yuv_planar(struct ipuv3_channel *ch,
424 u32 pixel_format, int stride, int height) 408 u32 pixel_format, int stride, int height)
425{ 409{
426 int u_offset, v_offset; 410 int fourcc, u_offset, v_offset;
427 int uv_stride = 0; 411 int uv_stride = 0;
428 412
429 switch (pixel_format) { 413 fourcc = v4l2_pix_fmt_to_drm_fourcc(pixel_format);
430 case V4L2_PIX_FMT_YUV420: 414 switch (fourcc) {
431 case V4L2_PIX_FMT_YVU420: 415 case DRM_FORMAT_YUV420:
432 uv_stride = stride / 2; 416 uv_stride = stride / 2;
433 u_offset = stride * height; 417 u_offset = stride * height;
434 v_offset = u_offset + (uv_stride * height / 2); 418 v_offset = u_offset + (uv_stride * height / 2);
435 ipu_cpmem_set_yuv_planar_full(ch, pixel_format, stride,
436 u_offset, v_offset);
437 break; 419 break;
438 case V4L2_PIX_FMT_YUV422P: 420 case DRM_FORMAT_YVU420:
421 uv_stride = stride / 2;
422 v_offset = stride * height;
423 u_offset = v_offset + (uv_stride * height / 2);
424 break;
425 case DRM_FORMAT_YUV422:
439 uv_stride = stride / 2; 426 uv_stride = stride / 2;
440 u_offset = stride * height; 427 u_offset = stride * height;
441 v_offset = u_offset + (uv_stride * height); 428 v_offset = u_offset + (uv_stride * height);
442 ipu_cpmem_set_yuv_planar_full(ch, pixel_format, stride,
443 u_offset, v_offset);
444 break; 429 break;
445 case V4L2_PIX_FMT_NV12: 430 case DRM_FORMAT_NV12:
446 case V4L2_PIX_FMT_NV16: 431 case DRM_FORMAT_NV16:
432 uv_stride = stride;
447 u_offset = stride * height; 433 u_offset = stride * height;
448 ipu_cpmem_set_yuv_planar_full(ch, pixel_format, stride, 434 v_offset = 0;
449 u_offset, 0);
450 break; 435 break;
436 default:
437 return;
451 } 438 }
439 ipu_cpmem_set_yuv_planar_full(ch, uv_stride, u_offset, v_offset);
452} 440}
453EXPORT_SYMBOL_GPL(ipu_cpmem_set_yuv_planar); 441EXPORT_SYMBOL_GPL(ipu_cpmem_set_yuv_planar);
454 442
@@ -684,17 +672,25 @@ int ipu_cpmem_set_image(struct ipuv3_channel *ch, struct ipu_image *image)
684 672
685 switch (pix->pixelformat) { 673 switch (pix->pixelformat) {
686 case V4L2_PIX_FMT_YUV420: 674 case V4L2_PIX_FMT_YUV420:
687 case V4L2_PIX_FMT_YVU420:
688 offset = Y_OFFSET(pix, image->rect.left, image->rect.top); 675 offset = Y_OFFSET(pix, image->rect.left, image->rect.top);
689 u_offset = U_OFFSET(pix, image->rect.left, 676 u_offset = U_OFFSET(pix, image->rect.left,
690 image->rect.top) - offset; 677 image->rect.top) - offset;
691 v_offset = V_OFFSET(pix, image->rect.left, 678 v_offset = V_OFFSET(pix, image->rect.left,
692 image->rect.top) - offset; 679 image->rect.top) - offset;
693 680
694 ipu_cpmem_set_yuv_planar_full(ch, pix->pixelformat, 681 ipu_cpmem_set_yuv_planar_full(ch, pix->bytesperline / 2,
695 pix->bytesperline,
696 u_offset, v_offset); 682 u_offset, v_offset);
697 break; 683 break;
684 case V4L2_PIX_FMT_YVU420:
685 offset = Y_OFFSET(pix, image->rect.left, image->rect.top);
686 u_offset = U_OFFSET(pix, image->rect.left,
687 image->rect.top) - offset;
688 v_offset = V_OFFSET(pix, image->rect.left,
689 image->rect.top) - offset;
690
691 ipu_cpmem_set_yuv_planar_full(ch, pix->bytesperline / 2,
692 v_offset, u_offset);
693 break;
698 case V4L2_PIX_FMT_YUV422P: 694 case V4L2_PIX_FMT_YUV422P:
699 offset = Y_OFFSET(pix, image->rect.left, image->rect.top); 695 offset = Y_OFFSET(pix, image->rect.left, image->rect.top);
700 u_offset = U2_OFFSET(pix, image->rect.left, 696 u_offset = U2_OFFSET(pix, image->rect.left,
@@ -702,8 +698,7 @@ int ipu_cpmem_set_image(struct ipuv3_channel *ch, struct ipu_image *image)
702 v_offset = V2_OFFSET(pix, image->rect.left, 698 v_offset = V2_OFFSET(pix, image->rect.left,
703 image->rect.top) - offset; 699 image->rect.top) - offset;
704 700
705 ipu_cpmem_set_yuv_planar_full(ch, pix->pixelformat, 701 ipu_cpmem_set_yuv_planar_full(ch, pix->bytesperline / 2,
706 pix->bytesperline,
707 u_offset, v_offset); 702 u_offset, v_offset);
708 break; 703 break;
709 case V4L2_PIX_FMT_NV12: 704 case V4L2_PIX_FMT_NV12:
@@ -712,8 +707,7 @@ int ipu_cpmem_set_image(struct ipuv3_channel *ch, struct ipu_image *image)
712 image->rect.top) - offset; 707 image->rect.top) - offset;
713 v_offset = 0; 708 v_offset = 0;
714 709
715 ipu_cpmem_set_yuv_planar_full(ch, pix->pixelformat, 710 ipu_cpmem_set_yuv_planar_full(ch, pix->bytesperline,
716 pix->bytesperline,
717 u_offset, v_offset); 711 u_offset, v_offset);
718 break; 712 break;
719 case V4L2_PIX_FMT_NV16: 713 case V4L2_PIX_FMT_NV16:
@@ -722,8 +716,7 @@ int ipu_cpmem_set_image(struct ipuv3_channel *ch, struct ipu_image *image)
722 image->rect.top) - offset; 716 image->rect.top) - offset;
723 v_offset = 0; 717 v_offset = 0;
724 718
725 ipu_cpmem_set_yuv_planar_full(ch, pix->pixelformat, 719 ipu_cpmem_set_yuv_planar_full(ch, pix->bytesperline,
726 pix->bytesperline,
727 u_offset, v_offset); 720 u_offset, v_offset);
728 break; 721 break;
729 case V4L2_PIX_FMT_UYVY: 722 case V4L2_PIX_FMT_UYVY:
diff --git a/drivers/gpu/ipu-v3/ipu-dmfc.c b/drivers/gpu/ipu-v3/ipu-dmfc.c
index 042c3958e2a0..837b1ec22800 100644
--- a/drivers/gpu/ipu-v3/ipu-dmfc.c
+++ b/drivers/gpu/ipu-v3/ipu-dmfc.c
@@ -350,11 +350,13 @@ out:
350} 350}
351EXPORT_SYMBOL_GPL(ipu_dmfc_alloc_bandwidth); 351EXPORT_SYMBOL_GPL(ipu_dmfc_alloc_bandwidth);
352 352
353int ipu_dmfc_init_channel(struct dmfc_channel *dmfc, int width) 353void ipu_dmfc_config_wait4eot(struct dmfc_channel *dmfc, int width)
354{ 354{
355 struct ipu_dmfc_priv *priv = dmfc->priv; 355 struct ipu_dmfc_priv *priv = dmfc->priv;
356 u32 dmfc_gen1; 356 u32 dmfc_gen1;
357 357
358 mutex_lock(&priv->mutex);
359
358 dmfc_gen1 = readl(priv->base + DMFC_GENERAL1); 360 dmfc_gen1 = readl(priv->base + DMFC_GENERAL1);
359 361
360 if ((dmfc->slots * 64 * 4) / width > dmfc->data->max_fifo_lines) 362 if ((dmfc->slots * 64 * 4) / width > dmfc->data->max_fifo_lines)
@@ -364,9 +366,9 @@ int ipu_dmfc_init_channel(struct dmfc_channel *dmfc, int width)
364 366
365 writel(dmfc_gen1, priv->base + DMFC_GENERAL1); 367 writel(dmfc_gen1, priv->base + DMFC_GENERAL1);
366 368
367 return 0; 369 mutex_unlock(&priv->mutex);
368} 370}
369EXPORT_SYMBOL_GPL(ipu_dmfc_init_channel); 371EXPORT_SYMBOL_GPL(ipu_dmfc_config_wait4eot);
370 372
371struct dmfc_channel *ipu_dmfc_get(struct ipu_soc *ipu, int ipu_channel) 373struct dmfc_channel *ipu_dmfc_get(struct ipu_soc *ipu, int ipu_channel)
372{ 374{
diff --git a/include/drm/ttm/ttm_bo_api.h b/include/drm/ttm/ttm_bo_api.h
index afae2316bd43..055a08ddac02 100644
--- a/include/drm/ttm/ttm_bo_api.h
+++ b/include/drm/ttm/ttm_bo_api.h
@@ -92,7 +92,7 @@ struct ttm_placement {
92 */ 92 */
93struct ttm_bus_placement { 93struct ttm_bus_placement {
94 void *addr; 94 void *addr;
95 unsigned long base; 95 phys_addr_t base;
96 unsigned long size; 96 unsigned long size;
97 unsigned long offset; 97 unsigned long offset;
98 bool is_iomem; 98 bool is_iomem;
diff --git a/include/video/imx-ipu-v3.h b/include/video/imx-ipu-v3.h
index eeba75395f7d..ad66589f2ae6 100644
--- a/include/video/imx-ipu-v3.h
+++ b/include/video/imx-ipu-v3.h
@@ -194,8 +194,9 @@ int ipu_cpmem_set_format_rgb(struct ipuv3_channel *ch,
194int ipu_cpmem_set_format_passthrough(struct ipuv3_channel *ch, int width); 194int ipu_cpmem_set_format_passthrough(struct ipuv3_channel *ch, int width);
195void ipu_cpmem_set_yuv_interleaved(struct ipuv3_channel *ch, u32 pixel_format); 195void ipu_cpmem_set_yuv_interleaved(struct ipuv3_channel *ch, u32 pixel_format);
196void ipu_cpmem_set_yuv_planar_full(struct ipuv3_channel *ch, 196void ipu_cpmem_set_yuv_planar_full(struct ipuv3_channel *ch,
197 u32 pixel_format, int stride, 197 unsigned int uv_stride,
198 int u_offset, int v_offset); 198 unsigned int u_offset,
199 unsigned int v_offset);
199void ipu_cpmem_set_yuv_planar(struct ipuv3_channel *ch, 200void ipu_cpmem_set_yuv_planar(struct ipuv3_channel *ch,
200 u32 pixel_format, int stride, int height); 201 u32 pixel_format, int stride, int height);
201int ipu_cpmem_set_fmt(struct ipuv3_channel *ch, u32 drm_fourcc); 202int ipu_cpmem_set_fmt(struct ipuv3_channel *ch, u32 drm_fourcc);
@@ -236,7 +237,7 @@ void ipu_dmfc_disable_channel(struct dmfc_channel *dmfc);
236int ipu_dmfc_alloc_bandwidth(struct dmfc_channel *dmfc, 237int ipu_dmfc_alloc_bandwidth(struct dmfc_channel *dmfc,
237 unsigned long bandwidth_mbs, int burstsize); 238 unsigned long bandwidth_mbs, int burstsize);
238void ipu_dmfc_free_bandwidth(struct dmfc_channel *dmfc); 239void ipu_dmfc_free_bandwidth(struct dmfc_channel *dmfc);
239int ipu_dmfc_init_channel(struct dmfc_channel *dmfc, int width); 240void ipu_dmfc_config_wait4eot(struct dmfc_channel *dmfc, int width);
240struct dmfc_channel *ipu_dmfc_get(struct ipu_soc *ipu, int ipuv3_channel); 241struct dmfc_channel *ipu_dmfc_get(struct ipu_soc *ipu, int ipuv3_channel);
241void ipu_dmfc_put(struct dmfc_channel *dmfc); 242void ipu_dmfc_put(struct dmfc_channel *dmfc);
242 243