ARM: sun5i: Allow PLL3 2x fixed factor clock to change PLL3 rate

In order to be able to properly generate its pixel clock, the pll3-2x fixed
factor needs to be able to change the PLL3 rate too.

Add the needed extra compatible so that it behaves that way.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

1 files changed, 1 insertions, 1 deletions

diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi
index 0840612b5ed6..e374f4fc8073 100644
--- a/arch/arm/boot/dts/sun5i.dtsi
+++ b/arch/arm/boot/dts/sun5i.dtsi
@@ -130,7 +130,7 @@
                 };
 
                 pll3x2: pll3x2_clk {
-                        compatible = "fixed-factor-clock";
+                        compatible = "allwinner,sun4i-a10-pll3-2x-clk", "fixed-factor-clock";
                         #clock-cells = <0>;
                         clock-div = <1>;
                         clock-mult = <2>;