diff options
author | John Crispin <blogic@openwrt.org> | 2015-11-04 21:59:58 -0500 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2015-11-11 02:38:03 -0500 |
commit | 73afa6c4208257ea1733a03918fea731a18131e7 (patch) | |
tree | 6c04603025058017899ace02e0fb50a593e2978e | |
parent | b361bd762e7724e660a44955ae4840aa984e3871 (diff) |
MIPS: ralink: Add tty detection
MT7688 has several uarts that can be used for console. There are several
boards in the wild, that use ttyS1 or ttyS2. This patch applies a simply
autodetection routine to figure out which ttyS the bootloader used as
console. The uarts come up in 6 bit mode by default. The bootloader will
have set 8 bit mode on the console. Find that 8bit tty and use it.
Signed-off-by: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/11459/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
-rw-r--r-- | arch/mips/ralink/early_printk.c | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/arch/mips/ralink/early_printk.c b/arch/mips/ralink/early_printk.c index 255d695ec8c6..3c59ffe5f5f5 100644 --- a/arch/mips/ralink/early_printk.c +++ b/arch/mips/ralink/early_printk.c | |||
@@ -25,11 +25,13 @@ | |||
25 | #define MT7628_CHIP_NAME1 0x20203832 | 25 | #define MT7628_CHIP_NAME1 0x20203832 |
26 | 26 | ||
27 | #define UART_REG_TX 0x04 | 27 | #define UART_REG_TX 0x04 |
28 | #define UART_REG_LCR 0x0c | ||
28 | #define UART_REG_LSR 0x14 | 29 | #define UART_REG_LSR 0x14 |
29 | #define UART_REG_LSR_RT2880 0x1c | 30 | #define UART_REG_LSR_RT2880 0x1c |
30 | 31 | ||
31 | static __iomem void *uart_membase = (__iomem void *) KSEG1ADDR(EARLY_UART_BASE); | 32 | static __iomem void *uart_membase = (__iomem void *) KSEG1ADDR(EARLY_UART_BASE); |
32 | static __iomem void *chipid_membase = (__iomem void *) KSEG1ADDR(CHIPID_BASE); | 33 | static __iomem void *chipid_membase = (__iomem void *) KSEG1ADDR(CHIPID_BASE); |
34 | static int init_complete; | ||
33 | 35 | ||
34 | static inline void uart_w32(u32 val, unsigned reg) | 36 | static inline void uart_w32(u32 val, unsigned reg) |
35 | { | 37 | { |
@@ -47,8 +49,32 @@ static inline int soc_is_mt7628(void) | |||
47 | (__raw_readl(chipid_membase) == MT7628_CHIP_NAME1); | 49 | (__raw_readl(chipid_membase) == MT7628_CHIP_NAME1); |
48 | } | 50 | } |
49 | 51 | ||
52 | static void find_uart_base(void) | ||
53 | { | ||
54 | int i; | ||
55 | |||
56 | if (!soc_is_mt7628()) | ||
57 | return; | ||
58 | |||
59 | for (i = 0; i < 3; i++) { | ||
60 | u32 reg = uart_r32(UART_REG_LCR + (0x100 * i)); | ||
61 | |||
62 | if (!reg) | ||
63 | continue; | ||
64 | |||
65 | uart_membase = (__iomem void *) KSEG1ADDR(EARLY_UART_BASE + | ||
66 | (0x100 * i)); | ||
67 | break; | ||
68 | } | ||
69 | } | ||
70 | |||
50 | void prom_putchar(unsigned char ch) | 71 | void prom_putchar(unsigned char ch) |
51 | { | 72 | { |
73 | if (!init_complete) { | ||
74 | find_uart_base(); | ||
75 | init_complete = 1; | ||
76 | } | ||
77 | |||
52 | if (IS_ENABLED(CONFIG_SOC_MT7621) || soc_is_mt7628()) { | 78 | if (IS_ENABLED(CONFIG_SOC_MT7621) || soc_is_mt7628()) { |
53 | uart_w32(ch, UART_TX); | 79 | uart_w32(ch, UART_TX); |
54 | while ((uart_r32(UART_REG_LSR) & UART_LSR_THRE) == 0) | 80 | while ((uart_r32(UART_REG_LSR) & UART_LSR_THRE) == 0) |