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authorMichael Turquette <mturquette@baylibre.com>2016-05-23 18:44:26 -0400
committerMichael Turquette <mturquette@baylibre.com>2016-06-22 21:07:31 -0400
commit738f66d3211d7ae0cd0012ba6457dac9a03bfd6b (patch)
tree555daf5390d4f71e13faa433eb94544dd2811312
parent2cc9e7ec219819db10474160d65837c6c260522a (diff)
clk: gxbb: add AmLogic GXBB clk controller driver
The gxbb clock controller is the primary clock generation unit for the AmLogic GXBB SoC. It is clocked by a fixed 24MHz xtal, contains several PLLs and the usual post-dividers, muxes, dividers and leaf gates that are fed into various IP blocks in the SoC. Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Diffstat
-rw-r--r--drivers/clk/meson/Kconfig7
-rw-r--r--drivers/clk/meson/Makefile1
-rw-r--r--drivers/clk/meson/gxbb.c954
-rw-r--r--drivers/clk/meson/gxbb.h271
-rw-r--r--include/dt-bindings/clock/gxbb-clkc.h12
5 files changed, 1245 insertions, 0 deletions
diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
index 7bb19ad7369e..19480bcc7046 100644
--- a/drivers/clk/meson/Kconfig
+++ b/drivers/clk/meson/Kconfig
@@ -10,3 +10,10 @@ config COMMON_CLK_MESON8B
10 Support for the clock controller on AmLogic S805 devices, aka 10 Support for the clock controller on AmLogic S805 devices, aka
11 meson8b. Say Y if you want peripherals and CPU frequency scaling to 11 meson8b. Say Y if you want peripherals and CPU frequency scaling to
12 work. 12 work.
13
14config COMMON_CLK_GXBB
15 bool
16 depends on COMMON_CLK_AMLOGIC
17 help
18 Support for the clock controller on AmLogic S905 devices, aka gxbb.
19 Say Y if you want peripherals and CPU frequency scaling to work.
diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index 7667218b5e46..197e40175166 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -4,3 +4,4 @@
4 4
5obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-cpu.o clk-mpll.o 5obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-cpu.o clk-mpll.o
6obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b-clkc.o 6obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b-clkc.o
7obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o
diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
new file mode 100644
index 000000000000..007b7157cf4b
--- /dev/null
+++ b/drivers/clk/meson/gxbb.c
@@ -0,0 +1,954 @@
1/*
2 * Copyright (c) 2016 AmLogic, Inc.
3 * Michael Turquette <mturquette@baylibre.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18#include <linux/clk.h>
19#include <linux/clk-provider.h>
20#include <linux/of_address.h>
21#include <linux/platform_device.h>
22#include <linux/module.h>
23
24#include "clkc.h"
25#include "gxbb.h"
26
27static DEFINE_SPINLOCK(clk_lock);
28
29static const struct pll_rate_table sys_pll_rate_table[] = {
30 PLL_RATE(24000000, 56, 1, 2),
31 PLL_RATE(48000000, 64, 1, 2),
32 PLL_RATE(72000000, 72, 1, 2),
33 PLL_RATE(96000000, 64, 1, 2),
34 PLL_RATE(120000000, 80, 1, 2),
35 PLL_RATE(144000000, 96, 1, 2),
36 PLL_RATE(168000000, 56, 1, 1),
37 PLL_RATE(192000000, 64, 1, 1),
38 PLL_RATE(216000000, 72, 1, 1),
39 PLL_RATE(240000000, 80, 1, 1),
40 PLL_RATE(264000000, 88, 1, 1),
41 PLL_RATE(288000000, 96, 1, 1),
42 PLL_RATE(312000000, 52, 1, 2),
43 PLL_RATE(336000000, 56, 1, 2),
44 PLL_RATE(360000000, 60, 1, 2),
45 PLL_RATE(384000000, 64, 1, 2),
46 PLL_RATE(408000000, 68, 1, 2),
47 PLL_RATE(432000000, 72, 1, 2),
48 PLL_RATE(456000000, 76, 1, 2),
49 PLL_RATE(480000000, 80, 1, 2),
50 PLL_RATE(504000000, 84, 1, 2),
51 PLL_RATE(528000000, 88, 1, 2),
52 PLL_RATE(552000000, 92, 1, 2),
53 PLL_RATE(576000000, 96, 1, 2),
54 PLL_RATE(600000000, 50, 1, 1),
55 PLL_RATE(624000000, 52, 1, 1),
56 PLL_RATE(648000000, 54, 1, 1),
57 PLL_RATE(672000000, 56, 1, 1),
58 PLL_RATE(696000000, 58, 1, 1),
59 PLL_RATE(720000000, 60, 1, 1),
60 PLL_RATE(744000000, 62, 1, 1),
61 PLL_RATE(768000000, 64, 1, 1),
62 PLL_RATE(792000000, 66, 1, 1),
63 PLL_RATE(816000000, 68, 1, 1),
64 PLL_RATE(840000000, 70, 1, 1),
65 PLL_RATE(864000000, 72, 1, 1),
66 PLL_RATE(888000000, 74, 1, 1),
67 PLL_RATE(912000000, 76, 1, 1),
68 PLL_RATE(936000000, 78, 1, 1),
69 PLL_RATE(960000000, 80, 1, 1),
70 PLL_RATE(984000000, 82, 1, 1),
71 PLL_RATE(1008000000, 84, 1, 1),
72 PLL_RATE(1032000000, 86, 1, 1),
73 PLL_RATE(1056000000, 88, 1, 1),
74 PLL_RATE(1080000000, 90, 1, 1),
75 PLL_RATE(1104000000, 92, 1, 1),
76 PLL_RATE(1128000000, 94, 1, 1),
77 PLL_RATE(1152000000, 96, 1, 1),
78 PLL_RATE(1176000000, 98, 1, 1),
79 PLL_RATE(1200000000, 50, 1, 0),
80 PLL_RATE(1224000000, 51, 1, 0),
81 PLL_RATE(1248000000, 52, 1, 0),
82 PLL_RATE(1272000000, 53, 1, 0),
83 PLL_RATE(1296000000, 54, 1, 0),
84 PLL_RATE(1320000000, 55, 1, 0),
85 PLL_RATE(1344000000, 56, 1, 0),
86 PLL_RATE(1368000000, 57, 1, 0),
87 PLL_RATE(1392000000, 58, 1, 0),
88 PLL_RATE(1416000000, 59, 1, 0),
89 PLL_RATE(1440000000, 60, 1, 0),
90 PLL_RATE(1464000000, 61, 1, 0),
91 PLL_RATE(1488000000, 62, 1, 0),
92 PLL_RATE(1512000000, 63, 1, 0),
93 PLL_RATE(1536000000, 64, 1, 0),
94 PLL_RATE(1560000000, 65, 1, 0),
95 PLL_RATE(1584000000, 66, 1, 0),
96 PLL_RATE(1608000000, 67, 1, 0),
97 PLL_RATE(1632000000, 68, 1, 0),
98 PLL_RATE(1656000000, 68, 1, 0),
99 PLL_RATE(1680000000, 68, 1, 0),
100 PLL_RATE(1704000000, 68, 1, 0),
101 PLL_RATE(1728000000, 69, 1, 0),
102 PLL_RATE(1752000000, 69, 1, 0),
103 PLL_RATE(1776000000, 69, 1, 0),
104 PLL_RATE(1800000000, 69, 1, 0),
105 PLL_RATE(1824000000, 70, 1, 0),
106 PLL_RATE(1848000000, 70, 1, 0),
107 PLL_RATE(1872000000, 70, 1, 0),
108 PLL_RATE(1896000000, 70, 1, 0),
109 PLL_RATE(1920000000, 71, 1, 0),
110 PLL_RATE(1944000000, 71, 1, 0),
111 PLL_RATE(1968000000, 71, 1, 0),
112 PLL_RATE(1992000000, 71, 1, 0),
113 PLL_RATE(2016000000, 72, 1, 0),
114 PLL_RATE(2040000000, 72, 1, 0),
115 PLL_RATE(2064000000, 72, 1, 0),
116 PLL_RATE(2088000000, 72, 1, 0),
117 PLL_RATE(2112000000, 73, 1, 0),
118 { /* sentinel */ },
119};
120
121static const struct pll_rate_table gp0_pll_rate_table[] = {
122 PLL_RATE(96000000, 32, 1, 3),
123 PLL_RATE(99000000, 33, 1, 3),
124 PLL_RATE(102000000, 34, 1, 3),
125 PLL_RATE(105000000, 35, 1, 3),
126 PLL_RATE(108000000, 36, 1, 3),
127 PLL_RATE(111000000, 37, 1, 3),
128 PLL_RATE(114000000, 38, 1, 3),
129 PLL_RATE(117000000, 39, 1, 3),
130 PLL_RATE(120000000, 40, 1, 3),
131 PLL_RATE(123000000, 41, 1, 3),
132 PLL_RATE(126000000, 42, 1, 3),
133 PLL_RATE(129000000, 43, 1, 3),
134 PLL_RATE(132000000, 44, 1, 3),
135 PLL_RATE(135000000, 45, 1, 3),
136 PLL_RATE(138000000, 46, 1, 3),
137 PLL_RATE(141000000, 47, 1, 3),
138 PLL_RATE(144000000, 48, 1, 3),
139 PLL_RATE(147000000, 49, 1, 3),
140 PLL_RATE(150000000, 50, 1, 3),
141 PLL_RATE(153000000, 51, 1, 3),
142 PLL_RATE(156000000, 52, 1, 3),
143 PLL_RATE(159000000, 53, 1, 3),
144 PLL_RATE(162000000, 54, 1, 3),
145 PLL_RATE(165000000, 55, 1, 3),
146 PLL_RATE(168000000, 56, 1, 3),
147 PLL_RATE(171000000, 57, 1, 3),
148 PLL_RATE(174000000, 58, 1, 3),
149 PLL_RATE(177000000, 59, 1, 3),
150 PLL_RATE(180000000, 60, 1, 3),
151 PLL_RATE(183000000, 61, 1, 3),
152 PLL_RATE(186000000, 62, 1, 3),
153 PLL_RATE(192000000, 32, 1, 2),
154 PLL_RATE(198000000, 33, 1, 2),
155 PLL_RATE(204000000, 34, 1, 2),
156 PLL_RATE(210000000, 35, 1, 2),
157 PLL_RATE(216000000, 36, 1, 2),
158 PLL_RATE(222000000, 37, 1, 2),
159 PLL_RATE(228000000, 38, 1, 2),
160 PLL_RATE(234000000, 39, 1, 2),
161 PLL_RATE(240000000, 40, 1, 2),
162 PLL_RATE(246000000, 41, 1, 2),
163 PLL_RATE(252000000, 42, 1, 2),
164 PLL_RATE(258000000, 43, 1, 2),
165 PLL_RATE(264000000, 44, 1, 2),
166 PLL_RATE(270000000, 45, 1, 2),
167 PLL_RATE(276000000, 46, 1, 2),
168 PLL_RATE(282000000, 47, 1, 2),
169 PLL_RATE(288000000, 48, 1, 2),
170 PLL_RATE(294000000, 49, 1, 2),
171 PLL_RATE(300000000, 50, 1, 2),
172 PLL_RATE(306000000, 51, 1, 2),
173 PLL_RATE(312000000, 52, 1, 2),
174 PLL_RATE(318000000, 53, 1, 2),
175 PLL_RATE(324000000, 54, 1, 2),
176 PLL_RATE(330000000, 55, 1, 2),
177 PLL_RATE(336000000, 56, 1, 2),
178 PLL_RATE(342000000, 57, 1, 2),
179 PLL_RATE(348000000, 58, 1, 2),
180 PLL_RATE(354000000, 59, 1, 2),
181 PLL_RATE(360000000, 60, 1, 2),
182 PLL_RATE(366000000, 61, 1, 2),
183 PLL_RATE(372000000, 62, 1, 2),
184 PLL_RATE(384000000, 32, 1, 1),
185 PLL_RATE(396000000, 33, 1, 1),
186 PLL_RATE(408000000, 34, 1, 1),
187 PLL_RATE(420000000, 35, 1, 1),
188 PLL_RATE(432000000, 36, 1, 1),
189 PLL_RATE(444000000, 37, 1, 1),
190 PLL_RATE(456000000, 38, 1, 1),
191 PLL_RATE(468000000, 39, 1, 1),
192 PLL_RATE(480000000, 40, 1, 1),
193 PLL_RATE(492000000, 41, 1, 1),
194 PLL_RATE(504000000, 42, 1, 1),
195 PLL_RATE(516000000, 43, 1, 1),
196 PLL_RATE(528000000, 44, 1, 1),
197 PLL_RATE(540000000, 45, 1, 1),
198 PLL_RATE(552000000, 46, 1, 1),
199 PLL_RATE(564000000, 47, 1, 1),
200 PLL_RATE(576000000, 48, 1, 1),
201 PLL_RATE(588000000, 49, 1, 1),
202 PLL_RATE(600000000, 50, 1, 1),
203 PLL_RATE(612000000, 51, 1, 1),
204 PLL_RATE(624000000, 52, 1, 1),
205 PLL_RATE(636000000, 53, 1, 1),
206 PLL_RATE(648000000, 54, 1, 1),
207 PLL_RATE(660000000, 55, 1, 1),
208 PLL_RATE(672000000, 56, 1, 1),
209 PLL_RATE(684000000, 57, 1, 1),
210 PLL_RATE(696000000, 58, 1, 1),
211 PLL_RATE(708000000, 59, 1, 1),
212 PLL_RATE(720000000, 60, 1, 1),
213 PLL_RATE(732000000, 61, 1, 1),
214 PLL_RATE(744000000, 62, 1, 1),
215 PLL_RATE(768000000, 32, 1, 0),
216 PLL_RATE(792000000, 33, 1, 0),
217 PLL_RATE(816000000, 34, 1, 0),
218 PLL_RATE(840000000, 35, 1, 0),
219 PLL_RATE(864000000, 36, 1, 0),
220 PLL_RATE(888000000, 37, 1, 0),
221 PLL_RATE(912000000, 38, 1, 0),
222 PLL_RATE(936000000, 39, 1, 0),
223 PLL_RATE(960000000, 40, 1, 0),
224 PLL_RATE(984000000, 41, 1, 0),
225 PLL_RATE(1008000000, 42, 1, 0),
226 PLL_RATE(1032000000, 43, 1, 0),
227 PLL_RATE(1056000000, 44, 1, 0),
228 PLL_RATE(1080000000, 45, 1, 0),
229 PLL_RATE(1104000000, 46, 1, 0),
230 PLL_RATE(1128000000, 47, 1, 0),
231 PLL_RATE(1152000000, 48, 1, 0),
232 PLL_RATE(1176000000, 49, 1, 0),
233 PLL_RATE(1200000000, 50, 1, 0),
234 PLL_RATE(1224000000, 51, 1, 0),
235 PLL_RATE(1248000000, 52, 1, 0),
236 PLL_RATE(1272000000, 53, 1, 0),
237 PLL_RATE(1296000000, 54, 1, 0),
238 PLL_RATE(1320000000, 55, 1, 0),
239 PLL_RATE(1344000000, 56, 1, 0),
240 PLL_RATE(1368000000, 57, 1, 0),
241 PLL_RATE(1392000000, 58, 1, 0),
242 PLL_RATE(1416000000, 59, 1, 0),
243 PLL_RATE(1440000000, 60, 1, 0),
244 PLL_RATE(1464000000, 61, 1, 0),
245 PLL_RATE(1488000000, 62, 1, 0),
246 { /* sentinel */ },
247};
248
249static const struct clk_div_table cpu_div_table[] = {
250 { .val = 1, .div = 1 },
251 { .val = 2, .div = 2 },
252 { .val = 3, .div = 3 },
253 { .val = 2, .div = 4 },
254 { .val = 3, .div = 6 },
255 { .val = 4, .div = 8 },
256 { .val = 5, .div = 10 },
257 { .val = 6, .div = 12 },
258 { .val = 7, .div = 14 },
259 { .val = 8, .div = 16 },
260 { /* sentinel */ },
261};
262
263static struct meson_clk_pll gxbb_fixed_pll = {
264 .m = {
265 .reg_off = HHI_MPLL_CNTL,
266 .shift = 0,
267 .width = 9,
268 },
269 .n = {
270 .reg_off = HHI_MPLL_CNTL,
271 .shift = 9,
272 .width = 5,
273 },
274 .od = {
275 .reg_off = HHI_MPLL_CNTL,
276 .shift = 16,
277 .width = 2,
278 },
279 .lock = &clk_lock,
280 .hw.init = &(struct clk_init_data){
281 .name = "fixed_pll",
282 .ops = &meson_clk_pll_ro_ops,
283 .parent_names = (const char *[]){ "xtal" },
284 .num_parents = 1,
285 .flags = CLK_GET_RATE_NOCACHE,
286 },
287};
288
289static struct meson_clk_pll gxbb_hdmi_pll = {
290 .m = {
291 .reg_off = HHI_HDMI_PLL_CNTL,
292 .shift = 0,
293 .width = 9,
294 },
295 .n = {
296 .reg_off = HHI_HDMI_PLL_CNTL,
297 .shift = 9,
298 .width = 5,
299 },
300 .frac = {
301 .reg_off = HHI_HDMI_PLL_CNTL2,
302 .shift = 0,
303 .width = 12,
304 },
305 .od = {
306 .reg_off = HHI_HDMI_PLL_CNTL2,
307 .shift = 16,
308 .width = 2,
309 },
310 .od2 = {
311 .reg_off = HHI_HDMI_PLL_CNTL2,
312 .shift = 22,
313 .width = 2,
314 },
315 .lock = &clk_lock,
316 .hw.init = &(struct clk_init_data){
317 .name = "hdmi_pll",
318 .ops = &meson_clk_pll_ro_ops,
319 .parent_names = (const char *[]){ "xtal" },
320 .num_parents = 1,
321 .flags = CLK_GET_RATE_NOCACHE,
322 },
323};
324
325static struct meson_clk_pll gxbb_sys_pll = {
326 .m = {
327 .reg_off = HHI_SYS_PLL_CNTL,
328 .shift = 0,
329 .width = 9,
330 },
331 .n = {
332 .reg_off = HHI_SYS_PLL_CNTL,
333 .shift = 9,
334 .width = 5,
335 },
336 .od = {
337 .reg_off = HHI_SYS_PLL_CNTL,
338 .shift = 10,
339 .width = 2,
340 },
341 .rate_table = sys_pll_rate_table,
342 .rate_count = ARRAY_SIZE(sys_pll_rate_table),
343 .lock = &clk_lock,
344 .hw.init = &(struct clk_init_data){
345 .name = "sys_pll",
346 .ops = &meson_clk_pll_ro_ops,
347 .parent_names = (const char *[]){ "xtal" },
348 .num_parents = 1,
349 .flags = CLK_GET_RATE_NOCACHE,
350 },
351};
352
353static struct meson_clk_pll gxbb_gp0_pll = {
354 .m = {
355 .reg_off = HHI_GP0_PLL_CNTL,
356 .shift = 0,
357 .width = 9,
358 },
359 .n = {
360 .reg_off = HHI_GP0_PLL_CNTL,
361 .shift = 9,
362 .width = 5,
363 },
364 .od = {
365 .reg_off = HHI_GP0_PLL_CNTL,
366 .shift = 16,
367 .width = 2,
368 },
369 .rate_table = gp0_pll_rate_table,
370 .rate_count = ARRAY_SIZE(gp0_pll_rate_table),
371 .lock = &clk_lock,
372 .hw.init = &(struct clk_init_data){
373 .name = "gp0_pll",
374 .ops = &meson_clk_pll_ops,
375 .parent_names = (const char *[]){ "xtal" },
376 .num_parents = 1,
377 .flags = CLK_GET_RATE_NOCACHE,
378 },
379};
380
381static struct clk_fixed_factor gxbb_fclk_div2 = {
382 .mult = 1,
383 .div = 2,
384 .hw.init = &(struct clk_init_data){
385 .name = "fclk_div2",
386 .ops = &clk_fixed_factor_ops,
387 .parent_names = (const char *[]){ "fixed_pll" },
388 .num_parents = 1,
389 },
390};
391
392static struct clk_fixed_factor gxbb_fclk_div3 = {
393 .mult = 1,
394 .div = 3,
395 .hw.init = &(struct clk_init_data){
396 .name = "fclk_div3",
397 .ops = &clk_fixed_factor_ops,
398 .parent_names = (const char *[]){ "fixed_pll" },
399 .num_parents = 1,
400 },
401};
402
403static struct clk_fixed_factor gxbb_fclk_div4 = {
404 .mult = 1,
405 .div = 4,
406 .hw.init = &(struct clk_init_data){
407 .name = "fclk_div4",
408 .ops = &clk_fixed_factor_ops,
409 .parent_names = (const char *[]){ "fixed_pll" },
410 .num_parents = 1,
411 },
412};
413
414static struct clk_fixed_factor gxbb_fclk_div5 = {
415 .mult = 1,
416 .div = 5,
417 .hw.init = &(struct clk_init_data){
418 .name = "fclk_div5",
419 .ops = &clk_fixed_factor_ops,
420 .parent_names = (const char *[]){ "fixed_pll" },
421 .num_parents = 1,
422 },
423};
424
425static struct clk_fixed_factor gxbb_fclk_div7 = {
426 .mult = 1,
427 .div = 7,
428 .hw.init = &(struct clk_init_data){
429 .name = "fclk_div7",
430 .ops = &clk_fixed_factor_ops,
431 .parent_names = (const char *[]){ "fixed_pll" },
432 .num_parents = 1,
433 },
434};
435
436static struct meson_clk_mpll gxbb_mpll0 = {
437 .sdm = {
438 .reg_off = HHI_MPLL_CNTL7,
439 .shift = 0,
440 .width = 14,
441 },
442 .n2 = {
443 .reg_off = HHI_MPLL_CNTL7,
444 .shift = 16,
445 .width = 9,
446 },
447 .lock = &clk_lock,
448 .hw.init = &(struct clk_init_data){
449 .name = "mpll0",
450 .ops = &meson_clk_mpll_ro_ops,
451 .parent_names = (const char *[]){ "fixed_pll" },
452 .num_parents = 1,
453 },
454};
455
456static struct meson_clk_mpll gxbb_mpll1 = {
457 .sdm = {
458 .reg_off = HHI_MPLL_CNTL8,
459 .shift = 0,
460 .width = 14,
461 },
462 .n2 = {
463 .reg_off = HHI_MPLL_CNTL8,
464 .shift = 16,
465 .width = 9,
466 },
467 .lock = &clk_lock,
468 .hw.init = &(struct clk_init_data){
469 .name = "mpll1",
470 .ops = &meson_clk_mpll_ro_ops,
471 .parent_names = (const char *[]){ "fixed_pll" },
472 .num_parents = 1,
473 },
474};
475
476static struct meson_clk_mpll gxbb_mpll2 = {
477 .sdm = {
478 .reg_off = HHI_MPLL_CNTL9,
479 .shift = 0,
480 .width = 14,
481 },
482 .n2 = {
483 .reg_off = HHI_MPLL_CNTL9,
484 .shift = 16,
485 .width = 9,
486 },
487 .lock = &clk_lock,
488 .hw.init = &(struct clk_init_data){
489 .name = "mpll2",
490 .ops = &meson_clk_mpll_ro_ops,
491 .parent_names = (const char *[]){ "fixed_pll" },
492 .num_parents = 1,
493 },
494};
495
496/*
497 * FIXME cpu clocks and the legacy composite clocks (e.g. clk81) are both PLL
498 * post-dividers and should be modeled with their respective PLLs via the
499 * forthcoming coordinated clock rates feature
500 */
501static struct meson_clk_cpu gxbb_cpu_clk = {
502 .reg_off = HHI_SYS_CPU_CLK_CNTL1,
503 .div_table = cpu_div_table,
504 .clk_nb.notifier_call = meson_clk_cpu_notifier_cb,
505 .hw.init = &(struct clk_init_data){
506 .name = "cpu_clk",
507 .ops = &meson_clk_cpu_ops,
508 .parent_names = (const char *[]){ "sys_pll" },
509 .num_parents = 1,
510 },
511};
512
513static u32 mux_table_clk81[] = { 6, 5, 7 };
514
515static struct clk_mux gxbb_mpeg_clk_sel = {
516 .reg = (void *)HHI_MPEG_CLK_CNTL,
517 .mask = 0x7,
518 .shift = 12,
519 .flags = CLK_MUX_READ_ONLY,
520 .table = mux_table_clk81,
521 .lock = &clk_lock,
522 .hw.init = &(struct clk_init_data){
523 .name = "mpeg_clk_sel",
524 .ops = &clk_mux_ro_ops,
525 /*
526 * FIXME bits 14:12 selects from 8 possible parents:
527 * xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2,
528 * fclk_div4, fclk_div3, fclk_div5
529 */
530 .parent_names = (const char *[]){ "fclk_div3", "fclk_div4",
531 "fclk_div5" },
532 .num_parents = 3,
533 .flags = (CLK_SET_RATE_NO_REPARENT | CLK_IGNORE_UNUSED),
534 },
535};
536
537static struct clk_divider gxbb_mpeg_clk_div = {
538 .reg = (void *)HHI_MPEG_CLK_CNTL,
539 .shift = 0,
540 .width = 7,
541 .lock = &clk_lock,
542 .hw.init = &(struct clk_init_data){
543 .name = "mpeg_clk_div",
544 .ops = &clk_divider_ops,
545 .parent_names = (const char *[]){ "mpeg_clk_sel" },
546 .num_parents = 1,
547 .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED),
548 },
549};
550
551/* the mother of dragons^W gates */
552static struct clk_gate gxbb_clk81 = {
553 .reg = (void *)HHI_MPEG_CLK_CNTL,
554 .bit_idx = 7,
555 .lock = &clk_lock,
556 .hw.init = &(struct clk_init_data){
557 .name = "clk81",
558 .ops = &clk_gate_ops,
559 .parent_names = (const char *[]){ "mpeg_clk_div" },
560 .num_parents = 1,
561 .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED | CLK_IS_CRITICAL),
562 },
563};
564
565/* Everything Else (EE) domain gates */
566static MESON_GATE(ddr, HHI_GCLK_MPEG0, 0);
567static MESON_GATE(dos, HHI_GCLK_MPEG0, 1);
568static MESON_GATE(isa, HHI_GCLK_MPEG0, 5);
569static MESON_GATE(pl301, HHI_GCLK_MPEG0, 6);
570static MESON_GATE(periphs, HHI_GCLK_MPEG0, 7);
571static MESON_GATE(spicc, HHI_GCLK_MPEG0, 8);
572static MESON_GATE(i2c, HHI_GCLK_MPEG0, 9);
573static MESON_GATE(sar_adc, HHI_GCLK_MPEG0, 10);
574static MESON_GATE(smart_card, HHI_GCLK_MPEG0, 11);
575static MESON_GATE(rng0, HHI_GCLK_MPEG0, 12);
576static MESON_GATE(uart0, HHI_GCLK_MPEG0, 13);
577static MESON_GATE(sdhc, HHI_GCLK_MPEG0, 14);
578static MESON_GATE(stream, HHI_GCLK_MPEG0, 15);
579static MESON_GATE(async_fifo, HHI_GCLK_MPEG0, 16);
580static MESON_GATE(sdio, HHI_GCLK_MPEG0, 17);
581static MESON_GATE(abuf, HHI_GCLK_MPEG0, 18);
582static MESON_GATE(hiu_iface, HHI_GCLK_MPEG0, 19);
583static MESON_GATE(assist_misc, HHI_GCLK_MPEG0, 23);
584static MESON_GATE(spi, HHI_GCLK_MPEG0, 30);
585
586static MESON_GATE(i2s_spdif, HHI_GCLK_MPEG1, 2);
587static MESON_GATE(eth, HHI_GCLK_MPEG1, 3);
588static MESON_GATE(demux, HHI_GCLK_MPEG1, 4);
589static MESON_GATE(aiu_glue, HHI_GCLK_MPEG1, 6);
590static MESON_GATE(iec958, HHI_GCLK_MPEG1, 7);
591static MESON_GATE(i2s_out, HHI_GCLK_MPEG1, 8);
592static MESON_GATE(amclk, HHI_GCLK_MPEG1, 9);
593static MESON_GATE(aififo2, HHI_GCLK_MPEG1, 10);
594static MESON_GATE(mixer, HHI_GCLK_MPEG1, 11);
595static MESON_GATE(mixer_iface, HHI_GCLK_MPEG1, 12);
596static MESON_GATE(adc, HHI_GCLK_MPEG1, 13);
597static MESON_GATE(blkmv, HHI_GCLK_MPEG1, 14);
598static MESON_GATE(aiu, HHI_GCLK_MPEG1, 15);
599static MESON_GATE(uart1, HHI_GCLK_MPEG1, 16);
600static MESON_GATE(g2d, HHI_GCLK_MPEG1, 20);
601static MESON_GATE(usb0, HHI_GCLK_MPEG1, 21);
602static MESON_GATE(usb1, HHI_GCLK_MPEG1, 22);
603static MESON_GATE(reset, HHI_GCLK_MPEG1, 23);
604static MESON_GATE(nand, HHI_GCLK_MPEG1, 24);
605static MESON_GATE(dos_parser, HHI_GCLK_MPEG1, 25);
606static MESON_GATE(usb, HHI_GCLK_MPEG1, 26);
607static MESON_GATE(vdin1, HHI_GCLK_MPEG1, 28);
608static MESON_GATE(ahb_arb0, HHI_GCLK_MPEG1, 29);
609static MESON_GATE(efuse, HHI_GCLK_MPEG1, 30);
610static MESON_GATE(boot_rom, HHI_GCLK_MPEG1, 31);
611
612static MESON_GATE(ahb_data_bus, HHI_GCLK_MPEG2, 1);
613static MESON_GATE(ahb_ctrl_bus, HHI_GCLK_MPEG2, 2);
614static MESON_GATE(hdmi_intr_sync, HHI_GCLK_MPEG2, 3);
615static MESON_GATE(hdmi_pclk, HHI_GCLK_MPEG2, 4);
616static MESON_GATE(usb1_ddr_bridge, HHI_GCLK_MPEG2, 8);
617static MESON_GATE(usb0_ddr_bridge, HHI_GCLK_MPEG2, 9);
618static MESON_GATE(mmc_pclk, HHI_GCLK_MPEG2, 11);
619static MESON_GATE(dvin, HHI_GCLK_MPEG2, 12);
620static MESON_GATE(uart2, HHI_GCLK_MPEG2, 15);
621static MESON_GATE(sana, HHI_GCLK_MPEG2, 22);
622static MESON_GATE(vpu_intr, HHI_GCLK_MPEG2, 25);
623static MESON_GATE(sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26);
624static MESON_GATE(clk81_a53, HHI_GCLK_MPEG2, 29);
625
626static MESON_GATE(vclk2_venci0, HHI_GCLK_OTHER, 1);
627static MESON_GATE(vclk2_venci1, HHI_GCLK_OTHER, 2);
628static MESON_GATE(vclk2_vencp0, HHI_GCLK_OTHER, 3);
629static MESON_GATE(vclk2_vencp1, HHI_GCLK_OTHER, 4);
630static MESON_GATE(gclk_venci_int0, HHI_GCLK_OTHER, 8);
631static MESON_GATE(gclk_vencp_int, HHI_GCLK_OTHER, 9);
632static MESON_GATE(dac_clk, HHI_GCLK_OTHER, 10);
633static MESON_GATE(aoclk_gate, HHI_GCLK_OTHER, 14);
634static MESON_GATE(iec958_gate, HHI_GCLK_OTHER, 16);
635static MESON_GATE(enc480p, HHI_GCLK_OTHER, 20);
636static MESON_GATE(rng1, HHI_GCLK_OTHER, 21);
637static MESON_GATE(gclk_venci_int1, HHI_GCLK_OTHER, 22);
638static MESON_GATE(vclk2_venclmcc, HHI_GCLK_OTHER, 24);
639static MESON_GATE(vclk2_vencl, HHI_GCLK_OTHER, 25);
640static MESON_GATE(vclk_other, HHI_GCLK_OTHER, 26);
641static MESON_GATE(edp, HHI_GCLK_OTHER, 31);
642
643/* Always On (AO) domain gates */
644
645static MESON_GATE(ao_media_cpu, HHI_GCLK_AO, 0);
646static MESON_GATE(ao_ahb_sram, HHI_GCLK_AO, 1);
647static MESON_GATE(ao_ahb_bus, HHI_GCLK_AO, 2);
648static MESON_GATE(ao_iface, HHI_GCLK_AO, 3);
649static MESON_GATE(ao_i2c, HHI_GCLK_AO, 4);
650
651/* Array of all clocks provided by this provider */
652
653static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
654 .hws = {
655 [CLKID_SYS_PLL] = &gxbb_sys_pll.hw,
656 [CLKID_CPUCLK] = &gxbb_cpu_clk.hw,
657 [CLKID_HDMI_PLL] = &gxbb_hdmi_pll.hw,
658 [CLKID_FIXED_PLL] = &gxbb_fixed_pll.hw,
659 [CLKID_FCLK_DIV2] = &gxbb_fclk_div2.hw,
660 [CLKID_FCLK_DIV3] = &gxbb_fclk_div3.hw,
661 [CLKID_FCLK_DIV4] = &gxbb_fclk_div4.hw,
662 [CLKID_FCLK_DIV5] = &gxbb_fclk_div5.hw,
663 [CLKID_FCLK_DIV7] = &gxbb_fclk_div7.hw,
664 [CLKID_GP0_PLL] = &gxbb_gp0_pll.hw,
665 [CLKID_MPEG_SEL] = &gxbb_mpeg_clk_sel.hw,
666 [CLKID_MPEG_DIV] = &gxbb_mpeg_clk_div.hw,
667 [CLKID_CLK81] = &gxbb_clk81.hw,
668 [CLKID_MPLL0] = &gxbb_mpll0.hw,
669 [CLKID_MPLL1] = &gxbb_mpll1.hw,
670 [CLKID_MPLL2] = &gxbb_mpll2.hw,
671 [CLKID_DDR] = &gxbb_ddr.hw,
672 [CLKID_DOS] = &gxbb_dos.hw,
673 [CLKID_ISA] = &gxbb_isa.hw,
674 [CLKID_PL301] = &gxbb_pl301.hw,
675 [CLKID_PERIPHS] = &gxbb_periphs.hw,
676 [CLKID_SPICC] = &gxbb_spicc.hw,
677 [CLKID_I2C] = &gxbb_i2c.hw,
678 [CLKID_SAR_ADC] = &gxbb_sar_adc.hw,
679 [CLKID_SMART_CARD] = &gxbb_smart_card.hw,
680 [CLKID_RNG0] = &gxbb_rng0.hw,
681 [CLKID_UART0] = &gxbb_uart0.hw,
682 [CLKID_SDHC] = &gxbb_sdhc.hw,
683 [CLKID_STREAM] = &gxbb_stream.hw,
684 [CLKID_ASYNC_FIFO] = &gxbb_async_fifo.hw,
685 [CLKID_SDIO] = &gxbb_sdio.hw,
686 [CLKID_ABUF] = &gxbb_abuf.hw,
687 [CLKID_HIU_IFACE] = &gxbb_hiu_iface.hw,
688 [CLKID_ASSIST_MISC] = &gxbb_assist_misc.hw,
689 [CLKID_SPI] = &gxbb_spi.hw,
690 [CLKID_I2S_SPDIF] = &gxbb_i2s_spdif.hw,
691 [CLKID_ETH] = &gxbb_eth.hw,
692 [CLKID_DEMUX] = &gxbb_demux.hw,
693 [CLKID_AIU_GLUE] = &gxbb_aiu_glue.hw,
694 [CLKID_IEC958] = &gxbb_iec958.hw,
695 [CLKID_I2S_OUT] = &gxbb_i2s_out.hw,
696 [CLKID_AMCLK] = &gxbb_amclk.hw,
697 [CLKID_AIFIFO2] = &gxbb_aififo2.hw,
698 [CLKID_MIXER] = &gxbb_mixer.hw,
699 [CLKID_MIXER_IFACE] = &gxbb_mixer_iface.hw,
700 [CLKID_ADC] = &gxbb_adc.hw,
701 [CLKID_BLKMV] = &gxbb_blkmv.hw,
702 [CLKID_AIU] = &gxbb_aiu.hw,
703 [CLKID_UART1] = &gxbb_uart1.hw,
704 [CLKID_G2D] = &gxbb_g2d.hw,
705 [CLKID_USB0] = &gxbb_usb0.hw,
706 [CLKID_USB1] = &gxbb_usb1.hw,
707 [CLKID_RESET] = &gxbb_reset.hw,
708 [CLKID_NAND] = &gxbb_nand.hw,
709 [CLKID_DOS_PARSER] = &gxbb_dos_parser.hw,
710 [CLKID_USB] = &gxbb_usb.hw,
711 [CLKID_VDIN1] = &gxbb_vdin1.hw,
712 [CLKID_AHB_ARB0] = &gxbb_ahb_arb0.hw,
713 [CLKID_EFUSE] = &gxbb_efuse.hw,
714 [CLKID_BOOT_ROM] = &gxbb_boot_rom.hw,
715 [CLKID_AHB_DATA_BUS] = &gxbb_ahb_data_bus.hw,
716 [CLKID_AHB_CTRL_BUS] = &gxbb_ahb_ctrl_bus.hw,
717 [CLKID_HDMI_INTR_SYNC] = &gxbb_hdmi_intr_sync.hw,
718 [CLKID_HDMI_PCLK] = &gxbb_hdmi_pclk.hw,
719 [CLKID_USB1_DDR_BRIDGE] = &gxbb_usb1_ddr_bridge.hw,
720 [CLKID_USB0_DDR_BRIDGE] = &gxbb_usb0_ddr_bridge.hw,
721 [CLKID_MMC_PCLK] = &gxbb_mmc_pclk.hw,
722 [CLKID_DVIN] = &gxbb_dvin.hw,
723 [CLKID_UART2] = &gxbb_uart2.hw,
724 [CLKID_SANA] = &gxbb_sana.hw,
725 [CLKID_VPU_INTR] = &gxbb_vpu_intr.hw,
726 [CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw,
727 [CLKID_CLK81_A53] = &gxbb_clk81_a53.hw,
728 [CLKID_VCLK2_VENCI0] = &gxbb_vclk2_venci0.hw,
729 [CLKID_VCLK2_VENCI1] = &gxbb_vclk2_venci1.hw,
730 [CLKID_VCLK2_VENCP0] = &gxbb_vclk2_vencp0.hw,
731 [CLKID_VCLK2_VENCP1] = &gxbb_vclk2_vencp1.hw,
732 [CLKID_GCLK_VENCI_INT0] = &gxbb_gclk_venci_int0.hw,
733 [CLKID_GCLK_VENCI_INT] = &gxbb_gclk_vencp_int.hw,
734 [CLKID_DAC_CLK] = &gxbb_dac_clk.hw,
735 [CLKID_AOCLK_GATE] = &gxbb_aoclk_gate.hw,
736 [CLKID_IEC958_GATE] = &gxbb_iec958_gate.hw,
737 [CLKID_ENC480P] = &gxbb_enc480p.hw,
738 [CLKID_RNG1] = &gxbb_rng1.hw,
739 [CLKID_GCLK_VENCI_INT1] = &gxbb_gclk_venci_int1.hw,
740 [CLKID_VCLK2_VENCLMCC] = &gxbb_vclk2_venclmcc.hw,
741 [CLKID_VCLK2_VENCL] = &gxbb_vclk2_vencl.hw,
742 [CLKID_VCLK_OTHER] = &gxbb_vclk_other.hw,
743 [CLKID_EDP] = &gxbb_edp.hw,
744 [CLKID_AO_MEDIA_CPU] = &gxbb_ao_media_cpu.hw,
745 [CLKID_AO_AHB_SRAM] = &gxbb_ao_ahb_sram.hw,
746 [CLKID_AO_AHB_BUS] = &gxbb_ao_ahb_bus.hw,
747 [CLKID_AO_IFACE] = &gxbb_ao_iface.hw,
748 [CLKID_AO_I2C] = &gxbb_ao_i2c.hw,
749 },
750 .num = NR_CLKS,
751};
752
753/* Convenience tables to populate base addresses in .probe */
754
755static struct meson_clk_pll *const gxbb_clk_plls[] = {
756 &gxbb_fixed_pll,
757 &gxbb_hdmi_pll,
758 &gxbb_sys_pll,
759 &gxbb_gp0_pll,
760};
761
762static struct meson_clk_mpll *const gxbb_clk_mplls[] = {
763 &gxbb_mpll0,
764 &gxbb_mpll1,
765 &gxbb_mpll2,
766};
767
768static struct clk_gate *gxbb_clk_gates[] = {
769 &gxbb_clk81,
770 &gxbb_ddr,
771 &gxbb_dos,
772 &gxbb_isa,
773 &gxbb_pl301,
774 &gxbb_periphs,
775 &gxbb_spicc,
776 &gxbb_i2c,
777 &gxbb_sar_adc,
778 &gxbb_smart_card,
779 &gxbb_rng0,
780 &gxbb_uart0,
781 &gxbb_sdhc,
782 &gxbb_stream,
783 &gxbb_async_fifo,
784 &gxbb_sdio,
785 &gxbb_abuf,
786 &gxbb_hiu_iface,
787 &gxbb_assist_misc,
788 &gxbb_spi,
789 &gxbb_i2s_spdif,
790 &gxbb_eth,
791 &gxbb_demux,
792 &gxbb_aiu_glue,
793 &gxbb_iec958,
794 &gxbb_i2s_out,
795 &gxbb_amclk,
796 &gxbb_aififo2,
797 &gxbb_mixer,
798 &gxbb_mixer_iface,
799 &gxbb_adc,
800 &gxbb_blkmv,
801 &gxbb_aiu,
802 &gxbb_uart1,
803 &gxbb_g2d,
804 &gxbb_usb0,
805 &gxbb_usb1,
806 &gxbb_reset,
807 &gxbb_nand,
808 &gxbb_dos_parser,
809 &gxbb_usb,
810 &gxbb_vdin1,
811 &gxbb_ahb_arb0,
812 &gxbb_efuse,
813 &gxbb_boot_rom,
814 &gxbb_ahb_data_bus,
815 &gxbb_ahb_ctrl_bus,
816 &gxbb_hdmi_intr_sync,
817 &gxbb_hdmi_pclk,
818 &gxbb_usb1_ddr_bridge,
819 &gxbb_usb0_ddr_bridge,
820 &gxbb_mmc_pclk,
821 &gxbb_dvin,
822 &gxbb_uart2,
823 &gxbb_sana,
824 &gxbb_vpu_intr,
825 &gxbb_sec_ahb_ahb3_bridge,
826 &gxbb_clk81_a53,
827 &gxbb_vclk2_venci0,
828 &gxbb_vclk2_venci1,
829 &gxbb_vclk2_vencp0,
830 &gxbb_vclk2_vencp1,
831 &gxbb_gclk_venci_int0,
832 &gxbb_gclk_vencp_int,
833 &gxbb_dac_clk,
834 &gxbb_aoclk_gate,
835 &gxbb_iec958_gate,
836 &gxbb_enc480p,
837 &gxbb_rng1,
838 &gxbb_gclk_venci_int1,
839 &gxbb_vclk2_venclmcc,
840 &gxbb_vclk2_vencl,
841 &gxbb_vclk_other,
842 &gxbb_edp,
843 &gxbb_ao_media_cpu,
844 &gxbb_ao_ahb_sram,
845 &gxbb_ao_ahb_bus,
846 &gxbb_ao_iface,
847 &gxbb_ao_i2c,
848};
849
850static int gxbb_clkc_probe(struct platform_device *pdev)
851{
852 void __iomem *clk_base;
853 int ret, clkid, i;
854 struct clk_hw *parent_hw;
855 struct clk *parent_clk;
856 struct device *dev = &pdev->dev;
857
858 /* Generic clocks and PLLs */
859 clk_base = of_iomap(dev->of_node, 0);
860 if (!clk_base) {
861 pr_err("%s: Unable to map clk base\n", __func__);
862 return -ENXIO;
863 }
864
865 /* Populate base address for PLLs */
866 for (i = 0; i < ARRAY_SIZE(gxbb_clk_plls); i++)
867 gxbb_clk_plls[i]->base = clk_base;
868
869 /* Populate base address for MPLLs */
870 for (i = 0; i < ARRAY_SIZE(gxbb_clk_mplls); i++)
871 gxbb_clk_mplls[i]->base = clk_base;
872
873 /* Populate the base address for CPU clk */
874 gxbb_cpu_clk.base = clk_base;
875
876 /* Populate the base address for the MPEG clks */
877 gxbb_mpeg_clk_sel.reg = clk_base + (u64)gxbb_mpeg_clk_sel.reg;
878 gxbb_mpeg_clk_div.reg = clk_base + (u64)gxbb_mpeg_clk_div.reg;
879
880 /* Populate base address for gates */
881 for (i = 0; i < ARRAY_SIZE(gxbb_clk_gates); i++)
882 gxbb_clk_gates[i]->reg = clk_base +
883 (u64)gxbb_clk_gates[i]->reg;
884
885 /*
886 * register all clks
887 */
888 for (clkid = 0; clkid < NR_CLKS; clkid++) {
889 ret = devm_clk_hw_register(dev, gxbb_hw_onecell_data.hws[clkid]);
890 if (ret)
891 goto iounmap;
892 }
893
894 /*
895 * Register CPU clk notifier
896 *
897 * FIXME this is wrong for a lot of reasons. First, the muxes should be
898 * struct clk_hw objects. Second, we shouldn't program the muxes in
899 * notifier handlers. The tricky programming sequence will be handled
900 * by the forthcoming coordinated clock rates mechanism once that
901 * feature is released.
902 *
903 * Furthermore, looking up the parent this way is terrible. At some
904 * point we will stop allocating a default struct clk when registering
905 * a new clk_hw, and this hack will no longer work. Releasing the ccr
906 * feature before that time solves the problem :-)
907 */
908 parent_hw = clk_hw_get_parent(&gxbb_cpu_clk.hw);
909 parent_clk = parent_hw->clk;
910 ret = clk_notifier_register(parent_clk, &gxbb_cpu_clk.clk_nb);
911 if (ret) {
912 pr_err("%s: failed to register clock notifier for cpu_clk\n",
913 __func__);
914 goto iounmap;
915 }
916
917 return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
918 &gxbb_hw_onecell_data);
919
920iounmap:
921 iounmap(clk_base);
922 return ret;
923}
924
925static const struct of_device_id gxbb_clkc_match_table[] = {
926 { .compatible = "amlogic,gxbb-clkc" },
927 { }
928};
929MODULE_DEVICE_TABLE(of, gxbb_match_table);
930
931static struct platform_driver gxbb_driver = {
932 .probe = gxbb_clkc_probe,
933 .driver = {
934 .name = "gxbb-clkc",
935 .of_match_table = gxbb_clkc_match_table,
936 },
937};
938
939static int __init gxbb_clkc_init(void)
940{
941 return platform_driver_register(&gxbb_driver);
942}
943module_init(gxbb_clkc_init);
944
945static void __exit gxbb_clkc_exit(void)
946{
947 platform_driver_unregister(&gxbb_driver);
948}
949module_exit(gxbb_clkc_exit);
950
951MODULE_DESCRIPTION("AmLogic S905 / GXBB Clock Controller Driver");
952MODULE_LICENSE("GPL v2");
953MODULE_ALIAS("platform:gxbb-clkc");
954MODULE_AUTHOR("Michael Turquette <mturquette@baylibre.com>");
diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h
new file mode 100644
index 000000000000..a2adf3448b59
--- /dev/null
+++ b/drivers/clk/meson/gxbb.h
@@ -0,0 +1,271 @@
1/*
2 * This file is provided under a dual BSD/GPLv2 license. When using or
3 * redistributing this file, you may do so under either license.
4 *
5 * GPL LICENSE SUMMARY
6 *
7 * Copyright (c) 2016 AmLogic, Inc.
8 * Author: Michael Turquette <mturquette@baylibre.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
22 * The full GNU General Public License is included in this distribution
23 * in the file called COPYING
24 *
25 * BSD LICENSE
26 *
27 * Copyright (c) 2016 BayLibre, Inc.
28 * Author: Michael Turquette <mturquette@baylibre.com>
29 *
30 * Redistribution and use in source and binary forms, with or without
31 * modification, are permitted provided that the following conditions
32 * are met:
33 *
34 * * Redistributions of source code must retain the above copyright
35 * notice, this list of conditions and the following disclaimer.
36 * * Redistributions in binary form must reproduce the above copyright
37 * notice, this list of conditions and the following disclaimer in
38 * the documentation and/or other materials provided with the
39 * distribution.
40 * * Neither the name of Intel Corporation nor the names of its
41 * contributors may be used to endorse or promote products derived
42 * from this software without specific prior written permission.
43 *
44 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
45 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
46 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
47 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
48 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
49 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
50 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
51 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
52 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
53 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
54 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
55 */
56
57#ifndef __GXBB_H
58#define __GXBB_H
59
60/*
61 * Clock controller register offsets
62 *
63 * Register offsets from the data sheet are listed in comment blocks below.
64 * Those offsets must be multiplied by 4 before adding them to the base address
65 * to get the right value
66 */
67#define SCR 0x2C /* 0x0b offset in data sheet */
68#define TIMEOUT_VALUE 0x3c /* 0x0f offset in data sheet */
69
70#define HHI_GP0_PLL_CNTL 0x40 /* 0x10 offset in data sheet */
71#define HHI_GP0_PLL_CNTL2 0x44 /* 0x11 offset in data sheet */
72#define HHI_GP0_PLL_CNTL3 0x48 /* 0x12 offset in data sheet */
73#define HHI_GP0_PLL_CNTL4 0x4c /* 0x13 offset in data sheet */
74
75#define HHI_XTAL_DIVN_CNTL 0xbc /* 0x2f offset in data sheet */
76#define HHI_TIMER90K 0xec /* 0x3b offset in data sheet */
77
78#define HHI_MEM_PD_REG0 0x100 /* 0x40 offset in data sheet */
79#define HHI_MEM_PD_REG1 0x104 /* 0x41 offset in data sheet */
80#define HHI_VPU_MEM_PD_REG1 0x108 /* 0x42 offset in data sheet */
81#define HHI_VIID_CLK_DIV 0x128 /* 0x4a offset in data sheet */
82#define HHI_VIID_CLK_CNTL 0x12c /* 0x4b offset in data sheet */
83
84#define HHI_GCLK_MPEG0 0x140 /* 0x50 offset in data sheet */
85#define HHI_GCLK_MPEG1 0x144 /* 0x51 offset in data sheet */
86#define HHI_GCLK_MPEG2 0x148 /* 0x52 offset in data sheet */
87#define HHI_GCLK_OTHER 0x150 /* 0x54 offset in data sheet */
88#define HHI_GCLK_AO 0x154 /* 0x55 offset in data sheet */
89#define HHI_SYS_OSCIN_CNTL 0x158 /* 0x56 offset in data sheet */
90#define HHI_SYS_CPU_CLK_CNTL1 0x15c /* 0x57 offset in data sheet */
91#define HHI_SYS_CPU_RESET_CNTL 0x160 /* 0x58 offset in data sheet */
92#define HHI_VID_CLK_DIV 0x164 /* 0x59 offset in data sheet */
93
94#define HHI_MPEG_CLK_CNTL 0x174 /* 0x5d offset in data sheet */
95#define HHI_AUD_CLK_CNTL 0x178 /* 0x5e offset in data sheet */
96#define HHI_VID_CLK_CNTL 0x17c /* 0x5f offset in data sheet */
97#define HHI_AUD_CLK_CNTL2 0x190 /* 0x64 offset in data sheet */
98#define HHI_VID_CLK_CNTL2 0x194 /* 0x65 offset in data sheet */
99#define HHI_SYS_CPU_CLK_CNTL0 0x19c /* 0x67 offset in data sheet */
100#define HHI_VID_PLL_CLK_DIV 0x1a0 /* 0x68 offset in data sheet */
101#define HHI_AUD_CLK_CNTL3 0x1a4 /* 0x69 offset in data sheet */
102#define HHI_MALI_CLK_CNTL 0x1b0 /* 0x6c offset in data sheet */
103#define HHI_VPU_CLK_CNTL 0x1bC /* 0x6f offset in data sheet */
104
105#define HHI_HDMI_CLK_CNTL 0x1CC /* 0x73 offset in data sheet */
106#define HHI_VDEC_CLK_CNTL 0x1E0 /* 0x78 offset in data sheet */
107#define HHI_VDEC2_CLK_CNTL 0x1E4 /* 0x79 offset in data sheet */
108#define HHI_VDEC3_CLK_CNTL 0x1E8 /* 0x7a offset in data sheet */
109#define HHI_VDEC4_CLK_CNTL 0x1EC /* 0x7b offset in data sheet */
110#define HHI_HDCP22_CLK_CNTL 0x1F0 /* 0x7c offset in data sheet */
111#define HHI_VAPBCLK_CNTL 0x1F4 /* 0x7d offset in data sheet */
112
113#define HHI_VPU_CLKB_CNTL 0x20C /* 0x83 offset in data sheet */
114#define HHI_USB_CLK_CNTL 0x220 /* 0x88 offset in data sheet */
115#define HHI_32K_CLK_CNTL 0x224 /* 0x89 offset in data sheet */
116#define HHI_GEN_CLK_CNTL 0x228 /* 0x8a offset in data sheet */
117#define HHI_GEN_CLK_CNTL 0x228 /* 0x8a offset in data sheet */
118
119#define HHI_PCM_CLK_CNTL 0x258 /* 0x96 offset in data sheet */
120#define HHI_NAND_CLK_CNTL 0x25C /* 0x97 offset in data sheet */
121#define HHI_SD_EMMC_CLK_CNTL 0x264 /* 0x99 offset in data sheet */
122
123#define HHI_MPLL_CNTL 0x280 /* 0xa0 offset in data sheet */
124#define HHI_MPLL_CNTL2 0x284 /* 0xa1 offset in data sheet */
125#define HHI_MPLL_CNTL3 0x288 /* 0xa2 offset in data sheet */
126#define HHI_MPLL_CNTL4 0x28C /* 0xa3 offset in data sheet */
127#define HHI_MPLL_CNTL5 0x290 /* 0xa4 offset in data sheet */
128#define HHI_MPLL_CNTL6 0x294 /* 0xa5 offset in data sheet */
129#define HHI_MPLL_CNTL7 0x298 /* MP0, 0xa6 offset in data sheet */
130#define HHI_MPLL_CNTL8 0x29C /* MP1, 0xa7 offset in data sheet */
131#define HHI_MPLL_CNTL9 0x2A0 /* MP2, 0xa8 offset in data sheet */
132#define HHI_MPLL_CNTL10 0x2A4 /* MP2, 0xa9 offset in data sheet */
133
134#define HHI_MPLL3_CNTL0 0x2E0 /* 0xb8 offset in data sheet */
135#define HHI_MPLL3_CNTL1 0x2E4 /* 0xb9 offset in data sheet */
136#define HHI_VDAC_CNTL0 0x2F4 /* 0xbd offset in data sheet */
137#define HHI_VDAC_CNTL1 0x2F8 /* 0xbe offset in data sheet */
138
139#define HHI_SYS_PLL_CNTL 0x300 /* 0xc0 offset in data sheet */
140#define HHI_SYS_PLL_CNTL2 0x304 /* 0xc1 offset in data sheet */
141#define HHI_SYS_PLL_CNTL3 0x308 /* 0xc2 offset in data sheet */
142#define HHI_SYS_PLL_CNTL4 0x30c /* 0xc3 offset in data sheet */
143#define HHI_SYS_PLL_CNTL5 0x310 /* 0xc4 offset in data sheet */
144#define HHI_DPLL_TOP_I 0x318 /* 0xc6 offset in data sheet */
145#define HHI_DPLL_TOP2_I 0x31C /* 0xc7 offset in data sheet */
146#define HHI_HDMI_PLL_CNTL 0x320 /* 0xc8 offset in data sheet */
147#define HHI_HDMI_PLL_CNTL2 0x324 /* 0xc9 offset in data sheet */
148#define HHI_HDMI_PLL_CNTL3 0x328 /* 0xca offset in data sheet */
149#define HHI_HDMI_PLL_CNTL4 0x32C /* 0xcb offset in data sheet */
150#define HHI_HDMI_PLL_CNTL5 0x330 /* 0xcc offset in data sheet */
151#define HHI_HDMI_PLL_CNTL6 0x334 /* 0xcd offset in data sheet */
152#define HHI_HDMI_PLL_CNTL_I 0x338 /* 0xce offset in data sheet */
153#define HHI_HDMI_PLL_CNTL7 0x33C /* 0xcf offset in data sheet */
154
155#define HHI_HDMI_PHY_CNTL0 0x3A0 /* 0xe8 offset in data sheet */
156#define HHI_HDMI_PHY_CNTL1 0x3A4 /* 0xe9 offset in data sheet */
157#define HHI_HDMI_PHY_CNTL2 0x3A8 /* 0xea offset in data sheet */
158#define HHI_HDMI_PHY_CNTL3 0x3AC /* 0xeb offset in data sheet */
159
160#define HHI_VID_LOCK_CLK_CNTL 0x3C8 /* 0xf2 offset in data sheet */
161#define HHI_BT656_CLK_CNTL 0x3D4 /* 0xf5 offset in data sheet */
162#define HHI_SAR_CLK_CNTL 0x3D8 /* 0xf6 offset in data sheet */
163
164/*
165 * CLKID index values
166 *
167 * These indices are entirely contrived and do not map onto the hardware.
168 * Migrate them out of this header and into the DT header file when they need
169 * to be exposed to client nodes in DT: include/dt-bindings/clock/gxbb-clkc.h
170 */
171#define CLKID_SYS_PLL 0
172/* CLKID_CPUCLK */
173#define CLKID_HDMI_PLL 2
174#define CLKID_FIXED_PLL 3
175#define CLKID_FCLK_DIV2 4
176#define CLKID_FCLK_DIV3 5
177#define CLKID_FCLK_DIV4 6
178#define CLKID_FCLK_DIV5 7
179#define CLKID_FCLK_DIV7 8
180#define CLKID_GP0_PLL 9
181#define CLKID_MPEG_SEL 10
182#define CLKID_MPEG_DIV 11
183/* CLKID_CLK81 */
184#define CLKID_MPLL0 13
185#define CLKID_MPLL1 14
186#define CLKID_MPLL2 15
187#define CLKID_DDR 16
188#define CLKID_DOS 17
189#define CLKID_ISA 18
190#define CLKID_PL301 19
191#define CLKID_PERIPHS 20
192#define CLKID_SPICC 21
193#define CLKID_I2C 22
194#define CLKID_SAR_ADC 23
195#define CLKID_SMART_CARD 24
196#define CLKID_RNG0 25
197#define CLKID_UART0 26
198#define CLKID_SDHC 27
199#define CLKID_STREAM 28
200#define CLKID_ASYNC_FIFO 29
201#define CLKID_SDIO 30
202#define CLKID_ABUF 31
203#define CLKID_HIU_IFACE 32
204#define CLKID_ASSIST_MISC 33
205#define CLKID_SPI 34
206#define CLKID_I2S_SPDIF 35
207#define CLKID_ETH 36
208#define CLKID_DEMUX 37
209#define CLKID_AIU_GLUE 38
210#define CLKID_IEC958 39
211#define CLKID_I2S_OUT 40
212#define CLKID_AMCLK 41
213#define CLKID_AIFIFO2 42
214#define CLKID_MIXER 43
215#define CLKID_MIXER_IFACE 44
216#define CLKID_ADC 45
217#define CLKID_BLKMV 46
218#define CLKID_AIU 47
219#define CLKID_UART1 48
220#define CLKID_G2D 49
221#define CLKID_USB0 50
222#define CLKID_USB1 51
223#define CLKID_RESET 52
224#define CLKID_NAND 53
225#define CLKID_DOS_PARSER 54
226#define CLKID_USB 55
227#define CLKID_VDIN1 56
228#define CLKID_AHB_ARB0 57
229#define CLKID_EFUSE 58
230#define CLKID_BOOT_ROM 59
231#define CLKID_AHB_DATA_BUS 60
232#define CLKID_AHB_CTRL_BUS 61
233#define CLKID_HDMI_INTR_SYNC 62
234#define CLKID_HDMI_PCLK 63
235#define CLKID_USB1_DDR_BRIDGE 64
236#define CLKID_USB0_DDR_BRIDGE 65
237#define CLKID_MMC_PCLK 66
238#define CLKID_DVIN 67
239#define CLKID_UART2 68
240#define CLKID_SANA 69
241#define CLKID_VPU_INTR 70
242#define CLKID_SEC_AHB_AHB3_BRIDGE 71
243#define CLKID_CLK81_A53 72
244#define CLKID_VCLK2_VENCI0 73
245#define CLKID_VCLK2_VENCI1 74
246#define CLKID_VCLK2_VENCP0 75
247#define CLKID_VCLK2_VENCP1 76
248#define CLKID_GCLK_VENCI_INT0 77
249#define CLKID_GCLK_VENCI_INT 78
250#define CLKID_DAC_CLK 79
251#define CLKID_AOCLK_GATE 80
252#define CLKID_IEC958_GATE 81
253#define CLKID_ENC480P 82
254#define CLKID_RNG1 83
255#define CLKID_GCLK_VENCI_INT1 84
256#define CLKID_VCLK2_VENCLMCC 85
257#define CLKID_VCLK2_VENCL 86
258#define CLKID_VCLK_OTHER 87
259#define CLKID_EDP 88
260#define CLKID_AO_MEDIA_CPU 89
261#define CLKID_AO_AHB_SRAM 90
262#define CLKID_AO_AHB_BUS 91
263#define CLKID_AO_IFACE 92
264#define CLKID_AO_I2C 93
265
266#define NR_CLKS 94
267
268/* include the CLKIDs that have been made part of the stable DT binding */
269#include <dt-bindings/clock/gxbb-clkc.h>
270
271#endif /* __GXBB_H */
diff --git a/include/dt-bindings/clock/gxbb-clkc.h b/include/dt-bindings/clock/gxbb-clkc.h
new file mode 100644
index 000000000000..f889d80246cb
--- /dev/null
+++ b/include/dt-bindings/clock/gxbb-clkc.h
@@ -0,0 +1,12 @@
1/*
2 * GXBB clock tree IDs
3 */
4
5#ifndef __GXBB_CLKC_H
6#define __GXBB_CLKC_H
7
8#define CLKID_CPUCLK 1
9#define CLKID_CLK81 12
10#define CLKID_ETH 36
11
12#endif /* __GXBB_CLKC_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-22 20:33:23 -0400