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authorBard Liao <bardliao@realtek.com>2016-10-20 23:02:28 -0400
committerMark Brown <broonie@kernel.org>2016-10-24 12:50:06 -0400
commit73444723b2b5b53ca2759daeecda90c9c7fa3629 (patch)
tree82bfe2a7529f00077fa663cd5b25a83cdca93805
parent7e7e76bd5693dc940dfea7df9e7b58655f0eae00 (diff)
ASoC: rt5663: rename rt5668 as rt5663 v2
The "rt5668" codec supported in this driver is actually a revision of "rt5663". So the patch is renamed to "rt5663 v2" Signed-off-by: Bard Liao <bardliao@realtek.com> Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat
-rw-r--r--Documentation/devicetree/bindings/sound/rt5663.txt6
-rw-r--r--sound/soc/codecs/rt5663.c1130
-rw-r--r--sound/soc/codecs/rt5663.h1154
3 files changed, 1140 insertions, 1150 deletions
diff --git a/Documentation/devicetree/bindings/sound/rt5663.txt b/Documentation/devicetree/bindings/sound/rt5663.txt
index 7d3c974c6e2e..70eaeaed2b18 100644
--- a/Documentation/devicetree/bindings/sound/rt5663.txt
+++ b/Documentation/devicetree/bindings/sound/rt5663.txt
@@ -1,10 +1,10 @@
1RT5663/RT5668 audio CODEC 1RT5663 audio CODEC
2 2
3This device supports I2C only. 3This device supports I2C only.
4 4
5Required properties: 5Required properties:
6 6
7- compatible : One of "realtek,rt5663" or "realtek,rt5668". 7- compatible : "realtek,rt5663".
8 8
9- reg : The I2C address of the device. 9- reg : The I2C address of the device.
10 10
@@ -12,7 +12,7 @@ Required properties:
12 12
13Optional properties: 13Optional properties:
14 14
15Pins on the device (for linking into audio routes) for RT5663/RT5668: 15Pins on the device (for linking into audio routes) for RT5663:
16 16
17 * IN1P 17 * IN1P
18 * IN1N 18 * IN1N
diff --git a/sound/soc/codecs/rt5663.c b/sound/soc/codecs/rt5663.c
index f30e0b461602..ff968d93f31f 100644
--- a/sound/soc/codecs/rt5663.c
+++ b/sound/soc/codecs/rt5663.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * rt5663.c -- RT5668/RT5663 ALSA SoC audio codec driver 2 * rt5663.c -- RT5663 ALSA SoC audio codec driver
3 * 3 *
4 * Copyright 2016 Realtek Semiconductor Corp. 4 * Copyright 2016 Realtek Semiconductor Corp.
5 * Author: Jack Yu <jack.yu@realtek.com> 5 * Author: Jack Yu <jack.yu@realtek.com>
@@ -30,12 +30,12 @@
30#include "rt5663.h" 30#include "rt5663.h"
31#include "rl6231.h" 31#include "rl6231.h"
32 32
33#define RT5668_DEVICE_ID 0x6451 33#define RT5663_DEVICE_ID_2 0x6451
34#define RT5663_DEVICE_ID 0x6406 34#define RT5663_DEVICE_ID_1 0x6406
35 35
36enum { 36enum {
37 CODEC_TYPE_RT5668, 37 CODEC_VER_1,
38 CODEC_TYPE_RT5663, 38 CODEC_VER_0,
39}; 39};
40 40
41struct rt5663_priv { 41struct rt5663_priv {
@@ -45,7 +45,7 @@ struct rt5663_priv {
45 struct snd_soc_jack *hs_jack; 45 struct snd_soc_jack *hs_jack;
46 struct timer_list btn_check_timer; 46 struct timer_list btn_check_timer;
47 47
48 int codec_type; 48 int codec_ver;
49 int sysclk; 49 int sysclk;
50 int sysclk_src; 50 int sysclk_src;
51 int lrck; 51 int lrck;
@@ -57,7 +57,7 @@ struct rt5663_priv {
57 int jack_type; 57 int jack_type;
58}; 58};
59 59
60static const struct reg_default rt5668_reg[] = { 60static const struct reg_default rt5663_v2_reg[] = {
61 { 0x0000, 0x0000 }, 61 { 0x0000, 0x0000 },
62 { 0x0001, 0xc8c8 }, 62 { 0x0001, 0xc8c8 },
63 { 0x0002, 0x8080 }, 63 { 0x0002, 0x8080 },
@@ -730,7 +730,7 @@ static bool rt5663_volatile_register(struct device *dev, unsigned int reg)
730 case RT5663_ADC_EQ_1: 730 case RT5663_ADC_EQ_1:
731 case RT5663_INT_ST_1: 731 case RT5663_INT_ST_1:
732 case RT5663_INT_ST_2: 732 case RT5663_INT_ST_2:
733 case RT5663_GPIO_STA: 733 case RT5663_GPIO_STA1:
734 case RT5663_SIN_GEN_1: 734 case RT5663_SIN_GEN_1:
735 case RT5663_IL_CMD_1: 735 case RT5663_IL_CMD_1:
736 case RT5663_IL_CMD_5: 736 case RT5663_IL_CMD_5:
@@ -846,7 +846,7 @@ static bool rt5663_readable_register(struct device *dev, unsigned int reg)
846 case RT5663_INT_ST_2: 846 case RT5663_INT_ST_2:
847 case RT5663_GPIO_1: 847 case RT5663_GPIO_1:
848 case RT5663_GPIO_2: 848 case RT5663_GPIO_2:
849 case RT5663_GPIO_STA: 849 case RT5663_GPIO_STA1:
850 case RT5663_SIN_GEN_1: 850 case RT5663_SIN_GEN_1:
851 case RT5663_SIN_GEN_2: 851 case RT5663_SIN_GEN_2:
852 case RT5663_SIN_GEN_3: 852 case RT5663_SIN_GEN_3:
@@ -1036,23 +1036,23 @@ static bool rt5663_readable_register(struct device *dev, unsigned int reg)
1036 } 1036 }
1037} 1037}
1038 1038
1039static bool rt5668_volatile_register(struct device *dev, unsigned int reg) 1039static bool rt5663_v2_volatile_register(struct device *dev, unsigned int reg)
1040{ 1040{
1041 switch (reg) { 1041 switch (reg) {
1042 case RT5663_RESET: 1042 case RT5663_RESET:
1043 case RT5668_CBJ_TYPE_2: 1043 case RT5663_CBJ_TYPE_2:
1044 case RT5668_PDM_OUT_CTL: 1044 case RT5663_PDM_OUT_CTL:
1045 case RT5668_PDM_I2C_DATA_CTL1: 1045 case RT5663_PDM_I2C_DATA_CTL1:
1046 case RT5668_PDM_I2C_DATA_CTL4: 1046 case RT5663_PDM_I2C_DATA_CTL4:
1047 case RT5668_ALC_BK_GAIN: 1047 case RT5663_ALC_BK_GAIN:
1048 case RT5663_PLL_2: 1048 case RT5663_PLL_2:
1049 case RT5663_MICBIAS_1: 1049 case RT5663_MICBIAS_1:
1050 case RT5663_ADC_EQ_1: 1050 case RT5663_ADC_EQ_1:
1051 case RT5663_INT_ST_1: 1051 case RT5663_INT_ST_1:
1052 case RT5668_GPIO_STA: 1052 case RT5663_GPIO_STA2:
1053 case RT5663_IL_CMD_1: 1053 case RT5663_IL_CMD_1:
1054 case RT5663_IL_CMD_5: 1054 case RT5663_IL_CMD_5:
1055 case RT5668_A_JD_CTRL: 1055 case RT5663_A_JD_CTRL:
1056 case RT5663_JD_CTRL2: 1056 case RT5663_JD_CTRL2:
1057 case RT5663_VENDOR_ID: 1057 case RT5663_VENDOR_ID:
1058 case RT5663_VENDOR_ID_1: 1058 case RT5663_VENDOR_ID_1:
@@ -1061,15 +1061,15 @@ static bool rt5668_volatile_register(struct device *dev, unsigned int reg)
1061 case RT5663_STO_DRE_5: 1061 case RT5663_STO_DRE_5:
1062 case RT5663_STO_DRE_6: 1062 case RT5663_STO_DRE_6:
1063 case RT5663_STO_DRE_7: 1063 case RT5663_STO_DRE_7:
1064 case RT5668_MONO_DYNA_6: 1064 case RT5663_MONO_DYNA_6:
1065 case RT5668_STO1_SIL_DET: 1065 case RT5663_STO1_SIL_DET:
1066 case RT5668_MONOL_SIL_DET: 1066 case RT5663_MONOL_SIL_DET:
1067 case RT5668_MONOR_SIL_DET: 1067 case RT5663_MONOR_SIL_DET:
1068 case RT5668_STO2_DAC_SIL: 1068 case RT5663_STO2_DAC_SIL:
1069 case RT5668_MONO_AMP_CAL_ST1: 1069 case RT5663_MONO_AMP_CAL_ST1:
1070 case RT5668_MONO_AMP_CAL_ST2: 1070 case RT5663_MONO_AMP_CAL_ST2:
1071 case RT5668_MONO_AMP_CAL_ST3: 1071 case RT5663_MONO_AMP_CAL_ST3:
1072 case RT5668_MONO_AMP_CAL_ST4: 1072 case RT5663_MONO_AMP_CAL_ST4:
1073 case RT5663_HP_IMP_SEN_2: 1073 case RT5663_HP_IMP_SEN_2:
1074 case RT5663_HP_IMP_SEN_3: 1074 case RT5663_HP_IMP_SEN_3:
1075 case RT5663_HP_IMP_SEN_4: 1075 case RT5663_HP_IMP_SEN_4:
@@ -1083,218 +1083,218 @@ static bool rt5668_volatile_register(struct device *dev, unsigned int reg)
1083 case RT5663_HP_CALIB_ST7: 1083 case RT5663_HP_CALIB_ST7:
1084 case RT5663_HP_CALIB_ST8: 1084 case RT5663_HP_CALIB_ST8:
1085 case RT5663_HP_CALIB_ST9: 1085 case RT5663_HP_CALIB_ST9:
1086 case RT5668_HP_CALIB_ST10: 1086 case RT5663_HP_CALIB_ST10:
1087 case RT5668_HP_CALIB_ST11: 1087 case RT5663_HP_CALIB_ST11:
1088 return true; 1088 return true;
1089 default: 1089 default:
1090 return false; 1090 return false;
1091 } 1091 }
1092} 1092}
1093 1093
1094static bool rt5668_readable_register(struct device *dev, unsigned int reg) 1094static bool rt5663_v2_readable_register(struct device *dev, unsigned int reg)
1095{ 1095{
1096 switch (reg) { 1096 switch (reg) {
1097 case RT5668_LOUT_CTRL: 1097 case RT5663_LOUT_CTRL:
1098 case RT5668_HP_AMP_2: 1098 case RT5663_HP_AMP_2:
1099 case RT5668_MONO_OUT: 1099 case RT5663_MONO_OUT:
1100 case RT5668_MONO_GAIN: 1100 case RT5663_MONO_GAIN:
1101 case RT5668_AEC_BST: 1101 case RT5663_AEC_BST:
1102 case RT5668_IN1_IN2: 1102 case RT5663_IN1_IN2:
1103 case RT5668_IN3_IN4: 1103 case RT5663_IN3_IN4:
1104 case RT5668_INL1_INR1: 1104 case RT5663_INL1_INR1:
1105 case RT5668_CBJ_TYPE_2: 1105 case RT5663_CBJ_TYPE_2:
1106 case RT5668_CBJ_TYPE_3: 1106 case RT5663_CBJ_TYPE_3:
1107 case RT5668_CBJ_TYPE_4: 1107 case RT5663_CBJ_TYPE_4:
1108 case RT5668_CBJ_TYPE_5: 1108 case RT5663_CBJ_TYPE_5:
1109 case RT5668_CBJ_TYPE_8: 1109 case RT5663_CBJ_TYPE_8:
1110 case RT5668_DAC3_DIG_VOL: 1110 case RT5663_DAC3_DIG_VOL:
1111 case RT5668_DAC3_CTRL: 1111 case RT5663_DAC3_CTRL:
1112 case RT5668_MONO_ADC_DIG_VOL: 1112 case RT5663_MONO_ADC_DIG_VOL:
1113 case RT5668_STO2_ADC_DIG_VOL: 1113 case RT5663_STO2_ADC_DIG_VOL:
1114 case RT5668_MONO_ADC_BST_GAIN: 1114 case RT5663_MONO_ADC_BST_GAIN:
1115 case RT5668_STO2_ADC_BST_GAIN: 1115 case RT5663_STO2_ADC_BST_GAIN:
1116 case RT5668_SIDETONE_CTRL: 1116 case RT5663_SIDETONE_CTRL:
1117 case RT5668_MONO1_ADC_MIXER: 1117 case RT5663_MONO1_ADC_MIXER:
1118 case RT5668_STO2_ADC_MIXER: 1118 case RT5663_STO2_ADC_MIXER:
1119 case RT5668_MONO_DAC_MIXER: 1119 case RT5663_MONO_DAC_MIXER:
1120 case RT5668_DAC2_SRC_CTRL: 1120 case RT5663_DAC2_SRC_CTRL:
1121 case RT5668_IF_3_4_DATA_CTL: 1121 case RT5663_IF_3_4_DATA_CTL:
1122 case RT5668_IF_5_DATA_CTL: 1122 case RT5663_IF_5_DATA_CTL:
1123 case RT5668_PDM_OUT_CTL: 1123 case RT5663_PDM_OUT_CTL:
1124 case RT5668_PDM_I2C_DATA_CTL1: 1124 case RT5663_PDM_I2C_DATA_CTL1:
1125 case RT5668_PDM_I2C_DATA_CTL2: 1125 case RT5663_PDM_I2C_DATA_CTL2:
1126 case RT5668_PDM_I2C_DATA_CTL3: 1126 case RT5663_PDM_I2C_DATA_CTL3:
1127 case RT5668_PDM_I2C_DATA_CTL4: 1127 case RT5663_PDM_I2C_DATA_CTL4:
1128 case RT5668_RECMIX1_NEW: 1128 case RT5663_RECMIX1_NEW:
1129 case RT5668_RECMIX1L_0: 1129 case RT5663_RECMIX1L_0:
1130 case RT5668_RECMIX1L: 1130 case RT5663_RECMIX1L:
1131 case RT5668_RECMIX1R_0: 1131 case RT5663_RECMIX1R_0:
1132 case RT5668_RECMIX1R: 1132 case RT5663_RECMIX1R:
1133 case RT5668_RECMIX2_NEW: 1133 case RT5663_RECMIX2_NEW:
1134 case RT5668_RECMIX2_L_2: 1134 case RT5663_RECMIX2_L_2:
1135 case RT5668_RECMIX2_R: 1135 case RT5663_RECMIX2_R:
1136 case RT5668_RECMIX2_R_2: 1136 case RT5663_RECMIX2_R_2:
1137 case RT5668_CALIB_REC_LR: 1137 case RT5663_CALIB_REC_LR:
1138 case RT5668_ALC_BK_GAIN: 1138 case RT5663_ALC_BK_GAIN:
1139 case RT5668_MONOMIX_GAIN: 1139 case RT5663_MONOMIX_GAIN:
1140 case RT5668_MONOMIX_IN_GAIN: 1140 case RT5663_MONOMIX_IN_GAIN:
1141 case RT5668_OUT_MIXL_GAIN: 1141 case RT5663_OUT_MIXL_GAIN:
1142 case RT5668_OUT_LMIX_IN_GAIN: 1142 case RT5663_OUT_LMIX_IN_GAIN:
1143 case RT5668_OUT_RMIX_IN_GAIN: 1143 case RT5663_OUT_RMIX_IN_GAIN:
1144 case RT5668_OUT_RMIX_IN_GAIN1: 1144 case RT5663_OUT_RMIX_IN_GAIN1:
1145 case RT5668_LOUT_MIXER_CTRL: 1145 case RT5663_LOUT_MIXER_CTRL:
1146 case RT5668_PWR_VOL: 1146 case RT5663_PWR_VOL:
1147 case RT5668_ADCDAC_RST: 1147 case RT5663_ADCDAC_RST:
1148 case RT5668_I2S34_SDP: 1148 case RT5663_I2S34_SDP:
1149 case RT5668_I2S5_SDP: 1149 case RT5663_I2S5_SDP:
1150 case RT5668_TDM_5: 1150 case RT5663_TDM_6:
1151 case RT5668_TDM_6: 1151 case RT5663_TDM_7:
1152 case RT5668_TDM_7: 1152 case RT5663_TDM_8:
1153 case RT5668_TDM_8: 1153 case RT5663_TDM_9:
1154 case RT5668_ASRC_3: 1154 case RT5663_ASRC_3:
1155 case RT5668_ASRC_6: 1155 case RT5663_ASRC_6:
1156 case RT5668_ASRC_7: 1156 case RT5663_ASRC_7:
1157 case RT5668_PLL_TRK_13: 1157 case RT5663_PLL_TRK_13:
1158 case RT5668_I2S_M_CLK_CTL: 1158 case RT5663_I2S_M_CLK_CTL:
1159 case RT5668_FDIV_I2S34_M_CLK: 1159 case RT5663_FDIV_I2S34_M_CLK:
1160 case RT5668_FDIV_I2S34_M_CLK2: 1160 case RT5663_FDIV_I2S34_M_CLK2:
1161 case RT5668_FDIV_I2S5_M_CLK: 1161 case RT5663_FDIV_I2S5_M_CLK:
1162 case RT5668_FDIV_I2S5_M_CLK2: 1162 case RT5663_FDIV_I2S5_M_CLK2:
1163 case RT5668_IRQ_4: 1163 case RT5663_V2_IRQ_4:
1164 case RT5668_GPIO_3: 1164 case RT5663_GPIO_3:
1165 case RT5668_GPIO_4: 1165 case RT5663_GPIO_4:
1166 case RT5668_GPIO_STA: 1166 case RT5663_GPIO_STA2:
1167 case RT5668_HP_AMP_DET1: 1167 case RT5663_HP_AMP_DET1:
1168 case RT5668_HP_AMP_DET2: 1168 case RT5663_HP_AMP_DET2:
1169 case RT5668_HP_AMP_DET3: 1169 case RT5663_HP_AMP_DET3:
1170 case RT5668_MID_BD_HP_AMP: 1170 case RT5663_MID_BD_HP_AMP:
1171 case RT5668_LOW_BD_HP_AMP: 1171 case RT5663_LOW_BD_HP_AMP:
1172 case RT5668_SOF_VOL_ZC2: 1172 case RT5663_SOF_VOL_ZC2:
1173 case RT5668_ADC_STO2_ADJ1: 1173 case RT5663_ADC_STO2_ADJ1:
1174 case RT5668_ADC_STO2_ADJ2: 1174 case RT5663_ADC_STO2_ADJ2:
1175 case RT5668_A_JD_CTRL: 1175 case RT5663_A_JD_CTRL:
1176 case RT5668_JD1_TRES_CTRL: 1176 case RT5663_JD1_TRES_CTRL:
1177 case RT5668_JD2_TRES_CTRL: 1177 case RT5663_JD2_TRES_CTRL:
1178 case RT5668_JD_CTRL2: 1178 case RT5663_V2_JD_CTRL2:
1179 case RT5668_DUM_REG_2: 1179 case RT5663_DUM_REG_2:
1180 case RT5668_DUM_REG_3: 1180 case RT5663_DUM_REG_3:
1181 case RT5663_VENDOR_ID: 1181 case RT5663_VENDOR_ID:
1182 case RT5663_VENDOR_ID_1: 1182 case RT5663_VENDOR_ID_1:
1183 case RT5663_VENDOR_ID_2: 1183 case RT5663_VENDOR_ID_2:
1184 case RT5668_DACADC_DIG_VOL2: 1184 case RT5663_DACADC_DIG_VOL2:
1185 case RT5668_DIG_IN_PIN2: 1185 case RT5663_DIG_IN_PIN2:
1186 case RT5668_PAD_DRV_CTL1: 1186 case RT5663_PAD_DRV_CTL1:
1187 case RT5668_SOF_RAM_DEPOP: 1187 case RT5663_SOF_RAM_DEPOP:
1188 case RT5668_VOL_TEST: 1188 case RT5663_VOL_TEST:
1189 case RT5668_TEST_MODE_3: 1189 case RT5663_TEST_MODE_4:
1190 case RT5668_TEST_MODE_4: 1190 case RT5663_TEST_MODE_5:
1191 case RT5663_STO_DRE_9: 1191 case RT5663_STO_DRE_9:
1192 case RT5668_MONO_DYNA_1: 1192 case RT5663_MONO_DYNA_1:
1193 case RT5668_MONO_DYNA_2: 1193 case RT5663_MONO_DYNA_2:
1194 case RT5668_MONO_DYNA_3: 1194 case RT5663_MONO_DYNA_3:
1195 case RT5668_MONO_DYNA_4: 1195 case RT5663_MONO_DYNA_4:
1196 case RT5668_MONO_DYNA_5: 1196 case RT5663_MONO_DYNA_5:
1197 case RT5668_MONO_DYNA_6: 1197 case RT5663_MONO_DYNA_6:
1198 case RT5668_STO1_SIL_DET: 1198 case RT5663_STO1_SIL_DET:
1199 case RT5668_MONOL_SIL_DET: 1199 case RT5663_MONOL_SIL_DET:
1200 case RT5668_MONOR_SIL_DET: 1200 case RT5663_MONOR_SIL_DET:
1201 case RT5668_STO2_DAC_SIL: 1201 case RT5663_STO2_DAC_SIL:
1202 case RT5668_PWR_SAV_CTL1: 1202 case RT5663_PWR_SAV_CTL1:
1203 case RT5668_PWR_SAV_CTL2: 1203 case RT5663_PWR_SAV_CTL2:
1204 case RT5668_PWR_SAV_CTL3: 1204 case RT5663_PWR_SAV_CTL3:
1205 case RT5668_PWR_SAV_CTL4: 1205 case RT5663_PWR_SAV_CTL4:
1206 case RT5668_PWR_SAV_CTL5: 1206 case RT5663_PWR_SAV_CTL5:
1207 case RT5668_PWR_SAV_CTL6: 1207 case RT5663_PWR_SAV_CTL6:
1208 case RT5668_MONO_AMP_CAL1: 1208 case RT5663_MONO_AMP_CAL1:
1209 case RT5668_MONO_AMP_CAL2: 1209 case RT5663_MONO_AMP_CAL2:
1210 case RT5668_MONO_AMP_CAL3: 1210 case RT5663_MONO_AMP_CAL3:
1211 case RT5668_MONO_AMP_CAL4: 1211 case RT5663_MONO_AMP_CAL4:
1212 case RT5668_MONO_AMP_CAL5: 1212 case RT5663_MONO_AMP_CAL5:
1213 case RT5668_MONO_AMP_CAL6: 1213 case RT5663_MONO_AMP_CAL6:
1214 case RT5668_MONO_AMP_CAL7: 1214 case RT5663_MONO_AMP_CAL7:
1215 case RT5668_MONO_AMP_CAL_ST1: 1215 case RT5663_MONO_AMP_CAL_ST1:
1216 case RT5668_MONO_AMP_CAL_ST2: 1216 case RT5663_MONO_AMP_CAL_ST2:
1217 case RT5668_MONO_AMP_CAL_ST3: 1217 case RT5663_MONO_AMP_CAL_ST3:
1218 case RT5668_MONO_AMP_CAL_ST4: 1218 case RT5663_MONO_AMP_CAL_ST4:
1219 case RT5668_MONO_AMP_CAL_ST5: 1219 case RT5663_MONO_AMP_CAL_ST5:
1220 case RT5668_HP_IMP_SEN_13: 1220 case RT5663_V2_HP_IMP_SEN_13:
1221 case RT5668_HP_IMP_SEN_14: 1221 case RT5663_V2_HP_IMP_SEN_14:
1222 case RT5668_HP_IMP_SEN_6: 1222 case RT5663_V2_HP_IMP_SEN_6:
1223 case RT5668_HP_IMP_SEN_7: 1223 case RT5663_V2_HP_IMP_SEN_7:
1224 case RT5668_HP_IMP_SEN_8: 1224 case RT5663_V2_HP_IMP_SEN_8:
1225 case RT5668_HP_IMP_SEN_9: 1225 case RT5663_V2_HP_IMP_SEN_9:
1226 case RT5668_HP_IMP_SEN_10: 1226 case RT5663_V2_HP_IMP_SEN_10:
1227 case RT5668_HP_LOGIC_3: 1227 case RT5663_HP_LOGIC_3:
1228 case RT5668_HP_CALIB_ST10: 1228 case RT5663_HP_CALIB_ST10:
1229 case RT5668_HP_CALIB_ST11: 1229 case RT5663_HP_CALIB_ST11:
1230 case RT5668_PRO_REG_TBL_4: 1230 case RT5663_PRO_REG_TBL_4:
1231 case RT5668_PRO_REG_TBL_5: 1231 case RT5663_PRO_REG_TBL_5:
1232 case RT5668_PRO_REG_TBL_6: 1232 case RT5663_PRO_REG_TBL_6:
1233 case RT5668_PRO_REG_TBL_7: 1233 case RT5663_PRO_REG_TBL_7:
1234 case RT5668_PRO_REG_TBL_8: 1234 case RT5663_PRO_REG_TBL_8:
1235 case RT5668_PRO_REG_TBL_9: 1235 case RT5663_PRO_REG_TBL_9:
1236 case RT5668_SAR_ADC_INL_1: 1236 case RT5663_SAR_ADC_INL_1:
1237 case RT5668_SAR_ADC_INL_2: 1237 case RT5663_SAR_ADC_INL_2:
1238 case RT5668_SAR_ADC_INL_3: 1238 case RT5663_SAR_ADC_INL_3:
1239 case RT5668_SAR_ADC_INL_4: 1239 case RT5663_SAR_ADC_INL_4:
1240 case RT5668_SAR_ADC_INL_5: 1240 case RT5663_SAR_ADC_INL_5:
1241 case RT5668_SAR_ADC_INL_6: 1241 case RT5663_SAR_ADC_INL_6:
1242 case RT5668_SAR_ADC_INL_7: 1242 case RT5663_SAR_ADC_INL_7:
1243 case RT5668_SAR_ADC_INL_8: 1243 case RT5663_SAR_ADC_INL_8:
1244 case RT5668_SAR_ADC_INL_9: 1244 case RT5663_SAR_ADC_INL_9:
1245 case RT5668_SAR_ADC_INL_10: 1245 case RT5663_SAR_ADC_INL_10:
1246 case RT5668_SAR_ADC_INL_11: 1246 case RT5663_SAR_ADC_INL_11:
1247 case RT5668_SAR_ADC_INL_12: 1247 case RT5663_SAR_ADC_INL_12:
1248 case RT5668_DRC_CTRL_1: 1248 case RT5663_DRC_CTRL_1:
1249 case RT5668_DRC1_CTRL_2: 1249 case RT5663_DRC1_CTRL_2:
1250 case RT5668_DRC1_CTRL_3: 1250 case RT5663_DRC1_CTRL_3:
1251 case RT5668_DRC1_CTRL_4: 1251 case RT5663_DRC1_CTRL_4:
1252 case RT5668_DRC1_CTRL_5: 1252 case RT5663_DRC1_CTRL_5:
1253 case RT5668_DRC1_CTRL_6: 1253 case RT5663_DRC1_CTRL_6:
1254 case RT5668_DRC1_HD_CTRL_1: 1254 case RT5663_DRC1_HD_CTRL_1:
1255 case RT5668_DRC1_HD_CTRL_2: 1255 case RT5663_DRC1_HD_CTRL_2:
1256 case RT5668_DRC1_PRI_REG_1: 1256 case RT5663_DRC1_PRI_REG_1:
1257 case RT5668_DRC1_PRI_REG_2: 1257 case RT5663_DRC1_PRI_REG_2:
1258 case RT5668_DRC1_PRI_REG_3: 1258 case RT5663_DRC1_PRI_REG_3:
1259 case RT5668_DRC1_PRI_REG_4: 1259 case RT5663_DRC1_PRI_REG_4:
1260 case RT5668_DRC1_PRI_REG_5: 1260 case RT5663_DRC1_PRI_REG_5:
1261 case RT5668_DRC1_PRI_REG_6: 1261 case RT5663_DRC1_PRI_REG_6:
1262 case RT5668_DRC1_PRI_REG_7: 1262 case RT5663_DRC1_PRI_REG_7:
1263 case RT5668_DRC1_PRI_REG_8: 1263 case RT5663_DRC1_PRI_REG_8:
1264 case RT5668_ALC_PGA_CTL_1: 1264 case RT5663_ALC_PGA_CTL_1:
1265 case RT5668_ALC_PGA_CTL_2: 1265 case RT5663_ALC_PGA_CTL_2:
1266 case RT5668_ALC_PGA_CTL_3: 1266 case RT5663_ALC_PGA_CTL_3:
1267 case RT5668_ALC_PGA_CTL_4: 1267 case RT5663_ALC_PGA_CTL_4:
1268 case RT5668_ALC_PGA_CTL_5: 1268 case RT5663_ALC_PGA_CTL_5:
1269 case RT5668_ALC_PGA_CTL_6: 1269 case RT5663_ALC_PGA_CTL_6:
1270 case RT5668_ALC_PGA_CTL_7: 1270 case RT5663_ALC_PGA_CTL_7:
1271 case RT5668_ALC_PGA_CTL_8: 1271 case RT5663_ALC_PGA_CTL_8:
1272 case RT5668_ALC_PGA_REG_1: 1272 case RT5663_ALC_PGA_REG_1:
1273 case RT5668_ALC_PGA_REG_2: 1273 case RT5663_ALC_PGA_REG_2:
1274 case RT5668_ALC_PGA_REG_3: 1274 case RT5663_ALC_PGA_REG_3:
1275 case RT5668_ADC_EQ_RECOV_1: 1275 case RT5663_ADC_EQ_RECOV_1:
1276 case RT5668_ADC_EQ_RECOV_2: 1276 case RT5663_ADC_EQ_RECOV_2:
1277 case RT5668_ADC_EQ_RECOV_3: 1277 case RT5663_ADC_EQ_RECOV_3:
1278 case RT5668_ADC_EQ_RECOV_4: 1278 case RT5663_ADC_EQ_RECOV_4:
1279 case RT5668_ADC_EQ_RECOV_5: 1279 case RT5663_ADC_EQ_RECOV_5:
1280 case RT5668_ADC_EQ_RECOV_6: 1280 case RT5663_ADC_EQ_RECOV_6:
1281 case RT5668_ADC_EQ_RECOV_7: 1281 case RT5663_ADC_EQ_RECOV_7:
1282 case RT5668_ADC_EQ_RECOV_8: 1282 case RT5663_ADC_EQ_RECOV_8:
1283 case RT5668_ADC_EQ_RECOV_9: 1283 case RT5663_ADC_EQ_RECOV_9:
1284 case RT5668_ADC_EQ_RECOV_10: 1284 case RT5663_ADC_EQ_RECOV_10:
1285 case RT5668_ADC_EQ_RECOV_11: 1285 case RT5663_ADC_EQ_RECOV_11:
1286 case RT5668_ADC_EQ_RECOV_12: 1286 case RT5663_ADC_EQ_RECOV_12:
1287 case RT5668_ADC_EQ_RECOV_13: 1287 case RT5663_ADC_EQ_RECOV_13:
1288 case RT5668_VID_HIDDEN: 1288 case RT5663_VID_HIDDEN:
1289 case RT5668_VID_CUSTOMER: 1289 case RT5663_VID_CUSTOMER:
1290 case RT5668_SCAN_MODE: 1290 case RT5663_SCAN_MODE:
1291 case RT5668_I2C_BYPA: 1291 case RT5663_I2C_BYPA:
1292 return true; 1292 return true;
1293 case RT5663_TDM_1: 1293 case RT5663_TDM_1:
1294 case RT5663_DEPOP_3: 1294 case RT5663_DEPOP_3:
1295 case RT5663_ASRC_11_2: 1295 case RT5663_ASRC_11_2:
1296 case RT5663_INT_ST_2: 1296 case RT5663_INT_ST_2:
1297 case RT5663_GPIO_STA: 1297 case RT5663_GPIO_STA1:
1298 case RT5663_SIN_GEN_1: 1298 case RT5663_SIN_GEN_1:
1299 case RT5663_SIN_GEN_2: 1299 case RT5663_SIN_GEN_2:
1300 case RT5663_SIN_GEN_3: 1300 case RT5663_SIN_GEN_3:
@@ -1344,7 +1344,7 @@ static bool rt5668_readable_register(struct device *dev, unsigned int reg)
1344} 1344}
1345 1345
1346static const DECLARE_TLV_DB_SCALE(rt5663_hp_vol_tlv, -2400, 150, 0); 1346static const DECLARE_TLV_DB_SCALE(rt5663_hp_vol_tlv, -2400, 150, 0);
1347static const DECLARE_TLV_DB_SCALE(rt5668_hp_vol_tlv, -2250, 150, 0); 1347static const DECLARE_TLV_DB_SCALE(rt5663_v2_hp_vol_tlv, -2250, 150, 0);
1348static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0); 1348static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
1349static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0); 1349static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
1350 1350
@@ -1374,57 +1374,57 @@ static void rt5663_enable_push_button_irq(struct snd_soc_codec *codec,
1374 1374
1375 if (enable) { 1375 if (enable) {
1376 snd_soc_update_bits(codec, RT5663_IL_CMD_6, 1376 snd_soc_update_bits(codec, RT5663_IL_CMD_6,
1377 RT5668_EN_4BTN_INL_MASK, RT5668_EN_4BTN_INL_EN); 1377 RT5663_EN_4BTN_INL_MASK, RT5663_EN_4BTN_INL_EN);
1378 /* reset in-line command */ 1378 /* reset in-line command */
1379 snd_soc_update_bits(codec, RT5663_IL_CMD_6, 1379 snd_soc_update_bits(codec, RT5663_IL_CMD_6,
1380 RT5668_RESET_4BTN_INL_MASK, 1380 RT5663_RESET_4BTN_INL_MASK,
1381 RT5668_RESET_4BTN_INL_RESET); 1381 RT5663_RESET_4BTN_INL_RESET);
1382 snd_soc_update_bits(codec, RT5663_IL_CMD_6, 1382 snd_soc_update_bits(codec, RT5663_IL_CMD_6,
1383 RT5668_RESET_4BTN_INL_MASK, 1383 RT5663_RESET_4BTN_INL_MASK,
1384 RT5668_RESET_4BTN_INL_NOR); 1384 RT5663_RESET_4BTN_INL_NOR);
1385 switch (rt5663->codec_type) { 1385 switch (rt5663->codec_ver) {
1386 case CODEC_TYPE_RT5668: 1386 case CODEC_VER_1:
1387 snd_soc_update_bits(codec, RT5663_IRQ_3, 1387 snd_soc_update_bits(codec, RT5663_IRQ_3,
1388 RT5668_EN_IRQ_INLINE_MASK, 1388 RT5663_V2_EN_IRQ_INLINE_MASK,
1389 RT5668_EN_IRQ_INLINE_NOR); 1389 RT5663_V2_EN_IRQ_INLINE_NOR);
1390 break; 1390 break;
1391 case CODEC_TYPE_RT5663: 1391 case CODEC_VER_0:
1392 snd_soc_update_bits(codec, RT5663_IRQ_2, 1392 snd_soc_update_bits(codec, RT5663_IRQ_2,
1393 RT5663_EN_IRQ_INLINE_MASK, 1393 RT5663_EN_IRQ_INLINE_MASK,
1394 RT5663_EN_IRQ_INLINE_NOR); 1394 RT5663_EN_IRQ_INLINE_NOR);
1395 break; 1395 break;
1396 default: 1396 default:
1397 dev_err(codec->dev, "Unknown CODEC_TYPE\n"); 1397 dev_err(codec->dev, "Unknown CODEC Version\n");
1398 } 1398 }
1399 } else { 1399 } else {
1400 switch (rt5663->codec_type) { 1400 switch (rt5663->codec_ver) {
1401 case CODEC_TYPE_RT5668: 1401 case CODEC_VER_1:
1402 snd_soc_update_bits(codec, RT5663_IRQ_3, 1402 snd_soc_update_bits(codec, RT5663_IRQ_3,
1403 RT5668_EN_IRQ_INLINE_MASK, 1403 RT5663_V2_EN_IRQ_INLINE_MASK,
1404 RT5668_EN_IRQ_INLINE_BYP); 1404 RT5663_V2_EN_IRQ_INLINE_BYP);
1405 break; 1405 break;
1406 case CODEC_TYPE_RT5663: 1406 case CODEC_VER_0:
1407 snd_soc_update_bits(codec, RT5663_IRQ_2, 1407 snd_soc_update_bits(codec, RT5663_IRQ_2,
1408 RT5663_EN_IRQ_INLINE_MASK, 1408 RT5663_EN_IRQ_INLINE_MASK,
1409 RT5663_EN_IRQ_INLINE_BYP); 1409 RT5663_EN_IRQ_INLINE_BYP);
1410 break; 1410 break;
1411 default: 1411 default:
1412 dev_err(codec->dev, "Unknown CODEC_TYPE\n"); 1412 dev_err(codec->dev, "Unknown CODEC Version\n");
1413 } 1413 }
1414 snd_soc_update_bits(codec, RT5663_IL_CMD_6, 1414 snd_soc_update_bits(codec, RT5663_IL_CMD_6,
1415 RT5668_EN_4BTN_INL_MASK, RT5668_EN_4BTN_INL_DIS); 1415 RT5663_EN_4BTN_INL_MASK, RT5663_EN_4BTN_INL_DIS);
1416 /* reset in-line command */ 1416 /* reset in-line command */
1417 snd_soc_update_bits(codec, RT5663_IL_CMD_6, 1417 snd_soc_update_bits(codec, RT5663_IL_CMD_6,
1418 RT5668_RESET_4BTN_INL_MASK, 1418 RT5663_RESET_4BTN_INL_MASK,
1419 RT5668_RESET_4BTN_INL_RESET); 1419 RT5663_RESET_4BTN_INL_RESET);
1420 snd_soc_update_bits(codec, RT5663_IL_CMD_6, 1420 snd_soc_update_bits(codec, RT5663_IL_CMD_6,
1421 RT5668_RESET_4BTN_INL_MASK, 1421 RT5663_RESET_4BTN_INL_MASK,
1422 RT5668_RESET_4BTN_INL_NOR); 1422 RT5663_RESET_4BTN_INL_NOR);
1423 } 1423 }
1424} 1424}
1425 1425
1426/** 1426/**
1427 * rt5668_jack_detect - Detect headset. 1427 * rt5663_v2_jack_detect - Detect headset.
1428 * @codec: SoC audio codec device. 1428 * @codec: SoC audio codec device.
1429 * @jack_insert: Jack insert or not. 1429 * @jack_insert: Jack insert or not.
1430 * 1430 *
@@ -1433,16 +1433,16 @@ static void rt5663_enable_push_button_irq(struct snd_soc_codec *codec,
1433 * Returns detect status. 1433 * Returns detect status.
1434 */ 1434 */
1435 1435
1436static int rt5668_jack_detect(struct snd_soc_codec *codec, int jack_insert) 1436static int rt5663_v2_jack_detect(struct snd_soc_codec *codec, int jack_insert)
1437{ 1437{
1438 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec); 1438 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
1439 struct rt5663_priv *rt5668 = snd_soc_codec_get_drvdata(codec); 1439 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
1440 int val, i = 0, sleep_time[5] = {300, 150, 100, 50, 30}; 1440 int val, i = 0, sleep_time[5] = {300, 150, 100, 50, 30};
1441 1441
1442 dev_dbg(codec->dev, "%s jack_insert:%d\n", __func__, jack_insert); 1442 dev_dbg(codec->dev, "%s jack_insert:%d\n", __func__, jack_insert);
1443 if (jack_insert) { 1443 if (jack_insert) {
1444 snd_soc_write(codec, RT5668_CBJ_TYPE_2, 0x8040); 1444 snd_soc_write(codec, RT5663_CBJ_TYPE_2, 0x8040);
1445 snd_soc_write(codec, RT5668_CBJ_TYPE_3, 0x1484); 1445 snd_soc_write(codec, RT5663_CBJ_TYPE_3, 0x1484);
1446 1446
1447 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS1"); 1447 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS1");
1448 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS2"); 1448 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS2");
@@ -1450,12 +1450,12 @@ static int rt5668_jack_detect(struct snd_soc_codec *codec, int jack_insert)
1450 snd_soc_dapm_force_enable_pin(dapm, "CBJ Power"); 1450 snd_soc_dapm_force_enable_pin(dapm, "CBJ Power");
1451 snd_soc_dapm_sync(dapm); 1451 snd_soc_dapm_sync(dapm);
1452 snd_soc_update_bits(codec, RT5663_RC_CLK, 1452 snd_soc_update_bits(codec, RT5663_RC_CLK,
1453 RT5668_DIG_1M_CLK_MASK, RT5668_DIG_1M_CLK_EN); 1453 RT5663_DIG_1M_CLK_MASK, RT5663_DIG_1M_CLK_EN);
1454 snd_soc_update_bits(codec, RT5663_RECMIX, 0x8, 0x8); 1454 snd_soc_update_bits(codec, RT5663_RECMIX, 0x8, 0x8);
1455 1455
1456 while (i < 5) { 1456 while (i < 5) {
1457 msleep(sleep_time[i]); 1457 msleep(sleep_time[i]);
1458 val = snd_soc_read(codec, RT5668_CBJ_TYPE_2) & 0x0003; 1458 val = snd_soc_read(codec, RT5663_CBJ_TYPE_2) & 0x0003;
1459 if (val == 0x1 || val == 0x2 || val == 0x3) 1459 if (val == 0x1 || val == 0x2 || val == 0x3)
1460 break; 1460 break;
1461 dev_dbg(codec->dev, "%s: MX-0011 val=%x sleep %d\n", 1461 dev_dbg(codec->dev, "%s: MX-0011 val=%x sleep %d\n",
@@ -1466,7 +1466,7 @@ static int rt5668_jack_detect(struct snd_soc_codec *codec, int jack_insert)
1466 switch (val) { 1466 switch (val) {
1467 case 1: 1467 case 1:
1468 case 2: 1468 case 2:
1469 rt5668->jack_type = SND_JACK_HEADSET; 1469 rt5663->jack_type = SND_JACK_HEADSET;
1470 rt5663_enable_push_button_irq(codec, true); 1470 rt5663_enable_push_button_irq(codec, true);
1471 break; 1471 break;
1472 default: 1472 default:
@@ -1475,13 +1475,13 @@ static int rt5668_jack_detect(struct snd_soc_codec *codec, int jack_insert)
1475 snd_soc_dapm_disable_pin(dapm, "Mic Det Power"); 1475 snd_soc_dapm_disable_pin(dapm, "Mic Det Power");
1476 snd_soc_dapm_disable_pin(dapm, "CBJ Power"); 1476 snd_soc_dapm_disable_pin(dapm, "CBJ Power");
1477 snd_soc_dapm_sync(dapm); 1477 snd_soc_dapm_sync(dapm);
1478 rt5668->jack_type = SND_JACK_HEADPHONE; 1478 rt5663->jack_type = SND_JACK_HEADPHONE;
1479 break; 1479 break;
1480 } 1480 }
1481 } else { 1481 } else {
1482 snd_soc_update_bits(codec, RT5663_RECMIX, 0x8, 0x0); 1482 snd_soc_update_bits(codec, RT5663_RECMIX, 0x8, 0x0);
1483 1483
1484 if (rt5668->jack_type == SND_JACK_HEADSET) { 1484 if (rt5663->jack_type == SND_JACK_HEADSET) {
1485 rt5663_enable_push_button_irq(codec, false); 1485 rt5663_enable_push_button_irq(codec, false);
1486 snd_soc_dapm_disable_pin(dapm, "MICBIAS1"); 1486 snd_soc_dapm_disable_pin(dapm, "MICBIAS1");
1487 snd_soc_dapm_disable_pin(dapm, "MICBIAS2"); 1487 snd_soc_dapm_disable_pin(dapm, "MICBIAS2");
@@ -1489,11 +1489,11 @@ static int rt5668_jack_detect(struct snd_soc_codec *codec, int jack_insert)
1489 snd_soc_dapm_disable_pin(dapm, "CBJ Power"); 1489 snd_soc_dapm_disable_pin(dapm, "CBJ Power");
1490 snd_soc_dapm_sync(dapm); 1490 snd_soc_dapm_sync(dapm);
1491 } 1491 }
1492 rt5668->jack_type = 0; 1492 rt5663->jack_type = 0;
1493 } 1493 }
1494 1494
1495 dev_dbg(codec->dev, "jack_type = %d\n", rt5668->jack_type); 1495 dev_dbg(codec->dev, "jack_type = %d\n", rt5663->jack_type);
1496 return rt5668->jack_type; 1496 return rt5663->jack_type;
1497} 1497}
1498 1498
1499/** 1499/**
@@ -1514,11 +1514,11 @@ static int rt5663_jack_detect(struct snd_soc_codec *codec, int jack_insert)
1514 1514
1515 if (jack_insert) { 1515 if (jack_insert) {
1516 snd_soc_update_bits(codec, RT5663_DIG_MISC, 1516 snd_soc_update_bits(codec, RT5663_DIG_MISC,
1517 RT5668_DIG_GATE_CTRL_MASK, RT5668_DIG_GATE_CTRL_EN); 1517 RT5663_DIG_GATE_CTRL_MASK, RT5663_DIG_GATE_CTRL_EN);
1518 snd_soc_update_bits(codec, RT5663_HP_CHARGE_PUMP_1, 1518 snd_soc_update_bits(codec, RT5663_HP_CHARGE_PUMP_1,
1519 RT5663_SI_HP_MASK | RT5668_OSW_HP_L_MASK | 1519 RT5663_SI_HP_MASK | RT5663_OSW_HP_L_MASK |
1520 RT5668_OSW_HP_R_MASK, RT5663_SI_HP_EN | 1520 RT5663_OSW_HP_R_MASK, RT5663_SI_HP_EN |
1521 RT5668_OSW_HP_L_DIS | RT5668_OSW_HP_R_DIS); 1521 RT5663_OSW_HP_L_DIS | RT5663_OSW_HP_R_DIS);
1522 snd_soc_update_bits(codec, RT5663_DUMMY_1, 1522 snd_soc_update_bits(codec, RT5663_DUMMY_1,
1523 RT5663_EMB_CLK_MASK | RT5663_HPA_CPL_BIAS_MASK | 1523 RT5663_EMB_CLK_MASK | RT5663_HPA_CPL_BIAS_MASK |
1524 RT5663_HPA_CPR_BIAS_MASK, RT5663_EMB_CLK_EN | 1524 RT5663_HPA_CPR_BIAS_MASK, RT5663_EMB_CLK_EN |
@@ -1530,17 +1530,17 @@ static int rt5663_jack_detect(struct snd_soc_codec *codec, int jack_insert)
1530 RT5663_PWR_MIC_DET_MASK, RT5663_PWR_MIC_DET_ON); 1530 RT5663_PWR_MIC_DET_MASK, RT5663_PWR_MIC_DET_ON);
1531 /* BST1 power on for JD */ 1531 /* BST1 power on for JD */
1532 snd_soc_update_bits(codec, RT5663_PWR_ANLG_2, 1532 snd_soc_update_bits(codec, RT5663_PWR_ANLG_2,
1533 RT5668_PWR_BST1_MASK, RT5668_PWR_BST1_ON); 1533 RT5663_PWR_BST1_MASK, RT5663_PWR_BST1_ON);
1534 snd_soc_update_bits(codec, RT5663_EM_JACK_TYPE_1, 1534 snd_soc_update_bits(codec, RT5663_EM_JACK_TYPE_1,
1535 RT5663_CBJ_DET_MASK | RT5663_EXT_JD_MASK | 1535 RT5663_CBJ_DET_MASK | RT5663_EXT_JD_MASK |
1536 RT5663_POL_EXT_JD_MASK, RT5663_CBJ_DET_EN | 1536 RT5663_POL_EXT_JD_MASK, RT5663_CBJ_DET_EN |
1537 RT5663_EXT_JD_EN | RT5663_POL_EXT_JD_EN); 1537 RT5663_EXT_JD_EN | RT5663_POL_EXT_JD_EN);
1538 snd_soc_update_bits(codec, RT5663_PWR_ANLG_1, 1538 snd_soc_update_bits(codec, RT5663_PWR_ANLG_1,
1539 RT5668_PWR_MB_MASK | RT5668_LDO1_DVO_MASK | 1539 RT5663_PWR_MB_MASK | RT5663_LDO1_DVO_MASK |
1540 RT5668_AMP_HP_MASK, RT5668_PWR_MB | 1540 RT5663_AMP_HP_MASK, RT5663_PWR_MB |
1541 RT5668_LDO1_DVO_0_9V | RT5668_AMP_HP_3X); 1541 RT5663_LDO1_DVO_0_9V | RT5663_AMP_HP_3X);
1542 snd_soc_update_bits(codec, RT5663_AUTO_1MRC_CLK, 1542 snd_soc_update_bits(codec, RT5663_AUTO_1MRC_CLK,
1543 RT5668_IRQ_POW_SAV_MASK, RT5668_IRQ_POW_SAV_EN); 1543 RT5663_IRQ_POW_SAV_MASK, RT5663_IRQ_POW_SAV_EN);
1544 snd_soc_update_bits(codec, RT5663_IRQ_1, 1544 snd_soc_update_bits(codec, RT5663_IRQ_1,
1545 RT5663_EN_IRQ_JD1_MASK, RT5663_EN_IRQ_JD1_EN); 1545 RT5663_EN_IRQ_JD1_MASK, RT5663_EN_IRQ_JD1_EN);
1546 while (i < 5) { 1546 while (i < 5) {
@@ -1619,13 +1619,13 @@ static bool rt5663_check_jd_status(struct snd_soc_codec *codec)
1619 dev_dbg(codec->dev, "%s val=%x\n", __func__, val); 1619 dev_dbg(codec->dev, "%s val=%x\n", __func__, val);
1620 1620
1621 /* JD1 */ 1621 /* JD1 */
1622 switch (rt5663->codec_type) { 1622 switch (rt5663->codec_ver) {
1623 case CODEC_TYPE_RT5668: 1623 case CODEC_VER_1:
1624 return !(val & 0x2000); 1624 return !(val & 0x2000);
1625 case CODEC_TYPE_RT5663: 1625 case CODEC_VER_0:
1626 return !(val & 0x1000); 1626 return !(val & 0x1000);
1627 default: 1627 default:
1628 dev_err(codec->dev, "Unknown CODEC_TYPE\n"); 1628 dev_err(codec->dev, "Unknown CODEC Version\n");
1629 } 1629 }
1630 1630
1631 return false; 1631 return false;
@@ -1645,15 +1645,16 @@ static void rt5663_jack_detect_work(struct work_struct *work)
1645 /* jack in */ 1645 /* jack in */
1646 if (rt5663->jack_type == 0) { 1646 if (rt5663->jack_type == 0) {
1647 /* jack was out, report jack type */ 1647 /* jack was out, report jack type */
1648 switch (rt5663->codec_type) { 1648 switch (rt5663->codec_ver) {
1649 case CODEC_TYPE_RT5668: 1649 case CODEC_VER_1:
1650 report = rt5668_jack_detect(rt5663->codec, 1); 1650 report = rt5663_v2_jack_detect(
1651 rt5663->codec, 1);
1651 break; 1652 break;
1652 case CODEC_TYPE_RT5663: 1653 case CODEC_VER_0:
1653 report = rt5663_jack_detect(rt5663->codec, 1); 1654 report = rt5663_jack_detect(rt5663->codec, 1);
1654 break; 1655 break;
1655 default: 1656 default:
1656 dev_err(codec->dev, "Unknown CODEC_TYPE\n"); 1657 dev_err(codec->dev, "Unknown CODEC Version\n");
1657 } 1658 }
1658 } else { 1659 } else {
1659 /* jack is already in, report button event */ 1660 /* jack is already in, report button event */
@@ -1702,15 +1703,15 @@ static void rt5663_jack_detect_work(struct work_struct *work)
1702 } 1703 }
1703 } else { 1704 } else {
1704 /* jack out */ 1705 /* jack out */
1705 switch (rt5663->codec_type) { 1706 switch (rt5663->codec_ver) {
1706 case CODEC_TYPE_RT5668: 1707 case CODEC_VER_1:
1707 report = rt5668_jack_detect(rt5663->codec, 0); 1708 report = rt5663_v2_jack_detect(rt5663->codec, 0);
1708 break; 1709 break;
1709 case CODEC_TYPE_RT5663: 1710 case CODEC_VER_0:
1710 report = rt5663_jack_detect(rt5663->codec, 0); 1711 report = rt5663_jack_detect(rt5663->codec, 0);
1711 break; 1712 break;
1712 default: 1713 default:
1713 dev_err(codec->dev, "Unknown CODEC_TYPE\n"); 1714 dev_err(codec->dev, "Unknown CODEC Version\n");
1714 } 1715 }
1715 } 1716 }
1716 dev_dbg(codec->dev, "%s jack report: 0x%04x\n", __func__, report); 1717 dev_dbg(codec->dev, "%s jack report: 0x%04x\n", __func__, report);
@@ -1722,24 +1723,24 @@ static void rt5663_jack_detect_work(struct work_struct *work)
1722static const struct snd_kcontrol_new rt5663_snd_controls[] = { 1723static const struct snd_kcontrol_new rt5663_snd_controls[] = {
1723 /* DAC Digital Volume */ 1724 /* DAC Digital Volume */
1724 SOC_DOUBLE_TLV("DAC Playback Volume", RT5663_STO1_DAC_DIG_VOL, 1725 SOC_DOUBLE_TLV("DAC Playback Volume", RT5663_STO1_DAC_DIG_VOL,
1725 RT5668_DAC_L1_VOL_SHIFT + 1, RT5668_DAC_R1_VOL_SHIFT + 1, 1726 RT5663_DAC_L1_VOL_SHIFT + 1, RT5663_DAC_R1_VOL_SHIFT + 1,
1726 87, 0, dac_vol_tlv), 1727 87, 0, dac_vol_tlv),
1727 /* ADC Digital Volume Control */ 1728 /* ADC Digital Volume Control */
1728 SOC_DOUBLE("ADC Capture Switch", RT5663_STO1_ADC_DIG_VOL, 1729 SOC_DOUBLE("ADC Capture Switch", RT5663_STO1_ADC_DIG_VOL,
1729 RT5668_ADC_L_MUTE_SHIFT, RT5668_ADC_R_MUTE_SHIFT, 1, 1), 1730 RT5663_ADC_L_MUTE_SHIFT, RT5663_ADC_R_MUTE_SHIFT, 1, 1),
1730 SOC_DOUBLE_TLV("ADC Capture Volume", RT5663_STO1_ADC_DIG_VOL, 1731 SOC_DOUBLE_TLV("ADC Capture Volume", RT5663_STO1_ADC_DIG_VOL,
1731 RT5668_ADC_L_VOL_SHIFT + 1, RT5668_ADC_R_VOL_SHIFT + 1, 1732 RT5663_ADC_L_VOL_SHIFT + 1, RT5663_ADC_R_VOL_SHIFT + 1,
1732 63, 0, adc_vol_tlv), 1733 63, 0, adc_vol_tlv),
1733}; 1734};
1734 1735
1735static const struct snd_kcontrol_new rt5668_specific_controls[] = { 1736static const struct snd_kcontrol_new rt5663_v2_specific_controls[] = {
1736 /* Headphone Output Volume */ 1737 /* Headphone Output Volume */
1737 SOC_DOUBLE_R_TLV("Headphone Playback Volume", RT5663_HP_LCH_DRE, 1738 SOC_DOUBLE_R_TLV("Headphone Playback Volume", RT5663_HP_LCH_DRE,
1738 RT5663_HP_RCH_DRE, RT5668_GAIN_HP_SHIFT, 15, 1, 1739 RT5663_HP_RCH_DRE, RT5663_GAIN_HP_SHIFT, 15, 1,
1739 rt5668_hp_vol_tlv), 1740 rt5663_v2_hp_vol_tlv),
1740 /* Mic Boost Volume */ 1741 /* Mic Boost Volume */
1741 SOC_SINGLE_TLV("IN1 Capture Volume", RT5668_AEC_BST, 1742 SOC_SINGLE_TLV("IN1 Capture Volume", RT5663_AEC_BST,
1742 RT5668_GAIN_CBJ_SHIFT, 8, 0, in_bst_tlv), 1743 RT5663_GAIN_CBJ_SHIFT, 8, 0, in_bst_tlv),
1743}; 1744};
1744 1745
1745static const struct snd_kcontrol_new rt5663_specific_controls[] = { 1746static const struct snd_kcontrol_new rt5663_specific_controls[] = {
@@ -1775,15 +1776,15 @@ static int rt5663_is_using_asrc(struct snd_soc_dapm_widget *w,
1775 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 1776 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1776 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec); 1777 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
1777 1778
1778 if (rt5663->codec_type == CODEC_TYPE_RT5668) { 1779 if (rt5663->codec_ver == CODEC_VER_1) {
1779 switch (w->shift) { 1780 switch (w->shift) {
1780 case RT5668_ADC_STO1_ASRC_SHIFT: 1781 case RT5663_ADC_STO1_ASRC_SHIFT:
1781 reg = RT5668_ASRC_3; 1782 reg = RT5663_ASRC_3;
1782 shift = RT5668_AD_STO1_TRACK_SHIFT; 1783 shift = RT5663_V2_AD_STO1_TRACK_SHIFT;
1783 break; 1784 break;
1784 case RT5668_DAC_STO1_ASRC_SHIFT: 1785 case RT5663_DAC_STO1_ASRC_SHIFT:
1785 reg = RT5663_ASRC_2; 1786 reg = RT5663_ASRC_2;
1786 shift = RT5668_DA_STO1_TRACK_SHIFT; 1787 shift = RT5663_DA_STO1_TRACK_SHIFT;
1787 break; 1788 break;
1788 default: 1789 default:
1789 return 0; 1790 return 0;
@@ -1820,17 +1821,17 @@ static int rt5663_i2s_use_asrc(struct snd_soc_dapm_widget *source,
1820 1821
1821 da_asrc_en = (snd_soc_read(codec, RT5663_ASRC_2) & 1822 da_asrc_en = (snd_soc_read(codec, RT5663_ASRC_2) &
1822 RT5663_DA_STO1_TRACK_MASK) ? 1 : 0; 1823 RT5663_DA_STO1_TRACK_MASK) ? 1 : 0;
1823 switch (rt5663->codec_type) { 1824 switch (rt5663->codec_ver) {
1824 case CODEC_TYPE_RT5668: 1825 case CODEC_VER_1:
1825 ad_asrc_en = (snd_soc_read(codec, RT5668_ASRC_3) & 1826 ad_asrc_en = (snd_soc_read(codec, RT5663_ASRC_3) &
1826 RT5668_AD_STO1_TRACK_MASK) ? 1 : 0; 1827 RT5663_V2_AD_STO1_TRACK_MASK) ? 1 : 0;
1827 break; 1828 break;
1828 case CODEC_TYPE_RT5663: 1829 case CODEC_VER_0:
1829 ad_asrc_en = (snd_soc_read(codec, RT5663_ASRC_2) & 1830 ad_asrc_en = (snd_soc_read(codec, RT5663_ASRC_2) &
1830 RT5663_AD_STO1_TRACK_MASK) ? 1 : 0; 1831 RT5663_AD_STO1_TRACK_MASK) ? 1 : 0;
1831 break; 1832 break;
1832 default: 1833 default:
1833 dev_err(codec->dev, "Unknown CODEC_TYPE\n"); 1834 dev_err(codec->dev, "Unknown CODEC Version\n");
1834 return 1; 1835 return 1;
1835 } 1836 }
1836 1837
@@ -1849,7 +1850,7 @@ static int rt5663_i2s_use_asrc(struct snd_soc_dapm_widget *source,
1849 * @filter_mask: mask of filters. 1850 * @filter_mask: mask of filters.
1850 * @clk_src: clock source 1851 * @clk_src: clock source
1851 * 1852 *
1852 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5668 can 1853 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5663 can
1853 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to 1854 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
1854 * support special i2s clock format such as Intel's 100fs(100 * sampling rate). 1855 * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
1855 * ASRC function will track i2s clock and generate a corresponding system clock 1856 * ASRC function will track i2s clock and generate a corresponding system clock
@@ -1860,7 +1861,7 @@ static int rt5663_i2s_use_asrc(struct snd_soc_dapm_widget *source,
1860int rt5663_sel_asrc_clk_src(struct snd_soc_codec *codec, 1861int rt5663_sel_asrc_clk_src(struct snd_soc_codec *codec,
1861 unsigned int filter_mask, unsigned int clk_src) 1862 unsigned int filter_mask, unsigned int clk_src)
1862{ 1863{
1863 struct rt5663_priv *rt5668 = snd_soc_codec_get_drvdata(codec); 1864 struct rt5663_priv *rt5663 = snd_soc_codec_get_drvdata(codec);
1864 unsigned int asrc2_mask = 0; 1865 unsigned int asrc2_mask = 0;
1865 unsigned int asrc2_value = 0; 1866 unsigned int asrc2_value = 0;
1866 unsigned int asrc3_mask = 0; 1867 unsigned int asrc3_mask = 0;
@@ -1876,22 +1877,22 @@ int rt5663_sel_asrc_clk_src(struct snd_soc_codec *codec,
1876 } 1877 }
1877 1878
1878 if (filter_mask & RT5663_DA_STEREO_FILTER) { 1879 if (filter_mask & RT5663_DA_STEREO_FILTER) {
1879 asrc2_mask |= RT5668_DA_STO1_TRACK_MASK; 1880 asrc2_mask |= RT5663_DA_STO1_TRACK_MASK;
1880 asrc2_value |= clk_src << RT5668_DA_STO1_TRACK_SHIFT; 1881 asrc2_value |= clk_src << RT5663_DA_STO1_TRACK_SHIFT;
1881 } 1882 }
1882 1883
1883 if (filter_mask & RT5663_AD_STEREO_FILTER) { 1884 if (filter_mask & RT5663_AD_STEREO_FILTER) {
1884 switch (rt5668->codec_type) { 1885 switch (rt5663->codec_ver) {
1885 case CODEC_TYPE_RT5668: 1886 case CODEC_VER_1:
1886 asrc3_mask |= RT5668_AD_STO1_TRACK_MASK; 1887 asrc3_mask |= RT5663_V2_AD_STO1_TRACK_MASK;
1887 asrc3_value |= clk_src << RT5668_AD_STO1_TRACK_SHIFT; 1888 asrc3_value |= clk_src << RT5663_V2_AD_STO1_TRACK_SHIFT;
1888 break; 1889 break;
1889 case CODEC_TYPE_RT5663: 1890 case CODEC_VER_0:
1890 asrc2_mask |= RT5663_AD_STO1_TRACK_MASK; 1891 asrc2_mask |= RT5663_AD_STO1_TRACK_MASK;
1891 asrc2_value |= clk_src << RT5663_AD_STO1_TRACK_SHIFT; 1892 asrc2_value |= clk_src << RT5663_AD_STO1_TRACK_SHIFT;
1892 break; 1893 break;
1893 default: 1894 default:
1894 dev_err(codec->dev, "Unknown CODEC_TYPE\n"); 1895 dev_err(codec->dev, "Unknown CODEC Version\n");
1895 } 1896 }
1896 } 1897 }
1897 1898
@@ -1900,7 +1901,7 @@ int rt5663_sel_asrc_clk_src(struct snd_soc_codec *codec,
1900 asrc2_value); 1901 asrc2_value);
1901 1902
1902 if (asrc3_mask) 1903 if (asrc3_mask)
1903 snd_soc_update_bits(codec, RT5668_ASRC_3, asrc3_mask, 1904 snd_soc_update_bits(codec, RT5663_ASRC_3, asrc3_mask,
1904 asrc3_value); 1905 asrc3_value);
1905 1906
1906 return 0; 1907 return 0;
@@ -1908,82 +1909,82 @@ int rt5663_sel_asrc_clk_src(struct snd_soc_codec *codec,
1908EXPORT_SYMBOL_GPL(rt5663_sel_asrc_clk_src); 1909EXPORT_SYMBOL_GPL(rt5663_sel_asrc_clk_src);
1909 1910
1910/* Analog Mixer */ 1911/* Analog Mixer */
1911static const struct snd_kcontrol_new rt5668_recmix1l[] = { 1912static const struct snd_kcontrol_new rt5663_recmix1l[] = {
1912 SOC_DAPM_SINGLE("BST2 Switch", RT5668_RECMIX1L, 1913 SOC_DAPM_SINGLE("BST2 Switch", RT5663_RECMIX1L,
1913 RT5668_RECMIX1L_BST2_SHIFT, 1, 1), 1914 RT5663_RECMIX1L_BST2_SHIFT, 1, 1),
1914 SOC_DAPM_SINGLE("BST1 CBJ Switch", RT5668_RECMIX1L, 1915 SOC_DAPM_SINGLE("BST1 CBJ Switch", RT5663_RECMIX1L,
1915 RT5668_RECMIX1L_BST1_CBJ_SHIFT, 1, 1), 1916 RT5663_RECMIX1L_BST1_CBJ_SHIFT, 1, 1),
1916}; 1917};
1917 1918
1918static const struct snd_kcontrol_new rt5668_recmix1r[] = { 1919static const struct snd_kcontrol_new rt5663_recmix1r[] = {
1919 SOC_DAPM_SINGLE("BST2 Switch", RT5668_RECMIX1R, 1920 SOC_DAPM_SINGLE("BST2 Switch", RT5663_RECMIX1R,
1920 RT5668_RECMIX1R_BST2_SHIFT, 1, 1), 1921 RT5663_RECMIX1R_BST2_SHIFT, 1, 1),
1921}; 1922};
1922 1923
1923/* Digital Mixer */ 1924/* Digital Mixer */
1924static const struct snd_kcontrol_new rt5663_sto1_adc_l_mix[] = { 1925static const struct snd_kcontrol_new rt5663_sto1_adc_l_mix[] = {
1925 SOC_DAPM_SINGLE("ADC1 Switch", RT5663_STO1_ADC_MIXER, 1926 SOC_DAPM_SINGLE("ADC1 Switch", RT5663_STO1_ADC_MIXER,
1926 RT5668_M_STO1_ADC_L1_SHIFT, 1, 1), 1927 RT5663_M_STO1_ADC_L1_SHIFT, 1, 1),
1927 SOC_DAPM_SINGLE("ADC2 Switch", RT5663_STO1_ADC_MIXER, 1928 SOC_DAPM_SINGLE("ADC2 Switch", RT5663_STO1_ADC_MIXER,
1928 RT5668_M_STO1_ADC_L2_SHIFT, 1, 1), 1929 RT5663_M_STO1_ADC_L2_SHIFT, 1, 1),
1929}; 1930};
1930 1931
1931static const struct snd_kcontrol_new rt5668_sto1_adc_r_mix[] = { 1932static const struct snd_kcontrol_new rt5663_sto1_adc_r_mix[] = {
1932 SOC_DAPM_SINGLE("ADC1 Switch", RT5663_STO1_ADC_MIXER, 1933 SOC_DAPM_SINGLE("ADC1 Switch", RT5663_STO1_ADC_MIXER,
1933 RT5668_M_STO1_ADC_R1_SHIFT, 1, 1), 1934 RT5663_M_STO1_ADC_R1_SHIFT, 1, 1),
1934 SOC_DAPM_SINGLE("ADC2 Switch", RT5663_STO1_ADC_MIXER, 1935 SOC_DAPM_SINGLE("ADC2 Switch", RT5663_STO1_ADC_MIXER,
1935 RT5668_M_STO1_ADC_R2_SHIFT, 1, 1), 1936 RT5663_M_STO1_ADC_R2_SHIFT, 1, 1),
1936}; 1937};
1937 1938
1938static const struct snd_kcontrol_new rt5663_adda_l_mix[] = { 1939static const struct snd_kcontrol_new rt5663_adda_l_mix[] = {
1939 SOC_DAPM_SINGLE("ADC L Switch", RT5663_AD_DA_MIXER, 1940 SOC_DAPM_SINGLE("ADC L Switch", RT5663_AD_DA_MIXER,
1940 RT5668_M_ADCMIX_L_SHIFT, 1, 1), 1941 RT5663_M_ADCMIX_L_SHIFT, 1, 1),
1941 SOC_DAPM_SINGLE("DAC L Switch", RT5663_AD_DA_MIXER, 1942 SOC_DAPM_SINGLE("DAC L Switch", RT5663_AD_DA_MIXER,
1942 RT5668_M_DAC1_L_SHIFT, 1, 1), 1943 RT5663_M_DAC1_L_SHIFT, 1, 1),
1943}; 1944};
1944 1945
1945static const struct snd_kcontrol_new rt5663_adda_r_mix[] = { 1946static const struct snd_kcontrol_new rt5663_adda_r_mix[] = {
1946 SOC_DAPM_SINGLE("ADC R Switch", RT5663_AD_DA_MIXER, 1947 SOC_DAPM_SINGLE("ADC R Switch", RT5663_AD_DA_MIXER,
1947 RT5668_M_ADCMIX_R_SHIFT, 1, 1), 1948 RT5663_M_ADCMIX_R_SHIFT, 1, 1),
1948 SOC_DAPM_SINGLE("DAC R Switch", RT5663_AD_DA_MIXER, 1949 SOC_DAPM_SINGLE("DAC R Switch", RT5663_AD_DA_MIXER,
1949 RT5668_M_DAC1_R_SHIFT, 1, 1), 1950 RT5663_M_DAC1_R_SHIFT, 1, 1),
1950}; 1951};
1951 1952
1952static const struct snd_kcontrol_new rt5663_sto1_dac_l_mix[] = { 1953static const struct snd_kcontrol_new rt5663_sto1_dac_l_mix[] = {
1953 SOC_DAPM_SINGLE("DAC L Switch", RT5663_STO_DAC_MIXER, 1954 SOC_DAPM_SINGLE("DAC L Switch", RT5663_STO_DAC_MIXER,
1954 RT5668_M_DAC_L1_STO_L_SHIFT, 1, 1), 1955 RT5663_M_DAC_L1_STO_L_SHIFT, 1, 1),
1955 SOC_DAPM_SINGLE("DAC R Switch", RT5663_STO_DAC_MIXER, 1956 SOC_DAPM_SINGLE("DAC R Switch", RT5663_STO_DAC_MIXER,
1956 RT5668_M_DAC_R1_STO_L_SHIFT, 1, 1), 1957 RT5663_M_DAC_R1_STO_L_SHIFT, 1, 1),
1957}; 1958};
1958 1959
1959static const struct snd_kcontrol_new rt5663_sto1_dac_r_mix[] = { 1960static const struct snd_kcontrol_new rt5663_sto1_dac_r_mix[] = {
1960 SOC_DAPM_SINGLE("DAC L Switch", RT5663_STO_DAC_MIXER, 1961 SOC_DAPM_SINGLE("DAC L Switch", RT5663_STO_DAC_MIXER,
1961 RT5668_M_DAC_L1_STO_R_SHIFT, 1, 1), 1962 RT5663_M_DAC_L1_STO_R_SHIFT, 1, 1),
1962 SOC_DAPM_SINGLE("DAC R Switch", RT5663_STO_DAC_MIXER, 1963 SOC_DAPM_SINGLE("DAC R Switch", RT5663_STO_DAC_MIXER,
1963 RT5668_M_DAC_R1_STO_R_SHIFT, 1, 1), 1964 RT5663_M_DAC_R1_STO_R_SHIFT, 1, 1),
1964}; 1965};
1965 1966
1966/* Out Switch */ 1967/* Out Switch */
1967static const struct snd_kcontrol_new rt5668_hpo_switch = 1968static const struct snd_kcontrol_new rt5663_hpo_switch =
1968 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5668_HP_AMP_2, 1969 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5663_HP_AMP_2,
1969 RT5668_EN_DAC_HPO_SHIFT, 1, 0); 1970 RT5663_EN_DAC_HPO_SHIFT, 1, 0);
1970 1971
1971/* Stereo ADC source */ 1972/* Stereo ADC source */
1972static const char * const rt5668_sto1_adc_src[] = { 1973static const char * const rt5663_sto1_adc_src[] = {
1973 "ADC L", "ADC R" 1974 "ADC L", "ADC R"
1974}; 1975};
1975 1976
1976static SOC_ENUM_SINGLE_DECL(rt5668_sto1_adcl_enum, RT5663_STO1_ADC_MIXER, 1977static SOC_ENUM_SINGLE_DECL(rt5663_sto1_adcl_enum, RT5663_STO1_ADC_MIXER,
1977 RT5668_STO1_ADC_L_SRC_SHIFT, rt5668_sto1_adc_src); 1978 RT5663_STO1_ADC_L_SRC_SHIFT, rt5663_sto1_adc_src);
1978 1979
1979static const struct snd_kcontrol_new rt5668_sto1_adcl_mux = 1980static const struct snd_kcontrol_new rt5663_sto1_adcl_mux =
1980 SOC_DAPM_ENUM("STO1 ADC L Mux", rt5668_sto1_adcl_enum); 1981 SOC_DAPM_ENUM("STO1 ADC L Mux", rt5663_sto1_adcl_enum);
1981 1982
1982static SOC_ENUM_SINGLE_DECL(rt5668_sto1_adcr_enum, RT5663_STO1_ADC_MIXER, 1983static SOC_ENUM_SINGLE_DECL(rt5663_sto1_adcr_enum, RT5663_STO1_ADC_MIXER,
1983 RT5668_STO1_ADC_R_SRC_SHIFT, rt5668_sto1_adc_src); 1984 RT5663_STO1_ADC_R_SRC_SHIFT, rt5663_sto1_adc_src);
1984 1985
1985static const struct snd_kcontrol_new rt5668_sto1_adcr_mux = 1986static const struct snd_kcontrol_new rt5663_sto1_adcr_mux =
1986 SOC_DAPM_ENUM("STO1 ADC R Mux", rt5668_sto1_adcr_enum); 1987 SOC_DAPM_ENUM("STO1 ADC R Mux", rt5663_sto1_adcr_enum);
1987 1988
1988/* RT5663: Analog DACL1 input source */ 1989/* RT5663: Analog DACL1 input source */
1989static const char * const rt5663_alg_dacl_src[] = { 1990static const char * const rt5663_alg_dacl_src[] = {
@@ -2015,12 +2016,12 @@ static int rt5663_hp_event(struct snd_soc_dapm_widget *w,
2015 2016
2016 switch (event) { 2017 switch (event) {
2017 case SND_SOC_DAPM_POST_PMU: 2018 case SND_SOC_DAPM_POST_PMU:
2018 if (rt5663->codec_type == CODEC_TYPE_RT5668) { 2019 if (rt5663->codec_ver == CODEC_VER_1) {
2019 snd_soc_update_bits(codec, RT5663_HP_CHARGE_PUMP_1, 2020 snd_soc_update_bits(codec, RT5663_HP_CHARGE_PUMP_1,
2020 RT5668_SEL_PM_HP_SHIFT, RT5668_SEL_PM_HP_HIGH); 2021 RT5663_SEL_PM_HP_SHIFT, RT5663_SEL_PM_HP_HIGH);
2021 snd_soc_update_bits(codec, RT5663_HP_LOGIC_2, 2022 snd_soc_update_bits(codec, RT5663_HP_LOGIC_2,
2022 RT5668_HP_SIG_SRC1_MASK, 2023 RT5663_HP_SIG_SRC1_MASK,
2023 RT5668_HP_SIG_SRC1_SILENCE); 2024 RT5663_HP_SIG_SRC1_SILENCE);
2024 } else { 2025 } else {
2025 snd_soc_write(codec, RT5663_DEPOP_2, 0x3003); 2026 snd_soc_write(codec, RT5663_DEPOP_2, 0x3003);
2026 snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x000b, 2027 snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x000b,
@@ -2028,7 +2029,7 @@ static int rt5663_hp_event(struct snd_soc_dapm_widget *w,
2028 snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x0030, 2029 snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x0030,
2029 0x0030); 2030 0x0030);
2030 snd_soc_update_bits(codec, RT5663_HP_CHARGE_PUMP_1, 2031 snd_soc_update_bits(codec, RT5663_HP_CHARGE_PUMP_1,
2031 RT5668_OVCD_HP_MASK, RT5668_OVCD_HP_DIS); 2032 RT5663_OVCD_HP_MASK, RT5663_OVCD_HP_DIS);
2032 snd_soc_write(codec, RT5663_HP_CHARGE_PUMP_2, 0x1371); 2033 snd_soc_write(codec, RT5663_HP_CHARGE_PUMP_2, 0x1371);
2033 snd_soc_write(codec, RT5663_HP_BIAS, 0xabba); 2034 snd_soc_write(codec, RT5663_HP_BIAS, 0xabba);
2034 snd_soc_write(codec, RT5663_CHARGE_PUMP_1, 0x2224); 2035 snd_soc_write(codec, RT5663_CHARGE_PUMP_1, 0x2224);
@@ -2041,14 +2042,14 @@ static int rt5663_hp_event(struct snd_soc_dapm_widget *w,
2041 break; 2042 break;
2042 2043
2043 case SND_SOC_DAPM_PRE_PMD: 2044 case SND_SOC_DAPM_PRE_PMD:
2044 if (rt5663->codec_type == CODEC_TYPE_RT5668) { 2045 if (rt5663->codec_ver == CODEC_VER_1) {
2045 snd_soc_update_bits(codec, RT5663_HP_LOGIC_2, 2046 snd_soc_update_bits(codec, RT5663_HP_LOGIC_2,
2046 RT5668_HP_SIG_SRC1_MASK, 2047 RT5663_HP_SIG_SRC1_MASK,
2047 RT5668_HP_SIG_SRC1_REG); 2048 RT5663_HP_SIG_SRC1_REG);
2048 } else { 2049 } else {
2049 snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x3000, 0x0); 2050 snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x3000, 0x0);
2050 snd_soc_update_bits(codec, RT5663_HP_CHARGE_PUMP_1, 2051 snd_soc_update_bits(codec, RT5663_HP_CHARGE_PUMP_1,
2051 RT5668_OVCD_HP_MASK, RT5668_OVCD_HP_EN); 2052 RT5663_OVCD_HP_MASK, RT5663_OVCD_HP_EN);
2052 snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x0030, 0x0); 2053 snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x0030, 0x0);
2053 snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x000b, 2054 snd_soc_update_bits(codec, RT5663_DEPOP_1, 0x000b,
2054 0x000b); 2055 0x000b);
@@ -2062,7 +2063,7 @@ static int rt5663_hp_event(struct snd_soc_dapm_widget *w,
2062 return 0; 2063 return 0;
2063} 2064}
2064 2065
2065static int rt5668_bst2_power(struct snd_soc_dapm_widget *w, 2066static int rt5663_bst2_power(struct snd_soc_dapm_widget *w,
2066 struct snd_kcontrol *kcontrol, int event) 2067 struct snd_kcontrol *kcontrol, int event)
2067{ 2068{
2068 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 2069 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
@@ -2070,13 +2071,13 @@ static int rt5668_bst2_power(struct snd_soc_dapm_widget *w,
2070 switch (event) { 2071 switch (event) {
2071 case SND_SOC_DAPM_POST_PMU: 2072 case SND_SOC_DAPM_POST_PMU:
2072 snd_soc_update_bits(codec, RT5663_PWR_ANLG_2, 2073 snd_soc_update_bits(codec, RT5663_PWR_ANLG_2,
2073 RT5668_PWR_BST2_MASK | RT5668_PWR_BST2_OP_MASK, 2074 RT5663_PWR_BST2_MASK | RT5663_PWR_BST2_OP_MASK,
2074 RT5668_PWR_BST2 | RT5668_PWR_BST2_OP); 2075 RT5663_PWR_BST2 | RT5663_PWR_BST2_OP);
2075 break; 2076 break;
2076 2077
2077 case SND_SOC_DAPM_PRE_PMD: 2078 case SND_SOC_DAPM_PRE_PMD:
2078 snd_soc_update_bits(codec, RT5663_PWR_ANLG_2, 2079 snd_soc_update_bits(codec, RT5663_PWR_ANLG_2,
2079 RT5668_PWR_BST2_MASK | RT5668_PWR_BST2_OP_MASK, 0); 2080 RT5663_PWR_BST2_MASK | RT5663_PWR_BST2_OP_MASK, 0);
2080 break; 2081 break;
2081 2082
2082 default: 2083 default:
@@ -2110,14 +2111,14 @@ static int rt5663_pre_div_power(struct snd_soc_dapm_widget *w,
2110} 2111}
2111 2112
2112static const struct snd_soc_dapm_widget rt5663_dapm_widgets[] = { 2113static const struct snd_soc_dapm_widget rt5663_dapm_widgets[] = {
2113 SND_SOC_DAPM_SUPPLY("PLL", RT5663_PWR_ANLG_3, RT5668_PWR_PLL_SHIFT, 0, 2114 SND_SOC_DAPM_SUPPLY("PLL", RT5663_PWR_ANLG_3, RT5663_PWR_PLL_SHIFT, 0,
2114 NULL, 0), 2115 NULL, 0),
2115 2116
2116 /* micbias */ 2117 /* micbias */
2117 SND_SOC_DAPM_MICBIAS("MICBIAS1", RT5663_PWR_ANLG_2, 2118 SND_SOC_DAPM_MICBIAS("MICBIAS1", RT5663_PWR_ANLG_2,
2118 RT5668_PWR_MB1_SHIFT, 0), 2119 RT5663_PWR_MB1_SHIFT, 0),
2119 SND_SOC_DAPM_MICBIAS("MICBIAS2", RT5663_PWR_ANLG_2, 2120 SND_SOC_DAPM_MICBIAS("MICBIAS2", RT5663_PWR_ANLG_2,
2120 RT5668_PWR_MB2_SHIFT, 0), 2121 RT5663_PWR_MB2_SHIFT, 0),
2121 2122
2122 /* Input Lines */ 2123 /* Input Lines */
2123 SND_SOC_DAPM_INPUT("IN1P"), 2124 SND_SOC_DAPM_INPUT("IN1P"),
@@ -2125,14 +2126,14 @@ static const struct snd_soc_dapm_widget rt5663_dapm_widgets[] = {
2125 2126
2126 /* REC Mixer Power */ 2127 /* REC Mixer Power */
2127 SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5663_PWR_ANLG_2, 2128 SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5663_PWR_ANLG_2,
2128 RT5668_PWR_RECMIX1_SHIFT, 0, NULL, 0), 2129 RT5663_PWR_RECMIX1_SHIFT, 0, NULL, 0),
2129 2130
2130 /* ADCs */ 2131 /* ADCs */
2131 SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0), 2132 SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0),
2132 SND_SOC_DAPM_SUPPLY("ADC L Power", RT5663_PWR_DIG_1, 2133 SND_SOC_DAPM_SUPPLY("ADC L Power", RT5663_PWR_DIG_1,
2133 RT5668_PWR_ADC_L1_SHIFT, 0, NULL, 0), 2134 RT5663_PWR_ADC_L1_SHIFT, 0, NULL, 0),
2134 SND_SOC_DAPM_SUPPLY("ADC Clock", RT5663_CHOP_ADC, 2135 SND_SOC_DAPM_SUPPLY("ADC Clock", RT5663_CHOP_ADC,
2135 RT5668_CKGEN_ADCC_SHIFT, 0, NULL, 0), 2136 RT5663_CKGEN_ADCC_SHIFT, 0, NULL, 0),
2136 2137
2137 /* ADC Mixer */ 2138 /* ADC Mixer */
2138 SND_SOC_DAPM_MIXER("STO1 ADC MIXL", SND_SOC_NOPM, 2139 SND_SOC_DAPM_MIXER("STO1 ADC MIXL", SND_SOC_NOPM,
@@ -2141,10 +2142,10 @@ static const struct snd_soc_dapm_widget rt5663_dapm_widgets[] = {
2141 2142
2142 /* ADC Filter Power */ 2143 /* ADC Filter Power */
2143 SND_SOC_DAPM_SUPPLY("STO1 ADC Filter", RT5663_PWR_DIG_2, 2144 SND_SOC_DAPM_SUPPLY("STO1 ADC Filter", RT5663_PWR_DIG_2,
2144 RT5668_PWR_ADC_S1F_SHIFT, 0, NULL, 0), 2145 RT5663_PWR_ADC_S1F_SHIFT, 0, NULL, 0),
2145 2146
2146 /* Digital Interface */ 2147 /* Digital Interface */
2147 SND_SOC_DAPM_SUPPLY("I2S", RT5663_PWR_DIG_1, RT5668_PWR_I2S1_SHIFT, 0, 2148 SND_SOC_DAPM_SUPPLY("I2S", RT5663_PWR_DIG_1, RT5663_PWR_I2S1_SHIFT, 0,
2148 NULL, 0), 2149 NULL, 0),
2149 SND_SOC_DAPM_PGA("IF DAC", SND_SOC_NOPM, 0, 0, NULL, 0), 2150 SND_SOC_DAPM_PGA("IF DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2150 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0), 2151 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
@@ -2166,7 +2167,7 @@ static const struct snd_soc_dapm_widget rt5663_dapm_widgets[] = {
2166 2167
2167 /* DAC Mixer */ 2168 /* DAC Mixer */
2168 SND_SOC_DAPM_SUPPLY("STO1 DAC Filter", RT5663_PWR_DIG_2, 2169 SND_SOC_DAPM_SUPPLY("STO1 DAC Filter", RT5663_PWR_DIG_2,
2169 RT5668_PWR_DAC_S1F_SHIFT, 0, NULL, 0), 2170 RT5663_PWR_DAC_S1F_SHIFT, 0, NULL, 0),
2170 SND_SOC_DAPM_MIXER("STO1 DAC MIXL", SND_SOC_NOPM, 0, 0, 2171 SND_SOC_DAPM_MIXER("STO1 DAC MIXL", SND_SOC_NOPM, 0, 0,
2171 rt5663_sto1_dac_l_mix, ARRAY_SIZE(rt5663_sto1_dac_l_mix)), 2172 rt5663_sto1_dac_l_mix, ARRAY_SIZE(rt5663_sto1_dac_l_mix)),
2172 SND_SOC_DAPM_MIXER("STO1 DAC MIXR", SND_SOC_NOPM, 0, 0, 2173 SND_SOC_DAPM_MIXER("STO1 DAC MIXR", SND_SOC_NOPM, 0, 0,
@@ -2174,9 +2175,9 @@ static const struct snd_soc_dapm_widget rt5663_dapm_widgets[] = {
2174 2175
2175 /* DACs */ 2176 /* DACs */
2176 SND_SOC_DAPM_SUPPLY("STO1 DAC L Power", RT5663_PWR_DIG_1, 2177 SND_SOC_DAPM_SUPPLY("STO1 DAC L Power", RT5663_PWR_DIG_1,
2177 RT5668_PWR_DAC_L1_SHIFT, 0, NULL, 0), 2178 RT5663_PWR_DAC_L1_SHIFT, 0, NULL, 0),
2178 SND_SOC_DAPM_SUPPLY("STO1 DAC R Power", RT5663_PWR_DIG_1, 2179 SND_SOC_DAPM_SUPPLY("STO1 DAC R Power", RT5663_PWR_DIG_1,
2179 RT5668_PWR_DAC_R1_SHIFT, 0, NULL, 0), 2180 RT5663_PWR_DAC_R1_SHIFT, 0, NULL, 0),
2180 SND_SOC_DAPM_DAC("DAC L", NULL, SND_SOC_NOPM, 0, 0), 2181 SND_SOC_DAPM_DAC("DAC L", NULL, SND_SOC_NOPM, 0, 0),
2181 SND_SOC_DAPM_DAC("DAC R", NULL, SND_SOC_NOPM, 0, 0), 2182 SND_SOC_DAPM_DAC("DAC R", NULL, SND_SOC_NOPM, 0, 0),
2182 2183
@@ -2189,21 +2190,21 @@ static const struct snd_soc_dapm_widget rt5663_dapm_widgets[] = {
2189 SND_SOC_DAPM_OUTPUT("HPOR"), 2190 SND_SOC_DAPM_OUTPUT("HPOR"),
2190}; 2191};
2191 2192
2192static const struct snd_soc_dapm_widget rt5668_specific_dapm_widgets[] = { 2193static const struct snd_soc_dapm_widget rt5663_v2_specific_dapm_widgets[] = {
2193 SND_SOC_DAPM_SUPPLY("LDO2", RT5663_PWR_ANLG_3, 2194 SND_SOC_DAPM_SUPPLY("LDO2", RT5663_PWR_ANLG_3,
2194 RT5668_PWR_LDO2_SHIFT, 0, NULL, 0), 2195 RT5663_PWR_LDO2_SHIFT, 0, NULL, 0),
2195 SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5668_PWR_VOL, 2196 SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5663_PWR_VOL,
2196 RT5668_PWR_MIC_DET_SHIFT, 0, NULL, 0), 2197 RT5663_V2_PWR_MIC_DET_SHIFT, 0, NULL, 0),
2197 SND_SOC_DAPM_SUPPLY("LDO DAC", RT5663_PWR_DIG_1, 2198 SND_SOC_DAPM_SUPPLY("LDO DAC", RT5663_PWR_DIG_1,
2198 RT5668_PWR_LDO_DACREF_SHIFT, 0, NULL, 0), 2199 RT5663_PWR_LDO_DACREF_SHIFT, 0, NULL, 0),
2199 2200
2200 /* ASRC */ 2201 /* ASRC */
2201 SND_SOC_DAPM_SUPPLY("I2S ASRC", RT5663_ASRC_1, 2202 SND_SOC_DAPM_SUPPLY("I2S ASRC", RT5663_ASRC_1,
2202 RT5668_I2S1_ASRC_SHIFT, 0, NULL, 0), 2203 RT5663_I2S1_ASRC_SHIFT, 0, NULL, 0),
2203 SND_SOC_DAPM_SUPPLY("DAC ASRC", RT5663_ASRC_1, 2204 SND_SOC_DAPM_SUPPLY("DAC ASRC", RT5663_ASRC_1,
2204 RT5668_DAC_STO1_ASRC_SHIFT, 0, NULL, 0), 2205 RT5663_DAC_STO1_ASRC_SHIFT, 0, NULL, 0),
2205 SND_SOC_DAPM_SUPPLY("ADC ASRC", RT5663_ASRC_1, 2206 SND_SOC_DAPM_SUPPLY("ADC ASRC", RT5663_ASRC_1,
2206 RT5668_ADC_STO1_ASRC_SHIFT, 0, NULL, 0), 2207 RT5663_ADC_STO1_ASRC_SHIFT, 0, NULL, 0),
2207 2208
2208 /* Input Lines */ 2209 /* Input Lines */
2209 SND_SOC_DAPM_INPUT("IN2P"), 2210 SND_SOC_DAPM_INPUT("IN2P"),
@@ -2212,51 +2213,51 @@ static const struct snd_soc_dapm_widget rt5668_specific_dapm_widgets[] = {
2212 /* Boost */ 2213 /* Boost */
2213 SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM, 0, 0, NULL, 0), 2214 SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM, 0, 0, NULL, 0),
2214 SND_SOC_DAPM_SUPPLY("CBJ Power", RT5663_PWR_ANLG_3, 2215 SND_SOC_DAPM_SUPPLY("CBJ Power", RT5663_PWR_ANLG_3,
2215 RT5668_PWR_CBJ_SHIFT, 0, NULL, 0), 2216 RT5663_PWR_CBJ_SHIFT, 0, NULL, 0),
2216 SND_SOC_DAPM_PGA("BST2", SND_SOC_NOPM, 0, 0, NULL, 0), 2217 SND_SOC_DAPM_PGA("BST2", SND_SOC_NOPM, 0, 0, NULL, 0),
2217 SND_SOC_DAPM_SUPPLY("BST2 Power", SND_SOC_NOPM, 0, 0, 2218 SND_SOC_DAPM_SUPPLY("BST2 Power", SND_SOC_NOPM, 0, 0,
2218 rt5668_bst2_power, SND_SOC_DAPM_PRE_PMD | 2219 rt5663_bst2_power, SND_SOC_DAPM_PRE_PMD |
2219 SND_SOC_DAPM_POST_PMU), 2220 SND_SOC_DAPM_POST_PMU),
2220 2221
2221 /* REC Mixer */ 2222 /* REC Mixer */
2222 SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5668_recmix1l, 2223 SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5663_recmix1l,
2223 ARRAY_SIZE(rt5668_recmix1l)), 2224 ARRAY_SIZE(rt5663_recmix1l)),
2224 SND_SOC_DAPM_MIXER("RECMIX1R", SND_SOC_NOPM, 0, 0, rt5668_recmix1r, 2225 SND_SOC_DAPM_MIXER("RECMIX1R", SND_SOC_NOPM, 0, 0, rt5663_recmix1r,
2225 ARRAY_SIZE(rt5668_recmix1r)), 2226 ARRAY_SIZE(rt5663_recmix1r)),
2226 SND_SOC_DAPM_SUPPLY("RECMIX1R Power", RT5663_PWR_ANLG_2, 2227 SND_SOC_DAPM_SUPPLY("RECMIX1R Power", RT5663_PWR_ANLG_2,
2227 RT5668_PWR_RECMIX2_SHIFT, 0, NULL, 0), 2228 RT5663_PWR_RECMIX2_SHIFT, 0, NULL, 0),
2228 2229
2229 /* ADC */ 2230 /* ADC */
2230 SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0), 2231 SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0),
2231 SND_SOC_DAPM_SUPPLY("ADC R Power", RT5663_PWR_DIG_1, 2232 SND_SOC_DAPM_SUPPLY("ADC R Power", RT5663_PWR_DIG_1,
2232 RT5668_PWR_ADC_R1_SHIFT, 0, NULL, 0), 2233 RT5663_PWR_ADC_R1_SHIFT, 0, NULL, 0),
2233 2234
2234 /* ADC Mux */ 2235 /* ADC Mux */
2235 SND_SOC_DAPM_PGA("STO1 ADC L1", RT5663_STO1_ADC_MIXER, 2236 SND_SOC_DAPM_PGA("STO1 ADC L1", RT5663_STO1_ADC_MIXER,
2236 RT5668_STO1_ADC_L1_SRC_SHIFT, 0, NULL, 0), 2237 RT5663_STO1_ADC_L1_SRC_SHIFT, 0, NULL, 0),
2237 SND_SOC_DAPM_PGA("STO1 ADC R1", RT5663_STO1_ADC_MIXER, 2238 SND_SOC_DAPM_PGA("STO1 ADC R1", RT5663_STO1_ADC_MIXER,
2238 RT5668_STO1_ADC_R1_SRC_SHIFT, 0, NULL, 0), 2239 RT5663_STO1_ADC_R1_SRC_SHIFT, 0, NULL, 0),
2239 SND_SOC_DAPM_PGA("STO1 ADC L2", RT5663_STO1_ADC_MIXER, 2240 SND_SOC_DAPM_PGA("STO1 ADC L2", RT5663_STO1_ADC_MIXER,
2240 RT5668_STO1_ADC_L2_SRC_SHIFT, 1, NULL, 0), 2241 RT5663_STO1_ADC_L2_SRC_SHIFT, 1, NULL, 0),
2241 SND_SOC_DAPM_PGA("STO1 ADC R2", RT5663_STO1_ADC_MIXER, 2242 SND_SOC_DAPM_PGA("STO1 ADC R2", RT5663_STO1_ADC_MIXER,
2242 RT5668_STO1_ADC_R2_SRC_SHIFT, 1, NULL, 0), 2243 RT5663_STO1_ADC_R2_SRC_SHIFT, 1, NULL, 0),
2243 2244
2244 SND_SOC_DAPM_MUX("STO1 ADC L Mux", SND_SOC_NOPM, 0, 0, 2245 SND_SOC_DAPM_MUX("STO1 ADC L Mux", SND_SOC_NOPM, 0, 0,
2245 &rt5668_sto1_adcl_mux), 2246 &rt5663_sto1_adcl_mux),
2246 SND_SOC_DAPM_MUX("STO1 ADC R Mux", SND_SOC_NOPM, 0, 0, 2247 SND_SOC_DAPM_MUX("STO1 ADC R Mux", SND_SOC_NOPM, 0, 0,
2247 &rt5668_sto1_adcr_mux), 2248 &rt5663_sto1_adcr_mux),
2248 2249
2249 /* ADC Mix */ 2250 /* ADC Mix */
2250 SND_SOC_DAPM_MIXER("STO1 ADC MIXR", SND_SOC_NOPM, 0, 0, 2251 SND_SOC_DAPM_MIXER("STO1 ADC MIXR", SND_SOC_NOPM, 0, 0,
2251 rt5668_sto1_adc_r_mix, ARRAY_SIZE(rt5668_sto1_adc_r_mix)), 2252 rt5663_sto1_adc_r_mix, ARRAY_SIZE(rt5663_sto1_adc_r_mix)),
2252 2253
2253 /* Analog DAC Clock */ 2254 /* Analog DAC Clock */
2254 SND_SOC_DAPM_SUPPLY("DAC Clock", RT5663_CHOP_DAC_L, 2255 SND_SOC_DAPM_SUPPLY("DAC Clock", RT5663_CHOP_DAC_L,
2255 RT5668_CKGEN_DAC1_SHIFT, 0, NULL, 0), 2256 RT5663_CKGEN_DAC1_SHIFT, 0, NULL, 0),
2256 2257
2257 /* Headphone out */ 2258 /* Headphone out */
2258 SND_SOC_DAPM_SWITCH("HPO Playback", SND_SOC_NOPM, 0, 0, 2259 SND_SOC_DAPM_SWITCH("HPO Playback", SND_SOC_NOPM, 0, 0,
2259 &rt5668_hpo_switch), 2260 &rt5663_hpo_switch),
2260}; 2261};
2261 2262
2262static const struct snd_soc_dapm_widget rt5663_specific_dapm_widgets[] = { 2263static const struct snd_soc_dapm_widget rt5663_specific_dapm_widgets[] = {
@@ -2267,7 +2268,7 @@ static const struct snd_soc_dapm_widget rt5663_specific_dapm_widgets[] = {
2267 2268
2268 /* LDO */ 2269 /* LDO */
2269 SND_SOC_DAPM_SUPPLY("LDO ADC", RT5663_PWR_DIG_1, 2270 SND_SOC_DAPM_SUPPLY("LDO ADC", RT5663_PWR_DIG_1,
2270 RT5668_PWR_LDO_DACREF_SHIFT, 0, NULL, 0), 2271 RT5663_PWR_LDO_DACREF_SHIFT, 0, NULL, 0),
2271 2272
2272 /* ASRC */ 2273 /* ASRC */
2273 SND_SOC_DAPM_SUPPLY("I2S ASRC", RT5663_ASRC_1, 2274 SND_SOC_DAPM_SUPPLY("I2S ASRC", RT5663_ASRC_1,
@@ -2341,7 +2342,7 @@ static const struct snd_soc_dapm_route rt5663_dapm_routes[] = {
2341 { "HP Amp", NULL, "DAC R" }, 2342 { "HP Amp", NULL, "DAC R" },
2342}; 2343};
2343 2344
2344static const struct snd_soc_dapm_route rt5668_specific_dapm_routes[] = { 2345static const struct snd_soc_dapm_route rt5663_v2_specific_dapm_routes[] = {
2345 { "MICBIAS1", NULL, "LDO2" }, 2346 { "MICBIAS1", NULL, "LDO2" },
2346 { "MICBIAS2", NULL, "LDO2" }, 2347 { "MICBIAS2", NULL, "LDO2" },
2347 2348
@@ -2440,26 +2441,26 @@ static int rt5663_hw_params(struct snd_pcm_substream *substream,
2440 2441
2441 switch (params_width(params)) { 2442 switch (params_width(params)) {
2442 case 8: 2443 case 8:
2443 val_len = RT5668_I2S_DL_8; 2444 val_len = RT5663_I2S_DL_8;
2444 break; 2445 break;
2445 case 16: 2446 case 16:
2446 val_len = RT5668_I2S_DL_16; 2447 val_len = RT5663_I2S_DL_16;
2447 break; 2448 break;
2448 case 20: 2449 case 20:
2449 val_len = RT5668_I2S_DL_20; 2450 val_len = RT5663_I2S_DL_20;
2450 break; 2451 break;
2451 case 24: 2452 case 24:
2452 val_len = RT5668_I2S_DL_24; 2453 val_len = RT5663_I2S_DL_24;
2453 break; 2454 break;
2454 default: 2455 default:
2455 return -EINVAL; 2456 return -EINVAL;
2456 } 2457 }
2457 2458
2458 snd_soc_update_bits(codec, RT5663_I2S1_SDP, 2459 snd_soc_update_bits(codec, RT5663_I2S1_SDP,
2459 RT5668_I2S_DL_MASK, val_len); 2460 RT5663_I2S_DL_MASK, val_len);
2460 2461
2461 snd_soc_update_bits(codec, RT5663_ADDA_CLK_1, 2462 snd_soc_update_bits(codec, RT5663_ADDA_CLK_1,
2462 RT5668_I2S_PD1_MASK, pre_div << RT5668_I2S_PD1_SHIFT); 2463 RT5663_I2S_PD1_MASK, pre_div << RT5663_I2S_PD1_SHIFT);
2463 2464
2464 return 0; 2465 return 0;
2465} 2466}
@@ -2473,7 +2474,7 @@ static int rt5663_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2473 case SND_SOC_DAIFMT_CBM_CFM: 2474 case SND_SOC_DAIFMT_CBM_CFM:
2474 break; 2475 break;
2475 case SND_SOC_DAIFMT_CBS_CFS: 2476 case SND_SOC_DAIFMT_CBS_CFS:
2476 reg_val |= RT5668_I2S_MS_S; 2477 reg_val |= RT5663_I2S_MS_S;
2477 break; 2478 break;
2478 default: 2479 default:
2479 return -EINVAL; 2480 return -EINVAL;
@@ -2483,7 +2484,7 @@ static int rt5663_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2483 case SND_SOC_DAIFMT_NB_NF: 2484 case SND_SOC_DAIFMT_NB_NF:
2484 break; 2485 break;
2485 case SND_SOC_DAIFMT_IB_NF: 2486 case SND_SOC_DAIFMT_IB_NF:
2486 reg_val |= RT5668_I2S_BP_INV; 2487 reg_val |= RT5663_I2S_BP_INV;
2487 break; 2488 break;
2488 default: 2489 default:
2489 return -EINVAL; 2490 return -EINVAL;
@@ -2493,20 +2494,20 @@ static int rt5663_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2493 case SND_SOC_DAIFMT_I2S: 2494 case SND_SOC_DAIFMT_I2S:
2494 break; 2495 break;
2495 case SND_SOC_DAIFMT_LEFT_J: 2496 case SND_SOC_DAIFMT_LEFT_J:
2496 reg_val |= RT5668_I2S_DF_LEFT; 2497 reg_val |= RT5663_I2S_DF_LEFT;
2497 break; 2498 break;
2498 case SND_SOC_DAIFMT_DSP_A: 2499 case SND_SOC_DAIFMT_DSP_A:
2499 reg_val |= RT5668_I2S_DF_PCM_A; 2500 reg_val |= RT5663_I2S_DF_PCM_A;
2500 break; 2501 break;
2501 case SND_SOC_DAIFMT_DSP_B: 2502 case SND_SOC_DAIFMT_DSP_B:
2502 reg_val |= RT5668_I2S_DF_PCM_B; 2503 reg_val |= RT5663_I2S_DF_PCM_B;
2503 break; 2504 break;
2504 default: 2505 default:
2505 return -EINVAL; 2506 return -EINVAL;
2506 } 2507 }
2507 2508
2508 snd_soc_update_bits(codec, RT5663_I2S1_SDP, RT5668_I2S_MS_MASK | 2509 snd_soc_update_bits(codec, RT5663_I2S1_SDP, RT5663_I2S_MS_MASK |
2509 RT5668_I2S_BP_MASK | RT5668_I2S_DF_MASK, reg_val); 2510 RT5663_I2S_BP_MASK | RT5663_I2S_DF_MASK, reg_val);
2510 2511
2511 return 0; 2512 return 0;
2512} 2513}
@@ -2535,7 +2536,7 @@ static int rt5663_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
2535 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id); 2536 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
2536 return -EINVAL; 2537 return -EINVAL;
2537 } 2538 }
2538 snd_soc_update_bits(codec, RT5663_GLB_CLK, RT5668_SCLK_SRC_MASK, 2539 snd_soc_update_bits(codec, RT5663_GLB_CLK, RT5663_SCLK_SRC_MASK,
2539 reg_val); 2540 reg_val);
2540 rt5663->sysclk = freq; 2541 rt5663->sysclk = freq;
2541 rt5663->sysclk_src = clk_id; 2542 rt5663->sysclk_src = clk_id;
@@ -2569,17 +2570,17 @@ static int rt5663_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
2569 return 0; 2570 return 0;
2570 } 2571 }
2571 2572
2572 switch (rt5663->codec_type) { 2573 switch (rt5663->codec_ver) {
2573 case CODEC_TYPE_RT5668: 2574 case CODEC_VER_1:
2574 mask = RT5668_PLL1_SRC_MASK; 2575 mask = RT5663_V2_PLL1_SRC_MASK;
2575 shift = RT5668_PLL1_SRC_SHIFT; 2576 shift = RT5663_V2_PLL1_SRC_SHIFT;
2576 break; 2577 break;
2577 case CODEC_TYPE_RT5663: 2578 case CODEC_VER_0:
2578 mask = RT5663_PLL1_SRC_MASK; 2579 mask = RT5663_PLL1_SRC_MASK;
2579 shift = RT5663_PLL1_SRC_SHIFT; 2580 shift = RT5663_PLL1_SRC_SHIFT;
2580 break; 2581 break;
2581 default: 2582 default:
2582 dev_err(codec->dev, "Unknown CODEC_TYPE\n"); 2583 dev_err(codec->dev, "Unknown CODEC Version\n");
2583 return -EINVAL; 2584 return -EINVAL;
2584 } 2585 }
2585 2586
@@ -2607,10 +2608,10 @@ static int rt5663_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
2607 pll_code.k_code); 2608 pll_code.k_code);
2608 2609
2609 snd_soc_write(codec, RT5663_PLL_1, 2610 snd_soc_write(codec, RT5663_PLL_1,
2610 pll_code.n_code << RT5668_PLL_N_SHIFT | pll_code.k_code); 2611 pll_code.n_code << RT5663_PLL_N_SHIFT | pll_code.k_code);
2611 snd_soc_write(codec, RT5663_PLL_2, 2612 snd_soc_write(codec, RT5663_PLL_2,
2612 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5668_PLL_M_SHIFT | 2613 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5663_PLL_M_SHIFT |
2613 pll_code.m_bp << RT5668_PLL_M_BP_SHIFT); 2614 pll_code.m_bp << RT5663_PLL_M_BP_SHIFT);
2614 2615
2615 rt5663->pll_in = freq_in; 2616 rt5663->pll_in = freq_in;
2616 rt5663->pll_out = freq_out; 2617 rt5663->pll_out = freq_out;
@@ -2627,20 +2628,20 @@ static int rt5663_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
2627 unsigned int val = 0, reg; 2628 unsigned int val = 0, reg;
2628 2629
2629 if (rx_mask || tx_mask) 2630 if (rx_mask || tx_mask)
2630 val |= RT5668_TDM_MODE_TDM; 2631 val |= RT5663_TDM_MODE_TDM;
2631 2632
2632 switch (slots) { 2633 switch (slots) {
2633 case 4: 2634 case 4:
2634 val |= RT5668_TDM_IN_CH_4; 2635 val |= RT5663_TDM_IN_CH_4;
2635 val |= RT5668_TDM_OUT_CH_4; 2636 val |= RT5663_TDM_OUT_CH_4;
2636 break; 2637 break;
2637 case 6: 2638 case 6:
2638 val |= RT5668_TDM_IN_CH_6; 2639 val |= RT5663_TDM_IN_CH_6;
2639 val |= RT5668_TDM_OUT_CH_6; 2640 val |= RT5663_TDM_OUT_CH_6;
2640 break; 2641 break;
2641 case 8: 2642 case 8:
2642 val |= RT5668_TDM_IN_CH_8; 2643 val |= RT5663_TDM_IN_CH_8;
2643 val |= RT5668_TDM_OUT_CH_8; 2644 val |= RT5663_TDM_OUT_CH_8;
2644 break; 2645 break;
2645 case 2: 2646 case 2:
2646 break; 2647 break;
@@ -2650,16 +2651,16 @@ static int rt5663_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
2650 2651
2651 switch (slot_width) { 2652 switch (slot_width) {
2652 case 20: 2653 case 20:
2653 val |= RT5668_TDM_IN_LEN_20; 2654 val |= RT5663_TDM_IN_LEN_20;
2654 val |= RT5668_TDM_OUT_LEN_20; 2655 val |= RT5663_TDM_OUT_LEN_20;
2655 break; 2656 break;
2656 case 24: 2657 case 24:
2657 val |= RT5668_TDM_IN_LEN_24; 2658 val |= RT5663_TDM_IN_LEN_24;
2658 val |= RT5668_TDM_OUT_LEN_24; 2659 val |= RT5663_TDM_OUT_LEN_24;
2659 break; 2660 break;
2660 case 32: 2661 case 32:
2661 val |= RT5668_TDM_IN_LEN_32; 2662 val |= RT5663_TDM_IN_LEN_32;
2662 val |= RT5668_TDM_OUT_LEN_32; 2663 val |= RT5663_TDM_OUT_LEN_32;
2663 break; 2664 break;
2664 case 16: 2665 case 16:
2665 break; 2666 break;
@@ -2667,21 +2668,21 @@ static int rt5663_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
2667 return -EINVAL; 2668 return -EINVAL;
2668 } 2669 }
2669 2670
2670 switch (rt5663->codec_type) { 2671 switch (rt5663->codec_ver) {
2671 case CODEC_TYPE_RT5668: 2672 case CODEC_VER_1:
2672 reg = RT5663_TDM_2; 2673 reg = RT5663_TDM_2;
2673 break; 2674 break;
2674 case CODEC_TYPE_RT5663: 2675 case CODEC_VER_0:
2675 reg = RT5663_TDM_1; 2676 reg = RT5663_TDM_1;
2676 break; 2677 break;
2677 default: 2678 default:
2678 dev_err(codec->dev, "Unknown CODEC_TYPE\n"); 2679 dev_err(codec->dev, "Unknown CODEC Version\n");
2679 return -EINVAL; 2680 return -EINVAL;
2680 } 2681 }
2681 2682
2682 snd_soc_update_bits(codec, reg, RT5668_TDM_MODE_MASK | 2683 snd_soc_update_bits(codec, reg, RT5663_TDM_MODE_MASK |
2683 RT5668_TDM_IN_CH_MASK | RT5668_TDM_OUT_CH_MASK | 2684 RT5663_TDM_IN_CH_MASK | RT5663_TDM_OUT_CH_MASK |
2684 RT5668_TDM_IN_LEN_MASK | RT5668_TDM_OUT_LEN_MASK, val); 2685 RT5663_TDM_IN_LEN_MASK | RT5663_TDM_OUT_LEN_MASK, val);
2685 2686
2686 return 0; 2687 return 0;
2687} 2688}
@@ -2694,8 +2695,8 @@ static int rt5663_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
2694 2695
2695 dev_dbg(codec->dev, "%s ratio = %d\n", __func__, ratio); 2696 dev_dbg(codec->dev, "%s ratio = %d\n", __func__, ratio);
2696 2697
2697 if (rt5663->codec_type == CODEC_TYPE_RT5668) 2698 if (rt5663->codec_ver == CODEC_VER_1)
2698 reg = RT5668_TDM_8; 2699 reg = RT5663_TDM_9;
2699 else 2700 else
2700 reg = RT5663_TDM_5; 2701 reg = RT5663_TDM_5;
2701 2702
@@ -2736,47 +2737,47 @@ static int rt5663_set_bias_level(struct snd_soc_codec *codec,
2736 switch (level) { 2737 switch (level) {
2737 case SND_SOC_BIAS_ON: 2738 case SND_SOC_BIAS_ON:
2738 snd_soc_update_bits(codec, RT5663_PWR_ANLG_1, 2739 snd_soc_update_bits(codec, RT5663_PWR_ANLG_1,
2739 RT5668_PWR_FV1_MASK | RT5668_PWR_FV2_MASK, 2740 RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK,
2740 RT5668_PWR_FV1 | RT5668_PWR_FV2); 2741 RT5663_PWR_FV1 | RT5663_PWR_FV2);
2741 break; 2742 break;
2742 2743
2743 case SND_SOC_BIAS_PREPARE: 2744 case SND_SOC_BIAS_PREPARE:
2744 if (rt5663->codec_type == CODEC_TYPE_RT5668) { 2745 if (rt5663->codec_ver == CODEC_VER_1) {
2745 snd_soc_update_bits(codec, RT5663_DIG_MISC, 2746 snd_soc_update_bits(codec, RT5663_DIG_MISC,
2746 RT5668_DIG_GATE_CTRL_MASK, 2747 RT5663_DIG_GATE_CTRL_MASK,
2747 RT5668_DIG_GATE_CTRL_EN); 2748 RT5663_DIG_GATE_CTRL_EN);
2748 snd_soc_update_bits(codec, RT5663_SIG_CLK_DET, 2749 snd_soc_update_bits(codec, RT5663_SIG_CLK_DET,
2749 RT5668_EN_ANA_CLK_DET_MASK | 2750 RT5663_EN_ANA_CLK_DET_MASK |
2750 RT5668_PWR_CLK_DET_MASK, 2751 RT5663_PWR_CLK_DET_MASK,
2751 RT5668_EN_ANA_CLK_DET_AUTO | 2752 RT5663_EN_ANA_CLK_DET_AUTO |
2752 RT5668_PWR_CLK_DET_EN); 2753 RT5663_PWR_CLK_DET_EN);
2753 } 2754 }
2754 break; 2755 break;
2755 2756
2756 case SND_SOC_BIAS_STANDBY: 2757 case SND_SOC_BIAS_STANDBY:
2757 if (rt5663->codec_type == CODEC_TYPE_RT5668) 2758 if (rt5663->codec_ver == CODEC_VER_1)
2758 snd_soc_update_bits(codec, RT5663_DIG_MISC, 2759 snd_soc_update_bits(codec, RT5663_DIG_MISC,
2759 RT5668_DIG_GATE_CTRL_MASK, 2760 RT5663_DIG_GATE_CTRL_MASK,
2760 RT5668_DIG_GATE_CTRL_DIS); 2761 RT5663_DIG_GATE_CTRL_DIS);
2761 snd_soc_update_bits(codec, RT5663_PWR_ANLG_1, 2762 snd_soc_update_bits(codec, RT5663_PWR_ANLG_1,
2762 RT5668_PWR_VREF1_MASK | RT5668_PWR_VREF2_MASK | 2763 RT5663_PWR_VREF1_MASK | RT5663_PWR_VREF2_MASK |
2763 RT5668_PWR_FV1_MASK | RT5668_PWR_FV2_MASK | 2764 RT5663_PWR_FV1_MASK | RT5663_PWR_FV2_MASK |
2764 RT5668_PWR_MB_MASK, RT5668_PWR_VREF1 | 2765 RT5663_PWR_MB_MASK, RT5663_PWR_VREF1 |
2765 RT5668_PWR_VREF2 | RT5668_PWR_MB); 2766 RT5663_PWR_VREF2 | RT5663_PWR_MB);
2766 usleep_range(10000, 10005); 2767 usleep_range(10000, 10005);
2767 if (rt5663->codec_type == CODEC_TYPE_RT5668) { 2768 if (rt5663->codec_ver == CODEC_VER_1) {
2768 snd_soc_update_bits(codec, RT5663_SIG_CLK_DET, 2769 snd_soc_update_bits(codec, RT5663_SIG_CLK_DET,
2769 RT5668_EN_ANA_CLK_DET_MASK | 2770 RT5663_EN_ANA_CLK_DET_MASK |
2770 RT5668_PWR_CLK_DET_MASK, 2771 RT5663_PWR_CLK_DET_MASK,
2771 RT5668_EN_ANA_CLK_DET_DIS | 2772 RT5663_EN_ANA_CLK_DET_DIS |
2772 RT5668_PWR_CLK_DET_DIS); 2773 RT5663_PWR_CLK_DET_DIS);
2773 } 2774 }
2774 break; 2775 break;
2775 2776
2776 case SND_SOC_BIAS_OFF: 2777 case SND_SOC_BIAS_OFF:
2777 snd_soc_update_bits(codec, RT5663_PWR_ANLG_1, 2778 snd_soc_update_bits(codec, RT5663_PWR_ANLG_1,
2778 RT5668_PWR_VREF1_MASK | RT5668_PWR_VREF2_MASK | 2779 RT5663_PWR_VREF1_MASK | RT5663_PWR_VREF2_MASK |
2779 RT5668_PWR_FV1 | RT5668_PWR_FV2, 0x0); 2780 RT5663_PWR_FV1 | RT5663_PWR_FV2, 0x0);
2780 break; 2781 break;
2781 2782
2782 default: 2783 default:
@@ -2793,18 +2794,18 @@ static int rt5663_probe(struct snd_soc_codec *codec)
2793 2794
2794 rt5663->codec = codec; 2795 rt5663->codec = codec;
2795 2796
2796 switch (rt5663->codec_type) { 2797 switch (rt5663->codec_ver) {
2797 case CODEC_TYPE_RT5668: 2798 case CODEC_VER_1:
2798 snd_soc_dapm_new_controls(dapm, 2799 snd_soc_dapm_new_controls(dapm,
2799 rt5668_specific_dapm_widgets, 2800 rt5663_v2_specific_dapm_widgets,
2800 ARRAY_SIZE(rt5668_specific_dapm_widgets)); 2801 ARRAY_SIZE(rt5663_v2_specific_dapm_widgets));
2801 snd_soc_dapm_add_routes(dapm, 2802 snd_soc_dapm_add_routes(dapm,
2802 rt5668_specific_dapm_routes, 2803 rt5663_v2_specific_dapm_routes,
2803 ARRAY_SIZE(rt5668_specific_dapm_routes)); 2804 ARRAY_SIZE(rt5663_v2_specific_dapm_routes));
2804 snd_soc_add_codec_controls(codec, rt5668_specific_controls, 2805 snd_soc_add_codec_controls(codec, rt5663_v2_specific_controls,
2805 ARRAY_SIZE(rt5668_specific_controls)); 2806 ARRAY_SIZE(rt5663_v2_specific_controls));
2806 break; 2807 break;
2807 case CODEC_TYPE_RT5663: 2808 case CODEC_VER_0:
2808 snd_soc_dapm_new_controls(dapm, 2809 snd_soc_dapm_new_controls(dapm,
2809 rt5663_specific_dapm_widgets, 2810 rt5663_specific_dapm_widgets,
2810 ARRAY_SIZE(rt5663_specific_dapm_widgets)); 2811 ARRAY_SIZE(rt5663_specific_dapm_widgets));
@@ -2905,16 +2906,16 @@ static struct snd_soc_codec_driver soc_codec_dev_rt5663 = {
2905 } 2906 }
2906}; 2907};
2907 2908
2908static const struct regmap_config rt5668_regmap = { 2909static const struct regmap_config rt5663_v2_regmap = {
2909 .reg_bits = 16, 2910 .reg_bits = 16,
2910 .val_bits = 16, 2911 .val_bits = 16,
2911 .use_single_rw = true, 2912 .use_single_rw = true,
2912 .max_register = 0x07fa, 2913 .max_register = 0x07fa,
2913 .volatile_reg = rt5668_volatile_register, 2914 .volatile_reg = rt5663_v2_volatile_register,
2914 .readable_reg = rt5668_readable_register, 2915 .readable_reg = rt5663_v2_readable_register,
2915 .cache_type = REGCACHE_RBTREE, 2916 .cache_type = REGCACHE_RBTREE,
2916 .reg_defaults = rt5668_reg, 2917 .reg_defaults = rt5663_v2_reg,
2917 .num_reg_defaults = ARRAY_SIZE(rt5668_reg), 2918 .num_reg_defaults = ARRAY_SIZE(rt5663_v2_reg),
2918}; 2919};
2919 2920
2920static const struct regmap_config rt5663_regmap = { 2921static const struct regmap_config rt5663_regmap = {
@@ -2939,7 +2940,6 @@ static const struct regmap_config temp_regmap = {
2939}; 2940};
2940 2941
2941static const struct i2c_device_id rt5663_i2c_id[] = { 2942static const struct i2c_device_id rt5663_i2c_id[] = {
2942 { "rt5668", 0 },
2943 { "rt5663", 0 }, 2943 { "rt5663", 0 },
2944 {} 2944 {}
2945}; 2945};
@@ -2947,7 +2947,6 @@ MODULE_DEVICE_TABLE(i2c, rt5663_i2c_id);
2947 2947
2948#if defined(CONFIG_OF) 2948#if defined(CONFIG_OF)
2949static const struct of_device_id rt5663_of_match[] = { 2949static const struct of_device_id rt5663_of_match[] = {
2950 { .compatible = "realtek,rt5668", },
2951 { .compatible = "realtek,rt5663", }, 2950 { .compatible = "realtek,rt5663", },
2952 {}, 2951 {},
2953}; 2952};
@@ -2956,80 +2955,79 @@ MODULE_DEVICE_TABLE(of, rt5663_of_match);
2956 2955
2957#ifdef CONFIG_ACPI 2956#ifdef CONFIG_ACPI
2958static struct acpi_device_id rt5663_acpi_match[] = { 2957static struct acpi_device_id rt5663_acpi_match[] = {
2959 { "10EC5668", 0},
2960 { "10EC5663", 0}, 2958 { "10EC5663", 0},
2961 {}, 2959 {},
2962}; 2960};
2963MODULE_DEVICE_TABLE(acpi, rt5663_acpi_match); 2961MODULE_DEVICE_TABLE(acpi, rt5663_acpi_match);
2964#endif 2962#endif
2965 2963
2966static void rt5668_calibrate(struct rt5663_priv *rt5668) 2964static void rt5663_v2_calibrate(struct rt5663_priv *rt5663)
2967{ 2965{
2968 regmap_write(rt5668->regmap, RT5663_BIAS_CUR_8, 0xa402); 2966 regmap_write(rt5663->regmap, RT5663_BIAS_CUR_8, 0xa402);
2969 regmap_write(rt5668->regmap, RT5663_PWR_DIG_1, 0x0100); 2967 regmap_write(rt5663->regmap, RT5663_PWR_DIG_1, 0x0100);
2970 regmap_write(rt5668->regmap, RT5663_RECMIX, 0x4040); 2968 regmap_write(rt5663->regmap, RT5663_RECMIX, 0x4040);
2971 regmap_write(rt5668->regmap, RT5663_DIG_MISC, 0x0001); 2969 regmap_write(rt5663->regmap, RT5663_DIG_MISC, 0x0001);
2972 regmap_write(rt5668->regmap, RT5663_RC_CLK, 0x0380); 2970 regmap_write(rt5663->regmap, RT5663_RC_CLK, 0x0380);
2973 regmap_write(rt5668->regmap, RT5663_GLB_CLK, 0x8000); 2971 regmap_write(rt5663->regmap, RT5663_GLB_CLK, 0x8000);
2974 regmap_write(rt5668->regmap, RT5663_ADDA_CLK_1, 0x1000); 2972 regmap_write(rt5663->regmap, RT5663_ADDA_CLK_1, 0x1000);
2975 regmap_write(rt5668->regmap, RT5663_CHOP_DAC_L, 0x3030); 2973 regmap_write(rt5663->regmap, RT5663_CHOP_DAC_L, 0x3030);
2976 regmap_write(rt5668->regmap, RT5663_CALIB_ADC, 0x3c05); 2974 regmap_write(rt5663->regmap, RT5663_CALIB_ADC, 0x3c05);
2977 regmap_write(rt5668->regmap, RT5663_PWR_ANLG_1, 0xa23e); 2975 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xa23e);
2978 msleep(40); 2976 msleep(40);
2979 regmap_write(rt5668->regmap, RT5663_PWR_ANLG_1, 0xf23e); 2977 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xf23e);
2980 regmap_write(rt5668->regmap, RT5663_HP_CALIB_2, 0x0321); 2978 regmap_write(rt5663->regmap, RT5663_HP_CALIB_2, 0x0321);
2981 regmap_write(rt5668->regmap, RT5663_HP_CALIB_1, 0xfc00); 2979 regmap_write(rt5663->regmap, RT5663_HP_CALIB_1, 0xfc00);
2982 msleep(500); 2980 msleep(500);
2983} 2981}
2984 2982
2985static void rt5663_calibrate(struct rt5663_priv *rt5668) 2983static void rt5663_calibrate(struct rt5663_priv *rt5663)
2986{ 2984{
2987 int value, count; 2985 int value, count;
2988 2986
2989 regmap_write(rt5668->regmap, RT5663_RC_CLK, 0x0280); 2987 regmap_write(rt5663->regmap, RT5663_RC_CLK, 0x0280);
2990 regmap_write(rt5668->regmap, RT5663_GLB_CLK, 0x8000); 2988 regmap_write(rt5663->regmap, RT5663_GLB_CLK, 0x8000);
2991 regmap_write(rt5668->regmap, RT5663_DIG_MISC, 0x8001); 2989 regmap_write(rt5663->regmap, RT5663_DIG_MISC, 0x8001);
2992 regmap_write(rt5668->regmap, RT5663_VREF_RECMIX, 0x0032); 2990 regmap_write(rt5663->regmap, RT5663_VREF_RECMIX, 0x0032);
2993 regmap_write(rt5668->regmap, RT5663_PWR_ANLG_1, 0xa2be); 2991 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xa2be);
2994 msleep(20); 2992 msleep(20);
2995 regmap_write(rt5668->regmap, RT5663_PWR_ANLG_1, 0xf2be); 2993 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_1, 0xf2be);
2996 regmap_write(rt5668->regmap, RT5663_PWR_DIG_2, 0x8400); 2994 regmap_write(rt5663->regmap, RT5663_PWR_DIG_2, 0x8400);
2997 regmap_write(rt5668->regmap, RT5663_CHOP_ADC, 0x3000); 2995 regmap_write(rt5663->regmap, RT5663_CHOP_ADC, 0x3000);
2998 regmap_write(rt5668->regmap, RT5663_DEPOP_1, 0x003b); 2996 regmap_write(rt5663->regmap, RT5663_DEPOP_1, 0x003b);
2999 regmap_write(rt5668->regmap, RT5663_PWR_DIG_1, 0x8df8); 2997 regmap_write(rt5663->regmap, RT5663_PWR_DIG_1, 0x8df8);
3000 regmap_write(rt5668->regmap, RT5663_PWR_ANLG_2, 0x0003); 2998 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_2, 0x0003);
3001 regmap_write(rt5668->regmap, RT5663_PWR_ANLG_3, 0x018c); 2999 regmap_write(rt5663->regmap, RT5663_PWR_ANLG_3, 0x018c);
3002 regmap_write(rt5668->regmap, RT5663_ADDA_CLK_1, 0x1111); 3000 regmap_write(rt5663->regmap, RT5663_ADDA_CLK_1, 0x1111);
3003 regmap_write(rt5668->regmap, RT5663_PRE_DIV_GATING_1, 0xffff); 3001 regmap_write(rt5663->regmap, RT5663_PRE_DIV_GATING_1, 0xffff);
3004 regmap_write(rt5668->regmap, RT5663_PRE_DIV_GATING_2, 0xffff); 3002 regmap_write(rt5663->regmap, RT5663_PRE_DIV_GATING_2, 0xffff);
3005 regmap_write(rt5668->regmap, RT5663_DEPOP_2, 0x3003); 3003 regmap_write(rt5663->regmap, RT5663_DEPOP_2, 0x3003);
3006 regmap_write(rt5668->regmap, RT5663_DEPOP_1, 0x003b); 3004 regmap_write(rt5663->regmap, RT5663_DEPOP_1, 0x003b);
3007 regmap_write(rt5668->regmap, RT5663_HP_CHARGE_PUMP_1, 0x1e32); 3005 regmap_write(rt5663->regmap, RT5663_HP_CHARGE_PUMP_1, 0x1e32);
3008 regmap_write(rt5668->regmap, RT5663_HP_CHARGE_PUMP_2, 0x1371); 3006 regmap_write(rt5663->regmap, RT5663_HP_CHARGE_PUMP_2, 0x1371);
3009 regmap_write(rt5668->regmap, RT5663_DACREF_LDO, 0x3b0b); 3007 regmap_write(rt5663->regmap, RT5663_DACREF_LDO, 0x3b0b);
3010 regmap_write(rt5668->regmap, RT5663_STO_DAC_MIXER, 0x2080); 3008 regmap_write(rt5663->regmap, RT5663_STO_DAC_MIXER, 0x2080);
3011 regmap_write(rt5668->regmap, RT5663_BYPASS_STO_DAC, 0x000c); 3009 regmap_write(rt5663->regmap, RT5663_BYPASS_STO_DAC, 0x000c);
3012 regmap_write(rt5668->regmap, RT5663_HP_BIAS, 0xabba); 3010 regmap_write(rt5663->regmap, RT5663_HP_BIAS, 0xabba);
3013 regmap_write(rt5668->regmap, RT5663_CHARGE_PUMP_1, 0x2224); 3011 regmap_write(rt5663->regmap, RT5663_CHARGE_PUMP_1, 0x2224);
3014 regmap_write(rt5668->regmap, RT5663_HP_OUT_EN, 0x8088); 3012 regmap_write(rt5663->regmap, RT5663_HP_OUT_EN, 0x8088);
3015 regmap_write(rt5668->regmap, RT5663_STO_DRE_9, 0x0017); 3013 regmap_write(rt5663->regmap, RT5663_STO_DRE_9, 0x0017);
3016 regmap_write(rt5668->regmap, RT5663_STO_DRE_10, 0x0017); 3014 regmap_write(rt5663->regmap, RT5663_STO_DRE_10, 0x0017);
3017 regmap_write(rt5668->regmap, RT5663_STO1_ADC_MIXER, 0x4040); 3015 regmap_write(rt5663->regmap, RT5663_STO1_ADC_MIXER, 0x4040);
3018 regmap_write(rt5668->regmap, RT5663_RECMIX, 0x0005); 3016 regmap_write(rt5663->regmap, RT5663_RECMIX, 0x0005);
3019 regmap_write(rt5668->regmap, RT5663_ADDA_RST, 0xc000); 3017 regmap_write(rt5663->regmap, RT5663_ADDA_RST, 0xc000);
3020 regmap_write(rt5668->regmap, RT5663_STO1_HPF_ADJ1, 0x3320); 3018 regmap_write(rt5663->regmap, RT5663_STO1_HPF_ADJ1, 0x3320);
3021 regmap_write(rt5668->regmap, RT5663_HP_CALIB_2, 0x00c9); 3019 regmap_write(rt5663->regmap, RT5663_HP_CALIB_2, 0x00c9);
3022 regmap_write(rt5668->regmap, RT5663_DUMMY_1, 0x004c); 3020 regmap_write(rt5663->regmap, RT5663_DUMMY_1, 0x004c);
3023 regmap_write(rt5668->regmap, RT5663_ANA_BIAS_CUR_1, 0x7766); 3021 regmap_write(rt5663->regmap, RT5663_ANA_BIAS_CUR_1, 0x7766);
3024 regmap_write(rt5668->regmap, RT5663_BIAS_CUR_8, 0x4702); 3022 regmap_write(rt5663->regmap, RT5663_BIAS_CUR_8, 0x4702);
3025 msleep(200); 3023 msleep(200);
3026 regmap_write(rt5668->regmap, RT5663_HP_CALIB_1, 0x0069); 3024 regmap_write(rt5663->regmap, RT5663_HP_CALIB_1, 0x0069);
3027 regmap_write(rt5668->regmap, RT5663_HP_CALIB_3, 0x06c2); 3025 regmap_write(rt5663->regmap, RT5663_HP_CALIB_3, 0x06c2);
3028 regmap_write(rt5668->regmap, RT5663_HP_CALIB_1_1, 0x7b00); 3026 regmap_write(rt5663->regmap, RT5663_HP_CALIB_1_1, 0x7b00);
3029 regmap_write(rt5668->regmap, RT5663_HP_CALIB_1_1, 0xfb00); 3027 regmap_write(rt5663->regmap, RT5663_HP_CALIB_1_1, 0xfb00);
3030 count = 0; 3028 count = 0;
3031 while (true) { 3029 while (true) {
3032 regmap_read(rt5668->regmap, RT5663_HP_CALIB_1_1, &value); 3030 regmap_read(rt5663->regmap, RT5663_HP_CALIB_1_1, &value);
3033 if (value & 0x8000) 3031 if (value & 0x8000)
3034 usleep_range(10000, 10005); 3032 usleep_range(10000, 10005);
3035 else 3033 else
@@ -3066,17 +3064,17 @@ static int rt5663_i2c_probe(struct i2c_client *i2c,
3066 } 3064 }
3067 regmap_read(regmap, RT5663_VENDOR_ID_2, &val); 3065 regmap_read(regmap, RT5663_VENDOR_ID_2, &val);
3068 switch (val) { 3066 switch (val) {
3069 case RT5668_DEVICE_ID: 3067 case RT5663_DEVICE_ID_2:
3070 rt5663->regmap = devm_regmap_init_i2c(i2c, &rt5668_regmap); 3068 rt5663->regmap = devm_regmap_init_i2c(i2c, &rt5663_v2_regmap);
3071 rt5663->codec_type = CODEC_TYPE_RT5668; 3069 rt5663->codec_ver = CODEC_VER_1;
3072 break; 3070 break;
3073 case RT5663_DEVICE_ID: 3071 case RT5663_DEVICE_ID_1:
3074 rt5663->regmap = devm_regmap_init_i2c(i2c, &rt5663_regmap); 3072 rt5663->regmap = devm_regmap_init_i2c(i2c, &rt5663_regmap);
3075 rt5663->codec_type = CODEC_TYPE_RT5663; 3073 rt5663->codec_ver = CODEC_VER_0;
3076 break; 3074 break;
3077 default: 3075 default:
3078 dev_err(&i2c->dev, 3076 dev_err(&i2c->dev,
3079 "Device with ID register %#x is not rt5663 or rt5668\n", 3077 "Device with ID register %#x is not rt5663\n",
3080 val); 3078 val);
3081 return -ENODEV; 3079 return -ENODEV;
3082 } 3080 }
@@ -3091,11 +3089,11 @@ static int rt5663_i2c_probe(struct i2c_client *i2c,
3091 /* reset and calibrate */ 3089 /* reset and calibrate */
3092 regmap_write(rt5663->regmap, RT5663_RESET, 0); 3090 regmap_write(rt5663->regmap, RT5663_RESET, 0);
3093 regcache_cache_bypass(rt5663->regmap, true); 3091 regcache_cache_bypass(rt5663->regmap, true);
3094 switch (rt5663->codec_type) { 3092 switch (rt5663->codec_ver) {
3095 case CODEC_TYPE_RT5668: 3093 case CODEC_VER_1:
3096 rt5668_calibrate(rt5663); 3094 rt5663_v2_calibrate(rt5663);
3097 break; 3095 break;
3098 case CODEC_TYPE_RT5663: 3096 case CODEC_VER_0:
3099 rt5663_calibrate(rt5663); 3097 rt5663_calibrate(rt5663);
3100 break; 3098 break;
3101 default: 3099 default:
@@ -3106,44 +3104,44 @@ static int rt5663_i2c_probe(struct i2c_client *i2c,
3106 dev_dbg(&i2c->dev, "calibrate done\n"); 3104 dev_dbg(&i2c->dev, "calibrate done\n");
3107 3105
3108 /* GPIO1 as IRQ */ 3106 /* GPIO1 as IRQ */
3109 regmap_update_bits(rt5663->regmap, RT5663_GPIO_1, RT5668_GP1_PIN_MASK, 3107 regmap_update_bits(rt5663->regmap, RT5663_GPIO_1, RT5663_GP1_PIN_MASK,
3110 RT5668_GP1_PIN_IRQ); 3108 RT5663_GP1_PIN_IRQ);
3111 /* 4btn inline command debounce */ 3109 /* 4btn inline command debounce */
3112 regmap_update_bits(rt5663->regmap, RT5663_IL_CMD_5, 3110 regmap_update_bits(rt5663->regmap, RT5663_IL_CMD_5,
3113 RT5668_4BTN_CLK_DEB_MASK, RT5668_4BTN_CLK_DEB_65MS); 3111 RT5663_4BTN_CLK_DEB_MASK, RT5663_4BTN_CLK_DEB_65MS);
3114 3112
3115 switch (rt5663->codec_type) { 3113 switch (rt5663->codec_ver) {
3116 case CODEC_TYPE_RT5668: 3114 case CODEC_VER_1:
3117 regmap_write(rt5663->regmap, RT5663_BIAS_CUR_8, 0xa402); 3115 regmap_write(rt5663->regmap, RT5663_BIAS_CUR_8, 0xa402);
3118 /* JD1 */ 3116 /* JD1 */
3119 regmap_update_bits(rt5663->regmap, RT5663_AUTO_1MRC_CLK, 3117 regmap_update_bits(rt5663->regmap, RT5663_AUTO_1MRC_CLK,
3120 RT5668_IRQ_POW_SAV_MASK | RT5668_IRQ_POW_SAV_JD1_MASK, 3118 RT5663_IRQ_POW_SAV_MASK | RT5663_IRQ_POW_SAV_JD1_MASK,
3121 RT5668_IRQ_POW_SAV_EN | RT5668_IRQ_POW_SAV_JD1_EN); 3119 RT5663_IRQ_POW_SAV_EN | RT5663_IRQ_POW_SAV_JD1_EN);
3122 regmap_update_bits(rt5663->regmap, RT5663_PWR_ANLG_2, 3120 regmap_update_bits(rt5663->regmap, RT5663_PWR_ANLG_2,
3123 RT5668_PWR_JD1_MASK, RT5668_PWR_JD1); 3121 RT5663_PWR_JD1_MASK, RT5663_PWR_JD1);
3124 regmap_update_bits(rt5663->regmap, RT5663_IRQ_1, 3122 regmap_update_bits(rt5663->regmap, RT5663_IRQ_1,
3125 RT5668_EN_CB_JD_MASK, RT5668_EN_CB_JD_EN); 3123 RT5663_EN_CB_JD_MASK, RT5663_EN_CB_JD_EN);
3126 3124
3127 regmap_update_bits(rt5663->regmap, RT5663_HP_LOGIC_2, 3125 regmap_update_bits(rt5663->regmap, RT5663_HP_LOGIC_2,
3128 RT5668_HP_SIG_SRC1_MASK, RT5668_HP_SIG_SRC1_REG); 3126 RT5663_HP_SIG_SRC1_MASK, RT5663_HP_SIG_SRC1_REG);
3129 regmap_update_bits(rt5663->regmap, RT5663_RECMIX, 3127 regmap_update_bits(rt5663->regmap, RT5663_RECMIX,
3130 RT5668_VREF_BIAS_MASK | RT5668_CBJ_DET_MASK | 3128 RT5663_VREF_BIAS_MASK | RT5663_CBJ_DET_MASK |
3131 RT5668_DET_TYPE_MASK, RT5668_VREF_BIAS_REG | 3129 RT5663_DET_TYPE_MASK, RT5663_VREF_BIAS_REG |
3132 RT5668_CBJ_DET_EN | RT5668_DET_TYPE_QFN); 3130 RT5663_CBJ_DET_EN | RT5663_DET_TYPE_QFN);
3133 /* Set GPIO4 and GPIO8 as input for combo jack */ 3131 /* Set GPIO4 and GPIO8 as input for combo jack */
3134 regmap_update_bits(rt5663->regmap, RT5663_GPIO_2, 3132 regmap_update_bits(rt5663->regmap, RT5663_GPIO_2,
3135 RT5668_GP4_PIN_CONF_MASK, RT5668_GP4_PIN_CONF_INPUT); 3133 RT5663_GP4_PIN_CONF_MASK, RT5663_GP4_PIN_CONF_INPUT);
3136 regmap_update_bits(rt5663->regmap, RT5668_GPIO_3, 3134 regmap_update_bits(rt5663->regmap, RT5663_GPIO_3,
3137 RT5668_GP8_PIN_CONF_MASK, RT5668_GP8_PIN_CONF_INPUT); 3135 RT5663_GP8_PIN_CONF_MASK, RT5663_GP8_PIN_CONF_INPUT);
3138 regmap_update_bits(rt5663->regmap, RT5663_PWR_ANLG_1, 3136 regmap_update_bits(rt5663->regmap, RT5663_PWR_ANLG_1,
3139 RT5668_LDO1_DVO_MASK | RT5668_AMP_HP_MASK, 3137 RT5663_LDO1_DVO_MASK | RT5663_AMP_HP_MASK,
3140 RT5668_LDO1_DVO_0_9V | RT5668_AMP_HP_3X); 3138 RT5663_LDO1_DVO_0_9V | RT5663_AMP_HP_3X);
3141 break; 3139 break;
3142 case CODEC_TYPE_RT5663: 3140 case CODEC_VER_0:
3143 regmap_update_bits(rt5663->regmap, RT5663_DIG_MISC, 3141 regmap_update_bits(rt5663->regmap, RT5663_DIG_MISC,
3144 RT5668_DIG_GATE_CTRL_MASK, RT5668_DIG_GATE_CTRL_EN); 3142 RT5663_DIG_GATE_CTRL_MASK, RT5663_DIG_GATE_CTRL_EN);
3145 regmap_update_bits(rt5663->regmap, RT5663_AUTO_1MRC_CLK, 3143 regmap_update_bits(rt5663->regmap, RT5663_AUTO_1MRC_CLK,
3146 RT5668_IRQ_POW_SAV_MASK, RT5668_IRQ_POW_SAV_EN); 3144 RT5663_IRQ_POW_SAV_MASK, RT5663_IRQ_POW_SAV_EN);
3147 regmap_update_bits(rt5663->regmap, RT5663_IRQ_1, 3145 regmap_update_bits(rt5663->regmap, RT5663_IRQ_1,
3148 RT5663_EN_IRQ_JD1_MASK, RT5663_EN_IRQ_JD1_EN); 3146 RT5663_EN_IRQ_JD1_MASK, RT5663_EN_IRQ_JD1_EN);
3149 regmap_update_bits(rt5663->regmap, RT5663_GPIO_1, 3147 regmap_update_bits(rt5663->regmap, RT5663_GPIO_1,
diff --git a/sound/soc/codecs/rt5663.h b/sound/soc/codecs/rt5663.h
index 252c2761791e..d77fae619f2f 100644
--- a/sound/soc/codecs/rt5663.h
+++ b/sound/soc/codecs/rt5663.h
@@ -18,655 +18,652 @@
18#define RT5663_VENDOR_ID_1 0x00fe 18#define RT5663_VENDOR_ID_1 0x00fe
19#define RT5663_VENDOR_ID_2 0x00ff 19#define RT5663_VENDOR_ID_2 0x00ff
20 20
21#define RT5668_LOUT_CTRL 0x0001 21#define RT5663_LOUT_CTRL 0x0001
22#define RT5668_HP_AMP_2 0x0003 22#define RT5663_HP_AMP_2 0x0003
23#define RT5668_MONO_OUT 0x0004 23#define RT5663_MONO_OUT 0x0004
24#define RT5668_MONO_GAIN 0x0007 24#define RT5663_MONO_GAIN 0x0007
25 25
26#define RT5668_AEC_BST 0x000b 26#define RT5663_AEC_BST 0x000b
27#define RT5668_IN1_IN2 0x000c 27#define RT5663_IN1_IN2 0x000c
28#define RT5668_IN3_IN4 0x000d 28#define RT5663_IN3_IN4 0x000d
29#define RT5668_INL1_INR1 0x000f 29#define RT5663_INL1_INR1 0x000f
30#define RT5668_CBJ_TYPE_2 0x0011 30#define RT5663_CBJ_TYPE_2 0x0011
31#define RT5668_CBJ_TYPE_3 0x0012 31#define RT5663_CBJ_TYPE_3 0x0012
32#define RT5668_CBJ_TYPE_4 0x0013 32#define RT5663_CBJ_TYPE_4 0x0013
33#define RT5668_CBJ_TYPE_5 0x0014 33#define RT5663_CBJ_TYPE_5 0x0014
34#define RT5668_CBJ_TYPE_8 0x0017 34#define RT5663_CBJ_TYPE_8 0x0017
35 35
36/* I/O - ADC/DAC/DMIC */ 36/* I/O - ADC/DAC/DMIC */
37#define RT5668_DAC3_DIG_VOL 0x001a 37#define RT5663_DAC3_DIG_VOL 0x001a
38#define RT5668_DAC3_CTRL 0x001b 38#define RT5663_DAC3_CTRL 0x001b
39#define RT5668_MONO_ADC_DIG_VOL 0x001d 39#define RT5663_MONO_ADC_DIG_VOL 0x001d
40#define RT5668_STO2_ADC_DIG_VOL 0x001e 40#define RT5663_STO2_ADC_DIG_VOL 0x001e
41#define RT5668_MONO_ADC_BST_GAIN 0x0020 41#define RT5663_MONO_ADC_BST_GAIN 0x0020
42#define RT5668_STO2_ADC_BST_GAIN 0x0021 42#define RT5663_STO2_ADC_BST_GAIN 0x0021
43#define RT5668_SIDETONE_CTRL 0x0024 43#define RT5663_SIDETONE_CTRL 0x0024
44/* Mixer - D-D */ 44/* Mixer - D-D */
45#define RT5668_MONO1_ADC_MIXER 0x0027 45#define RT5663_MONO1_ADC_MIXER 0x0027
46#define RT5668_STO2_ADC_MIXER 0x0028 46#define RT5663_STO2_ADC_MIXER 0x0028
47#define RT5668_MONO_DAC_MIXER 0x002b 47#define RT5663_MONO_DAC_MIXER 0x002b
48#define RT5668_DAC2_SRC_CTRL 0x002e 48#define RT5663_DAC2_SRC_CTRL 0x002e
49#define RT5668_IF_3_4_DATA_CTL 0x002f 49#define RT5663_IF_3_4_DATA_CTL 0x002f
50#define RT5668_IF_5_DATA_CTL 0x0030 50#define RT5663_IF_5_DATA_CTL 0x0030
51#define RT5668_PDM_OUT_CTL 0x0031 51#define RT5663_PDM_OUT_CTL 0x0031
52#define RT5668_PDM_I2C_DATA_CTL1 0x0032 52#define RT5663_PDM_I2C_DATA_CTL1 0x0032
53#define RT5668_PDM_I2C_DATA_CTL2 0x0033 53#define RT5663_PDM_I2C_DATA_CTL2 0x0033
54#define RT5668_PDM_I2C_DATA_CTL3 0x0034 54#define RT5663_PDM_I2C_DATA_CTL3 0x0034
55#define RT5668_PDM_I2C_DATA_CTL4 0x0035 55#define RT5663_PDM_I2C_DATA_CTL4 0x0035
56 56
57/*Mixer - Analog*/ 57/*Mixer - Analog*/
58#define RT5668_RECMIX1_NEW 0x003a 58#define RT5663_RECMIX1_NEW 0x003a
59#define RT5668_RECMIX1L_0 0x003b 59#define RT5663_RECMIX1L_0 0x003b
60#define RT5668_RECMIX1L 0x003c 60#define RT5663_RECMIX1L 0x003c
61#define RT5668_RECMIX1R_0 0x003d 61#define RT5663_RECMIX1R_0 0x003d
62#define RT5668_RECMIX1R 0x003e 62#define RT5663_RECMIX1R 0x003e
63#define RT5668_RECMIX2_NEW 0x003f 63#define RT5663_RECMIX2_NEW 0x003f
64#define RT5668_RECMIX2_L_2 0x0041 64#define RT5663_RECMIX2_L_2 0x0041
65#define RT5668_RECMIX2_R 0x0042 65#define RT5663_RECMIX2_R 0x0042
66#define RT5668_RECMIX2_R_2 0x0043 66#define RT5663_RECMIX2_R_2 0x0043
67#define RT5668_CALIB_REC_LR 0x0044 67#define RT5663_CALIB_REC_LR 0x0044
68#define RT5668_ALC_BK_GAIN 0x0049 68#define RT5663_ALC_BK_GAIN 0x0049
69#define RT5668_MONOMIX_GAIN 0x004a 69#define RT5663_MONOMIX_GAIN 0x004a
70#define RT5668_MONOMIX_IN_GAIN 0x004b 70#define RT5663_MONOMIX_IN_GAIN 0x004b
71#define RT5668_OUT_MIXL_GAIN 0x004d 71#define RT5663_OUT_MIXL_GAIN 0x004d
72#define RT5668_OUT_LMIX_IN_GAIN 0x004e 72#define RT5663_OUT_LMIX_IN_GAIN 0x004e
73#define RT5668_OUT_RMIX_IN_GAIN 0x004f 73#define RT5663_OUT_RMIX_IN_GAIN 0x004f
74#define RT5668_OUT_RMIX_IN_GAIN1 0x0050 74#define RT5663_OUT_RMIX_IN_GAIN1 0x0050
75#define RT5668_LOUT_MIXER_CTRL 0x0052 75#define RT5663_LOUT_MIXER_CTRL 0x0052
76/* Power */ 76/* Power */
77#define RT5668_PWR_VOL 0x0067 77#define RT5663_PWR_VOL 0x0067
78 78
79#define RT5668_ADCDAC_RST 0x006d 79#define RT5663_ADCDAC_RST 0x006d
80/* Format - ADC/DAC */ 80/* Format - ADC/DAC */
81#define RT5668_I2S34_SDP 0x0071 81#define RT5663_I2S34_SDP 0x0071
82#define RT5668_I2S5_SDP 0x0072 82#define RT5663_I2S5_SDP 0x0072
83/* Format - TDM Control */
84#define RT5668_TDM_5 0x007c
85#define RT5668_TDM_6 0x007d
86#define RT5668_TDM_7 0x007e
87#define RT5668_TDM_8 0x007f
88 83
89/* Function - Analog */ 84/* Function - Analog */
90#define RT5668_ASRC_3 0x0085 85#define RT5663_ASRC_3 0x0085
91#define RT5668_ASRC_6 0x0088 86#define RT5663_ASRC_6 0x0088
92#define RT5668_ASRC_7 0x0089 87#define RT5663_ASRC_7 0x0089
93#define RT5668_PLL_TRK_13 0x0099 88#define RT5663_PLL_TRK_13 0x0099
94#define RT5668_I2S_M_CLK_CTL 0x00a0 89#define RT5663_I2S_M_CLK_CTL 0x00a0
95#define RT5668_FDIV_I2S34_M_CLK 0x00a1 90#define RT5663_FDIV_I2S34_M_CLK 0x00a1
96#define RT5668_FDIV_I2S34_M_CLK2 0x00a2 91#define RT5663_FDIV_I2S34_M_CLK2 0x00a2
97#define RT5668_FDIV_I2S5_M_CLK 0x00a3 92#define RT5663_FDIV_I2S5_M_CLK 0x00a3
98#define RT5668_FDIV_I2S5_M_CLK2 0x00a4 93#define RT5663_FDIV_I2S5_M_CLK2 0x00a4
99 94
100/* Function - Digital */ 95/* Function - Digital */
101#define RT5668_IRQ_4 0x00b9 96#define RT5663_V2_IRQ_4 0x00b9
102#define RT5668_GPIO_3 0x00c2 97#define RT5663_GPIO_3 0x00c2
103#define RT5668_GPIO_4 0x00c3 98#define RT5663_GPIO_4 0x00c3
104#define RT5668_GPIO_STA 0x00c4 99#define RT5663_GPIO_STA2 0x00c4
105#define RT5668_HP_AMP_DET1 0x00d0 100#define RT5663_HP_AMP_DET1 0x00d0
106#define RT5668_HP_AMP_DET2 0x00d1 101#define RT5663_HP_AMP_DET2 0x00d1
107#define RT5668_HP_AMP_DET3 0x00d2 102#define RT5663_HP_AMP_DET3 0x00d2
108#define RT5668_MID_BD_HP_AMP 0x00d3 103#define RT5663_MID_BD_HP_AMP 0x00d3
109#define RT5668_LOW_BD_HP_AMP 0x00d4 104#define RT5663_LOW_BD_HP_AMP 0x00d4
110#define RT5668_SOF_VOL_ZC2 0x00da 105#define RT5663_SOF_VOL_ZC2 0x00da
111#define RT5668_ADC_STO2_ADJ1 0x00ee 106#define RT5663_ADC_STO2_ADJ1 0x00ee
112#define RT5668_ADC_STO2_ADJ2 0x00ef 107#define RT5663_ADC_STO2_ADJ2 0x00ef
113/* General Control */ 108/* General Control */
114#define RT5668_A_JD_CTRL 0x00f0 109#define RT5663_A_JD_CTRL 0x00f0
115#define RT5668_JD1_TRES_CTRL 0x00f1 110#define RT5663_JD1_TRES_CTRL 0x00f1
116#define RT5668_JD2_TRES_CTRL 0x00f2 111#define RT5663_JD2_TRES_CTRL 0x00f2
117#define RT5668_JD_CTRL2 0x00f7 112#define RT5663_V2_JD_CTRL2 0x00f7
118#define RT5668_DUM_REG_2 0x00fb 113#define RT5663_DUM_REG_2 0x00fb
119#define RT5668_DUM_REG_3 0x00fc 114#define RT5663_DUM_REG_3 0x00fc
120 115
121 116
122#define RT5668_DACADC_DIG_VOL2 0x0101 117#define RT5663_DACADC_DIG_VOL2 0x0101
123#define RT5668_DIG_IN_PIN2 0x0133 118#define RT5663_DIG_IN_PIN2 0x0133
124#define RT5668_PAD_DRV_CTL1 0x0136 119#define RT5663_PAD_DRV_CTL1 0x0136
125#define RT5668_SOF_RAM_DEPOP 0x0138 120#define RT5663_SOF_RAM_DEPOP 0x0138
126#define RT5668_VOL_TEST 0x013f 121#define RT5663_VOL_TEST 0x013f
127#define RT5668_TEST_MODE_3 0x0147 122#define RT5663_MONO_DYNA_1 0x0170
128#define RT5668_TEST_MODE_4 0x0148 123#define RT5663_MONO_DYNA_2 0x0171
129#define RT5668_MONO_DYNA_1 0x0170 124#define RT5663_MONO_DYNA_3 0x0172
130#define RT5668_MONO_DYNA_2 0x0171 125#define RT5663_MONO_DYNA_4 0x0173
131#define RT5668_MONO_DYNA_3 0x0172 126#define RT5663_MONO_DYNA_5 0x0174
132#define RT5668_MONO_DYNA_4 0x0173 127#define RT5663_MONO_DYNA_6 0x0175
133#define RT5668_MONO_DYNA_5 0x0174 128#define RT5663_STO1_SIL_DET 0x0190
134#define RT5668_MONO_DYNA_6 0x0175 129#define RT5663_MONOL_SIL_DET 0x0191
135#define RT5668_STO1_SIL_DET 0x0190 130#define RT5663_MONOR_SIL_DET 0x0192
136#define RT5668_MONOL_SIL_DET 0x0191 131#define RT5663_STO2_DAC_SIL 0x0193
137#define RT5668_MONOR_SIL_DET 0x0192 132#define RT5663_PWR_SAV_CTL1 0x0194
138#define RT5668_STO2_DAC_SIL 0x0193 133#define RT5663_PWR_SAV_CTL2 0x0195
139#define RT5668_PWR_SAV_CTL1 0x0194 134#define RT5663_PWR_SAV_CTL3 0x0196
140#define RT5668_PWR_SAV_CTL2 0x0195 135#define RT5663_PWR_SAV_CTL4 0x0197
141#define RT5668_PWR_SAV_CTL3 0x0196 136#define RT5663_PWR_SAV_CTL5 0x0198
142#define RT5668_PWR_SAV_CTL4 0x0197 137#define RT5663_PWR_SAV_CTL6 0x0199
143#define RT5668_PWR_SAV_CTL5 0x0198 138#define RT5663_MONO_AMP_CAL1 0x01a0
144#define RT5668_PWR_SAV_CTL6 0x0199 139#define RT5663_MONO_AMP_CAL2 0x01a1
145#define RT5668_MONO_AMP_CAL1 0x01a0 140#define RT5663_MONO_AMP_CAL3 0x01a2
146#define RT5668_MONO_AMP_CAL2 0x01a1 141#define RT5663_MONO_AMP_CAL4 0x01a3
147#define RT5668_MONO_AMP_CAL3 0x01a2 142#define RT5663_MONO_AMP_CAL5 0x01a4
148#define RT5668_MONO_AMP_CAL4 0x01a3 143#define RT5663_MONO_AMP_CAL6 0x01a5
149#define RT5668_MONO_AMP_CAL5 0x01a4 144#define RT5663_MONO_AMP_CAL7 0x01a6
150#define RT5668_MONO_AMP_CAL6 0x01a5 145#define RT5663_MONO_AMP_CAL_ST1 0x01a7
151#define RT5668_MONO_AMP_CAL7 0x01a6 146#define RT5663_MONO_AMP_CAL_ST2 0x01a8
152#define RT5668_MONO_AMP_CAL_ST1 0x01a7 147#define RT5663_MONO_AMP_CAL_ST3 0x01a9
153#define RT5668_MONO_AMP_CAL_ST2 0x01a8 148#define RT5663_MONO_AMP_CAL_ST4 0x01aa
154#define RT5668_MONO_AMP_CAL_ST3 0x01a9 149#define RT5663_MONO_AMP_CAL_ST5 0x01ab
155#define RT5668_MONO_AMP_CAL_ST4 0x01aa 150#define RT5663_V2_HP_IMP_SEN_13 0x01b9
156#define RT5668_MONO_AMP_CAL_ST5 0x01ab 151#define RT5663_V2_HP_IMP_SEN_14 0x01ba
157#define RT5668_HP_IMP_SEN_13 0x01b9 152#define RT5663_V2_HP_IMP_SEN_6 0x01bb
158#define RT5668_HP_IMP_SEN_14 0x01ba 153#define RT5663_V2_HP_IMP_SEN_7 0x01bc
159#define RT5668_HP_IMP_SEN_6 0x01bb 154#define RT5663_V2_HP_IMP_SEN_8 0x01bd
160#define RT5668_HP_IMP_SEN_7 0x01bc 155#define RT5663_V2_HP_IMP_SEN_9 0x01be
161#define RT5668_HP_IMP_SEN_8 0x01bd 156#define RT5663_V2_HP_IMP_SEN_10 0x01bf
162#define RT5668_HP_IMP_SEN_9 0x01be 157#define RT5663_HP_LOGIC_3 0x01dc
163#define RT5668_HP_IMP_SEN_10 0x01bf 158#define RT5663_HP_CALIB_ST10 0x01f3
164#define RT5668_HP_LOGIC_3 0x01dc 159#define RT5663_HP_CALIB_ST11 0x01f4
165#define RT5668_HP_CALIB_ST10 0x01f3 160#define RT5663_PRO_REG_TBL_4 0x0203
166#define RT5668_HP_CALIB_ST11 0x01f4 161#define RT5663_PRO_REG_TBL_5 0x0204
167#define RT5668_PRO_REG_TBL_4 0x0203 162#define RT5663_PRO_REG_TBL_6 0x0205
168#define RT5668_PRO_REG_TBL_5 0x0204 163#define RT5663_PRO_REG_TBL_7 0x0206
169#define RT5668_PRO_REG_TBL_6 0x0205 164#define RT5663_PRO_REG_TBL_8 0x0207
170#define RT5668_PRO_REG_TBL_7 0x0206 165#define RT5663_PRO_REG_TBL_9 0x0208
171#define RT5668_PRO_REG_TBL_8 0x0207 166#define RT5663_SAR_ADC_INL_1 0x0210
172#define RT5668_PRO_REG_TBL_9 0x0208 167#define RT5663_SAR_ADC_INL_2 0x0211
173#define RT5668_SAR_ADC_INL_1 0x0210 168#define RT5663_SAR_ADC_INL_3 0x0212
174#define RT5668_SAR_ADC_INL_2 0x0211 169#define RT5663_SAR_ADC_INL_4 0x0213
175#define RT5668_SAR_ADC_INL_3 0x0212 170#define RT5663_SAR_ADC_INL_5 0x0214
176#define RT5668_SAR_ADC_INL_4 0x0213 171#define RT5663_SAR_ADC_INL_6 0x0215
177#define RT5668_SAR_ADC_INL_5 0x0214 172#define RT5663_SAR_ADC_INL_7 0x0216
178#define RT5668_SAR_ADC_INL_6 0x0215 173#define RT5663_SAR_ADC_INL_8 0x0217
179#define RT5668_SAR_ADC_INL_7 0x0216 174#define RT5663_SAR_ADC_INL_9 0x0218
180#define RT5668_SAR_ADC_INL_8 0x0217 175#define RT5663_SAR_ADC_INL_10 0x0219
181#define RT5668_SAR_ADC_INL_9 0x0218 176#define RT5663_SAR_ADC_INL_11 0x021a
182#define RT5668_SAR_ADC_INL_10 0x0219 177#define RT5663_SAR_ADC_INL_12 0x021b
183#define RT5668_SAR_ADC_INL_11 0x021a 178#define RT5663_DRC_CTRL_1 0x02ff
184#define RT5668_SAR_ADC_INL_12 0x021b 179#define RT5663_DRC1_CTRL_2 0x0301
185#define RT5668_DRC_CTRL_1 0x02ff 180#define RT5663_DRC1_CTRL_3 0x0302
186#define RT5668_DRC1_CTRL_2 0x0301 181#define RT5663_DRC1_CTRL_4 0x0303
187#define RT5668_DRC1_CTRL_3 0x0302 182#define RT5663_DRC1_CTRL_5 0x0304
188#define RT5668_DRC1_CTRL_4 0x0303 183#define RT5663_DRC1_CTRL_6 0x0305
189#define RT5668_DRC1_CTRL_5 0x0304 184#define RT5663_DRC1_HD_CTRL_1 0x0306
190#define RT5668_DRC1_CTRL_6 0x0305 185#define RT5663_DRC1_HD_CTRL_2 0x0307
191#define RT5668_DRC1_HD_CTRL_1 0x0306 186#define RT5663_DRC1_PRI_REG_1 0x0310
192#define RT5668_DRC1_HD_CTRL_2 0x0307 187#define RT5663_DRC1_PRI_REG_2 0x0311
193#define RT5668_DRC1_PRI_REG_1 0x0310 188#define RT5663_DRC1_PRI_REG_3 0x0312
194#define RT5668_DRC1_PRI_REG_2 0x0311 189#define RT5663_DRC1_PRI_REG_4 0x0313
195#define RT5668_DRC1_PRI_REG_3 0x0312 190#define RT5663_DRC1_PRI_REG_5 0x0314
196#define RT5668_DRC1_PRI_REG_4 0x0313 191#define RT5663_DRC1_PRI_REG_6 0x0315
197#define RT5668_DRC1_PRI_REG_5 0x0314 192#define RT5663_DRC1_PRI_REG_7 0x0316
198#define RT5668_DRC1_PRI_REG_6 0x0315 193#define RT5663_DRC1_PRI_REG_8 0x0317
199#define RT5668_DRC1_PRI_REG_7 0x0316 194#define RT5663_ALC_PGA_CTL_1 0x0330
200#define RT5668_DRC1_PRI_REG_8 0x0317 195#define RT5663_ALC_PGA_CTL_2 0x0331
201#define RT5668_ALC_PGA_CTL_1 0x0330 196#define RT5663_ALC_PGA_CTL_3 0x0332
202#define RT5668_ALC_PGA_CTL_2 0x0331 197#define RT5663_ALC_PGA_CTL_4 0x0333
203#define RT5668_ALC_PGA_CTL_3 0x0332 198#define RT5663_ALC_PGA_CTL_5 0x0334
204#define RT5668_ALC_PGA_CTL_4 0x0333 199#define RT5663_ALC_PGA_CTL_6 0x0335
205#define RT5668_ALC_PGA_CTL_5 0x0334 200#define RT5663_ALC_PGA_CTL_7 0x0336
206#define RT5668_ALC_PGA_CTL_6 0x0335 201#define RT5663_ALC_PGA_CTL_8 0x0337
207#define RT5668_ALC_PGA_CTL_7 0x0336 202#define RT5663_ALC_PGA_REG_1 0x0338
208#define RT5668_ALC_PGA_CTL_8 0x0337 203#define RT5663_ALC_PGA_REG_2 0x0339
209#define RT5668_ALC_PGA_REG_1 0x0338 204#define RT5663_ALC_PGA_REG_3 0x033a
210#define RT5668_ALC_PGA_REG_2 0x0339 205#define RT5663_ADC_EQ_RECOV_1 0x03c0
211#define RT5668_ALC_PGA_REG_3 0x033a 206#define RT5663_ADC_EQ_RECOV_2 0x03c1
212#define RT5668_ADC_EQ_RECOV_1 0x03c0 207#define RT5663_ADC_EQ_RECOV_3 0x03c2
213#define RT5668_ADC_EQ_RECOV_2 0x03c1 208#define RT5663_ADC_EQ_RECOV_4 0x03c3
214#define RT5668_ADC_EQ_RECOV_3 0x03c2 209#define RT5663_ADC_EQ_RECOV_5 0x03c4
215#define RT5668_ADC_EQ_RECOV_4 0x03c3 210#define RT5663_ADC_EQ_RECOV_6 0x03c5
216#define RT5668_ADC_EQ_RECOV_5 0x03c4 211#define RT5663_ADC_EQ_RECOV_7 0x03c6
217#define RT5668_ADC_EQ_RECOV_6 0x03c5 212#define RT5663_ADC_EQ_RECOV_8 0x03c7
218#define RT5668_ADC_EQ_RECOV_7 0x03c6 213#define RT5663_ADC_EQ_RECOV_9 0x03c8
219#define RT5668_ADC_EQ_RECOV_8 0x03c7 214#define RT5663_ADC_EQ_RECOV_10 0x03c9
220#define RT5668_ADC_EQ_RECOV_9 0x03c8 215#define RT5663_ADC_EQ_RECOV_11 0x03ca
221#define RT5668_ADC_EQ_RECOV_10 0x03c9 216#define RT5663_ADC_EQ_RECOV_12 0x03cb
222#define RT5668_ADC_EQ_RECOV_11 0x03ca 217#define RT5663_ADC_EQ_RECOV_13 0x03cc
223#define RT5668_ADC_EQ_RECOV_12 0x03cb 218#define RT5663_VID_HIDDEN 0x03fe
224#define RT5668_ADC_EQ_RECOV_13 0x03cc 219#define RT5663_VID_CUSTOMER 0x03ff
225#define RT5668_VID_HIDDEN 0x03fe 220#define RT5663_SCAN_MODE 0x07f0
226#define RT5668_VID_CUSTOMER 0x03ff 221#define RT5663_I2C_BYPA 0x07fa
227#define RT5668_SCAN_MODE 0x07f0
228#define RT5668_I2C_BYPA 0x07fa
229 222
230/* Headphone Amp Control 2 (0x0003) */ 223/* Headphone Amp Control 2 (0x0003) */
231#define RT5668_EN_DAC_HPO_MASK (0x1 << 14) 224#define RT5663_EN_DAC_HPO_MASK (0x1 << 14)
232#define RT5668_EN_DAC_HPO_SHIFT 14 225#define RT5663_EN_DAC_HPO_SHIFT 14
233#define RT5668_EN_DAC_HPO_DIS (0x0 << 14) 226#define RT5663_EN_DAC_HPO_DIS (0x0 << 14)
234#define RT5668_EN_DAC_HPO_EN (0x1 << 14) 227#define RT5663_EN_DAC_HPO_EN (0x1 << 14)
235 228
236/*Headphone Amp L/R Analog Gain and Digital NG2 Gain Control (0x0005 0x0006)*/ 229/*Headphone Amp L/R Analog Gain and Digital NG2 Gain Control (0x0005 0x0006)*/
237#define RT5668_GAIN_HP (0x1f << 8) 230#define RT5663_GAIN_HP (0x1f << 8)
238#define RT5668_GAIN_HP_SHIFT 8 231#define RT5663_GAIN_HP_SHIFT 8
239 232
240/* AEC BST Control (0x000b) */ 233/* AEC BST Control (0x000b) */
241#define RT5668_GAIN_CBJ_MASK (0xf << 8) 234#define RT5663_GAIN_CBJ_MASK (0xf << 8)
242#define RT5668_GAIN_CBJ_SHIFT 8 235#define RT5663_GAIN_CBJ_SHIFT 8
243 236
244/* IN1 Control / MIC GND REF (0x000c) */ 237/* IN1 Control / MIC GND REF (0x000c) */
245#define RT5668_IN1_DF_MASK (0x1 << 15) 238#define RT5663_IN1_DF_MASK (0x1 << 15)
246#define RT5668_IN1_DF_SHIFT 15 239#define RT5663_IN1_DF_SHIFT 15
247 240
248/* Combo Jack and Type Detection Control 1 (0x0010) */ 241/* Combo Jack and Type Detection Control 1 (0x0010) */
249#define RT5668_CBJ_DET_MASK (0x1 << 15) 242#define RT5663_CBJ_DET_MASK (0x1 << 15)
250#define RT5668_CBJ_DET_SHIFT 15 243#define RT5663_CBJ_DET_SHIFT 15
251#define RT5668_CBJ_DET_DIS (0x0 << 15) 244#define RT5663_CBJ_DET_DIS (0x0 << 15)
252#define RT5668_CBJ_DET_EN (0x1 << 15) 245#define RT5663_CBJ_DET_EN (0x1 << 15)
253#define RT5668_DET_TYPE_MASK (0x1 << 12) 246#define RT5663_DET_TYPE_MASK (0x1 << 12)
254#define RT5668_DET_TYPE_SHIFT 12 247#define RT5663_DET_TYPE_SHIFT 12
255#define RT5668_DET_TYPE_WLCSP (0x0 << 12) 248#define RT5663_DET_TYPE_WLCSP (0x0 << 12)
256#define RT5668_DET_TYPE_QFN (0x1 << 12) 249#define RT5663_DET_TYPE_QFN (0x1 << 12)
257#define RT5668_VREF_BIAS_MASK (0x1 << 6) 250#define RT5663_VREF_BIAS_MASK (0x1 << 6)
258#define RT5668_VREF_BIAS_SHIFT 6 251#define RT5663_VREF_BIAS_SHIFT 6
259#define RT5668_VREF_BIAS_FSM (0x0 << 6) 252#define RT5663_VREF_BIAS_FSM (0x0 << 6)
260#define RT5668_VREF_BIAS_REG (0x1 << 6) 253#define RT5663_VREF_BIAS_REG (0x1 << 6)
261 254
262/* REC Left Mixer Control 2 (0x003c) */ 255/* REC Left Mixer Control 2 (0x003c) */
263#define RT5668_RECMIX1L_BST1_CBJ (0x1 << 7) 256#define RT5663_RECMIX1L_BST1_CBJ (0x1 << 7)
264#define RT5668_RECMIX1L_BST1_CBJ_SHIFT 7 257#define RT5663_RECMIX1L_BST1_CBJ_SHIFT 7
265#define RT5668_RECMIX1L_BST2 (0x1 << 4) 258#define RT5663_RECMIX1L_BST2 (0x1 << 4)
266#define RT5668_RECMIX1L_BST2_SHIFT 4 259#define RT5663_RECMIX1L_BST2_SHIFT 4
267 260
268/* REC Right Mixer Control 2 (0x003e) */ 261/* REC Right Mixer Control 2 (0x003e) */
269#define RT5668_RECMIX1R_BST2 (0x1 << 4) 262#define RT5663_RECMIX1R_BST2 (0x1 << 4)
270#define RT5668_RECMIX1R_BST2_SHIFT 4 263#define RT5663_RECMIX1R_BST2_SHIFT 4
271 264
272/* DAC1 Digital Volume (0x0019) */ 265/* DAC1 Digital Volume (0x0019) */
273#define RT5668_DAC_L1_VOL_MASK (0xff << 8) 266#define RT5663_DAC_L1_VOL_MASK (0xff << 8)
274#define RT5668_DAC_L1_VOL_SHIFT 8 267#define RT5663_DAC_L1_VOL_SHIFT 8
275#define RT5668_DAC_R1_VOL_MASK (0xff) 268#define RT5663_DAC_R1_VOL_MASK (0xff)
276#define RT5668_DAC_R1_VOL_SHIFT 0 269#define RT5663_DAC_R1_VOL_SHIFT 0
277 270
278/* ADC Digital Volume Control (0x001c) */ 271/* ADC Digital Volume Control (0x001c) */
279#define RT5668_ADC_L_MUTE_MASK (0x1 << 15) 272#define RT5663_ADC_L_MUTE_MASK (0x1 << 15)
280#define RT5668_ADC_L_MUTE_SHIFT 15 273#define RT5663_ADC_L_MUTE_SHIFT 15
281#define RT5668_ADC_L_VOL_MASK (0x7f << 8) 274#define RT5663_ADC_L_VOL_MASK (0x7f << 8)
282#define RT5668_ADC_L_VOL_SHIFT 8 275#define RT5663_ADC_L_VOL_SHIFT 8
283#define RT5668_ADC_R_MUTE_MASK (0x1 << 7) 276#define RT5663_ADC_R_MUTE_MASK (0x1 << 7)
284#define RT5668_ADC_R_MUTE_SHIFT 7 277#define RT5663_ADC_R_MUTE_SHIFT 7
285#define RT5668_ADC_R_VOL_MASK (0x7f) 278#define RT5663_ADC_R_VOL_MASK (0x7f)
286#define RT5668_ADC_R_VOL_SHIFT 0 279#define RT5663_ADC_R_VOL_SHIFT 0
287 280
288/* Stereo ADC Mixer Control (0x0026) */ 281/* Stereo ADC Mixer Control (0x0026) */
289#define RT5668_M_STO1_ADC_L1 (0x1 << 15) 282#define RT5663_M_STO1_ADC_L1 (0x1 << 15)
290#define RT5668_M_STO1_ADC_L1_SHIFT 15 283#define RT5663_M_STO1_ADC_L1_SHIFT 15
291#define RT5668_M_STO1_ADC_L2 (0x1 << 14) 284#define RT5663_M_STO1_ADC_L2 (0x1 << 14)
292#define RT5668_M_STO1_ADC_L2_SHIFT 14 285#define RT5663_M_STO1_ADC_L2_SHIFT 14
293#define RT5668_STO1_ADC_L1_SRC (0x1 << 13) 286#define RT5663_STO1_ADC_L1_SRC (0x1 << 13)
294#define RT5668_STO1_ADC_L1_SRC_SHIFT 13 287#define RT5663_STO1_ADC_L1_SRC_SHIFT 13
295#define RT5668_STO1_ADC_L2_SRC (0x1 << 12) 288#define RT5663_STO1_ADC_L2_SRC (0x1 << 12)
296#define RT5668_STO1_ADC_L2_SRC_SHIFT 12 289#define RT5663_STO1_ADC_L2_SRC_SHIFT 12
297#define RT5668_STO1_ADC_L_SRC (0x3 << 10) 290#define RT5663_STO1_ADC_L_SRC (0x3 << 10)
298#define RT5668_STO1_ADC_L_SRC_SHIFT 10 291#define RT5663_STO1_ADC_L_SRC_SHIFT 10
299#define RT5668_M_STO1_ADC_R1 (0x1 << 7) 292#define RT5663_M_STO1_ADC_R1 (0x1 << 7)
300#define RT5668_M_STO1_ADC_R1_SHIFT 7 293#define RT5663_M_STO1_ADC_R1_SHIFT 7
301#define RT5668_M_STO1_ADC_R2 (0x1 << 6) 294#define RT5663_M_STO1_ADC_R2 (0x1 << 6)
302#define RT5668_M_STO1_ADC_R2_SHIFT 6 295#define RT5663_M_STO1_ADC_R2_SHIFT 6
303#define RT5668_STO1_ADC_R1_SRC (0x1 << 5) 296#define RT5663_STO1_ADC_R1_SRC (0x1 << 5)
304#define RT5668_STO1_ADC_R1_SRC_SHIFT 5 297#define RT5663_STO1_ADC_R1_SRC_SHIFT 5
305#define RT5668_STO1_ADC_R2_SRC (0x1 << 4) 298#define RT5663_STO1_ADC_R2_SRC (0x1 << 4)
306#define RT5668_STO1_ADC_R2_SRC_SHIFT 4 299#define RT5663_STO1_ADC_R2_SRC_SHIFT 4
307#define RT5668_STO1_ADC_R_SRC (0x3 << 2) 300#define RT5663_STO1_ADC_R_SRC (0x3 << 2)
308#define RT5668_STO1_ADC_R_SRC_SHIFT 2 301#define RT5663_STO1_ADC_R_SRC_SHIFT 2
309 302
310/* ADC Mixer to DAC Mixer Control (0x0029) */ 303/* ADC Mixer to DAC Mixer Control (0x0029) */
311#define RT5668_M_ADCMIX_L (0x1 << 15) 304#define RT5663_M_ADCMIX_L (0x1 << 15)
312#define RT5668_M_ADCMIX_L_SHIFT 15 305#define RT5663_M_ADCMIX_L_SHIFT 15
313#define RT5668_M_DAC1_L (0x1 << 14) 306#define RT5663_M_DAC1_L (0x1 << 14)
314#define RT5668_M_DAC1_L_SHIFT 14 307#define RT5663_M_DAC1_L_SHIFT 14
315#define RT5668_M_ADCMIX_R (0x1 << 7) 308#define RT5663_M_ADCMIX_R (0x1 << 7)
316#define RT5668_M_ADCMIX_R_SHIFT 7 309#define RT5663_M_ADCMIX_R_SHIFT 7
317#define RT5668_M_DAC1_R (0x1 << 6) 310#define RT5663_M_DAC1_R (0x1 << 6)
318#define RT5668_M_DAC1_R_SHIFT 6 311#define RT5663_M_DAC1_R_SHIFT 6
319 312
320/* Stereo DAC Mixer Control (0x002a) */ 313/* Stereo DAC Mixer Control (0x002a) */
321#define RT5668_M_DAC_L1_STO_L (0x1 << 15) 314#define RT5663_M_DAC_L1_STO_L (0x1 << 15)
322#define RT5668_M_DAC_L1_STO_L_SHIFT 15 315#define RT5663_M_DAC_L1_STO_L_SHIFT 15
323#define RT5668_M_DAC_R1_STO_L (0x1 << 13) 316#define RT5663_M_DAC_R1_STO_L (0x1 << 13)
324#define RT5668_M_DAC_R1_STO_L_SHIFT 13 317#define RT5663_M_DAC_R1_STO_L_SHIFT 13
325#define RT5668_M_DAC_L1_STO_R (0x1 << 7) 318#define RT5663_M_DAC_L1_STO_R (0x1 << 7)
326#define RT5668_M_DAC_L1_STO_R_SHIFT 7 319#define RT5663_M_DAC_L1_STO_R_SHIFT 7
327#define RT5668_M_DAC_R1_STO_R (0x1 << 5) 320#define RT5663_M_DAC_R1_STO_R (0x1 << 5)
328#define RT5668_M_DAC_R1_STO_R_SHIFT 5 321#define RT5663_M_DAC_R1_STO_R_SHIFT 5
329 322
330/* Power Management for Digital 1 (0x0061) */ 323/* Power Management for Digital 1 (0x0061) */
331#define RT5668_PWR_I2S1 (0x1 << 15) 324#define RT5663_PWR_I2S1 (0x1 << 15)
332#define RT5668_PWR_I2S1_SHIFT 15 325#define RT5663_PWR_I2S1_SHIFT 15
333#define RT5668_PWR_DAC_L1 (0x1 << 11) 326#define RT5663_PWR_DAC_L1 (0x1 << 11)
334#define RT5668_PWR_DAC_L1_SHIFT 11 327#define RT5663_PWR_DAC_L1_SHIFT 11
335#define RT5668_PWR_DAC_R1 (0x1 << 10) 328#define RT5663_PWR_DAC_R1 (0x1 << 10)
336#define RT5668_PWR_DAC_R1_SHIFT 10 329#define RT5663_PWR_DAC_R1_SHIFT 10
337#define RT5668_PWR_LDO_DACREF_MASK (0x1 << 8) 330#define RT5663_PWR_LDO_DACREF_MASK (0x1 << 8)
338#define RT5668_PWR_LDO_DACREF_SHIFT 8 331#define RT5663_PWR_LDO_DACREF_SHIFT 8
339#define RT5668_PWR_LDO_DACREF_ON (0x1 << 8) 332#define RT5663_PWR_LDO_DACREF_ON (0x1 << 8)
340#define RT5668_PWR_LDO_DACREF_DOWN (0x0 << 8) 333#define RT5663_PWR_LDO_DACREF_DOWN (0x0 << 8)
341#define RT5668_PWR_LDO_SHIFT 8 334#define RT5663_PWR_LDO_SHIFT 8
342#define RT5668_PWR_ADC_L1 (0x1 << 4) 335#define RT5663_PWR_ADC_L1 (0x1 << 4)
343#define RT5668_PWR_ADC_L1_SHIFT 4 336#define RT5663_PWR_ADC_L1_SHIFT 4
344#define RT5668_PWR_ADC_R1 (0x1 << 3) 337#define RT5663_PWR_ADC_R1 (0x1 << 3)
345#define RT5668_PWR_ADC_R1_SHIFT 3 338#define RT5663_PWR_ADC_R1_SHIFT 3
346 339
347/* Power Management for Digital 2 (0x0062) */ 340/* Power Management for Digital 2 (0x0062) */
348#define RT5668_PWR_ADC_S1F (0x1 << 15) 341#define RT5663_PWR_ADC_S1F (0x1 << 15)
349#define RT5668_PWR_ADC_S1F_SHIFT 15 342#define RT5663_PWR_ADC_S1F_SHIFT 15
350#define RT5668_PWR_DAC_S1F (0x1 << 10) 343#define RT5663_PWR_DAC_S1F (0x1 << 10)
351#define RT5668_PWR_DAC_S1F_SHIFT 10 344#define RT5663_PWR_DAC_S1F_SHIFT 10
352 345
353/* Power Management for Analog 1 (0x0063) */ 346/* Power Management for Analog 1 (0x0063) */
354#define RT5668_PWR_VREF1 (0x1 << 15) 347#define RT5663_PWR_VREF1 (0x1 << 15)
355#define RT5668_PWR_VREF1_MASK (0x1 << 15) 348#define RT5663_PWR_VREF1_MASK (0x1 << 15)
356#define RT5668_PWR_VREF1_SHIFT 15 349#define RT5663_PWR_VREF1_SHIFT 15
357#define RT5668_PWR_FV1 (0x1 << 14) 350#define RT5663_PWR_FV1 (0x1 << 14)
358#define RT5668_PWR_FV1_MASK (0x1 << 14) 351#define RT5663_PWR_FV1_MASK (0x1 << 14)
359#define RT5668_PWR_FV1_SHIFT 14 352#define RT5663_PWR_FV1_SHIFT 14
360#define RT5668_PWR_VREF2 (0x1 << 13) 353#define RT5663_PWR_VREF2 (0x1 << 13)
361#define RT5668_PWR_VREF2_MASK (0x1 << 13) 354#define RT5663_PWR_VREF2_MASK (0x1 << 13)
362#define RT5668_PWR_VREF2_SHIFT 13 355#define RT5663_PWR_VREF2_SHIFT 13
363#define RT5668_PWR_FV2 (0x1 << 12) 356#define RT5663_PWR_FV2 (0x1 << 12)
364#define RT5668_PWR_FV2_MASK (0x1 << 12) 357#define RT5663_PWR_FV2_MASK (0x1 << 12)
365#define RT5668_PWR_FV2_SHIFT 12 358#define RT5663_PWR_FV2_SHIFT 12
366#define RT5668_PWR_MB (0x1 << 9) 359#define RT5663_PWR_MB (0x1 << 9)
367#define RT5668_PWR_MB_MASK (0x1 << 9) 360#define RT5663_PWR_MB_MASK (0x1 << 9)
368#define RT5668_PWR_MB_SHIFT 9 361#define RT5663_PWR_MB_SHIFT 9
369#define RT5668_AMP_HP_MASK (0x3 << 2) 362#define RT5663_AMP_HP_MASK (0x3 << 2)
370#define RT5668_AMP_HP_SHIFT 2 363#define RT5663_AMP_HP_SHIFT 2
371#define RT5668_AMP_HP_1X (0x0 << 2) 364#define RT5663_AMP_HP_1X (0x0 << 2)
372#define RT5668_AMP_HP_3X (0x1 << 2) 365#define RT5663_AMP_HP_3X (0x1 << 2)
373#define RT5668_AMP_HP_5X (0x3 << 2) 366#define RT5663_AMP_HP_5X (0x3 << 2)
374#define RT5668_LDO1_DVO_MASK (0x3) 367#define RT5663_LDO1_DVO_MASK (0x3)
375#define RT5668_LDO1_DVO_SHIFT 0 368#define RT5663_LDO1_DVO_SHIFT 0
376#define RT5668_LDO1_DVO_0_9V (0x0) 369#define RT5663_LDO1_DVO_0_9V (0x0)
377#define RT5668_LDO1_DVO_1_0V (0x1) 370#define RT5663_LDO1_DVO_1_0V (0x1)
378#define RT5668_LDO1_DVO_1_2V (0x2) 371#define RT5663_LDO1_DVO_1_2V (0x2)
379#define RT5668_LDO1_DVO_1_4V (0x3) 372#define RT5663_LDO1_DVO_1_4V (0x3)
380 373
381/* Power Management for Analog 2 (0x0064) */ 374/* Power Management for Analog 2 (0x0064) */
382#define RT5668_PWR_BST1 (0x1 << 15) 375#define RT5663_PWR_BST1 (0x1 << 15)
383#define RT5668_PWR_BST1_MASK (0x1 << 15) 376#define RT5663_PWR_BST1_MASK (0x1 << 15)
384#define RT5668_PWR_BST1_SHIFT 15 377#define RT5663_PWR_BST1_SHIFT 15
385#define RT5668_PWR_BST1_OFF (0x0 << 15) 378#define RT5663_PWR_BST1_OFF (0x0 << 15)
386#define RT5668_PWR_BST1_ON (0x1 << 15) 379#define RT5663_PWR_BST1_ON (0x1 << 15)
387#define RT5668_PWR_BST2 (0x1 << 14) 380#define RT5663_PWR_BST2 (0x1 << 14)
388#define RT5668_PWR_BST2_MASK (0x1 << 14) 381#define RT5663_PWR_BST2_MASK (0x1 << 14)
389#define RT5668_PWR_BST2_SHIFT 14 382#define RT5663_PWR_BST2_SHIFT 14
390#define RT5668_PWR_MB1 (0x1 << 11) 383#define RT5663_PWR_MB1 (0x1 << 11)
391#define RT5668_PWR_MB1_SHIFT 11 384#define RT5663_PWR_MB1_SHIFT 11
392#define RT5668_PWR_MB2 (0x1 << 10) 385#define RT5663_PWR_MB2 (0x1 << 10)
393#define RT5668_PWR_MB2_SHIFT 10 386#define RT5663_PWR_MB2_SHIFT 10
394#define RT5668_PWR_BST2_OP (0x1 << 6) 387#define RT5663_PWR_BST2_OP (0x1 << 6)
395#define RT5668_PWR_BST2_OP_MASK (0x1 << 6) 388#define RT5663_PWR_BST2_OP_MASK (0x1 << 6)
396#define RT5668_PWR_BST2_OP_SHIFT 6 389#define RT5663_PWR_BST2_OP_SHIFT 6
397#define RT5668_PWR_JD1 (0x1 << 3) 390#define RT5663_PWR_JD1 (0x1 << 3)
398#define RT5668_PWR_JD1_MASK (0x1 << 3) 391#define RT5663_PWR_JD1_MASK (0x1 << 3)
399#define RT5668_PWR_JD1_SHIFT 3 392#define RT5663_PWR_JD1_SHIFT 3
400#define RT5668_PWR_JD2 (0x1 << 2) 393#define RT5663_PWR_JD2 (0x1 << 2)
401#define RT5668_PWR_JD2_MASK (0x1 << 2) 394#define RT5663_PWR_JD2_MASK (0x1 << 2)
402#define RT5668_PWR_JD2_SHIFT 2 395#define RT5663_PWR_JD2_SHIFT 2
403#define RT5668_PWR_RECMIX1 (0x1 << 1) 396#define RT5663_PWR_RECMIX1 (0x1 << 1)
404#define RT5668_PWR_RECMIX1_SHIFT 1 397#define RT5663_PWR_RECMIX1_SHIFT 1
405#define RT5668_PWR_RECMIX2 (0x1) 398#define RT5663_PWR_RECMIX2 (0x1)
406#define RT5668_PWR_RECMIX2_SHIFT 0 399#define RT5663_PWR_RECMIX2_SHIFT 0
407 400
408/* Power Management for Analog 3 (0x0065) */ 401/* Power Management for Analog 3 (0x0065) */
409#define RT5668_PWR_CBJ_MASK (0x1 << 9) 402#define RT5663_PWR_CBJ_MASK (0x1 << 9)
410#define RT5668_PWR_CBJ_SHIFT 9 403#define RT5663_PWR_CBJ_SHIFT 9
411#define RT5668_PWR_CBJ_OFF (0x0 << 9) 404#define RT5663_PWR_CBJ_OFF (0x0 << 9)
412#define RT5668_PWR_CBJ_ON (0x1 << 9) 405#define RT5663_PWR_CBJ_ON (0x1 << 9)
413#define RT5668_PWR_PLL (0x1 << 6) 406#define RT5663_PWR_PLL (0x1 << 6)
414#define RT5668_PWR_PLL_SHIFT 6 407#define RT5663_PWR_PLL_SHIFT 6
415#define RT5668_PWR_LDO2 (0x1 << 2) 408#define RT5663_PWR_LDO2 (0x1 << 2)
416#define RT5668_PWR_LDO2_SHIFT 2 409#define RT5663_PWR_LDO2_SHIFT 2
417 410
418/* Power Management for Volume (0x0067) */ 411/* Power Management for Volume (0x0067) */
419#define RT5668_PWR_MIC_DET (0x1 << 5) 412#define RT5663_V2_PWR_MIC_DET (0x1 << 5)
420#define RT5668_PWR_MIC_DET_SHIFT 5 413#define RT5663_V2_PWR_MIC_DET_SHIFT 5
421 414
422/* MCLK and System Clock Detection Control (0x006b) */ 415/* MCLK and System Clock Detection Control (0x006b) */
423#define RT5668_EN_ANA_CLK_DET_MASK (0x1 << 15) 416#define RT5663_EN_ANA_CLK_DET_MASK (0x1 << 15)
424#define RT5668_EN_ANA_CLK_DET_SHIFT 15 417#define RT5663_EN_ANA_CLK_DET_SHIFT 15
425#define RT5668_EN_ANA_CLK_DET_DIS (0x0 << 15) 418#define RT5663_EN_ANA_CLK_DET_DIS (0x0 << 15)
426#define RT5668_EN_ANA_CLK_DET_AUTO (0x1 << 15) 419#define RT5663_EN_ANA_CLK_DET_AUTO (0x1 << 15)
427#define RT5668_PWR_CLK_DET_MASK (0x1) 420#define RT5663_PWR_CLK_DET_MASK (0x1)
428#define RT5668_PWR_CLK_DET_SHIFT 0 421#define RT5663_PWR_CLK_DET_SHIFT 0
429#define RT5668_PWR_CLK_DET_DIS (0x0) 422#define RT5663_PWR_CLK_DET_DIS (0x0)
430#define RT5668_PWR_CLK_DET_EN (0x1) 423#define RT5663_PWR_CLK_DET_EN (0x1)
431 424
432/* I2S1 Audio Serial Data Port Control (0x0070) */ 425/* I2S1 Audio Serial Data Port Control (0x0070) */
433#define RT5668_I2S_MS_MASK (0x1 << 15) 426#define RT5663_I2S_MS_MASK (0x1 << 15)
434#define RT5668_I2S_MS_SHIFT 15 427#define RT5663_I2S_MS_SHIFT 15
435#define RT5668_I2S_MS_M (0x0 << 15) 428#define RT5663_I2S_MS_M (0x0 << 15)
436#define RT5668_I2S_MS_S (0x1 << 15) 429#define RT5663_I2S_MS_S (0x1 << 15)
437#define RT5668_I2S_BP_MASK (0x1 << 8) 430#define RT5663_I2S_BP_MASK (0x1 << 8)
438#define RT5668_I2S_BP_SHIFT 8 431#define RT5663_I2S_BP_SHIFT 8
439#define RT5668_I2S_BP_NOR (0x0 << 8) 432#define RT5663_I2S_BP_NOR (0x0 << 8)
440#define RT5668_I2S_BP_INV (0x1 << 8) 433#define RT5663_I2S_BP_INV (0x1 << 8)
441#define RT5668_I2S_DL_MASK (0x3 << 4) 434#define RT5663_I2S_DL_MASK (0x3 << 4)
442#define RT5668_I2S_DL_SHIFT 4 435#define RT5663_I2S_DL_SHIFT 4
443#define RT5668_I2S_DL_16 (0x0 << 4) 436#define RT5663_I2S_DL_16 (0x0 << 4)
444#define RT5668_I2S_DL_20 (0x1 << 4) 437#define RT5663_I2S_DL_20 (0x1 << 4)
445#define RT5668_I2S_DL_24 (0x2 << 4) 438#define RT5663_I2S_DL_24 (0x2 << 4)
446#define RT5668_I2S_DL_8 (0x3 << 4) 439#define RT5663_I2S_DL_8 (0x3 << 4)
447#define RT5668_I2S_DF_MASK (0x7) 440#define RT5663_I2S_DF_MASK (0x7)
448#define RT5668_I2S_DF_SHIFT 0 441#define RT5663_I2S_DF_SHIFT 0
449#define RT5668_I2S_DF_I2S (0x0) 442#define RT5663_I2S_DF_I2S (0x0)
450#define RT5668_I2S_DF_LEFT (0x1) 443#define RT5663_I2S_DF_LEFT (0x1)
451#define RT5668_I2S_DF_PCM_A (0x2) 444#define RT5663_I2S_DF_PCM_A (0x2)
452#define RT5668_I2S_DF_PCM_B (0x3) 445#define RT5663_I2S_DF_PCM_B (0x3)
453#define RT5668_I2S_DF_PCM_A_N (0x6) 446#define RT5663_I2S_DF_PCM_A_N (0x6)
454#define RT5668_I2S_DF_PCM_B_N (0x7) 447#define RT5663_I2S_DF_PCM_B_N (0x7)
455 448
456/* ADC/DAC Clock Control 1 (0x0073) */ 449/* ADC/DAC Clock Control 1 (0x0073) */
457#define RT5668_I2S_PD1_MASK (0x7 << 12) 450#define RT5663_I2S_PD1_MASK (0x7 << 12)
458#define RT5668_I2S_PD1_SHIFT 12 451#define RT5663_I2S_PD1_SHIFT 12
459#define RT5668_M_I2S_DIV_MASK (0x7 << 8) 452#define RT5663_M_I2S_DIV_MASK (0x7 << 8)
460#define RT5668_M_I2S_DIV_SHIFT 8 453#define RT5663_M_I2S_DIV_SHIFT 8
461#define RT5668_CLK_SRC_MASK (0x3 << 4) 454#define RT5663_CLK_SRC_MASK (0x3 << 4)
462#define RT5668_CLK_SRC_MCLK (0x0 << 4) 455#define RT5663_CLK_SRC_MCLK (0x0 << 4)
463#define RT5668_CLK_SRC_PLL_OUT (0x1 << 4) 456#define RT5663_CLK_SRC_PLL_OUT (0x1 << 4)
464#define RT5668_CLK_SRC_DIV (0x2 << 4) 457#define RT5663_CLK_SRC_DIV (0x2 << 4)
465#define RT5668_CLK_SRC_RC (0x3 << 4) 458#define RT5663_CLK_SRC_RC (0x3 << 4)
466#define RT5668_DAC_OSR_MASK (0x3 << 2) 459#define RT5663_DAC_OSR_MASK (0x3 << 2)
467#define RT5668_DAC_OSR_SHIFT 2 460#define RT5663_DAC_OSR_SHIFT 2
468#define RT5668_DAC_OSR_128 (0x0 << 2) 461#define RT5663_DAC_OSR_128 (0x0 << 2)
469#define RT5668_DAC_OSR_64 (0x1 << 2) 462#define RT5663_DAC_OSR_64 (0x1 << 2)
470#define RT5668_DAC_OSR_32 (0x2 << 2) 463#define RT5663_DAC_OSR_32 (0x2 << 2)
471#define RT5668_ADC_OSR_MASK (0x3) 464#define RT5663_ADC_OSR_MASK (0x3)
472#define RT5668_ADC_OSR_SHIFT 0 465#define RT5663_ADC_OSR_SHIFT 0
473#define RT5668_ADC_OSR_128 (0x0) 466#define RT5663_ADC_OSR_128 (0x0)
474#define RT5668_ADC_OSR_64 (0x1) 467#define RT5663_ADC_OSR_64 (0x1)
475#define RT5668_ADC_OSR_32 (0x2) 468#define RT5663_ADC_OSR_32 (0x2)
476 469
477/* TDM1 control 1 (0x0078) */ 470/* TDM1 control 1 (0x0078) */
478#define RT5668_TDM_MODE_MASK (0x1 << 15) 471#define RT5663_TDM_MODE_MASK (0x1 << 15)
479#define RT5668_TDM_MODE_SHIFT 15 472#define RT5663_TDM_MODE_SHIFT 15
480#define RT5668_TDM_MODE_I2S (0x0 << 15) 473#define RT5663_TDM_MODE_I2S (0x0 << 15)
481#define RT5668_TDM_MODE_TDM (0x1 << 15) 474#define RT5663_TDM_MODE_TDM (0x1 << 15)
482#define RT5668_TDM_IN_CH_MASK (0x3 << 10) 475#define RT5663_TDM_IN_CH_MASK (0x3 << 10)
483#define RT5668_TDM_IN_CH_SHIFT 10 476#define RT5663_TDM_IN_CH_SHIFT 10
484#define RT5668_TDM_IN_CH_2 (0x0 << 10) 477#define RT5663_TDM_IN_CH_2 (0x0 << 10)
485#define RT5668_TDM_IN_CH_4 (0x1 << 10) 478#define RT5663_TDM_IN_CH_4 (0x1 << 10)
486#define RT5668_TDM_IN_CH_6 (0x2 << 10) 479#define RT5663_TDM_IN_CH_6 (0x2 << 10)
487#define RT5668_TDM_IN_CH_8 (0x3 << 10) 480#define RT5663_TDM_IN_CH_8 (0x3 << 10)
488#define RT5668_TDM_OUT_CH_MASK (0x3 << 8) 481#define RT5663_TDM_OUT_CH_MASK (0x3 << 8)
489#define RT5668_TDM_OUT_CH_SHIFT 8 482#define RT5663_TDM_OUT_CH_SHIFT 8
490#define RT5668_TDM_OUT_CH_2 (0x0 << 8) 483#define RT5663_TDM_OUT_CH_2 (0x0 << 8)
491#define RT5668_TDM_OUT_CH_4 (0x1 << 8) 484#define RT5663_TDM_OUT_CH_4 (0x1 << 8)
492#define RT5668_TDM_OUT_CH_6 (0x2 << 8) 485#define RT5663_TDM_OUT_CH_6 (0x2 << 8)
493#define RT5668_TDM_OUT_CH_8 (0x3 << 8) 486#define RT5663_TDM_OUT_CH_8 (0x3 << 8)
494#define RT5668_TDM_IN_LEN_MASK (0x3 << 6) 487#define RT5663_TDM_IN_LEN_MASK (0x3 << 6)
495#define RT5668_TDM_IN_LEN_SHIFT 6 488#define RT5663_TDM_IN_LEN_SHIFT 6
496#define RT5668_TDM_IN_LEN_16 (0x0 << 6) 489#define RT5663_TDM_IN_LEN_16 (0x0 << 6)
497#define RT5668_TDM_IN_LEN_20 (0x1 << 6) 490#define RT5663_TDM_IN_LEN_20 (0x1 << 6)
498#define RT5668_TDM_IN_LEN_24 (0x2 << 6) 491#define RT5663_TDM_IN_LEN_24 (0x2 << 6)
499#define RT5668_TDM_IN_LEN_32 (0x3 << 6) 492#define RT5663_TDM_IN_LEN_32 (0x3 << 6)
500#define RT5668_TDM_OUT_LEN_MASK (0x3 << 4) 493#define RT5663_TDM_OUT_LEN_MASK (0x3 << 4)
501#define RT5668_TDM_OUT_LEN_SHIFT 4 494#define RT5663_TDM_OUT_LEN_SHIFT 4
502#define RT5668_TDM_OUT_LEN_16 (0x0 << 4) 495#define RT5663_TDM_OUT_LEN_16 (0x0 << 4)
503#define RT5668_TDM_OUT_LEN_20 (0x1 << 4) 496#define RT5663_TDM_OUT_LEN_20 (0x1 << 4)
504#define RT5668_TDM_OUT_LEN_24 (0x2 << 4) 497#define RT5663_TDM_OUT_LEN_24 (0x2 << 4)
505#define RT5668_TDM_OUT_LEN_32 (0x3 << 4) 498#define RT5663_TDM_OUT_LEN_32 (0x3 << 4)
506 499
507/* Global Clock Control (0x0080) */ 500/* Global Clock Control (0x0080) */
508#define RT5668_SCLK_SRC_MASK (0x3 << 14) 501#define RT5663_SCLK_SRC_MASK (0x3 << 14)
509#define RT5668_SCLK_SRC_SHIFT 14 502#define RT5663_SCLK_SRC_SHIFT 14
510#define RT5668_SCLK_SRC_MCLK (0x0 << 14) 503#define RT5663_SCLK_SRC_MCLK (0x0 << 14)
511#define RT5668_SCLK_SRC_PLL1 (0x1 << 14) 504#define RT5663_SCLK_SRC_PLL1 (0x1 << 14)
512#define RT5668_SCLK_SRC_RCCLK (0x2 << 14) 505#define RT5663_SCLK_SRC_RCCLK (0x2 << 14)
513#define RT5668_PLL1_SRC_MASK (0x7 << 8) 506#define RT5663_PLL1_SRC_MASK (0x7 << 11)
514#define RT5668_PLL1_SRC_SHIFT 8 507#define RT5663_PLL1_SRC_SHIFT 11
515#define RT5668_PLL1_SRC_MCLK (0x0 << 8) 508#define RT5663_PLL1_SRC_MCLK (0x0 << 11)
516#define RT5668_PLL1_SRC_BCLK1 (0x1 << 8) 509#define RT5663_PLL1_SRC_BCLK1 (0x1 << 11)
517#define RT5668_PLL1_PD_MASK (0x1 << 4) 510#define RT5663_V2_PLL1_SRC_MASK (0x7 << 8)
518#define RT5668_PLL1_PD_SHIFT 4 511#define RT5663_V2_PLL1_SRC_SHIFT 8
519 512#define RT5663_V2_PLL1_SRC_MCLK (0x0 << 8)
520#define RT5668_PLL_INP_MAX 40000000 513#define RT5663_V2_PLL1_SRC_BCLK1 (0x1 << 8)
521#define RT5668_PLL_INP_MIN 256000 514#define RT5663_PLL1_PD_MASK (0x1 << 4)
515#define RT5663_PLL1_PD_SHIFT 4
516
517#define RT5663_PLL_INP_MAX 40000000
518#define RT5663_PLL_INP_MIN 256000
522/* PLL M/N/K Code Control 1 (0x0081) */ 519/* PLL M/N/K Code Control 1 (0x0081) */
523#define RT5668_PLL_N_MAX 0x001ff 520#define RT5663_PLL_N_MAX 0x001ff
524#define RT5668_PLL_N_MASK (RT5668_PLL_N_MAX << 7) 521#define RT5663_PLL_N_MASK (RT5663_PLL_N_MAX << 7)
525#define RT5668_PLL_N_SHIFT 7 522#define RT5663_PLL_N_SHIFT 7
526#define RT5668_PLL_K_MAX 0x001f 523#define RT5663_PLL_K_MAX 0x001f
527#define RT5668_PLL_K_MASK (RT5668_PLL_K_MAX) 524#define RT5663_PLL_K_MASK (RT5663_PLL_K_MAX)
528#define RT5668_PLL_K_SHIFT 0 525#define RT5663_PLL_K_SHIFT 0
529 526
530/* PLL M/N/K Code Control 2 (0x0082) */ 527/* PLL M/N/K Code Control 2 (0x0082) */
531#define RT5668_PLL_M_MAX 0x00f 528#define RT5663_PLL_M_MAX 0x00f
532#define RT5668_PLL_M_MASK (RT5668_PLL_M_MAX << 12) 529#define RT5663_PLL_M_MASK (RT5663_PLL_M_MAX << 12)
533#define RT5668_PLL_M_SHIFT 12 530#define RT5663_PLL_M_SHIFT 12
534#define RT5668_PLL_M_BP (0x1 << 11) 531#define RT5663_PLL_M_BP (0x1 << 11)
535#define RT5668_PLL_M_BP_SHIFT 11 532#define RT5663_PLL_M_BP_SHIFT 11
536 533
537/* PLL tracking mode 1 (0x0083) */ 534/* PLL tracking mode 1 (0x0083) */
538#define RT5668_I2S1_ASRC_MASK (0x1 << 13) 535#define RT5663_V2_I2S1_ASRC_MASK (0x1 << 13)
539#define RT5668_I2S1_ASRC_SHIFT 13 536#define RT5663_V2_I2S1_ASRC_SHIFT 13
540#define RT5668_DAC_STO1_ASRC_MASK (0x1 << 12) 537#define RT5663_V2_DAC_STO1_ASRC_MASK (0x1 << 12)
541#define RT5668_DAC_STO1_ASRC_SHIFT 12 538#define RT5663_V2_DAC_STO1_ASRC_SHIFT 12
542#define RT5668_ADC_STO1_ASRC_MASK (0x1 << 4) 539#define RT5663_V2_ADC_STO1_ASRC_MASK (0x1 << 4)
543#define RT5668_ADC_STO1_ASRC_SHIFT 4 540#define RT5663_V2_ADC_STO1_ASRC_SHIFT 4
544 541
545/* PLL tracking mode 2 (0x0084)*/ 542/* PLL tracking mode 2 (0x0084)*/
546#define RT5668_DA_STO1_TRACK_MASK (0x7 << 12) 543#define RT5663_DA_STO1_TRACK_MASK (0x7 << 12)
547#define RT5668_DA_STO1_TRACK_SHIFT 12 544#define RT5663_DA_STO1_TRACK_SHIFT 12
548#define RT5668_DA_STO1_TRACK_SYSCLK (0x0 << 12) 545#define RT5663_DA_STO1_TRACK_SYSCLK (0x0 << 12)
549#define RT5668_DA_STO1_TRACK_I2S1 (0x1 << 12) 546#define RT5663_DA_STO1_TRACK_I2S1 (0x1 << 12)
550 547
551/* PLL tracking mode 3 (0x0085)*/ 548/* PLL tracking mode 3 (0x0085)*/
552#define RT5668_AD_STO1_TRACK_MASK (0x7 << 12) 549#define RT5663_V2_AD_STO1_TRACK_MASK (0x7 << 12)
553#define RT5668_AD_STO1_TRACK_SHIFT 12 550#define RT5663_V2_AD_STO1_TRACK_SHIFT 12
554#define RT5668_AD_STO1_TRACK_SYSCLK (0x0 << 12) 551#define RT5663_V2_AD_STO1_TRACK_SYSCLK (0x0 << 12)
555#define RT5668_AD_STO1_TRACK_I2S1 (0x1 << 12) 552#define RT5663_V2_AD_STO1_TRACK_I2S1 (0x1 << 12)
556 553
557/* HPOUT Charge pump control 1 (0x0091) */ 554/* HPOUT Charge pump control 1 (0x0091) */
558#define RT5668_OSW_HP_L_MASK (0x1 << 11) 555#define RT5663_OSW_HP_L_MASK (0x1 << 11)
559#define RT5668_OSW_HP_L_SHIFT 11 556#define RT5663_OSW_HP_L_SHIFT 11
560#define RT5668_OSW_HP_L_EN (0x1 << 11) 557#define RT5663_OSW_HP_L_EN (0x1 << 11)
561#define RT5668_OSW_HP_L_DIS (0x0 << 11) 558#define RT5663_OSW_HP_L_DIS (0x0 << 11)
562#define RT5668_OSW_HP_R_MASK (0x1 << 10) 559#define RT5663_OSW_HP_R_MASK (0x1 << 10)
563#define RT5668_OSW_HP_R_SHIFT 10 560#define RT5663_OSW_HP_R_SHIFT 10
564#define RT5668_OSW_HP_R_EN (0x1 << 10) 561#define RT5663_OSW_HP_R_EN (0x1 << 10)
565#define RT5668_OSW_HP_R_DIS (0x0 << 10) 562#define RT5663_OSW_HP_R_DIS (0x0 << 10)
566#define RT5668_SEL_PM_HP_MASK (0x3 << 8) 563#define RT5663_SEL_PM_HP_MASK (0x3 << 8)
567#define RT5668_SEL_PM_HP_SHIFT 8 564#define RT5663_SEL_PM_HP_SHIFT 8
568#define RT5668_SEL_PM_HP_0_6 (0x0 << 8) 565#define RT5663_SEL_PM_HP_0_6 (0x0 << 8)
569#define RT5668_SEL_PM_HP_0_9 (0x1 << 8) 566#define RT5663_SEL_PM_HP_0_9 (0x1 << 8)
570#define RT5668_SEL_PM_HP_1_8 (0x2 << 8) 567#define RT5663_SEL_PM_HP_1_8 (0x2 << 8)
571#define RT5668_SEL_PM_HP_HIGH (0x3 << 8) 568#define RT5663_SEL_PM_HP_HIGH (0x3 << 8)
572#define RT5668_OVCD_HP_MASK (0x1 << 2) 569#define RT5663_OVCD_HP_MASK (0x1 << 2)
573#define RT5668_OVCD_HP_SHIFT 2 570#define RT5663_OVCD_HP_SHIFT 2
574#define RT5668_OVCD_HP_EN (0x1 << 2) 571#define RT5663_OVCD_HP_EN (0x1 << 2)
575#define RT5668_OVCD_HP_DIS (0x0 << 2) 572#define RT5663_OVCD_HP_DIS (0x0 << 2)
576 573
577/* RC Clock Control (0x0094) */ 574/* RC Clock Control (0x0094) */
578#define RT5668_DIG_25M_CLK_MASK (0x1 << 9) 575#define RT5663_DIG_25M_CLK_MASK (0x1 << 9)
579#define RT5668_DIG_25M_CLK_SHIFT 9 576#define RT5663_DIG_25M_CLK_SHIFT 9
580#define RT5668_DIG_25M_CLK_DIS (0x0 << 9) 577#define RT5663_DIG_25M_CLK_DIS (0x0 << 9)
581#define RT5668_DIG_25M_CLK_EN (0x1 << 9) 578#define RT5663_DIG_25M_CLK_EN (0x1 << 9)
582#define RT5668_DIG_1M_CLK_MASK (0x1 << 8) 579#define RT5663_DIG_1M_CLK_MASK (0x1 << 8)
583#define RT5668_DIG_1M_CLK_SHIFT 8 580#define RT5663_DIG_1M_CLK_SHIFT 8
584#define RT5668_DIG_1M_CLK_DIS (0x0 << 8) 581#define RT5663_DIG_1M_CLK_DIS (0x0 << 8)
585#define RT5668_DIG_1M_CLK_EN (0x1 << 8) 582#define RT5663_DIG_1M_CLK_EN (0x1 << 8)
586 583
587/* Auto Turn On 1M RC CLK (0x009f) */ 584/* Auto Turn On 1M RC CLK (0x009f) */
588#define RT5668_IRQ_POW_SAV_MASK (0x1 << 15) 585#define RT5663_IRQ_POW_SAV_MASK (0x1 << 15)
589#define RT5668_IRQ_POW_SAV_SHIFT 15 586#define RT5663_IRQ_POW_SAV_SHIFT 15
590#define RT5668_IRQ_POW_SAV_DIS (0x0 << 15) 587#define RT5663_IRQ_POW_SAV_DIS (0x0 << 15)
591#define RT5668_IRQ_POW_SAV_EN (0x1 << 15) 588#define RT5663_IRQ_POW_SAV_EN (0x1 << 15)
592#define RT5668_IRQ_POW_SAV_JD1_MASK (0x1 << 14) 589#define RT5663_IRQ_POW_SAV_JD1_MASK (0x1 << 14)
593#define RT5668_IRQ_POW_SAV_JD1_SHIFT 14 590#define RT5663_IRQ_POW_SAV_JD1_SHIFT 14
594#define RT5668_IRQ_POW_SAV_JD1_DIS (0x0 << 14) 591#define RT5663_IRQ_POW_SAV_JD1_DIS (0x0 << 14)
595#define RT5668_IRQ_POW_SAV_JD1_EN (0x1 << 14) 592#define RT5663_IRQ_POW_SAV_JD1_EN (0x1 << 14)
596 593
597/* IRQ Control 1 (0x00b6) */ 594/* IRQ Control 1 (0x00b6) */
598#define RT5668_EN_CB_JD_MASK (0x1 << 3) 595#define RT5663_EN_CB_JD_MASK (0x1 << 3)
599#define RT5668_EN_CB_JD_SHIFT 3 596#define RT5663_EN_CB_JD_SHIFT 3
600#define RT5668_EN_CB_JD_EN (0x1 << 3) 597#define RT5663_EN_CB_JD_EN (0x1 << 3)
601#define RT5668_EN_CB_JD_DIS (0x0 << 3) 598#define RT5663_EN_CB_JD_DIS (0x0 << 3)
602 599
603/* IRQ Control 3 (0x00b8) */ 600/* IRQ Control 3 (0x00b8) */
604#define RT5668_EN_IRQ_INLINE_MASK (0x1 << 6) 601#define RT5663_V2_EN_IRQ_INLINE_MASK (0x1 << 6)
605#define RT5668_EN_IRQ_INLINE_SHIFT 6 602#define RT5663_V2_EN_IRQ_INLINE_SHIFT 6
606#define RT5668_EN_IRQ_INLINE_BYP (0x0 << 6) 603#define RT5663_V2_EN_IRQ_INLINE_BYP (0x0 << 6)
607#define RT5668_EN_IRQ_INLINE_NOR (0x1 << 6) 604#define RT5663_V2_EN_IRQ_INLINE_NOR (0x1 << 6)
608 605
609/* GPIO Control 1 (0x00c0) */ 606/* GPIO Control 1 (0x00c0) */
610#define RT5668_GP1_PIN_MASK (0x1 << 15) 607#define RT5663_GP1_PIN_MASK (0x1 << 15)
611#define RT5668_GP1_PIN_SHIFT 15 608#define RT5663_GP1_PIN_SHIFT 15
612#define RT5668_GP1_PIN_GPIO1 (0x0 << 15) 609#define RT5663_GP1_PIN_GPIO1 (0x0 << 15)
613#define RT5668_GP1_PIN_IRQ (0x1 << 15) 610#define RT5663_GP1_PIN_IRQ (0x1 << 15)
614 611
615/* GPIO Control 2 (0x00c1) */ 612/* GPIO Control 2 (0x00c1) */
616#define RT5668_GP4_PIN_CONF_MASK (0x1 << 5) 613#define RT5663_GP4_PIN_CONF_MASK (0x1 << 5)
617#define RT5668_GP4_PIN_CONF_SHIFT 5 614#define RT5663_GP4_PIN_CONF_SHIFT 5
618#define RT5668_GP4_PIN_CONF_INPUT (0x0 << 5) 615#define RT5663_GP4_PIN_CONF_INPUT (0x0 << 5)
619#define RT5668_GP4_PIN_CONF_OUTPUT (0x1 << 5) 616#define RT5663_GP4_PIN_CONF_OUTPUT (0x1 << 5)
620 617
621/* GPIO Control 2 (0x00c2) */ 618/* GPIO Control 2 (0x00c2) */
622#define RT5668_GP8_PIN_CONF_MASK (0x1 << 13) 619#define RT5663_GP8_PIN_CONF_MASK (0x1 << 13)
623#define RT5668_GP8_PIN_CONF_SHIFT 13 620#define RT5663_GP8_PIN_CONF_SHIFT 13
624#define RT5668_GP8_PIN_CONF_INPUT (0x0 << 13) 621#define RT5663_GP8_PIN_CONF_INPUT (0x0 << 13)
625#define RT5668_GP8_PIN_CONF_OUTPUT (0x1 << 13) 622#define RT5663_GP8_PIN_CONF_OUTPUT (0x1 << 13)
626 623
627/* 4 Buttons Inline Command Function 1 (0x00df) */ 624/* 4 Buttons Inline Command Function 1 (0x00df) */
628#define RT5668_4BTN_CLK_DEB_MASK (0x3 << 2) 625#define RT5663_4BTN_CLK_DEB_MASK (0x3 << 2)
629#define RT5668_4BTN_CLK_DEB_SHIFT 2 626#define RT5663_4BTN_CLK_DEB_SHIFT 2
630#define RT5668_4BTN_CLK_DEB_8MS (0x0 << 2) 627#define RT5663_4BTN_CLK_DEB_8MS (0x0 << 2)
631#define RT5668_4BTN_CLK_DEB_16MS (0x1 << 2) 628#define RT5663_4BTN_CLK_DEB_16MS (0x1 << 2)
632#define RT5668_4BTN_CLK_DEB_32MS (0x2 << 2) 629#define RT5663_4BTN_CLK_DEB_32MS (0x2 << 2)
633#define RT5668_4BTN_CLK_DEB_65MS (0x3 << 2) 630#define RT5663_4BTN_CLK_DEB_65MS (0x3 << 2)
634 631
635/* Inline Command Function 6 (0x00e0) */ 632/* Inline Command Function 6 (0x00e0) */
636#define RT5668_EN_4BTN_INL_MASK (0x1 << 15) 633#define RT5663_EN_4BTN_INL_MASK (0x1 << 15)
637#define RT5668_EN_4BTN_INL_SHIFT 15 634#define RT5663_EN_4BTN_INL_SHIFT 15
638#define RT5668_EN_4BTN_INL_DIS (0x0 << 15) 635#define RT5663_EN_4BTN_INL_DIS (0x0 << 15)
639#define RT5668_EN_4BTN_INL_EN (0x1 << 15) 636#define RT5663_EN_4BTN_INL_EN (0x1 << 15)
640#define RT5668_RESET_4BTN_INL_MASK (0x1 << 14) 637#define RT5663_RESET_4BTN_INL_MASK (0x1 << 14)
641#define RT5668_RESET_4BTN_INL_SHIFT 14 638#define RT5663_RESET_4BTN_INL_SHIFT 14
642#define RT5668_RESET_4BTN_INL_RESET (0x0 << 14) 639#define RT5663_RESET_4BTN_INL_RESET (0x0 << 14)
643#define RT5668_RESET_4BTN_INL_NOR (0x1 << 14) 640#define RT5663_RESET_4BTN_INL_NOR (0x1 << 14)
644 641
645/* Digital Misc Control (0x00fa) */ 642/* Digital Misc Control (0x00fa) */
646#define RT5668_DIG_GATE_CTRL_MASK 0x1 643#define RT5663_DIG_GATE_CTRL_MASK 0x1
647#define RT5668_DIG_GATE_CTRL_SHIFT (0) 644#define RT5663_DIG_GATE_CTRL_SHIFT (0)
648#define RT5668_DIG_GATE_CTRL_DIS 0x0 645#define RT5663_DIG_GATE_CTRL_DIS 0x0
649#define RT5668_DIG_GATE_CTRL_EN 0x1 646#define RT5663_DIG_GATE_CTRL_EN 0x1
650 647
651/* Chopper and Clock control for DAC L (0x013a)*/ 648/* Chopper and Clock control for DAC L (0x013a)*/
652#define RT5668_CKXEN_DAC1_MASK (0x1 << 13) 649#define RT5663_CKXEN_DAC1_MASK (0x1 << 13)
653#define RT5668_CKXEN_DAC1_SHIFT 13 650#define RT5663_CKXEN_DAC1_SHIFT 13
654#define RT5668_CKGEN_DAC1_MASK (0x1 << 12) 651#define RT5663_CKGEN_DAC1_MASK (0x1 << 12)
655#define RT5668_CKGEN_DAC1_SHIFT 12 652#define RT5663_CKGEN_DAC1_SHIFT 12
656 653
657/* Chopper and Clock control for ADC (0x013b)*/ 654/* Chopper and Clock control for ADC (0x013b)*/
658#define RT5668_CKXEN_ADCC_MASK (0x1 << 13) 655#define RT5663_CKXEN_ADCC_MASK (0x1 << 13)
659#define RT5668_CKXEN_ADCC_SHIFT 13 656#define RT5663_CKXEN_ADCC_SHIFT 13
660#define RT5668_CKGEN_ADCC_MASK (0x1 << 12) 657#define RT5663_CKGEN_ADCC_MASK (0x1 << 12)
661#define RT5668_CKGEN_ADCC_SHIFT 12 658#define RT5663_CKGEN_ADCC_SHIFT 12
662 659
663/* HP Behavior Logic Control 2 (0x01db) */ 660/* HP Behavior Logic Control 2 (0x01db) */
664#define RT5668_HP_SIG_SRC1_MASK (0x3) 661#define RT5663_HP_SIG_SRC1_MASK (0x3)
665#define RT5668_HP_SIG_SRC1_SHIFT 0 662#define RT5663_HP_SIG_SRC1_SHIFT 0
666#define RT5668_HP_SIG_SRC1_HP_DC (0x0) 663#define RT5663_HP_SIG_SRC1_HP_DC (0x0)
667#define RT5668_HP_SIG_SRC1_HP_CALIB (0x1) 664#define RT5663_HP_SIG_SRC1_HP_CALIB (0x1)
668#define RT5668_HP_SIG_SRC1_REG (0x2) 665#define RT5663_HP_SIG_SRC1_REG (0x2)
669#define RT5668_HP_SIG_SRC1_SILENCE (0x3) 666#define RT5663_HP_SIG_SRC1_SILENCE (0x3)
670 667
671/* RT5663 specific register */ 668/* RT5663 specific register */
672#define RT5663_HP_OUT_EN 0x0002 669#define RT5663_HP_OUT_EN 0x0002
@@ -707,6 +704,10 @@
707#define RT5663_TDM_3 0x0079 704#define RT5663_TDM_3 0x0079
708#define RT5663_TDM_4 0x007a 705#define RT5663_TDM_4 0x007a
709#define RT5663_TDM_5 0x007b 706#define RT5663_TDM_5 0x007b
707#define RT5663_TDM_6 0x007c
708#define RT5663_TDM_7 0x007d
709#define RT5663_TDM_8 0x007e
710#define RT5663_TDM_9 0x007f
710#define RT5663_GLB_CLK 0x0080 711#define RT5663_GLB_CLK 0x0080
711#define RT5663_PLL_1 0x0081 712#define RT5663_PLL_1 0x0081
712#define RT5663_PLL_2 0x0082 713#define RT5663_PLL_2 0x0082
@@ -739,7 +740,7 @@
739#define RT5663_INT_ST_2 0x00bf 740#define RT5663_INT_ST_2 0x00bf
740#define RT5663_GPIO_1 0x00c0 741#define RT5663_GPIO_1 0x00c0
741#define RT5663_GPIO_2 0x00c1 742#define RT5663_GPIO_2 0x00c1
742#define RT5663_GPIO_STA 0x00c5 743#define RT5663_GPIO_STA1 0x00c5
743#define RT5663_SIN_GEN_1 0x00cb 744#define RT5663_SIN_GEN_1 0x00cb
744#define RT5663_SIN_GEN_2 0x00cc 745#define RT5663_SIN_GEN_2 0x00cc
745#define RT5663_SIN_GEN_3 0x00cd 746#define RT5663_SIN_GEN_3 0x00cd
@@ -800,6 +801,8 @@
800#define RT5663_TEST_MODE_1 0x0144 801#define RT5663_TEST_MODE_1 0x0144
801#define RT5663_TEST_MODE_2 0x0145 802#define RT5663_TEST_MODE_2 0x0145
802#define RT5663_TEST_MODE_3 0x0146 803#define RT5663_TEST_MODE_3 0x0146
804#define RT5663_TEST_MODE_4 0x0147
805#define RT5663_TEST_MODE_5 0x0148
803#define RT5663_STO_DRE_1 0x0160 806#define RT5663_STO_DRE_1 0x0160
804#define RT5663_STO_DRE_2 0x0161 807#define RT5663_STO_DRE_2 0x0161
805#define RT5663_STO_DRE_3 0x0162 808#define RT5663_STO_DRE_3 0x0162
@@ -921,19 +924,19 @@
921#define RT5663_ADC_EQ_POST_VOL_L 0x03f2 924#define RT5663_ADC_EQ_POST_VOL_L 0x03f2
922#define RT5663_ADC_EQ_POST_VOL_R 0x03f3 925#define RT5663_ADC_EQ_POST_VOL_R 0x03f3
923 926
924/* RT5663: RECMIX Control (0x0010) */ 927/* RECMIX Control (0x0010) */
925#define RT5663_RECMIX1_BST1_MASK (0x1) 928#define RT5663_RECMIX1_BST1_MASK (0x1)
926#define RT5663_RECMIX1_BST1_SHIFT 0 929#define RT5663_RECMIX1_BST1_SHIFT 0
927#define RT5663_RECMIX1_BST1_ON (0x0) 930#define RT5663_RECMIX1_BST1_ON (0x0)
928#define RT5663_RECMIX1_BST1_OFF (0x1) 931#define RT5663_RECMIX1_BST1_OFF (0x1)
929 932
930/* RT5663: Bypass Stereo1 DAC Mixer Control (0x002d) */ 933/* Bypass Stereo1 DAC Mixer Control (0x002d) */
931#define RT5663_DACL1_SRC_MASK (0x1 << 3) 934#define RT5663_DACL1_SRC_MASK (0x1 << 3)
932#define RT5663_DACL1_SRC_SHIFT 3 935#define RT5663_DACL1_SRC_SHIFT 3
933#define RT5663_DACR1_SRC_MASK (0x1 << 2) 936#define RT5663_DACR1_SRC_MASK (0x1 << 2)
934#define RT5663_DACR1_SRC_SHIFT 2 937#define RT5663_DACR1_SRC_SHIFT 2
935 938
936/* RT5663: TDM control 2 (0x0078) */ 939/* TDM control 2 (0x0078) */
937#define RT5663_DATA_SWAP_ADCDAT1_MASK (0x3 << 14) 940#define RT5663_DATA_SWAP_ADCDAT1_MASK (0x3 << 14)
938#define RT5663_DATA_SWAP_ADCDAT1_SHIFT 14 941#define RT5663_DATA_SWAP_ADCDAT1_SHIFT 14
939#define RT5663_DATA_SWAP_ADCDAT1_LR (0x0 << 14) 942#define RT5663_DATA_SWAP_ADCDAT1_LR (0x0 << 14)
@@ -941,7 +944,7 @@
941#define RT5663_DATA_SWAP_ADCDAT1_LL (0x2 << 14) 944#define RT5663_DATA_SWAP_ADCDAT1_LL (0x2 << 14)
942#define RT5663_DATA_SWAP_ADCDAT1_RR (0x3 << 14) 945#define RT5663_DATA_SWAP_ADCDAT1_RR (0x3 << 14)
943 946
944/* RT5663: TDM control 5 (0x007b) */ 947/* TDM control 5 (0x007b) */
945#define RT5663_TDM_LENGTN_MASK (0x3) 948#define RT5663_TDM_LENGTN_MASK (0x3)
946#define RT5663_TDM_LENGTN_SHIFT 0 949#define RT5663_TDM_LENGTN_SHIFT 0
947#define RT5663_TDM_LENGTN_16 (0x0) 950#define RT5663_TDM_LENGTN_16 (0x0)
@@ -949,17 +952,6 @@
949#define RT5663_TDM_LENGTN_24 (0x2) 952#define RT5663_TDM_LENGTN_24 (0x2)
950#define RT5663_TDM_LENGTN_32 (0x3) 953#define RT5663_TDM_LENGTN_32 (0x3)
951 954
952/* RT5663: Global Clock Control (0x0080) */
953#define RT5663_SCLK_SRC_MASK (0x3 << 14)
954#define RT5663_SCLK_SRC_SHIFT 14
955#define RT5663_SCLK_SRC_MCLK (0x0 << 14)
956#define RT5663_SCLK_SRC_PLL1 (0x1 << 14)
957#define RT5663_SCLK_SRC_RCCLK (0x2 << 14)
958#define RT5663_PLL1_SRC_MASK (0x7 << 11)
959#define RT5663_PLL1_SRC_SHIFT 11
960#define RT5663_PLL1_SRC_MCLK (0x0 << 11)
961#define RT5663_PLL1_SRC_BCLK1 (0x1 << 11)
962
963/* PLL tracking mode 1 (0x0083) */ 955/* PLL tracking mode 1 (0x0083) */
964#define RT5663_I2S1_ASRC_MASK (0x1 << 11) 956#define RT5663_I2S1_ASRC_MASK (0x1 << 11)
965#define RT5663_I2S1_ASRC_SHIFT 11 957#define RT5663_I2S1_ASRC_SHIFT 11
@@ -978,31 +970,31 @@
978#define RT5663_AD_STO1_TRACK_SYSCLK (0x0) 970#define RT5663_AD_STO1_TRACK_SYSCLK (0x0)
979#define RT5663_AD_STO1_TRACK_I2S1 (0x1) 971#define RT5663_AD_STO1_TRACK_I2S1 (0x1)
980 972
981/* RT5663: HPOUT Charge pump control 1 (0x0091) */ 973/* HPOUT Charge pump control 1 (0x0091) */
982#define RT5663_SI_HP_MASK (0x1 << 12) 974#define RT5663_SI_HP_MASK (0x1 << 12)
983#define RT5663_SI_HP_SHIFT 12 975#define RT5663_SI_HP_SHIFT 12
984#define RT5663_SI_HP_EN (0x1 << 12) 976#define RT5663_SI_HP_EN (0x1 << 12)
985#define RT5663_SI_HP_DIS (0x0 << 12) 977#define RT5663_SI_HP_DIS (0x0 << 12)
986 978
987/* RT5663: GPIO Control 2 (0x00b6) */ 979/* GPIO Control 2 (0x00b6) */
988#define RT5663_GP1_PIN_CONF_MASK (0x1 << 2) 980#define RT5663_GP1_PIN_CONF_MASK (0x1 << 2)
989#define RT5663_GP1_PIN_CONF_SHIFT 2 981#define RT5663_GP1_PIN_CONF_SHIFT 2
990#define RT5663_GP1_PIN_CONF_OUTPUT (0x1 << 2) 982#define RT5663_GP1_PIN_CONF_OUTPUT (0x1 << 2)
991#define RT5663_GP1_PIN_CONF_INPUT (0x0 << 2) 983#define RT5663_GP1_PIN_CONF_INPUT (0x0 << 2)
992 984
993/* RT5663: GPIO Control 2 (0x00b7) */ 985/* GPIO Control 2 (0x00b7) */
994#define RT5663_EN_IRQ_INLINE_MASK (0x1 << 3) 986#define RT5663_EN_IRQ_INLINE_MASK (0x1 << 3)
995#define RT5663_EN_IRQ_INLINE_SHIFT 3 987#define RT5663_EN_IRQ_INLINE_SHIFT 3
996#define RT5663_EN_IRQ_INLINE_NOR (0x1 << 3) 988#define RT5663_EN_IRQ_INLINE_NOR (0x1 << 3)
997#define RT5663_EN_IRQ_INLINE_BYP (0x0 << 3) 989#define RT5663_EN_IRQ_INLINE_BYP (0x0 << 3)
998 990
999/* RT5663: GPIO Control 1 (0x00c0) */ 991/* GPIO Control 1 (0x00c0) */
1000#define RT5663_GPIO1_TYPE_MASK (0x1 << 15) 992#define RT5663_GPIO1_TYPE_MASK (0x1 << 15)
1001#define RT5663_GPIO1_TYPE_SHIFT 15 993#define RT5663_GPIO1_TYPE_SHIFT 15
1002#define RT5663_GPIO1_TYPE_EN (0x1 << 15) 994#define RT5663_GPIO1_TYPE_EN (0x1 << 15)
1003#define RT5663_GPIO1_TYPE_DIS (0x0 << 15) 995#define RT5663_GPIO1_TYPE_DIS (0x0 << 15)
1004 996
1005/* RT5663: IRQ Control 1 (0x00c1) */ 997/* IRQ Control 1 (0x00c1) */
1006#define RT5663_EN_IRQ_JD1_MASK (0x1 << 6) 998#define RT5663_EN_IRQ_JD1_MASK (0x1 << 6)
1007#define RT5663_EN_IRQ_JD1_SHIFT 6 999#define RT5663_EN_IRQ_JD1_SHIFT 6
1008#define RT5663_EN_IRQ_JD1_EN (0x1 << 6) 1000#define RT5663_EN_IRQ_JD1_EN (0x1 << 6)
@@ -1012,13 +1004,13 @@
1012#define RT5663_SEL_GPIO1_EN (0x1 << 2) 1004#define RT5663_SEL_GPIO1_EN (0x1 << 2)
1013#define RT5663_SEL_GPIO1_DIS (0x0 << 2) 1005#define RT5663_SEL_GPIO1_DIS (0x0 << 2)
1014 1006
1015/* RT5663: Inline Command Function 2 (0x00dc) */ 1007/* Inline Command Function 2 (0x00dc) */
1016#define RT5663_PWR_MIC_DET_MASK (0x1) 1008#define RT5663_PWR_MIC_DET_MASK (0x1)
1017#define RT5663_PWR_MIC_DET_SHIFT 0 1009#define RT5663_PWR_MIC_DET_SHIFT 0
1018#define RT5663_PWR_MIC_DET_ON (0x1) 1010#define RT5663_PWR_MIC_DET_ON (0x1)
1019#define RT5663_PWR_MIC_DET_OFF (0x0) 1011#define RT5663_PWR_MIC_DET_OFF (0x0)
1020 1012
1021/* RT5663: Embeeded Jack and Type Detection Control 1 (0x00e6)*/ 1013/* Embeeded Jack and Type Detection Control 1 (0x00e6)*/
1022#define RT5663_CBJ_DET_MASK (0x1 << 15) 1014#define RT5663_CBJ_DET_MASK (0x1 << 15)
1023#define RT5663_CBJ_DET_SHIFT 15 1015#define RT5663_CBJ_DET_SHIFT 15
1024#define RT5663_CBJ_DET_DIS (0x0 << 15) 1016#define RT5663_CBJ_DET_DIS (0x0 << 15)
@@ -1032,17 +1024,17 @@
1032#define RT5663_POL_EXT_JD_EN (0x1 << 10) 1024#define RT5663_POL_EXT_JD_EN (0x1 << 10)
1033#define RT5663_POL_EXT_JD_DIS (0x0 << 10) 1025#define RT5663_POL_EXT_JD_DIS (0x0 << 10)
1034 1026
1035/* RT5663: DACREF LDO Control (0x0112)*/ 1027/* DACREF LDO Control (0x0112)*/
1036#define RT5663_PWR_LDO_DACREFL_MASK (0x1 << 9) 1028#define RT5663_PWR_LDO_DACREFL_MASK (0x1 << 9)
1037#define RT5663_PWR_LDO_DACREFL_SHIFT 9 1029#define RT5663_PWR_LDO_DACREFL_SHIFT 9
1038#define RT5663_PWR_LDO_DACREFR_MASK (0x1 << 1) 1030#define RT5663_PWR_LDO_DACREFR_MASK (0x1 << 1)
1039#define RT5663_PWR_LDO_DACREFR_SHIFT 1 1031#define RT5663_PWR_LDO_DACREFR_SHIFT 1
1040 1032
1041/* RT5663: Stereo Dynamic Range Enhancement Control 9 (0x0168, 0x0169)*/ 1033/* Stereo Dynamic Range Enhancement Control 9 (0x0168, 0x0169)*/
1042#define RT5663_DRE_GAIN_HP_MASK (0x1f) 1034#define RT5663_DRE_GAIN_HP_MASK (0x1f)
1043#define RT5663_DRE_GAIN_HP_SHIFT 0 1035#define RT5663_DRE_GAIN_HP_SHIFT 0
1044 1036
1045/* RT5663: Combo Jack Control (0x0250) */ 1037/* Combo Jack Control (0x0250) */
1046#define RT5663_INBUF_CBJ_BST1_MASK (0x1 << 11) 1038#define RT5663_INBUF_CBJ_BST1_MASK (0x1 << 11)
1047#define RT5663_INBUF_CBJ_BST1_SHIFT 11 1039#define RT5663_INBUF_CBJ_BST1_SHIFT 11
1048#define RT5663_INBUF_CBJ_BST1_ON (0x1 << 11) 1040#define RT5663_INBUF_CBJ_BST1_ON (0x1 << 11)
@@ -1052,11 +1044,11 @@
1052#define RT5663_CBJ_SENSE_BST1_L (0x1 << 10) 1044#define RT5663_CBJ_SENSE_BST1_L (0x1 << 10)
1053#define RT5663_CBJ_SENSE_BST1_R (0x0 << 10) 1045#define RT5663_CBJ_SENSE_BST1_R (0x0 << 10)
1054 1046
1055/* RT5663: Combo Jack Control (0x0251) */ 1047/* Combo Jack Control (0x0251) */
1056#define RT5663_GAIN_BST1_MASK (0xf) 1048#define RT5663_GAIN_BST1_MASK (0xf)
1057#define RT5663_GAIN_BST1_SHIFT 0 1049#define RT5663_GAIN_BST1_SHIFT 0
1058 1050
1059/* RT5663: Dummy register 1 (0x02fa) */ 1051/* Dummy register 1 (0x02fa) */
1060#define RT5663_EMB_CLK_MASK (0x1 << 9) 1052#define RT5663_EMB_CLK_MASK (0x1 << 9)
1061#define RT5663_EMB_CLK_SHIFT 9 1053#define RT5663_EMB_CLK_SHIFT 9
1062#define RT5663_EMB_CLK_EN (0x1 << 9) 1054#define RT5663_EMB_CLK_EN (0x1 << 9)
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-29 21:15:05 -0400