perf/x86/intel: Move NMI clearing to end of PMI handler

This avoids some problems with spurious PMIs on Haswell.
Haswell seems to behave more like P4 in this regard. Do
the same thing as the P4 perf handler by unmasking
the NMI only at the end. Shouldn't make any difference
for earlier family 6 cores.

(Tested on Haswell, IvyBridge, Westmere, Saltwell (Atom).)

Signed-off-by: Andi Kleen <ak@linux.intel.com>
Cc: Andi Kleen <ak@linux.jf.intel.com>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Link: http://lkml.kernel.org/r/1371515812-9646-5-git-send-email-andi@firstfloor.org
Signed-off-by: Ingo Molnar <mingo@kernel.org>

2 files changed, 13 insertions, 8 deletions

diff --git a/arch/x86/kernel/cpu/perf_event.h b/arch/x86/kernel/cpu/perf_event.h
index fb7fe44e6b96..f43473c50f52 100644
--- a/arch/x86/kernel/cpu/perf_event.h
+++ b/arch/x86/kernel/cpu/perf_event.h
@@ -378,6 +378,7 @@ struct x86_pmu {
         struct event_constraint *event_constraints;
         struct x86_pmu_quirk *quirks;
         int             perfctr_second_write;
+        bool            late_ack;
 
         /*
          * sysfs attrs
diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
index 4a4c4ba0c1d7..877672c43347 100644
--- a/arch/x86/kernel/cpu/perf_event_intel.c
+++ b/arch/x86/kernel/cpu/perf_event_intel.c
@@ -1185,15 +1185,11 @@ static int intel_pmu_handle_irq(struct pt_regs *regs)
         cpuc = &__get_cpu_var(cpu_hw_events);
 
         /*
-         * Some chipsets need to unmask the LVTPC in a particular spot
-         * inside the nmi handler.  As a result, the unmasking was pushed
-         * into all the nmi handlers.
-         *
-         * This handler doesn't seem to have any issues with the unmasking
-         * so it was left at the top.
+         * No known reason to not always do late ACK,
+         * but just in case do it opt-in.
          */
-        apic_write(APIC_LVTPC, APIC_DM_NMI);
-
+        if (!x86_pmu.late_ack)
+                apic_write(APIC_LVTPC, APIC_DM_NMI);
         intel_pmu_disable_all();
         handled = intel_pmu_drain_bts_buffer();
         status = intel_pmu_get_status();
@@ -1257,6 +1253,13 @@ again:
 
 done:
         intel_pmu_enable_all(0);
+        /*
+         * Only unmask the NMI after the overflow counters
+         * have been reset. This avoids spurious NMIs on
+         * Haswell CPUs.
+         */
+        if (x86_pmu.late_ack)
+                apic_write(APIC_LVTPC, APIC_DM_NMI);
         return handled;
 }
 
@@ -2260,6 +2263,7 @@ __init int intel_pmu_init(void)
         case 70:
         case 71:
         case 63:
+                x86_pmu.late_ack = true;
                 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids, sizeof(hw_cache_event_ids));
                 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));