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authorChanwoo Choi <cw00.choi@samsung.com>2016-04-15 02:32:52 -0400
committerSylwester Nawrocki <s.nawrocki@samsung.com>2016-04-15 12:13:42 -0400
commit72b67b3fcb5f500e73dfd42dce3a4749ba84e4bf (patch)
tree195a0b968746a56ddd1b1ff5e26a14593fb9ba42
parentf55532a0c0b8bb6148f4e07853b876ef73bc69ca (diff)
dt-bindings: clock: Add the clock id for ACLK clock of Exynos542x SoC
This patch adds the clock id for ACLK clock of Exynos542x SoC. ACLK clock means the source clock of AMBA AXI bus. This clock id should be used for Bus frequency scaling. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Tested-by: Markus Reichl <m.reichl@fivetechno.de> Tested-by: Anand Moon <linux.amoon@gmail.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
-rw-r--r--include/dt-bindings/clock/exynos5420.h24
1 files changed, 23 insertions, 1 deletions
diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h
index 7699ee9c16c0..17ab8394bec7 100644
--- a/include/dt-bindings/clock/exynos5420.h
+++ b/include/dt-bindings/clock/exynos5420.h
@@ -217,8 +217,30 @@
217 217
218/* divider clocks */ 218/* divider clocks */
219#define CLK_DOUT_PIXEL 768 219#define CLK_DOUT_PIXEL 768
220#define CLK_DOUT_ACLK400_WCORE 769
221#define CLK_DOUT_ACLK400_ISP 770
222#define CLK_DOUT_ACLK400_MSCL 771
223#define CLK_DOUT_ACLK200 772
224#define CLK_DOUT_ACLK200_FSYS2 773
225#define CLK_DOUT_ACLK100_NOC 774
226#define CLK_DOUT_PCLK200_FSYS 775
227#define CLK_DOUT_ACLK200_FSYS 776
228#define CLK_DOUT_ACLK333_432_GSCL 777
229#define CLK_DOUT_ACLK333_432_ISP 778
230#define CLK_DOUT_ACLK66 779
231#define CLK_DOUT_ACLK333_432_ISP0 780
232#define CLK_DOUT_ACLK266 781
233#define CLK_DOUT_ACLK166 782
234#define CLK_DOUT_ACLK333 783
235#define CLK_DOUT_ACLK333_G2D 784
236#define CLK_DOUT_ACLK266_G2D 785
237#define CLK_DOUT_ACLK_G3D 786
238#define CLK_DOUT_ACLK300_JPEG 787
239#define CLK_DOUT_ACLK300_DISP1 788
240#define CLK_DOUT_ACLK300_GSCL 789
241#define CLK_DOUT_ACLK400_DISP1 790
220 242
221/* must be greater than maximal clock id */ 243/* must be greater than maximal clock id */
222#define CLK_NR_CLKS 769 244#define CLK_NR_CLKS 791
223 245
224#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5420_H */ 246#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5420_H */